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Write one Conditional Signal Assignment VHDL code statement in the body of the
ARCHITECTURE to describe the behaviour of an OR gate.
Use these instructions:
Create a new VHDL source file called Qxxxxx. (where xxxxx are the last five digits of your
students number)
Enter the usual context clause at the top of the file. Now declare the top line and last line of an
ENTITY called Qxxxxx. It is common practice to place a each ENTITY in a single .vhd file that
is named identically to the ENTITY.
Now declare the inputs and outputs by typing PORT(….) into the ENTITY declaration. Name
the input signals A and B, and the output signal Y.
Solution
use IEEE.std_logic_1164.all;
entity orgate is
Port( A : in std_logic;
B : in std_logic;
Y : out std_logic
);
end orgate

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Write one Conditional Signal Assignment VHDL code statement in the b.pdf

  • 1. Write one Conditional Signal Assignment VHDL code statement in the body of the ARCHITECTURE to describe the behaviour of an OR gate. Use these instructions: Create a new VHDL source file called Qxxxxx. (where xxxxx are the last five digits of your students number) Enter the usual context clause at the top of the file. Now declare the top line and last line of an ENTITY called Qxxxxx. It is common practice to place a each ENTITY in a single .vhd file that is named identically to the ENTITY. Now declare the inputs and outputs by typing PORT(….) into the ENTITY declaration. Name the input signals A and B, and the output signal Y. Solution use IEEE.std_logic_1164.all; entity orgate is Port( A : in std_logic; B : in std_logic; Y : out std_logic ); end orgate