1. 1. Use of SSTA Tools for Evaluating BTI Impact on Combinational Circuits
2. On Deadlock Problem of On-Chip Buses Supporting Out-of-Order
Transactions
3. Delay Test for Diagnosis of Power Switches
4. Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating
5. Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal
Matrix Code
6. High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS
Technology
7. Incremental Trace-Buffer Insertion for FPGA Debug
8. LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM
Technology
9. Low-Complexity Reconfigurable Fast Filter Bank for Multi-Standard
Wireless Receivers
10. Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-
Through Scheme