UNIT 5
MEMORY
Memory Hierarchy with two levels
Major Differences between cache-main and main-
secondary-memory hierarchies
Memory Hierarchy with three levels
Memory Hierarchy with four levels
• Cost per bit Ci>Ci+1
• Access time tAi<tAi+1
• Storage capacity Si<Si+1
Important Figure of merits
Locality of Reference-Spatial
Locality of Reference-Temporal
STRUCTURE OF A CACHE MEMORY
CACHE ORGANIZATION-LOOK ASIDE
CACHE ORGANIZATION-LOOK THROUGH
CACHE-READ OPERATION
CACHE-WRITE OPERATION
Basic structure of a cache
Structure of an associative (content addressable) memory
Associative memory cell: (a) logic circuit and (b) symbol
A 4 x 4-bit associative memory array
Direct-mapped cache with block capacity of two
Memory
Interfacing
A 256KB direct-mapped cache for a microprocessor

unit 5 ppt.pptx