This document summarizes the design of a C band heterojunction bipolar transistor (HBT) differential low noise amplifier (LNA) for active microwave functions. It begins with an introduction to challenges in designing microwave circuits using silicon technologies. It then describes the design of a single-ended LNA followed by a differential LNA using the same design principles. Simulation results using ADS2010 show the differential LNA has a gain of over 10 dB from 2.1-3.7 GHz and a noise figure below 2 dB from 2-3.5 GHz. The differential structure provides advantages of noise and interference insensitivity compared to a single-ended design.
This document summarizes the performance evaluation of a three-element rectangular patch antenna array conformed on small radius cylindrical surfaces. Simulations were conducted for antenna arrays placed on cylinders with radii of 0.24λ and 0.32λ. The coupling between antenna elements was higher (~-1 dB) for the smaller 0.24λ radius cylinder compared to the 0.32λ radius cylinder which had coupling less than -18 dB. The cylindrical geometry affected the radiation patterns, making them more dependent on cylinder radius in the elevation plane but less so in the azimuth plane. The proposed antenna array maintained acceptable omnidirectional radiation patterns needed for wireless applications.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Reduction of mutual coupling between patch elements using split ring dgsIAEME Publication
The document summarizes research on reducing mutual coupling between patch antenna elements in an array using a split-ring defected ground structure (DGS). It first describes DGS units and their ability to disturb surface currents on the ground plane. It then presents a two-element patch antenna array integrated with a split-ring DGS cell placed between the elements. Simulation results show the DGS reduces mutual coupling between elements by 1.24 dB compared to without a DGS. The inclusion of the DGS also shifts the resonant frequency by 180 MHz but increases side lobe levels slightly. Overall, the DGS technique provides a way to reduce mutual coupling and compact the size of multi-element patch antenna arrays.
This white paper discusses the migration from DVB-S to DVB-S2 satellite communication standards and the related efficiencies. DVB-S2 provides improved forward error correction using LDPC coding, which allows for a 30% increase in bandwidth efficiency over DVB-S. This efficiency gain can be used to support more users within an existing bandwidth allocation or reduce the bandwidth needed to support the same number of users. The paper provides an example where migrating from DVB-S to DVB-S2 reduces the monthly operating expense for a satellite transmission by 30% by needing less bandwidth to support all users within the satellite footprint.
The SWAP: A Breakthrough in Hydrogen Sulfide Processingevanthowell
The SWAP: A breakthrough in hydrogen sulfide processing," presented by CEO Wolf Koch, to Sulphur 2011 Conference & Exhibition, Houston, November 10, 2011.
International Journal of Engineering Research and Development is an international premier peer reviewed open access engineering and technology journal promoting the discovery, innovation, advancement and dissemination of basic and transitional knowledge in engineering, technology and related disciplines.
We follow "Rigorous Publication" model - means that all articles appear on IJERD after full appraisal, effectiveness, legitimacy and reliability of research content. International Journal of Engineering Research and Development publishes papers online as well as provide hard copy of Journal to authors after publication of paper. It is intended to serve as a forum for researchers, practitioners and developers to exchange ideas and results for the advancement of Engineering & Technology.
The SpeedIT provides a partial acceleration of sparse linear solvers. Acceleration is achieved with a single reasonably priced NVIDIA Graphics Processing Unit (GPU) that supporst CUDA and proprietary advanced optimisation techniques.
Check also SpeedIT FLOW, our RANS single phase flow solver that runs fully on GPU: vratis.com/blog
Bhark, E.W., Structured History Matching Workflow using Parameterization and ...ebhark
This document discusses a new multiscale parameterization and history matching workflow for structured and unstructured grids. At the regional scale, it introduces a novel grid-connectivity-based parameterization that flexibly captures heterogeneity while reducing the number of parameters. At the local scale, it leverages established streamline-based methods to refine preferential flow paths. The workflow iterates between regional and local scales to history match production data in a computationally efficient manner.
This document summarizes the performance evaluation of a three-element rectangular patch antenna array conformed on small radius cylindrical surfaces. Simulations were conducted for antenna arrays placed on cylinders with radii of 0.24λ and 0.32λ. The coupling between antenna elements was higher (~-1 dB) for the smaller 0.24λ radius cylinder compared to the 0.32λ radius cylinder which had coupling less than -18 dB. The cylindrical geometry affected the radiation patterns, making them more dependent on cylinder radius in the elevation plane but less so in the azimuth plane. The proposed antenna array maintained acceptable omnidirectional radiation patterns needed for wireless applications.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Reduction of mutual coupling between patch elements using split ring dgsIAEME Publication
The document summarizes research on reducing mutual coupling between patch antenna elements in an array using a split-ring defected ground structure (DGS). It first describes DGS units and their ability to disturb surface currents on the ground plane. It then presents a two-element patch antenna array integrated with a split-ring DGS cell placed between the elements. Simulation results show the DGS reduces mutual coupling between elements by 1.24 dB compared to without a DGS. The inclusion of the DGS also shifts the resonant frequency by 180 MHz but increases side lobe levels slightly. Overall, the DGS technique provides a way to reduce mutual coupling and compact the size of multi-element patch antenna arrays.
This white paper discusses the migration from DVB-S to DVB-S2 satellite communication standards and the related efficiencies. DVB-S2 provides improved forward error correction using LDPC coding, which allows for a 30% increase in bandwidth efficiency over DVB-S. This efficiency gain can be used to support more users within an existing bandwidth allocation or reduce the bandwidth needed to support the same number of users. The paper provides an example where migrating from DVB-S to DVB-S2 reduces the monthly operating expense for a satellite transmission by 30% by needing less bandwidth to support all users within the satellite footprint.
The SWAP: A Breakthrough in Hydrogen Sulfide Processingevanthowell
The SWAP: A breakthrough in hydrogen sulfide processing," presented by CEO Wolf Koch, to Sulphur 2011 Conference & Exhibition, Houston, November 10, 2011.
International Journal of Engineering Research and Development is an international premier peer reviewed open access engineering and technology journal promoting the discovery, innovation, advancement and dissemination of basic and transitional knowledge in engineering, technology and related disciplines.
We follow "Rigorous Publication" model - means that all articles appear on IJERD after full appraisal, effectiveness, legitimacy and reliability of research content. International Journal of Engineering Research and Development publishes papers online as well as provide hard copy of Journal to authors after publication of paper. It is intended to serve as a forum for researchers, practitioners and developers to exchange ideas and results for the advancement of Engineering & Technology.
The SpeedIT provides a partial acceleration of sparse linear solvers. Acceleration is achieved with a single reasonably priced NVIDIA Graphics Processing Unit (GPU) that supporst CUDA and proprietary advanced optimisation techniques.
Check also SpeedIT FLOW, our RANS single phase flow solver that runs fully on GPU: vratis.com/blog
Bhark, E.W., Structured History Matching Workflow using Parameterization and ...ebhark
This document discusses a new multiscale parameterization and history matching workflow for structured and unstructured grids. At the regional scale, it introduces a novel grid-connectivity-based parameterization that flexibly captures heterogeneity while reducing the number of parameters. At the local scale, it leverages established streamline-based methods to refine preferential flow paths. The workflow iterates between regional and local scales to history match production data in a computationally efficient manner.
Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
The document describes the design of a compact printed antenna for UMTS and WiMAX applications. A rectangular microstrip patch antenna with two L-shaped slits is proposed to reduce the size by 73% compared to a conventional patch antenna. Simulation results show the antenna operates in three frequency bands with return losses of -16.37 dB at 2.03 GHz, -14.56 dB at 2.65 GHz, and -21.06 dB at 3.42 GHz and corresponding bandwidths of 15.02 MHz, 12.72 MHz, and 42.36 MHz respectively. Measured results agree reasonably well with simulations. The antenna achieves multiband operation and size reduction for wireless communication applications.
Modelling And Miniaturization of A 2-Bits Phase Shifter Using Koch Fractal Sh...IJERA Editor
Phase shifter is a key component in phase array antenna for the Radar application and the wireless communication system. This paper presents a novel design of miniaturised 2bits phase shifter using Koch fractal shapes of one iteration orders. The 3-section branch line coupler is used to extend the bandwidth of the phase shifter,this type of coupler is characterised by a low cost and simplicity of fabrication.Using the Koch fractal geometry the circuit size of the coupler is reduced to 6.36cm ×2.14cm at 2.4GHz. The simulation results show a good performance. So, over 2.1GHz-2.7GHzThe novel design of 2bits fractal reflection phase shifter based on the 3section show a return loss less than -20dB and the phase error varied between 0.1° and 0.4°for the four output phases . The circuit size of the phase shifter is reduced to9.5cm×2.1cm.
IJERD(www.ijerd.com)International Journal of Engineering Research and Develop...IJERD Editor
This document presents the design and analysis of a slotted diagonal shaped patch antenna with a hybrid coupler. Theoretical performance is analyzed using ADS software. Measured return loss is -15.65dB at 2.417GHz, agreeing with simulations. Circular polarization is achieved by directly connecting the hybrid coupler to the radiating element. The antenna has a gain of 3.319dB and directivity of 6.98dB, making it useful for wireless applications.
International Journal of Engineering Research and Development is an international premier peer reviewed open access engineering and technology journal promoting the discovery, innovation, advancement and dissemination of basic and transitional knowledge in engineering, technology and related disciplines.
We follow "Rigorous Publication" model - means that all articles appear on IJERD after full appraisal, effectiveness, legitimacy and reliability of research content. International Journal of Engineering Research and Development publishes papers online as well as provide hard copy of Journal to authors after publication of paper. It is intended to serve as a forum for researchers, practitioners and developers to exchange ideas and results for the advancement of Engineering & Technology.
IRJET- Design and Simulation of 12-Bit Current Steering DACIRJET Journal
This document describes the design and simulation of a 12-bit current steering digital-to-analog converter (DAC). It begins with an abstract that outlines the need to convert analog signals to digital for processing and then back to analog. It then discusses the objectives of designing a 12-bit segmented current steering DAC using a 180nm process with 3V supply at 2GHz speed. The document reviews current steering DAC architecture and its advantages of speed and accuracy. It then provides details on the design of a 3-bit current steering DAC segment including a binary-to-thermometer decoder, switch driver, differential switch, and cascode current mirror.
Delta-sigma ADC modulator for multibit data converters using passive adder en...journalBEEI
This paper introduces a multi-bit data converters (MDC) modulator of the 2nd order delta-sigma analog-to-digital converter use the passive adder proposed. The noise shaping quantizer can provide feedback that has generated quantization noise and perform additional shaping noise first-order by coupling noise method.Thus, two Integrator's with ring amplifier and the MDC is shaped by noise coupling quantizer know the 2nd-order noise coupled with somewhat of a DAC modulator. At a summing point, the inputs are summed and then filtered with a low pass filter. A cyclic second order response is generated with a data weighted averaging (DWA) technique in which the DACs ' outputs are limited to one of two states in the noise shaping responses. Mainly as a result of the harmonic distortion in circuits of amplifier. Transistor rate is equipped for the fully differential switched condenser integrator used, a comparator and DWA. The modulator with proposed DWA design, almost quarterly improved timing margin. A simulated SNDR of 92dB is obtained at 20 MHz sampling frequency; while a sinusoidal output of 4.112 dBFS is tested at 90µs besides 20 MHz as the bandwidth. The power consumption is 0.33 mW while the voltage of the supply is 1.2V.
Design and Fabrication of the Novel Miniaturized Microstrip Coupler 3dB Using...TELKOMNIKA JOURNAL
In this work, a novel miniaturized compact coupler using the shunt-stubs artificial transimission
lines with high and low impedances is presented. Design of the proposed coupler is accomplished by
modifying the length and impedance of the branch lines in the conventional structure with the planar
resonators in order to achieve branch line coupler with compact size and improvement of the
performances. First part of this work is focusing on the theorical study of the proposed resonators where
the equations are obtained. Secondly, the proposed coupler is designed on FR4 susbtrate, and simulated
by using the EM Solver (ADS from Agilent technologies and CST microwave studio) in order to operate in
the ISM band. The obtained results show good agreement with the simulations and the coupler shows a
good perfo6rmance in the hole bandwidth. The size of the proposed coupler is reduced around 50%
compared to the conventional design. The last part conerns the fabrication and test of the proposed
coupler. The measurement and simulation results are in good agreements.
This report describes the design of a 32K-bit sleepy SRAM to reduce leakage power through the use of sleep transistors. The design uses a 6T SRAM cell with additional nMOS and pMOS sleep transistors to control the subthreshold leakage current. Through transistor sizing and selecting a sleep transistor width/length of 1, the design achieves a 47% reduction in power without increasing the worst-case delay. A 3-segment Pi wire model is used to simulate the effects of wire resistance and capacitance.
The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of Z...IDES Editor
This work is about the analysis of dead time
variation on switching losses in a Zero Voltage Switching
(ZVS) synchronous buck converter (SBC) circuit. In high
frequency converter circuits, switching losses are
commonly linked with high and low side switches of SBC
circuit. They are activated externally by the gate driver
circuit. The duty ratio, dead time and resonant inductor
are the parameters that affect the efficiency of the circuit.
These variables can be adjusted for the optimization
purposes. The study primarily focuses on varying the
settings of input pulses of the MOSFETs in the resonant
gate driver circuit which consequently affects the
performance of the ZVS synchronous buck converter
circuit. Using the predetermined inductor of 9 nH, the
frequency is maintained at 1 MHz for each cycle
transition. The switching loss graph is obtained and
switching losses for both S1 and S2 are calculated and
compared to the findings from previous work. It has
shown a decrease in losses by 13.8 % in S1. A dead time of
15 ns has been determined to be optimized value in the
SBC design.
The document discusses the evolution and performance of WiMAX technology over different releases (Release 1.0, 1.5, and 2.0). Key points include:
- Performance metrics like peak/average spectral efficiency, data rates, and supported mobility increased with each new release through improvements like increased channel bandwidth, advanced antenna techniques, and modulation schemes.
- Release 2.0 supported carrier aggregation up to 100MHz and advanced MIMO techniques like 8x8 MIMO, providing significantly higher peak/average data rates and spectral efficiency compared to previous releases.
- The increased performance allowed supporting more subscribers per sector while maintaining the data rate per user, demonstrating a 642% growth in capacity from 2010 to 2015 through
The document provides an overview of how the GPS satellite system works:
- GPS uses 24 satellites orbiting Earth at 20,000 km to transmit timing signals.
- Satellites broadcast signals allowing receivers to calculate distances and determine the user's position.
- At least 4 satellite signals are needed to solve for the user's 3D position and clock bias/offset.
- Key concepts covered include satellite orbits, signal transmission delays, and calculating user position.
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...IJERD Editor
The document describes modifications made to a log periodic dipole antenna (LPDA) to make it more portable while maintaining performance. Specifically:
- The original LPDA had a boom length of 5.5 meters, which was reduced to 3.11 meters to improve portability.
- 38 elements were used on two booms to cover frequencies from 45MHz to 1000MHz. Plastic insulation and a spacing factor of 0.08 were used.
- The antenna was connected to a CALLISTO spectrometer via coaxial cable to convert radio signals for detection and measurement of solar bursts.
- Initial results showed the modified compact LPDA operated successfully while maintaining the desired frequency range and directivity.
This document analyzes trends in ADC performance as CMOS technology scales down to smaller node sizes. It examines a large dataset of over 1100 scientific publications on experimental CMOS ADCs from 1976 to 2010. The following trends are observed:
1) Noise floor increases with scaling due to lower supply voltages and reduced signal swing. Empirical data shows the noise floor approaching limits that prevent further improvement of sampling rate as nodes shrink past 90nm.
2) Sampling rate increases for low-resolution ADCs but decreases for high-resolution ADCs with scaling. Limits are estimated where noise prevents maintaining or improving sampling rate in newer nodes.
3) Monolithic integration of wideband ADCs for wireless is limited to nodes older
OPTIMIZATION OF CMOS 0.18 M LOW NOISE AMPLIFIER USING NSGA-II FOR UWBVLSICS Design
A design and optimization of 3-5 GHz single ended Radio Frequency (RF) Low Noise Amplifier (LNA) for ultra-wide-band (UWB) applications using standard UMC 0.18 µm CMOS technology is reported. Designing of RF circuit components is a challenging job, since even after performing lengthy calculations and finding parameter values it is less guarantee that the design performs as expected. In view of this the optimization tool; Elitist Non-Dominated Sorting Genetic Algorithm (NSGA-II); has been employed to get the optimized starting values of components in the proposed LNA design. The obtained NSGA-II parameters were simulated using Cadence Spectre- RF simulator. The designed Low Noise Amplifier achieves a power gain of 22 dB and a minimum Noise Figure of 3 dB is achieved. It dissipates 12.5 mW of power out of 1.8 V supply
This chapter discusses radio frequency integrated circuit design using nanoscale double-gate MOSFETs (DG-MOSFETs). It provides background on the advantages of DG-MOSFETs for digital and RF applications due to their ability to control short channel effects and reduce leakage currents. Simulation results showing the tunable threshold voltage of n-type DG-MOSFETs with varying back-gate bias are presented to validate compact models from Arizona State University.
DESIGN AND IMPLEMENTATION OF 10 BIT, 2MS/s SPLIT SAR ADC USING 0.18um CMOS TE...VLSICS Design
This paper focuses on Design and Implementation of 10 Bit, 2MS/s successive approximation Register (SAR) Analog to digital converter (ADC) using Split DAC architecture. This SAR ADC architecture is
designed and simulated using GPDK 0.18um CMOS technology. It consists of different blocks like sample
and hold, comparator, Successive Approximation Register (SAR) and Split Digital to analog converter(DAC). For each block of SAR ADC power is calculated. DAC is an important component within the SAR ADC. The charge redistribution DAC in a Split capacitor configuration has a total capacitance which is96.87% smaller compared to a conventional binary weighted design. Hence Split DAC gives an optimizedarchitecture and it consumes less power. Optimized design of DAC architecture ensures the accuracy ofthe components, which improves the performance of SAR ADC. Comparator constructed from resistances,capacitance and dependent voltage sources instead of MOS transistors. Dynamic range for SAR ADC
using split DAC is 60.19dB. The supply voltage is 1.2V. The total Power consumed by SAR ADC using
Split array DAC is 95.65114uW and SAR ADC using binary weighted capacitor DAC is 211.19084uW.
Optimization of Cmos 0.18 µM Low Noise Amplifier Using Nsga-Ii for UWB Applic...VLSICS Design
A design and optimization of 3-5 GHz single ended Radio Frequency (RF) Low Noise Amplifier (LNA) for
ultra-wide-band (UWB) applications using standard UMC 0.18 μm CMOS technology is reported.
Designing of RF circuit components is a challenging job, since even after performing lengthy calculations
and finding parameter values it is less guarantee that the design performs as expected. In view of this the
optimization tool; Elitist Non-Dominated Sorting Genetic Algorithm (NSGA-II); has been employed to get
the optimized starting values of components in the proposed LNA design. The obtained NSGA-II
parameters were simulated using Cadence Spectre- RF simulator. The designed Low Noise Amplifier
achieves a power gain of 22 dB and a minimum Noise Figure of 3 dB is achieved. It dissipates 12.5 mW of
power out of 1.8 V supply.
TDR-BASED DWS MODELING OF PASSIVE COMPONENTSPiero Belforte
1) Interconnection lengths of just a few centimeters can impact signal integrity for signals with rise times under 1 nanosecond due to reflections, dispersion, and skin effect. Distributed models are needed to account for these effects.
2) Measurements from a reflectometer can be used to create behavioral models in the time domain of passive components like cables and connectors. These measurement-based models capture effects that simpler lumped or distributed models cannot.
3) For a sample coaxial cable, reflectometer data was extracted and used to create S-parameter models of the cable in the DWS simulator. Simulations using these models matched the actual reflectometer measurements very closely, validating the behavioral modeling approach.
This document provides information about a circuit using a MAX-232 chip for serial communication between two PCs over a short distance using infrared diodes or longer distances using laser diodes. It includes diagrams of the internal functionality of the MAX-232 chip and the circuit configuration. It also provides theory on the components used, including phototransistors, infrared LEDs, resistors, capacitors, and the 8051 microcontroller. Programming for communication using C language on the 8051 is discussed.
This document analyzes the performance of a Bluetooth system using an optimized differential Gaussian frequency-shift keying (GFSK) demodulator. It first introduces Bluetooth technology and the GFSK modulation scheme. It then presents the system model and signal model for the Bluetooth transmission. The key contribution is developing an optimized differential GFSK demodulator that averages the phase over a portion of each symbol to improve performance compared to conventional differential demodulation that uses a single phase sample per symbol. Simulation results show the proposed demodulator achieves better bit error rate than conventional techniques.
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Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
The document describes the design of a compact printed antenna for UMTS and WiMAX applications. A rectangular microstrip patch antenna with two L-shaped slits is proposed to reduce the size by 73% compared to a conventional patch antenna. Simulation results show the antenna operates in three frequency bands with return losses of -16.37 dB at 2.03 GHz, -14.56 dB at 2.65 GHz, and -21.06 dB at 3.42 GHz and corresponding bandwidths of 15.02 MHz, 12.72 MHz, and 42.36 MHz respectively. Measured results agree reasonably well with simulations. The antenna achieves multiband operation and size reduction for wireless communication applications.
Modelling And Miniaturization of A 2-Bits Phase Shifter Using Koch Fractal Sh...IJERA Editor
Phase shifter is a key component in phase array antenna for the Radar application and the wireless communication system. This paper presents a novel design of miniaturised 2bits phase shifter using Koch fractal shapes of one iteration orders. The 3-section branch line coupler is used to extend the bandwidth of the phase shifter,this type of coupler is characterised by a low cost and simplicity of fabrication.Using the Koch fractal geometry the circuit size of the coupler is reduced to 6.36cm ×2.14cm at 2.4GHz. The simulation results show a good performance. So, over 2.1GHz-2.7GHzThe novel design of 2bits fractal reflection phase shifter based on the 3section show a return loss less than -20dB and the phase error varied between 0.1° and 0.4°for the four output phases . The circuit size of the phase shifter is reduced to9.5cm×2.1cm.
IJERD(www.ijerd.com)International Journal of Engineering Research and Develop...IJERD Editor
This document presents the design and analysis of a slotted diagonal shaped patch antenna with a hybrid coupler. Theoretical performance is analyzed using ADS software. Measured return loss is -15.65dB at 2.417GHz, agreeing with simulations. Circular polarization is achieved by directly connecting the hybrid coupler to the radiating element. The antenna has a gain of 3.319dB and directivity of 6.98dB, making it useful for wireless applications.
International Journal of Engineering Research and Development is an international premier peer reviewed open access engineering and technology journal promoting the discovery, innovation, advancement and dissemination of basic and transitional knowledge in engineering, technology and related disciplines.
We follow "Rigorous Publication" model - means that all articles appear on IJERD after full appraisal, effectiveness, legitimacy and reliability of research content. International Journal of Engineering Research and Development publishes papers online as well as provide hard copy of Journal to authors after publication of paper. It is intended to serve as a forum for researchers, practitioners and developers to exchange ideas and results for the advancement of Engineering & Technology.
IRJET- Design and Simulation of 12-Bit Current Steering DACIRJET Journal
This document describes the design and simulation of a 12-bit current steering digital-to-analog converter (DAC). It begins with an abstract that outlines the need to convert analog signals to digital for processing and then back to analog. It then discusses the objectives of designing a 12-bit segmented current steering DAC using a 180nm process with 3V supply at 2GHz speed. The document reviews current steering DAC architecture and its advantages of speed and accuracy. It then provides details on the design of a 3-bit current steering DAC segment including a binary-to-thermometer decoder, switch driver, differential switch, and cascode current mirror.
Delta-sigma ADC modulator for multibit data converters using passive adder en...journalBEEI
This paper introduces a multi-bit data converters (MDC) modulator of the 2nd order delta-sigma analog-to-digital converter use the passive adder proposed. The noise shaping quantizer can provide feedback that has generated quantization noise and perform additional shaping noise first-order by coupling noise method.Thus, two Integrator's with ring amplifier and the MDC is shaped by noise coupling quantizer know the 2nd-order noise coupled with somewhat of a DAC modulator. At a summing point, the inputs are summed and then filtered with a low pass filter. A cyclic second order response is generated with a data weighted averaging (DWA) technique in which the DACs ' outputs are limited to one of two states in the noise shaping responses. Mainly as a result of the harmonic distortion in circuits of amplifier. Transistor rate is equipped for the fully differential switched condenser integrator used, a comparator and DWA. The modulator with proposed DWA design, almost quarterly improved timing margin. A simulated SNDR of 92dB is obtained at 20 MHz sampling frequency; while a sinusoidal output of 4.112 dBFS is tested at 90µs besides 20 MHz as the bandwidth. The power consumption is 0.33 mW while the voltage of the supply is 1.2V.
Design and Fabrication of the Novel Miniaturized Microstrip Coupler 3dB Using...TELKOMNIKA JOURNAL
In this work, a novel miniaturized compact coupler using the shunt-stubs artificial transimission
lines with high and low impedances is presented. Design of the proposed coupler is accomplished by
modifying the length and impedance of the branch lines in the conventional structure with the planar
resonators in order to achieve branch line coupler with compact size and improvement of the
performances. First part of this work is focusing on the theorical study of the proposed resonators where
the equations are obtained. Secondly, the proposed coupler is designed on FR4 susbtrate, and simulated
by using the EM Solver (ADS from Agilent technologies and CST microwave studio) in order to operate in
the ISM band. The obtained results show good agreement with the simulations and the coupler shows a
good perfo6rmance in the hole bandwidth. The size of the proposed coupler is reduced around 50%
compared to the conventional design. The last part conerns the fabrication and test of the proposed
coupler. The measurement and simulation results are in good agreements.
This report describes the design of a 32K-bit sleepy SRAM to reduce leakage power through the use of sleep transistors. The design uses a 6T SRAM cell with additional nMOS and pMOS sleep transistors to control the subthreshold leakage current. Through transistor sizing and selecting a sleep transistor width/length of 1, the design achieves a 47% reduction in power without increasing the worst-case delay. A 3-segment Pi wire model is used to simulate the effects of wire resistance and capacitance.
The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of Z...IDES Editor
This work is about the analysis of dead time
variation on switching losses in a Zero Voltage Switching
(ZVS) synchronous buck converter (SBC) circuit. In high
frequency converter circuits, switching losses are
commonly linked with high and low side switches of SBC
circuit. They are activated externally by the gate driver
circuit. The duty ratio, dead time and resonant inductor
are the parameters that affect the efficiency of the circuit.
These variables can be adjusted for the optimization
purposes. The study primarily focuses on varying the
settings of input pulses of the MOSFETs in the resonant
gate driver circuit which consequently affects the
performance of the ZVS synchronous buck converter
circuit. Using the predetermined inductor of 9 nH, the
frequency is maintained at 1 MHz for each cycle
transition. The switching loss graph is obtained and
switching losses for both S1 and S2 are calculated and
compared to the findings from previous work. It has
shown a decrease in losses by 13.8 % in S1. A dead time of
15 ns has been determined to be optimized value in the
SBC design.
The document discusses the evolution and performance of WiMAX technology over different releases (Release 1.0, 1.5, and 2.0). Key points include:
- Performance metrics like peak/average spectral efficiency, data rates, and supported mobility increased with each new release through improvements like increased channel bandwidth, advanced antenna techniques, and modulation schemes.
- Release 2.0 supported carrier aggregation up to 100MHz and advanced MIMO techniques like 8x8 MIMO, providing significantly higher peak/average data rates and spectral efficiency compared to previous releases.
- The increased performance allowed supporting more subscribers per sector while maintaining the data rate per user, demonstrating a 642% growth in capacity from 2010 to 2015 through
The document provides an overview of how the GPS satellite system works:
- GPS uses 24 satellites orbiting Earth at 20,000 km to transmit timing signals.
- Satellites broadcast signals allowing receivers to calculate distances and determine the user's position.
- At least 4 satellite signals are needed to solve for the user's 3D position and clock bias/offset.
- Key concepts covered include satellite orbits, signal transmission delays, and calculating user position.
IJERD (www.ijerd.com) International Journal of Engineering Research and Devel...IJERD Editor
The document describes modifications made to a log periodic dipole antenna (LPDA) to make it more portable while maintaining performance. Specifically:
- The original LPDA had a boom length of 5.5 meters, which was reduced to 3.11 meters to improve portability.
- 38 elements were used on two booms to cover frequencies from 45MHz to 1000MHz. Plastic insulation and a spacing factor of 0.08 were used.
- The antenna was connected to a CALLISTO spectrometer via coaxial cable to convert radio signals for detection and measurement of solar bursts.
- Initial results showed the modified compact LPDA operated successfully while maintaining the desired frequency range and directivity.
This document analyzes trends in ADC performance as CMOS technology scales down to smaller node sizes. It examines a large dataset of over 1100 scientific publications on experimental CMOS ADCs from 1976 to 2010. The following trends are observed:
1) Noise floor increases with scaling due to lower supply voltages and reduced signal swing. Empirical data shows the noise floor approaching limits that prevent further improvement of sampling rate as nodes shrink past 90nm.
2) Sampling rate increases for low-resolution ADCs but decreases for high-resolution ADCs with scaling. Limits are estimated where noise prevents maintaining or improving sampling rate in newer nodes.
3) Monolithic integration of wideband ADCs for wireless is limited to nodes older
OPTIMIZATION OF CMOS 0.18 M LOW NOISE AMPLIFIER USING NSGA-II FOR UWBVLSICS Design
A design and optimization of 3-5 GHz single ended Radio Frequency (RF) Low Noise Amplifier (LNA) for ultra-wide-band (UWB) applications using standard UMC 0.18 µm CMOS technology is reported. Designing of RF circuit components is a challenging job, since even after performing lengthy calculations and finding parameter values it is less guarantee that the design performs as expected. In view of this the optimization tool; Elitist Non-Dominated Sorting Genetic Algorithm (NSGA-II); has been employed to get the optimized starting values of components in the proposed LNA design. The obtained NSGA-II parameters were simulated using Cadence Spectre- RF simulator. The designed Low Noise Amplifier achieves a power gain of 22 dB and a minimum Noise Figure of 3 dB is achieved. It dissipates 12.5 mW of power out of 1.8 V supply
This chapter discusses radio frequency integrated circuit design using nanoscale double-gate MOSFETs (DG-MOSFETs). It provides background on the advantages of DG-MOSFETs for digital and RF applications due to their ability to control short channel effects and reduce leakage currents. Simulation results showing the tunable threshold voltage of n-type DG-MOSFETs with varying back-gate bias are presented to validate compact models from Arizona State University.
DESIGN AND IMPLEMENTATION OF 10 BIT, 2MS/s SPLIT SAR ADC USING 0.18um CMOS TE...VLSICS Design
This paper focuses on Design and Implementation of 10 Bit, 2MS/s successive approximation Register (SAR) Analog to digital converter (ADC) using Split DAC architecture. This SAR ADC architecture is
designed and simulated using GPDK 0.18um CMOS technology. It consists of different blocks like sample
and hold, comparator, Successive Approximation Register (SAR) and Split Digital to analog converter(DAC). For each block of SAR ADC power is calculated. DAC is an important component within the SAR ADC. The charge redistribution DAC in a Split capacitor configuration has a total capacitance which is96.87% smaller compared to a conventional binary weighted design. Hence Split DAC gives an optimizedarchitecture and it consumes less power. Optimized design of DAC architecture ensures the accuracy ofthe components, which improves the performance of SAR ADC. Comparator constructed from resistances,capacitance and dependent voltage sources instead of MOS transistors. Dynamic range for SAR ADC
using split DAC is 60.19dB. The supply voltage is 1.2V. The total Power consumed by SAR ADC using
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Optimization of Cmos 0.18 µM Low Noise Amplifier Using Nsga-Ii for UWB Applic...VLSICS Design
A design and optimization of 3-5 GHz single ended Radio Frequency (RF) Low Noise Amplifier (LNA) for
ultra-wide-band (UWB) applications using standard UMC 0.18 μm CMOS technology is reported.
Designing of RF circuit components is a challenging job, since even after performing lengthy calculations
and finding parameter values it is less guarantee that the design performs as expected. In view of this the
optimization tool; Elitist Non-Dominated Sorting Genetic Algorithm (NSGA-II); has been employed to get
the optimized starting values of components in the proposed LNA design. The obtained NSGA-II
parameters were simulated using Cadence Spectre- RF simulator. The designed Low Noise Amplifier
achieves a power gain of 22 dB and a minimum Noise Figure of 3 dB is achieved. It dissipates 12.5 mW of
power out of 1.8 V supply.
TDR-BASED DWS MODELING OF PASSIVE COMPONENTSPiero Belforte
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This document provides information about a circuit using a MAX-232 chip for serial communication between two PCs over a short distance using infrared diodes or longer distances using laser diodes. It includes diagrams of the internal functionality of the MAX-232 chip and the circuit configuration. It also provides theory on the components used, including phototransistors, infrared LEDs, resistors, capacitors, and the 8051 microcontroller. Programming for communication using C language on the 8051 is discussed.
This document analyzes the performance of a Bluetooth system using an optimized differential Gaussian frequency-shift keying (GFSK) demodulator. It first introduces Bluetooth technology and the GFSK modulation scheme. It then presents the system model and signal model for the Bluetooth transmission. The key contribution is developing an optimized differential GFSK demodulator that averages the phase over a portion of each symbol to improve performance compared to conventional differential demodulation that uses a single phase sample per symbol. Simulation results show the proposed demodulator achieves better bit error rate than conventional techniques.
Similar to Research Inventy : International Journal of Engineering and Science (20)
Research Inventy : International Journal of Engineering and Science
1. RESEARCH INVENTY: International Journal of Engineering and Science
ISBN: 2319-6483, ISSN: 2278-4721, Vol. 2, Issue 1
(January 2013), PP 20-24
www.researchinventy.com
C band HBT Low Noise Amplifier for active
functions at microwaves
Toumaj KOHANDEL GARGARI
Istanbul Technical University
Abstract - This paper discusses the use of differential structures for active functions at microwaves. Starting
from the example of a single-ended LNA structure, we show the advantages of using a differential approach
with the design examples of a LNA structure. The LNA was designed in the BiCMOS HBT process. ADS2010
was simulated to obtain the preliminary results.
I. INTRODUCTION
Using Silicon technology has been restricted to low frequency digital and analogue applications during the
last three decades. Particularly within the last decade, Silicon-based ICs have resulted in an increasing of
importance for RF applications [1], because of the great advances Silicon, and Silicon-Germanium technologies
own. The amount of articles reporting the use of SiGe technology in RFIC designing has shown a significant.
Si/SiGe technology, as compared to GaAs, is noticeably advantageous, owing to its capability to reach more
compact and cost-effective circuits. Despite these advantages however, designers need to be aware of some new
constraints surrounding microwaves. The first major problem occurs when working with CAD tools. Because
silicon technology is classically used in digital and analogue applications at low frequencies, component libraries
are mostly developed in the field of CAD software using the same approach, as a natural trend. The philosophy
behind designing these circuits is very different from the one behind designing classical microwave analogue
circuits. Consequently, some components such as inductors are not accessible, for they were not classically used
at low frequencies. For some processes the same is also true for varactor diodes. Currently, some component
models are still not parameterized, hence making any optimization hard. Due to technological reasons, the ground
plane of a circuit on silicon is placed on the top of the substrate. Therefore, considering microstrip lines as a
serious option is not possible, even though recent studies have revealed the feasibility of transmission lines in
polymers such as BCB, enabling performances close to those achieved with GaAs [1], [2]. Regarding the design,
another problem may emerge from the specific conductivity of the doped Silicon (SiGe) substrate and its bad
isolation, which results in a significant increase in the number of parasitic capacitances.
These capacitances are not able to be neglected, concerning the other capacitances of the circuits. The leakage
currents also need to be paid a particular attention, due to the specific conductivity of the substrate. In order for
this problem to be solved, many manufacturers employ guard rings. These rings are buried layers which surround
the component, totally or in part, so that it is protected by acting as PN junction biased in inverse. All these
protection processes obviously allow a more compact implementation, as compared to GaAs, which can be
regarded as a positive point. It should be mentioned that, in designing circuits using bipolar transistors, the
designer needs to be familiar with particular biasing methods and topologies, and this complicates the design
procedure obviously. The SiGe BiCMOS HBT is a promising solution for designing active function at
microwaves, from among all the other Si/SiGe processes. BiCMOS HBT is the title assigned to heterojunction
bipolar transistor, for which the base is doped with Germanium. The designed chips work much faster by
applying this reliable and stable process. Moreover, this technology enjoys the integration capability of CMOS
process, which again, results in more compactness [4]-[7].
II. LNA SINGLE-STAGE DESIGN
Designing equations are the same as for the single stage LNA design which are summarized as:
L .g 1 (1)
Rin Rg s m j Ls
C gs
C gs
Can be restated as
Rin Rg Ra j[ X Ls X Cgs ] (2)
Where
L .g
Ra s m (3)
C gs
20
2. C band HBT Differential Low Noise Amplifier for active functions at microwaves
Hence, the impedance of the MOSFET without feedback
Rin Rg jX Cgs Rin jX Cgs (4)
Adding series feedback integrates the following term into the original input impedance:
R jX (5)
a Ls
Moreover, another inductor is added in series with the gate Lg that is chosen to resonate with the Cgs
Capacitor.
We are trying to achieve is the following:
L .g
Ra s m Where Rin may be say 50 ohms.
C gs
Lg is designed so that it cancels out Cgs at the resonant frequency i.e.
1
j Ls
0
C gs
(6)
In most LNA designs the value of Ls is chosen and the values of gm and Cgs are calculated to give the
required Rin.
Figure 1. Initial single-stage LNA schematic
III. DIFFERENTIAL LNA DESIGN
Figure 1 represents the differential LNA basic circuit. Each of the halves of the differential amplifier are
actually a single LNA which were designed earlier in this paper (ie with a 50ohm input impedance set by making
gm = 20mS), with the degenerating inductors (Ls) connected together at the „virtual earth‟, as shown in the
picture. At this time, the source of the current is attached to the negative supply which is set to provide twice the
current which is flowing down one of the sections of the LNA. Figure 2 represents ADS schematic showing the
differential LNA. Bear in mind that a differential signal should be supplied to each LNA input. An „ideal‟ Balun
(balanced to unbalanced) transformer has been applied here (also two AC sources could be applied each set to
0.5V and opposite polarity). Another balun is used on the amplifier output too, in order to re-combine the signal
to let the voltage gain to be simulated.
Applying differential structure was restricted to the low frequency applications for several years. As compared
to single-ended topologies, differential structures are of the following advantages :
Insensitivity to noise and interference coupled through supply lines and substrate.
The potential for using many linearization methods used for Tran conductance stages for low noise
amplifiers using this approach.
Smaller even-order distortion.
The schematic of differential LNA structure is shown in Fig 2, and the result which includes S-parameter
(Gain, impedance matching) and noise figure is shown in Figures 3 to 8. Gain between 2.1-3.7 GHz above 10 dB
and noise figure 2-3.5 GHz below 2.
21
3. C band HBT Differential Low Noise Amplifier for active functions at microwaves
Figure 2. Shamanic of Differential LNA
20
10
0
dB(S(2,2))
dB(S(2,1))
dB(S(1,2))
dB(S(1,1))
-10
-20
-30
-40
-50
-60
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0 freq, GHz
Figure 3. S-Parameteri of Differential LNA vs frequency
40
35
30
dB(S(2,1))
25
20
m2
m2 freq=3.000GHz
15
dB(S(2,1))=13.571
10
5
0
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
freq, GHz
Figure 4. S21 of Differential LNA vs frequency
2
0
m5
-2 freq=3.000GHz
dB(S(1,1))
-4
dB(S(1,1))=-10.477
-6
-8
m5
-10
-12
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
freq, GHz
Figure 5. input impedance matching of Differential LNA vs frequency
22
4. C band HBT Differential Low Noise Amplifier for active functions at microwaves
0
-5 m4
dB(S(2,2))
freq=3.000GHz
-10 dB(S(2,2))=-16.773
-15 m4
-20
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
freq, GHz
Figure 6. Output impedance matching of Differential LNA vs frequency
-35
-40
dB(S(1,2))
-45
-50
-55
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
freq, GHz
Figure 7. S12 of Differential LNA vs frequency
10
9
8
7
6 m1
nf(2)
5 freq=2.370GHz
4 nf(2)=0.929
3
2 m1
1
0
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
freq, GHz
Figure 8. Noise Figure of Differential LNA vs frequency
TABLE I. COMMPARE BETWEEN THIS PAPER AND REF [8]
Frequency(GHz) 1-3 2.6-
3.4
S21(dB) 9 11
S22(dB) -12 -10
S11(dB) -8 -10
Noise Figure(dB) 1.7 1-1.9
Power (mW) 46 35
Ref [8] This
work
IV. CONCLUSION
This paper gave the design of differential LNA by using advanced design system (ADS 2010). A design LNA
was given, with the associated step-by-step design process to meet a given specification. ADS simulations have
been given to predict the various circuit parameters of gain, noise figure and power consumption, all summarized
in Table 1.
23
5. C band HBT Differential Low Noise Amplifier for active functions at microwaves
REFERENCE
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[2] J.D. Cressler, "A new contender for Si-based RF and microwave circuit applications", IEEE Trans. on MTT, Invited Paper, vol. 46,
no.5, pp. 572-589, May 1998.
[3] D. Li, Y.Tsividis, "Active LC filters on silicon", IEE Proc.-Circuits Devices Syst., vol. 147, no. 1, February 2000.
[4] W.B. Khun, "Design of integrated, low power, radio receivers in BiCMOS technology", Dissertation presented to the faculty of the
Virginia Polytechnic Institute and State University, 1995.
[5] T.H Lee, “The Design of CMOS Radio Frequency Integrated Circuits”, Cambridge University Press, ISBN 0 521 63922 0, Chapter 2.
[6] C.S Kim, M Park, C-H Kim, Y C Hyeon, H K Yu, K Lee, K S Nam, “A fully integrated 1.9GHz CMOS Low-noise amplifier” in IEE
Microwave and guided wave letters, Vol 8, No 8 August 1998.
[7] T Soorapanth, T.H Lee, “RF Linearity of Short- Channel MOSFETs”, IEEE Journal of Solid State Circuits, vol. 32, no. 5, May 1997
[8] H. Bazzi, S. Bosse, L. Delage, B. Barelaud, L. Billonnet, B. Jarry, ‘Using HBT BiCMOS Differential Structures at Microwavesin SiGe
Technologies’ I.R.C.O.M.- UMR CNRS n 6615 – 87060 LIMOGES
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