This document describes a laboratory project to simulate a smart kitchen robot. The project involves designing a finite state machine and auxiliary circuits for the robot. The state machine has states like Idle, Cooking, Waiting for Ingredients. Microprogrammed design is used with Moore machine characteristics. Auxiliary circuits control recipe selection, step transitions, display output and motor speed. Block diagrams are provided for the state machine, registers, counters and other logic used.
Este documento descreve um trabalho sobre identificação de emoções em áudio usando parâmetros de entropia extraídos de amostras de voz. O documento discute os conceitos, métodos de extração de características, classificação proposta e testes realizados para identificar seis emoções primárias com taxas de acerto entre 5-85%.
Los árboles proporcionan muchos beneficios como frutas, oxígeno, regulación de la temperatura, prevención de la erosión y refugio para las aves, y embellecen el paisaje. El documento enfatiza la importancia de cuidar los árboles existentes y seguir plantando más árboles.
O documento descreve um curso técnico em publicidade que capacita estudantes a trabalhar com marketing, publicidade, propaganda e comunicação. Os alunos aprendem sobre criação de campanhas publicitárias, mídias digitais, design gráfico e pesquisa de mercado. O curso inclui aulas teóricas e práticas com equipamentos de ponta para que os alunos desenvolvam trabalhos reais. Ao concluir o curso, os alunos recebem um diploma de técnico em publicidade.
Situação de aprendizagem aparecida moreiraCiridinhaRP
Este documento apresenta uma situação de aprendizagem baseada no texto "Meu Primeiro Beijo", de Antonio Barreto. O texto narra a história do primeiro beijo do narrador com um colega de classe no ônibus da escola. A atividade propõe perguntas sobre o texto e sugere discussões interdisciplinares relacionando o tema do primeiro beijo a outras obras.
El Parkour no tiene límites, puede practicarse en espacios abiertos, al aire libre o en sitios cerrados, lo importante es estar bien entrenado y no sufrir riesgos innecesarios .
El documento resume la película "127 horas" sobre la historia real del alpinista Aron Ralston quien quedó atrapado en un cañón aislado en Utah por una roca que le aplastó el brazo. La película relata cómo Ralston debió sobrevivir durante 127 horas hasta que finalmente decidió amputarse el brazo con un cuchillo para liberarse y sobrevivir. El documento también menciona que el blogger de la autora incluye información sobre películas, novelas y gadgets como un reloj y el pronóstico del tiempo
Det här är ett läsförståelsematerial som vi använder med eleverna i åk 4, med lästräning och läsförståelse, som lägger grunden till goda resultat i alla ämnen.
Folk har trott på spöken i alla tider. Idag är det inte så många som tror på dem, därför att vi numera kan undersöka sådana saker. Jag säger till eleverna att det är ingen som någonsin har bevisat att spöken verkligen finns.
Este documento descreve um trabalho sobre identificação de emoções em áudio usando parâmetros de entropia extraídos de amostras de voz. O documento discute os conceitos, métodos de extração de características, classificação proposta e testes realizados para identificar seis emoções primárias com taxas de acerto entre 5-85%.
Los árboles proporcionan muchos beneficios como frutas, oxígeno, regulación de la temperatura, prevención de la erosión y refugio para las aves, y embellecen el paisaje. El documento enfatiza la importancia de cuidar los árboles existentes y seguir plantando más árboles.
O documento descreve um curso técnico em publicidade que capacita estudantes a trabalhar com marketing, publicidade, propaganda e comunicação. Os alunos aprendem sobre criação de campanhas publicitárias, mídias digitais, design gráfico e pesquisa de mercado. O curso inclui aulas teóricas e práticas com equipamentos de ponta para que os alunos desenvolvam trabalhos reais. Ao concluir o curso, os alunos recebem um diploma de técnico em publicidade.
Situação de aprendizagem aparecida moreiraCiridinhaRP
Este documento apresenta uma situação de aprendizagem baseada no texto "Meu Primeiro Beijo", de Antonio Barreto. O texto narra a história do primeiro beijo do narrador com um colega de classe no ônibus da escola. A atividade propõe perguntas sobre o texto e sugere discussões interdisciplinares relacionando o tema do primeiro beijo a outras obras.
El Parkour no tiene límites, puede practicarse en espacios abiertos, al aire libre o en sitios cerrados, lo importante es estar bien entrenado y no sufrir riesgos innecesarios .
El documento resume la película "127 horas" sobre la historia real del alpinista Aron Ralston quien quedó atrapado en un cañón aislado en Utah por una roca que le aplastó el brazo. La película relata cómo Ralston debió sobrevivir durante 127 horas hasta que finalmente decidió amputarse el brazo con un cuchillo para liberarse y sobrevivir. El documento también menciona que el blogger de la autora incluye información sobre películas, novelas y gadgets como un reloj y el pronóstico del tiempo
Det här är ett läsförståelsematerial som vi använder med eleverna i åk 4, med lästräning och läsförståelse, som lägger grunden till goda resultat i alla ämnen.
Folk har trott på spöken i alla tider. Idag är det inte så många som tror på dem, därför att vi numera kan undersöka sådana saker. Jag säger till eleverna att det är ingen som någonsin har bevisat att spöken verkligen finns.
El delfín mular es la especie más común en zoológicos y acuarios debido a su facilidad para adaptarse a la cautividad, pudiendo alcanzar los 3 metros de longitud. El boto es el delfín más pequeño que habita en aguas dulces y ha sido conocido por remontar 2000 km en el río Amazonas. En libertad, los delfines viven en manadas de hasta 100 ejemplares en mares templados y siguen a los barcos realizando piruetas que admiran a los observadores, alimentándose principalmente
La investigación es fundamental para el estudiante y para el profesional, esta forma parte del camino profesional antes, durante y después de lograr la profesión; ella nos acompaña desde el principio de los estudios y la vida misma.
Att undervisa i muntlig och skriftlig engelska språkfärdighetTina Forsberg
This document discusses teaching oral and written English language skills. It covers topics like English pronunciation, ideas for a 62-second speaking exercise, reading aloud, and providing feedback on speaking tests. The document expresses appreciation at the end.
This document discusses how technology is increasingly becoming a business enabler rather than just a cost center. It notes how cloud platforms allow businesses to focus on velocity and solving problems faster. It also discusses how user expectations are shaped by consumer technologies and how businesses want applications that provide seamless experiences like consumer apps. Finally, it talks about how IT leadership needs to focus on imagination and innovation rather than just migrating existing systems.
Este artículo discute las proyecciones de crecimiento de la población mundial, la cual alcanzará los 7,000 millones de personas en octubre de 2011. Se espera que la población mundial aumente a unos 10,000 millones de personas para finales de siglo, aunque a un ritmo más lento. Algunos expertos creen que este número podría ser menor debido a las tasas más bajas de fertilidad de lo esperado. Mientras tanto, África triplicará su población, e India reemplazará a China como el país más poblado
Este documento discute como lidar com parentes difíceis. Ele enfatiza a importância de perdoar, compreender e ter paciência com os parentes, mesmo quando eles não são amigos. Também sugere que as almas são colocadas juntas em famílias para terem a oportunidade de se reconciliar de vidas passadas.
Este documento describe un proyecto de aula para mejorar la ortografía y uso de signos de puntuación en estudiantes de tercero a quinto grado. El proyecto utilizará concursos, afiches, historietas y cuentos para motivar a los estudiantes de una manera lúdica y colaborativa mediante las TIC.
Call of Duty Black Ops presenta un modo historia durante las guerras de Vietnam donde sigues a Woods, y un modo zombis nazi donde controlas a John F. Kennedy u otros personajes históricos para enfrentarte a hordas de zombis. El modo multijugador permite desbloquear 15 niveles de prestigio al subir de nivel matando enemigos, y cuenta con varias armas de fuego como fusiles de asalto y automáticas con diferentes características de daño y alcance.
Este documento convida candidatos a participar de um processo seletivo para estagiários e assistentes de planejamento na JWT. Os candidatos devem escolher uma marca, analisar seu papel emocional e funcional para os consumidores, identificar um problema da marca e criar um brinquedo que represente a marca e solucione o problema, explicando como isso impactará os consumidores.
A JWT foi a agência mais premiada no Top of Mind da Folha de S.Paulo, com 7 clientes entre as marcas mais lembradas pelos brasileiros. Seu presidente Stefano Zunino atribui o sucesso à competência no marketing dos clientes e à contribuição da agência na comunicação fiel desse trabalho. A JWT conquistou prêmios como Top Grand Prix para a Nestlé e nas categorias de feminino, teen, chocolate, shampoo e sabonete.
Nick Maybury, Communications Manager, New Plymouth District Council
My Rates is an online tool developed for use alongside New Plymouth’s LTP consultation document. It was designed to show an individual ratepayer how the proposals in the plan affected the rates on ‘their property’. Nick will explain how the council developed the tool, how it fitted with the engagement New Plymouth did on the CD, and how it helped influence the overall results.
El documento describe cómo el iPhone ha mejorado la calidad de vida al facilitar el acceso a la información y la comunicación. El iPhone ayuda a encontrar información útil, establecer comunicación con otros a través de aplicaciones, y cumple funciones similares a un computador de manera fácil de usar. Sin embargo, también tiene limitaciones como su seguridad y eficiencia.
El documento habla sobre las Tecnologías de la Información y la Comunicación (TIC), incluyendo wikis, redes sociales, videos de la Web 2.0 y blogs personales. Explica que las TIC son el conjunto de tecnologías para gestionar, almacenar, enviar e información y procesar resultados. También discute las ventajas de las TIC como la interacción y el aprendizaje cooperativo, así como las desventajas como las distracciones y la pérdida de tiempo.
Manual dos combos Warwick BC 20 40 80 150 (PORTUGUÊS)Habro Group
Este manual fornece instruções sobre o uso de uma série de amplificadores compactos para baixo chamados Série BC da Warwick, descrevendo suas especificações técnicas, controles e instruções de segurança.
Uma família tenta fugir da destruição causada por homens misteriosos em Ragi. Eles matam a mãe e o pai na frente do filho Jimmy. Quando um dos homens ameaça matar Jimmy, ele é salvo, mas atira em Jimmy antes de partir, deixando a cidade em ruínas.
10 basics automatic mode control v1.00_enconfidencial
The document provides information about sequential function charts (SFC) in SIMATIC PCS 7, including:
1) SFCs are used for sequential control and allow advancing between states depending on conditions. They control functions like CFC charts via mode and state changes.
2) An SFC chart can include a maximum of 8 sequencers to represent different states of a sequential control system. Each sequencer can have 2-255 steps.
3) When a new sequencer is created in an SFC, it is inserted with an initial step, transition, and final step representing its initial state.
Applications of microcontroller(8051) vijaydeepakg
The document discusses various applications of microcontrollers including the 8051 microcontroller. It describes how microcontrollers can be used in mobile phones, automobiles, consumer electronics and more. It also provides examples of using microcontrollers to interface with displays like 7-segment LEDs and LCDs. Circuit diagrams and code are given to illustrate controlling stepper motors and reading input pins to control stepper motor direction.
The CX 2000 from Yokogawa is the next generation in process control. It combines recording, control and networking into a single, compact device ready to run on your process or OEM equipment. It delivers "Out of the box, ready to go" real-time and historical process monitoring. CX controls your process using internal PID loops and/or external controllers. One or more CXs link your process to the networked world with built-in Ethernet, web server, e-mail and FTP functions.
The experiment aims to design and test a daily production record system using a PLC. A sensor counts empty boxes on a conveyor and sends the count to the PLC. The PLC increments a counter and tracks the number of boxes against two batch targets of 10 and 20 boxes. When a batch is complete, an output turns on an indicator light. The counter can be reset after 24 hours to start a new daily record. The PLC logic uses contacts, counters, and comparators to track box counts and control output lights to monitor batch progress and completion.
Cataloge ge 3.control and_automation-20_vat300_e_c6-6-4_1_rev_bDien Ha The
This document describes various parameter functions for controlling the operation of an inverter drive.
It explains the settings for the run command method, run/stop methods, emergency stop logic and mode, control source switchover method, sequence input terminal functions, analog input terminal functions, auto start settings, parameter protection, operation panel functions, and analog input modes. Default settings and loading default values are also addressed.
The parameters provide options for remote control, stopping behavior, inputs, functions of terminals, startup settings, locking parameters from changes, display settings, and scaling analog inputs. Settings are selected using numeric codes for different control modes and behaviors.
El delfín mular es la especie más común en zoológicos y acuarios debido a su facilidad para adaptarse a la cautividad, pudiendo alcanzar los 3 metros de longitud. El boto es el delfín más pequeño que habita en aguas dulces y ha sido conocido por remontar 2000 km en el río Amazonas. En libertad, los delfines viven en manadas de hasta 100 ejemplares en mares templados y siguen a los barcos realizando piruetas que admiran a los observadores, alimentándose principalmente
La investigación es fundamental para el estudiante y para el profesional, esta forma parte del camino profesional antes, durante y después de lograr la profesión; ella nos acompaña desde el principio de los estudios y la vida misma.
Att undervisa i muntlig och skriftlig engelska språkfärdighetTina Forsberg
This document discusses teaching oral and written English language skills. It covers topics like English pronunciation, ideas for a 62-second speaking exercise, reading aloud, and providing feedback on speaking tests. The document expresses appreciation at the end.
This document discusses how technology is increasingly becoming a business enabler rather than just a cost center. It notes how cloud platforms allow businesses to focus on velocity and solving problems faster. It also discusses how user expectations are shaped by consumer technologies and how businesses want applications that provide seamless experiences like consumer apps. Finally, it talks about how IT leadership needs to focus on imagination and innovation rather than just migrating existing systems.
Este artículo discute las proyecciones de crecimiento de la población mundial, la cual alcanzará los 7,000 millones de personas en octubre de 2011. Se espera que la población mundial aumente a unos 10,000 millones de personas para finales de siglo, aunque a un ritmo más lento. Algunos expertos creen que este número podría ser menor debido a las tasas más bajas de fertilidad de lo esperado. Mientras tanto, África triplicará su población, e India reemplazará a China como el país más poblado
Este documento discute como lidar com parentes difíceis. Ele enfatiza a importância de perdoar, compreender e ter paciência com os parentes, mesmo quando eles não são amigos. Também sugere que as almas são colocadas juntas em famílias para terem a oportunidade de se reconciliar de vidas passadas.
Este documento describe un proyecto de aula para mejorar la ortografía y uso de signos de puntuación en estudiantes de tercero a quinto grado. El proyecto utilizará concursos, afiches, historietas y cuentos para motivar a los estudiantes de una manera lúdica y colaborativa mediante las TIC.
Call of Duty Black Ops presenta un modo historia durante las guerras de Vietnam donde sigues a Woods, y un modo zombis nazi donde controlas a John F. Kennedy u otros personajes históricos para enfrentarte a hordas de zombis. El modo multijugador permite desbloquear 15 niveles de prestigio al subir de nivel matando enemigos, y cuenta con varias armas de fuego como fusiles de asalto y automáticas con diferentes características de daño y alcance.
Este documento convida candidatos a participar de um processo seletivo para estagiários e assistentes de planejamento na JWT. Os candidatos devem escolher uma marca, analisar seu papel emocional e funcional para os consumidores, identificar um problema da marca e criar um brinquedo que represente a marca e solucione o problema, explicando como isso impactará os consumidores.
A JWT foi a agência mais premiada no Top of Mind da Folha de S.Paulo, com 7 clientes entre as marcas mais lembradas pelos brasileiros. Seu presidente Stefano Zunino atribui o sucesso à competência no marketing dos clientes e à contribuição da agência na comunicação fiel desse trabalho. A JWT conquistou prêmios como Top Grand Prix para a Nestlé e nas categorias de feminino, teen, chocolate, shampoo e sabonete.
Nick Maybury, Communications Manager, New Plymouth District Council
My Rates is an online tool developed for use alongside New Plymouth’s LTP consultation document. It was designed to show an individual ratepayer how the proposals in the plan affected the rates on ‘their property’. Nick will explain how the council developed the tool, how it fitted with the engagement New Plymouth did on the CD, and how it helped influence the overall results.
El documento describe cómo el iPhone ha mejorado la calidad de vida al facilitar el acceso a la información y la comunicación. El iPhone ayuda a encontrar información útil, establecer comunicación con otros a través de aplicaciones, y cumple funciones similares a un computador de manera fácil de usar. Sin embargo, también tiene limitaciones como su seguridad y eficiencia.
El documento habla sobre las Tecnologías de la Información y la Comunicación (TIC), incluyendo wikis, redes sociales, videos de la Web 2.0 y blogs personales. Explica que las TIC son el conjunto de tecnologías para gestionar, almacenar, enviar e información y procesar resultados. También discute las ventajas de las TIC como la interacción y el aprendizaje cooperativo, así como las desventajas como las distracciones y la pérdida de tiempo.
Manual dos combos Warwick BC 20 40 80 150 (PORTUGUÊS)Habro Group
Este manual fornece instruções sobre o uso de uma série de amplificadores compactos para baixo chamados Série BC da Warwick, descrevendo suas especificações técnicas, controles e instruções de segurança.
Uma família tenta fugir da destruição causada por homens misteriosos em Ragi. Eles matam a mãe e o pai na frente do filho Jimmy. Quando um dos homens ameaça matar Jimmy, ele é salvo, mas atira em Jimmy antes de partir, deixando a cidade em ruínas.
10 basics automatic mode control v1.00_enconfidencial
The document provides information about sequential function charts (SFC) in SIMATIC PCS 7, including:
1) SFCs are used for sequential control and allow advancing between states depending on conditions. They control functions like CFC charts via mode and state changes.
2) An SFC chart can include a maximum of 8 sequencers to represent different states of a sequential control system. Each sequencer can have 2-255 steps.
3) When a new sequencer is created in an SFC, it is inserted with an initial step, transition, and final step representing its initial state.
Applications of microcontroller(8051) vijaydeepakg
The document discusses various applications of microcontrollers including the 8051 microcontroller. It describes how microcontrollers can be used in mobile phones, automobiles, consumer electronics and more. It also provides examples of using microcontrollers to interface with displays like 7-segment LEDs and LCDs. Circuit diagrams and code are given to illustrate controlling stepper motors and reading input pins to control stepper motor direction.
The CX 2000 from Yokogawa is the next generation in process control. It combines recording, control and networking into a single, compact device ready to run on your process or OEM equipment. It delivers "Out of the box, ready to go" real-time and historical process monitoring. CX controls your process using internal PID loops and/or external controllers. One or more CXs link your process to the networked world with built-in Ethernet, web server, e-mail and FTP functions.
The experiment aims to design and test a daily production record system using a PLC. A sensor counts empty boxes on a conveyor and sends the count to the PLC. The PLC increments a counter and tracks the number of boxes against two batch targets of 10 and 20 boxes. When a batch is complete, an output turns on an indicator light. The counter can be reset after 24 hours to start a new daily record. The PLC logic uses contacts, counters, and comparators to track box counts and control output lights to monitor batch progress and completion.
Cataloge ge 3.control and_automation-20_vat300_e_c6-6-4_1_rev_bDien Ha The
This document describes various parameter functions for controlling the operation of an inverter drive.
It explains the settings for the run command method, run/stop methods, emergency stop logic and mode, control source switchover method, sequence input terminal functions, analog input terminal functions, auto start settings, parameter protection, operation panel functions, and analog input modes. Default settings and loading default values are also addressed.
The parameters provide options for remote control, stopping behavior, inputs, functions of terminals, startup settings, locking parameters from changes, display settings, and scaling analog inputs. Settings are selected using numeric codes for different control modes and behaviors.
Cataloge ge 3.control and_automation_dienhathe.com-4_20_vat300_e_c6-6-4_1_rev_bDien Ha The
This document describes various parameter settings for controlling functions and settings of an inverter drive. It explains the functions of parameters C00-0 through C13-1, which control run commands, stopping methods, sequence inputs, analog inputs, pulse train inputs, and more. Parameters can be set to select control logic, running modes, filtering, and default operation settings. Notes provide additional details on functional aspects like auto restart, emergency stopping, and protection of parameter changes.
This document defines the internal communication variables for controlling and monitoring the Altivar 28 variable speed drive using its RS485 serial link. It provides details on the DRIVECOM protocol standards used, including the definitions of bits in the control and status registers. It then lists and describes the general configuration, I/O configuration, and other parameter variables that can be read from and written to control the Altivar 28 drive.
The document describes the control and monitoring of the Altivar 28 variable speed controller using its internal serial communication variables. It defines the process using the serial link and lists the controller's internal variables. These include general configuration parameters, I/O configuration parameters, fault configuration parameters, adjustment parameters, control parameters, and monitoring parameters. It also summarizes the DRIVECOM communication standard and describes how the controller's status is represented and controlled via registers according to the standard.
This document describes interfacing an LCD display and keyboard to an 8051 microcontroller. It discusses connecting the LCD to output pins of the microcontroller to control the display. Commands are sent to initialize and update the LCD. A similar process of scanning rows and columns is used to interface a 4x4 keyboard matrix and detect which key is pressed by checking for a closed row and column. The document provides code examples to write characters to the LCD and scan the keyboard to identify pressed keys.
The document describes an automated bottle filling process that uses PLC automation. Key components include a SIEMENS PLC trainer, input signals like start/pause buttons and a photoelectric sensor, and output devices like a stepper motor conveyor belt. The system uses a state machine method with 3 binary digits to control the bottle filling, conveying, rejecting, and ejecting states. Programming is done using ladder logic and the SIEMENS TIA portal.
Lab 9 D-Flip Flops: Shift Register and Sequence CounterKatrina Little
This document describes an experiment involving designing a 4-bit shift register and sequence counter using D-flip flops. It includes building the circuits in an FPGA tool, simulating their operation, and downloading them to a development board. A debouncing circuit is added to prevent erroneous output from noisy button inputs. The objectives of introducing sequential circuit design and implementing a shift register and sequence counter are met.
The document discusses various topics related to microcontroller simulation and interfacing including:
1) A simulation represents a simpler model of a real situation that can be manipulated to determine experimental results. The document discusses using a simulator to show the effects of a given situation.
2) It describes Top View Simulator which simulates the popular 8-bit MCS 51 microcontroller family and includes windows to view the program, registers, memory, and other components.
3) Examples are given of interfacing microcontrollers with common devices like LEDs, LCDs, stepper motors, and 7-segment displays through programming and circuit diagrams.
This document describes experiments with analog to digital converters (ADCs) using an 8-bit and 10-bit converter to read voltage input and display the results on a 7-segment LED display. It provides algorithms and code for initializing the ADC, taking samples, and performing conversions to extract the digital values for display. Procedures are outlined for 8-bit and 10-bit conversions using interrupts or polling and arithmetic operations to handle the 10-bit values.
The document describes several programs written for microcontrollers to perform various tasks:
1) A program to convert packed BCD to ASCII and store the results in registers.
2) A program to display the text "SGBAU ME 1st" on an LCD screen using a microcontroller.
3) A program to multiplex the numbers 1, 2, 2, 4 on a four digit seven segment display using a microcontroller.
4) A program in GNUSim 8085 that performs all basic arithmetic operations like addition, subtraction, multiplication, and division on 8-bit numbers by loading values from memory locations and storing results back to memory locations.
5) A program to exchange
1. The document describes the design and implementation of a mod 6 direct down counter using J-K flip flops and the synchronous counters method.
2. The design exploits Karnaugh maps to determine the logic inputs for each J-K flip flop in order to minimize the logic functions.
3. The mod 6 down counter is implemented using Electronic Workbench software with 3 J-K flip flops that count synchronously from 5 to 0 on each clock pulse before repeating the cycle.
This document provides instructions for an electronics laboratory experiment on sequential systems. It includes:
1) An overview of the expected graduate profile and laboratory rules.
2) An explanation of sequential systems and how they differ from combinational systems.
3) Descriptions of up/down counters and how they work.
4) Instructions for building circuits with 555 timers and 193 and 404 logic chips to implement counters and observe their behavior.
Micro PLC_Manal for new comer plc learnerssuser6cedd3
This chapter provides an overview of the Micro PLC system. It describes the Micro PLC components, connectivity options to expansion modules and programming devices. Ordering information is also included to help with hardware selection. Specifically:
1. It describes the Micro PLC nomenclature and specifications.
2. It explains how to connect expansion modules, programming devices and MMIs to the Micro PLC.
3. It provides ordering information to assist with selecting the appropriate Micro PLC model and accessories.
This document discusses installation groups in SAP Utilities, which allow for data exchange between primary and secondary utility installations. It describes the customizing required to define installation group types, roles, and data exchange. An example billing scheme is provided where consumption from a secondary installation is transferred to the primary installation on billing. Various reports are also described to view installation group master data and billing documents.
Ch. 5 Control Task Basics 1 Chapter 5 Control Task Basi.docxaryan532920
Ch. 5 Control Task Basics 1
Chapter 5 Control Task Basics
Modeling the Control Task
Most verbal descriptions of a technical task are not effective in their scope and are unreliable and
not clear-cut. A technical sketch, on the other hand, is reliable but lacks description of the
human and therefore may miss important details. Several approaches are the usual best approach
to describing a process to be programmed. All these types of charts, descriptions, sketches, etc
are best in describing the engineering model. Even a mathematical equation is acceptable to help
the process.
The engineering model must be complete and exact. What is described must work in all
circumstances and under all conditions and produce a safe result (that also, in this world, must
make a profit).
A description of the engineering process may be described as follows:
Input (from customer) Phases Activities Output (to customer)
Inquiry Analysis
Problem Analysis
Requirement Analysis
Cost Calculation
Quotation
Order Design
Requirements
Definition/Design
Construction
Documents
Approval of Design
Documents
Implementation
Realization,
Production including
testing
Product
Delivery/Commissioning Installation
Erection in
operational
environment
Useable Facility
Acceptance
Commitment
Operation Service Customer benefits
Table 5-1 The Engineering Process
General steps in Logic/Control Engineering
1. Analysis of problem – getting a thorough understanding of the task, analyze the
behavior/function of the system
2. Design the
Solution
a. Hardware
b. Software – construct a model of the system which should be more precise as
verbal description (formal), a graphical representation of system solution,
independent from any technical implementation, allowing communication
between control and mechanical engineers
3. Implementation – just work, no creativity required (programmer shouldn’t be artist)
4. Test
5. Start up in Operational Environment
Ch. 5 Control Task Basics 2
Several methods exist to describe a technical task. Some are more closely linked to the technical
implementation such as Ladder Logic, Function Block Diagram, and a procedural language such
as C or C++. It is always advisable to start with a drawing of the process with the inputs and
outputs shown. A formal drawing may be prepared - referred to as a P&ID - to describe a
process or an informal drawing such as the one below may be used.
The Juice Condenser
V-2
High Level
Half Level
V-1
Temperature Sw
Agitator
Heat
Start
Done/Ready
Fig. 5-1 The Juice Maker
A description of the above process is as follows:
For saving transportation cost for apple juice, the juice is condensed in a process of evaporation.
The water is evaporated in the tank using heat. The process of the process includes the following
steps:
1. Operator pushes the start pushbutton.
2. Valve V-2 opens ...
This document discusses timers and interrupts on the ATmega328 microcontroller. It describes the digital I/O pins and functions for controlling them. It then covers the different types of interrupts including external interrupts from pins and pin change interrupts. The rest of the document details the timer/counter units 0, 1, and 2, including their registers, modes, and how to configure interrupts from timer events.
1. SISTEMAS DIGITAIS
LABORATÓRIO V
ROBOT DE COZINHA
André Cristóvão Neves Ferreira Nº 81715
Miguel João Vaz Nº81625
Turno: SD45L13
Docente Responsável: Helena Aidos
11/12/2014
e
18/12/2014
Quinta-feira Sala LSD1
2. SISTEMAS DIGITAIS
2014-2015, MEEC
2 | P á g i n a
1. INTRODUÇÃO
Com a seção de laboratório L5, dividida na semana 1 e na semana 2, existe o objetivo
de simular o funcionamento de um robot de cozinha, testando principalmente os
conhecimentos sobre máquinas de estados microprogramadas e com memórias ROMe
RAM, abordando como não podia deixar de ser outros aspetos mais simples lecionados
ao longo da disciplina de Sistemas Digitais.
Como projeto desejado possuía-se um robot de cozinhaque incluísse um modo de 9
receitas pré-programadas (ver Anexo A), cada uma dividida em etapas, assimcomo um
modo manual. Desejava-se ainda que a máquina de estados deste robot apresentasse,
pelo menos, os estados:
Idle;
Cooking;
Waiting Ingredient;
Setup Time (modo manual);
Setup Speed (modo manual).
2. PROJETO DA MÁQUINA DE ESTADOS
A máquina de estados foi pensada na forma de microprogramação explícita, visto que
simplifica a tabela da ROM (tabela com dimensões inferiores) comparativamente tanto
à forma simples (entradas entram na tabela) como à microprogramação implícita
(necessitar-se-ia talvez de mais estados transitórios e de maior número de bits que
codificam cada estado).
Sendo uma máquina microprogramada com as entradas ligadas a um multiplexer em
vez de à ROM, definindo apenas qual o estado seguinte, sabe-se que esta é
obrigatoriamente do tipo Moore, tendo em conta que as entradas não influenciam as
saídas.
Figura 1 – Diagrama da máquina de estados do robot de cozinha
REGISTO
4-bits
din
clk
dout4 4
ROM
E
Teste
4
3
MUX
ManualMode
Start
Cancel
FimdeEtapa
FimdeReceita
EsperaIngrediente
MUX
4
4
ES1
ES0
fast_clock
1
0
1
G 0
7
G
0
1
1
0 1 2 3 4 5 6 7
3. SISTEMAS DIGITAIS
2014-2015, MEEC
3 | P á g i n a
No planeamento do diagrama de estados, ao considerarem-se apenas os estados
iniciais Idle, Cooking, Waiting Ingredient, Setup Time e Setup Speed, verificou-se que
existiamum vasto número de ligações, envolvendo dependências de várias entradas do
circuito ao mesmo tempo. Isto impossibilitaria o recurso a uma máquina
microprogramada, independentemente de serimplícita ou explícita.De forma a resolver
este problema, foram sendo colocados diversos estados considerados transitórios cuja
função é simplesmente de conectar de uma maneira mais simples os estados principais
referidos anteriormente. Foi ainda realizada uma divisão do estado Cooking em Cooking
Recipe e Manual Cooking, sendo cada um a sua representação na fase das receitas
predefinidas e na fase manual, respetivamente.
Para melhor análise à figura do diagrama de estados, atente à tabela 1 que refere qual
a entrada representada na numeração existente junto a cadaseta de ligaçãode estados.
Manual Mode Start Cancel Fim de Etapa Fim de Receita Espera Ingrediente
X X X X X X
0000 0001 0010
1101
1100
1010
1011
0011
0100
0101
0110
0111
1000
1001
1-----
0-----
-1----
-0----
0-----
1-----
1-----
1-----
0-----
-1----
-1----
-1----
-1----
-0----
-0----
-0----
--1---
--0--- -0----
-1----
0-----
1110
---1--
---1--
---0--
---0--
----1- ----0-
-----1
-----0
Idle
Cooking
Recipe
Waiting
Ingredients
Setup
Speed
Setup
Time
Manual
Cooking
-0----
Tabela 1 – Legenda do diagrama de estados
Figura 2 – Diagrama de estados do robot de cozinha
4. SISTEMAS DIGITAIS
2014-2015, MEEC
4 | P á g i n a
E(3) E(2) E(1) E(0) ES0(3) ES0(2) ES0(1) ES0(0) ES1(3) ES1(2) ES1(1) ES1(0) Teste2 Teste1 teste0
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
0 0 0 1 0 0 1 0 0 0 0 1 0 0 1
0 0 1 0 1 1 0 1 0 0 1 1 0 0 0
0 0 1 1 0 1 0 0 0 0 1 1 0 0 1
0 1 0 0 0 0 1 0 0 1 0 1 0 0 0
0 1 0 1 0 1 0 0 0 1 1 0 0 0 1
0 1 1 0 0 1 1 1 0 1 0 0 0 1 0
0 1 1 1 0 1 1 0 1 0 0 0 0 0 1
1 0 0 0 0 0 1 0 0 1 0 0 0 0 0
1 0 0 1 0 0 1 0 0 1 0 0 0 0 0
1 0 1 0 1 1 0 0 1 0 1 1 1 0 1
1 0 1 1 1 0 1 1 1 1 0 0 0 0 1
1 1 0 0 1 0 1 0 1 1 1 0 0 1 1
1 1 0 1 0 0 1 0 1 1 0 0 0 0 1
1 1 1 0 1 1 0 0 0 0 1 0 1 0 0
3. PROJETO DOS CIRCUITOS AUXILIARES
A execução do robot de cozinha não se resume à máquina de estados. Existemoutros
circuitos, dependentes do estado atual e de certas entradas, que foram necessários
implementar de forma a obter-se os comportamentos desejados. Esses circuitos
auxiliares são:
Seleção da receita desejada (no estado Idle);
Transição de etapas (no estado Cooking Recipe);
Escolha do tempo de etapa manual (no estado Setup Time);
Escolha da velocidade de hélice durante etapa manual (no estado Setup
Speed);
Comportamento dos leds;
Números no display (possui várias hipóteses para estados diferentes);
Velocidade da hélice.
Deve-se mencionar que algumas partes dos circuitos auxiliares utilizados,
nomeadamente o bcd_updown_counter, o decimal_updown_counter, o relógio e o
fullseq, foram fornecidas pelos docentes responsáveis pela disciplina de Sistemas
Digitais, encontrando-se os seus diagramas lógicos representados na página posterior,
antecedendo as representações completas dos circuitos auxiliares.
Tabela 2 – Tabela de transição de estados; ES0 é o estado seguinte quando a entrada de que a transição depende vale 0;
ES1 é o estado seguinte quando a entrada de que a transição depende vale 1.
5. SISTEMAS DIGITAIS
2014-2015, MEEC
5 | P á g i n a
BCD
UP/DOWN
COUNTER
A(3:0)
4
A(3:0)
opop
en
en_next
en
BCD
UP/DOWN
COUNTER
A(7:4)
4
A(3:0)
op
en
en_next
Y(3:0)
4
Y(7:4)
4
Y(3:0)
Y(3:0)
en_out(0)
en_out(1)
BINARY
COMPARATOR
WITH 00h
(8-bit NAND GATE)
BINARY
COMPARATOR
WITH 59h
(8-bit NAND GATE)
8
8
is_min
op
is_max
op
saturate_down
saturate_up
Y(7:0) 0
1
S8
8
8A(7:0)
saturate
Geraçãodocarry
para opróximo
digito(décimal)
Digito(decimal)
menos significativo
Digito(decimal)
mais significativo
A(7:0)
A(7:0)
FULL
ADD/SUB op
opA(0)
C(1)
FULL
ADD/SUB
opA(1)
C(2)...C(3)
FULL
ADD/SUB
opA(3)
C(4)
Y(3) Y(1) Y(0)
A(i) op
Ya(i)Yb(i)
C(i)
Y(i)
Cc(i)C(i)
FULL ADD/SUB4-bit BINARY INC/DEC
4-bit
BINARY
INC/DEC
BINARY COMPARATOR
WITH 0h
(4-bit NAND GATE with
inputs 0,1,2,3 inverted)
BINARY COMPARATOR
WITH 9h
(4-bit NAND GATE with
inputs 1,2 inverted)
A
4
4
4
Amin
op
Amax
op
Sel(0)
Sel(1)
0
4
4
Y
A
opop
A
A
2
Sel(1:0)
1
2
3
4
4
1001
0000
en_next
0
1
S
A
en
4
4auxS
4
en
en
REGISTO
20-bits
20
1,2D
C1clk
cnt
20
Q
INITreset
G2
hold
(coloca o valor
a d1ceeh)
cnt_next
BINARY
COMPARATOR
WITH 00000h
(20-bit NOR GATE)
cnt_zero
1
0
cnt_next
20
20-bit BINARY DECREMENTER
cnt(0)cnt(1)cnt(2)
...
cnt(18)cnt(19)
20-bit BINARY
DECREMENTER
cnt_m1
20
d1cee(16)
hold en_64
REGISTO
6-bits
6
1,2D
C1clk
Q
SETreset
G2
6-bit BINARY DECREMENTER
cnt64(1)
...
6
(coloca o valor
a 111111)
cnt64_next
cnt64
cnt64(0)cnt64(2)cnt64(5)
6-bit BINARY
DECREMENTER
cnt64 cnt64_nxt
borrow64(0)
borrow64(0)borrow64(1)borrow64(2)borrow64(5)
borrow64(1)
borrow64(2)
borrow64(3)
borrow64(4)
borrow64(5)
t64
hold
cnt_zero
t16
hold
t8
hold
t1
Necessita deum registode20
bits, já querealiza a divisãodo
periododerelógiodiretamentea
partir dofast_clock (55MHz)
fullseq
B
clk
Q
8
8
INI
EN
Figura 3 – Diagrama lógico de bcd_updown_counter à esquerda e fullseq à direita
Figura 4 – Diagrama lógico de decimal_updown_counter
Figura 5 - Diagrama lógico de Relógio
6. SISTEMAS DIGITAIS
2014-2015, MEEC
6 | P á g i n a
FimdeEtapa e FimdeReceita são duas entradas da máquinas de estado que não são
associadas a botões físicos mas sima sinais dos circuitos auxiliares. Existe ainda o sinal
transcooking (ativo perante a presença de condições para a máquina de estados
transitar para o estado Cooking Recipe) que é importante para alguns circuitos.
T(7)
T(6)
T(5)
T(4)
T(3)
T(2)
T(1)
T(0)
Fi mdeEtapa
E(3)
E(2)
E(1)
E(0)
E(3)
E(2)
E(1)
E(0)
R(3)
R(2)
R(1)
R(0)
R(3)
R(2)
R(1)
R(0)
R(3)
R(2)
R(1)
R(0)
R(3)
R(2)
R(1)
R(0)
R(3)
R(2)
R(1)
R(0)
R(3)
R(2)
R(1)
R(0)
R(3)
R(2)
R(1)
R(0)
R(3)
R(2)
R(1)
R(0)
R(3)
R(2)
R(1)
R(0)
EsperaIngrediente
transcooki ng
Start
Start
E(3)
E(2)
E(1)
E(0)
E(3)
E(2)
E(1)
E(0)
E(3)
E(2)
E(1)
E(0)
E(3)
E(2)
E(1)
E(0)
et(3)
et(2)
et(1)
et(0)
Fi mdeReceita
Figura 6 – Diagrama lógico de sinais importantes para máquina de estados (FimdeEtapa e FimdeReceita)
e para circuitos auxiliares (transcooking)
7. SISTEMAS DIGITAIS
2014-2015, MEEC
7 | P á g i n a
Para a seleção da receita pretendida, que é efetuada com recurso aos botões up e
down, foram usados um bcd_updown_counter (que realiza as contas de soma e de
subtração desejadas) e um registo (que memoriza o número de receita selecionado
atualmente). Este circuito, tal como é referido no enunciado, apenas seria ativo durante
o estado Idle.
O circuito elaborado para a função de mudança de etapas envolve dois registos, um de
quatro bits e outro de oito bits, um bcd_updown_counter, um
decimal_updown_counter e dois multiplexers, um de cinco bits de seleção e outro de
dez. A representação das etapas encontra-se invertida, querendo com isto dizer que, ao
longo da receita, as etapas transitam para etapas codificadas por um número inferior,
até se atingir a etapa zero, que será a etapa final seja qual for a receita previamente
selecionada. Por exemplo, se a etapa atual estiver codificada com o valor três, ao fim de
o tempo dessa etapa, considerando a passagempara a próxima de forma automática, o
código da etapa em que seencontraria o robot seria dois.Estarepresentação das etapas
simplifica um circuito auxiliar relacionado com os displays, visto que uma das opções
para o que seria mostrado nos displays é precisamente o número de etapas restantes
(na representação escolhidao número de cadaetapa é igualanº total de etapas – ordem
cronológica da etapa atual). Com este método, torna-se claro que pretende-se que o
bcd_updown_counter, que decide qual o código da etapa seguinte, apenas realize a
operação de decrementar.
Como o número máximo de etapas na lista de receitas (Anexo A) é 8(10), que
corresponde a 1000(2), o registo necessariamente implementado para armazenar o
número de etapa possui quatro bits.
É preciso ter em consideração qual é que é a etapa inicial de cada receita assim como
em que circunstancias é que essa etapa é introduzida no registo. Para este efeito,
desenvolveu-se um multiplexer cujas entradas de seleção são o número da receita e um
sinal que se ativa quando ocorre uma transição na máquina de estados para o estado
Cooking Recipe.
Figura 7– Diagrama de selecionar receita
bcd_updown_counter
A
en
op
S 4
en_next
4A
op
en
Cout
en_next
REGISTO
4-bits
din
clk
dout
up
4 4
R
op
up
down
down
fast_clock
8. SISTEMAS DIGITAIS
2014-2015, MEEC
8 | P á g i n a
A sequência das etapas de cada receita, como é lógico, depende do tempo de cada
etapa. Ou seja, uma certa etapa só termina quando, contando o tempo após se ter
inicializado, decorrer por completo o tempo de etapa predefinido. Seguindo este
raciocínio, adicionou-se um registo de oito bits (quer-se representar o tempo por dois
nibbles, um para cada digito decimal), um decimal_updown_counter (que só
decrementa pois pretende-se descobrir quando é que o tempo de etapa chega a zero) e
outro multiplexer (que seleciona quando e que valor de tempo forçar no registo de oito
bits).
Por fim, obteve-se o circuito da figura 7.
O enunciado de laboratório menciona que os leds devem ser ativos conforme a
sequência elaborada nos laboratórios anteriores, alterando apenas a velocidade da
sequência proporcionalmente à velocidade atual da hélice do robot de cozinha. Existe
ainda a informação de que se pretende utilizar um contador para este efeito, contador
esse que iria contar sucessivamente ao longo da etapa desde o valor da velocidade da
hélice (compreendido entre 0 e 15) e 15, retornando a fazer a mesma contagem após
chegar a este número final.
Visto que a velocidade da hélice tem um valor com até dois dígitos decimais,
aproveitou-se o mesmo género de codificação já usado no tempo de etapa que consiste
em representar o valor em BCD (Binary Coded Decimal), ou seja, um nibble(4 bits) por
cada digito decimal.
Neste caso, optou-se que os leds só reproduzissem a sequência quando a máquina de
estados se encontrasse num estado de Cooking (Cooking Recipe ou Cooking Manual),
desativando-se completamente durante os restantes estados.
Figura 8– Diagrama de transição de etapas
bcd_updown_counter
A
en
op
S 4
en_next
4 ese
en_next
REGISTO
4-bits
din
clk
dout4 4
ese
1
REGISTO
8-bits
din2
clk
dout28 8
et
Cout2 T
enet
decimal_updown_counter
A
en
op S 8
8
Cout21
enT
fast_clock
MUX
0
1
2
3
0
1
G
0
3
MUX
0
1
1
2
G
0
32
et
0011
0001
Sele(0)
Sele(1)
Sele(2)
Sele(3)
Sele(4)
4
8
16
0000
0100
0101
0110
1000
0111
0010
es
.
..
17
16
18
19
20
21
22
23
24
25
26
.
..
32
MUX
0
1
2
3
0
G
0
3
MUX
32
64
1
2
G
0
512
TSeleT(4)
4
8
16
256
128
512
SeleT(0)
SeleT(1)
SeleT(2)
SeleT(3)
SeleT(8)
SeleT(5)
SeleT(6)
SeleT(7)
SeleT(9)
Sele(0) Sele(1) Sele(2) Sele(3) Sele(4)R(0) R(1) R(2) R(3) transcooking
SeleT(4)
SeleT(0) SeleT(1) SeleT(2)
SeleT(3)
SeleT(8)
SeleT(5)
SeleT(6) SeleT(7)
SeleT(9)
et(0) et(1) et(2)
et(3)et(3)
FimdeEtapa
transcooking
R(0) R(1)
R(2) R(3)
(VerVHDL
páginas
44-48)
9. SISTEMAS DIGITAIS
2014-2015, MEEC
9 | P á g i n a
Através de uma estrutura e organização semelhante ao circuito de seleção de receita,
obtém-se o circuito de seleção do tempo de etapa manual. A principal diferença reside
na substituição do bcd_updown_counter por um decimal_updown_counter.
O circuito da velocidade de hélice em modo manual é estruturalmente idêntico ao da
seleção do tempo de etapa manual, diferindo apenas nos nomes dos fios e na
determinação do enable.
Figura 9 – Diagrama de ativação dos leds
REGISTO
8-bits
din
clk
dout8 8
Cout A
decimal_updown_counter
A
en
op S 8
8
Cout
op
enM
fast_clock
T Cout
op
up
down
down
up
E(3)
E(2)
E(1)
E(0)
Start
enMT
Figura 10 – Diagrama de seleção de tempo de etapa manual
REGISTO
8-bits
din
clk
dout8 8
Vme A
decimal_updown_counter
A
en
op S 8
8
Vme
op
enMV
fast_clock
Vm Vme
op
up
down
down
up
E(3)
E(2)
E(1)
E(0)
Start
enMV
Figura 11 – Diagrama de seleção de velocidade de hélice de etapa manual
REGISTO
8-bits
din
clk
dout8 8
B
dout
decimal_updown_counter
A
en
op S 8
8
B0
EN
fast_clock
0
G
3
MUX
1
0
G
0
1
A
1
c15
ENseq c15
fullseq
B
clk
Q
8
8
INI
EN
0
ENseq
00000000
ledcooking
8
8
8
V
E(0)
E(1)
E(3)
B(7)
B(6)
B(5)
B(4)
B(3)
B(2)
B(1)
B(0)
c15
cooking
0
G
3
MUX
1
0
G
0
1
1
cooking
8
8
8
ledcooking
00000000 led
10. SISTEMAS DIGITAIS
2014-2015, MEEC
10 | P á g i n a
No display pode ser apresentado o tempo restante até ao fim da etapa, a velocidade
da hélice, o tempo restante até ao fim da receita, o número de etapas da receita
restantes (sendo estas primeiras quatro hipóteses selecionadas pelos interruptores Sel1
e Sel0), o tempo a escolher para a etapa manual, a velocidade da hélice a escolher para
a etapa manual ou a receita a escolher no estado Idle. Tendo em conta estas
informações, pareceu natural implementar um multiplexer que selecionaria qual das
opções apareceria no display.
Implementou-se ainda um circuito que define a velocidade da hélice do robot de
cozinha, tanto na fase das receitas como na fase manual (engloba a saída Vmdo circuito
que permite escolher a velocidade no modo manual). Necessitaram-se para este efeito
de dois multiplexers, um que contém as velocidades de hélice predefinidas de cada
etapa das receitas e outro que escolhe se a velocidade é a das receitas (estado Cooking
Recipe), a manual (estado Manual Cooking) ou se é zero (todos os outros estados).
Figura 12 – Diagrama lógico de display
0
G
15
MUX
1
0
G
0
15
dispe
1
Seldisp(0)
11
11
11
Seldisp(1)
Seldisp(2)
2
4
2
3
11
11
4
5
11
11
6
7
11
11
T11
V11
TL
et11
R11
dispedisp
Sel(0)Seldisp(0)
Sel(1)Seldisp(1)
IdleSeldisp(2)
Idle
E(3)
E(2)
E(1)
E(0)
Seldisp(3)
Seldisp(4)
11
11
11
11
11
11
11
11
8
9
10
11
12
13
14
15
Vm11
Tm11
SetupSpeedSeldisp(3)
Seldisp(4) SetupTime
E(3)
E(2)
E(1)
E(0)
SetupSpeed
E(3)
E(2)
E(1)
E(0)
SetupSpeed
5
6
(TL ver
VHDL
páginas
44-48)
MUX
0
1
2
3
0
1
G
0
3
MUX
0
1
1
2
G
0
7
Ve
E(0)
E(1)
E(2)
E(3)
4
8
3
2
4
5
6
7
8
9
10
11
12
13
MUX
0
1
2
5
0
G
0
3
MUX
32
64
1
2
G
0
511
VrSeleVr(4)
4
8
16
256
128
.
.
.
SeleVr(0)
SeleVr(1)
SeleVr(2)
SeleVr(3)
SeleVr(8)
SeleVr(5)
SeleVr(6)
SeleVr(7)
14
15
Vr
Vm
00000000
E(3)
E(2)
E(1)
E(0)
CookingRecipe
SeleVr(0) et(0) SeleVr(1) et(1)
SeleVr(2) et(2) SeleVr(3) et(3)
SeleVr(4) R(0) SeleVr(5) R(1)
SeleVr(6) R(2) SeleVr(7) R(3)
SeleVr(8) CookingRecipe
(VerVHDL
páginas 34-35)
Figura 13 – Diagrama lógico da velocidade da hélice
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4. FUNCIONAMENTO DO CIRCUITO
Como se pode verificar na figura 7, a simulação da máquina de estados decorre como
era espectável, tanto na fase de receitas como a transitar para a fase manual. Isto
verifica-sepois,no estado “0000”, apenas transita para “0001”quando ManualMode=0,
depois para “0010” quando Start=0, para “1101” quando ManualMode=0, para “1100”
quando Start=1, para “1010” quando FimdeEtapa=0, para “1011” quando
EsperaIngrediente=1, para “1100” quando Start=1, para “1110” quando FimdeEtapa=1,
para “0010” quando FimdeReceita=1 e para “0011” quando ManualMode=1.
5. CONCLUSÕES
Apesar da não execução do teste do circuito na placa BASYS2, consideramos que o
trabalho foi desenvolvido com qualidade e terá sido certamente um grande passo em
frente em termos de aprendizagem de sistemas digitais. Verificou-se de facto que as
memórias ROM, principalmente no caso de máquinas programadas, têm a capacidade
de simplificarde forma significativaproblemas complexos. Porém, tal como seaprendeu
nas aulas teóricas, convêm em algumas situações analisar se pretende-se de fator
utiliza-las em vez de lógica combinatória, visto que embora exista um acréscimo de
complexidade e de esforço necessário para implementar circuitos com portas lógicas
tradicionais, estaopção é geralmente a mais rápida (menor tempo de propagação) e por
vezes a mais eficiente em termos energéticos e até monetários.
Observando o que poderão ser possíveis aspetos a melhorar para futuros trabalhos,
talvez apenas o da programação em Xilinx, em que se verificou por vezes alguma
ineficácia e falta de rapidez em produzir códigos VHDL sem erros, e a gestão do tempo.
Figura 14– Simulação da máquina de estados
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ANEXO B
Endereço Dados
0h 0001000000000000
1h 0010000100100000
2h 1101001100000000
3h 0100001100100000
4h 0010010100000000
5h 0100011000100000
6h 0111010001000000
7h 0110100000100000
8h 1000100101100000
9h 0010010000000000
Ah 1100101110100000
Bh 1011110000100000
Ch 1010111001100000
Dh 0010110000100000
Eh 1100001010000000
Fh 0000000000000000
Números aleatórios usados para fazer com que o nº de dados seja uma potência de 2.
Ao endereço Fh, que se encontra fora do interesse para este caso, foram atribuído
como dados “00000000000” sendo que, apesar dos três bits menos significativos serem
aleatórios, os oito bits mais significativos foram considerados como “0” para evitar
estados lock-out (se a máquina de estados transitar para o estado Fh, esta transitará de
seguida para 0h, regressando para a sequência de estados desejada).
8 5 190 10 7 Automático
8 4 180 30 10 Automático
8 3 150 10 5 Automático
8 2 140 60 10 Espera ingrediente
8 1 80 60 7 Espera ingrediente
8 0 20 20 7 Automático
9 2 140 20 10 Espera ingrediente
9 1 120 20 15 Espera ingrediente
9 0 100 100 5 Automático
Tabela 3 – Lista de receitas e respetivos detalhes
Tabela 4 – Dados da memória ROM
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ANEXO C
De seguida encontram-se os códigos VHDL na respetiva ordem:
MaquinadeEstadosBimbi;
MaquinadeEstadosBimbi_testbench;
SelectReceita;
heliceleds;
countetapas;
helicespeed;
display;
ManualT;
ManualV;
ReceTimeLeft;
RobotCompleto;
ROM.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MaquinadeEstadosBimbi is
Port ( clk : in std_logic;
ManualMode : in std_logic;
Start : in std_logic;
Cancel : in std_logic;
FimdeEtapa : in std_logic;
FimdeReceita : in std_logic;
EsperaIngrediente : in std_logic;
ES0 : out STD_LOGIC_vector(3 downto 0);
ES1 : out STD_LOGIC_vector(3 downto 0);
ES : out std_logic_vector(3 downto 0);
Teste : out STD_LOGIC_vector(2 downto 0)
);
end MaquinadeEstadosBimbi;
architecture Behavioral of MaquinadeEstadosBimbi is
component rom_memory1
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Port (
address : in STD_LOGIC_VECTOR (3 downto 0);
data : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
signal X : std_logic_vector(4 downto 0);
signal din, dout, ES0e, ES1e, ESe, Ee, E : std_logic_vector(3 downto 0);
signal TesteIN : std_logic_vector(2 downto 0);
signal Xe : std_logic_vector(15 downto 0);
signal Ote : std_logic;
--"Ote" é a saída do multiplexer da máquina de estados micro-programada
explícita que é a entrada selecionada por Teste
begin
--Registo da máquina de estados
dout <= din when rising_edge(clk);
E <= dout;
din <= ESe;
rom1 : rom_memory1 Port Map(
address(3 downto 0) => E(3 downto 0),
data(15 downto 0) => Xe
);
--Multiplexer que seleciona a entrada desejada
Ote <= ManualMode when TesteIN="000" else
Start when TesteIN="001" else
Cancel when TesteIN="010" else
FimdeEtapa when TesteIN="011" else
FimdeReceita when TesteIN="100" else
EsperaIngrediente when TesteIN="101" else
ManualMode;
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--Multiplexer que seleciona o estado seguinte
ESe <= ES0e when Ote='0' else
ES1e;
Xe(4 downto 0) <= "00000";
TesteIN <= Xe(7 downto 5);
ES1e <= Xe(11 downto 8);
ES0e <= Xe(15 downto 12);
Teste <= TesteIN;
ES0 <= ES0e;
ES1 <= ES1e;
ES <= ESe;
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY MaquinadeEstadoBimbi_testbench IS
END MaquinadeEstadoBimbi_testbench;
ARCHITECTURE behavior OF MaquinadeEstadoBimbi_testbench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MaquinadeEstadosBimbi
PORT(
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clk : IN std_logic;
ManualMode : IN std_logic;
Start : IN std_logic;
Cancel : IN std_logic;
FimdeEtapa : IN std_logic;
FimdeReceita : IN std_logic;
EsperaIngrediente : IN std_logic;
ES0 : OUT std_logic_vector(3 downto 0);
ES1 : OUT std_logic_vector(3 downto 0);
ES : OUT std_logic_vector(3 downto 0);
Teste : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
--Inputs
signal E : std_logic_vector(3 downto 0) := "0000";
signal ManualMode : std_logic := '1';
signal Start : std_logic := '1';
signal Cancel : std_logic := '0';
signal FimdeEtapa : std_logic := '0';
signal FimdeReceita : std_logic := '0';
signal EsperaIngrediente : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal ES0 : std_logic_vector(3 downto 0);
signal ES1 : std_logic_vector(3 downto 0);
signal ES : std_logic_vector(3 downto 0);
signal Teste : std_logic_vector(2 downto 0);
-- Clock period definitions
constant clk_period : time := 15 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MaquinadeEstadosBimbi PORT MAP (
clk => clk,
ManualMode => ManualMode,
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Start => Start,
Cancel => Cancel,
FimdeEtapa => FimdeEtapa,
FimdeReceita => FimdeReceita,
EsperaIngrediente => EsperaIngrediente,
ES0 => ES0,
ES1 => ES1,
ES => ES,
Teste => Teste
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 40 ns;
ManualMode <= '0';
wait for 155 ns;
ManualMode <= '1';
wait for 200 ns;
ManualMode <= '0';
wait;
end process;
start_proc: process
begin
wait for 40 ns;
Start <= '0';
wait for 30 ns;
Start <= '1';
wait for 170 ns;
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Start <= '0';
wait for 180 ns;
Start <= '1';
wait for 240 ns;
Start <= '0';
wait;
end process;
esperaingredient_proc: process
begin
wait for 30 ns;
EsperaIngrediente <= '1';
wait;
end process;
fimdeetapa_proc : process
begin
wait for 135 ns;
FimdeEtapa <= '1';
wait;
end process;
fimdereceita_proc : process
begin
wait for 145 ns;
FimdeReceita <= '1';
wait;
end process;
END;
--Inputs
signal E : std_logic_vector(3 downto 0) := "0000";
signal ManualMode : std_logic := '1';
signal Start : std_logic := '1';
signal Cancel : std_logic := '0';
signal FimdeEtapa : std_logic := '0';
signal FimdeReceita : std_logic := '0';
signal EsperaIngrediente : std_logic := '0';
signal clk : std_logic := '0';
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--Outputs
signal ES0 : std_logic_vector(3 downto 0);
signal ES1 : std_logic_vector(3 downto 0);
signal ES : std_logic_vector(3 downto 0);
signal Teste : std_logic_vector(2 downto 0);
-- Clock period definitions
constant clk_period : time := 15 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MaquinadeEstadosBimbi PORT MAP (
clk => clk,
ManualMode => ManualMode,
Start => Start,
Cancel => Cancel,
FimdeEtapa => FimdeEtapa,
FimdeReceita => FimdeReceita,
EsperaIngrediente => EsperaIngrediente,
ES0 => ES0,
ES1 => ES1,
ES => ES,
Teste => Teste
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
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wait for 20 ns;
ManualMode <= '1';
wait for 20 ns;
ManualMode <= '0';
wait;
end process;
start_proc: process
begin
wait for 40 ns;
Start <= '0';
wait for 30 ns;
Start <= '1';
wait;
end process;
esperaingredient_proc: process
begin
wait for 30 ns;
EsperaIngrediente <= '1';
wait;
end process;
END;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity selecReceita is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
up : in STD_LOGIC;
clk : in std_logic;
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en : in STD_LOGIC;
down : in STD_LOGIC;
R : out std_logic_vector(3 downto 0));
end selecReceita;
architecture Behavioral of selecReceita is
component bcd_updown_counter
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
op : in STD_LOGIC;
en : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0);
en_next : out STD_LOGIC);
end component;
signal dout, din, Cout, E : std_logic_vector(3 downto 0);
signal op, en_next, ene : std_logic;
begin
genREG : for i in 0 to 3 generate
dout(i) <= din(i) when rising_edge(clk);
end generate;
din <= Cout;
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R <= dout;
counterbcd : bcd_updown_counter Port Map (
A(3 downto 0) => A(3 downto 0),
op => op,
en => en,
S(3 downto 0) => Cout(3 downto 0),
en_next => en_next);
op <= (down and not(up)) and (up xor down);
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity helice_leds is
Port ( clk : in STD_LOGIC;
EN : in STD_LOGIC;
V : in STD_LOGIC_vector(7 downto 0);
E : in std_logic_vector(3 downto 0);
led : out STD_LOGIC_vector(7 downto 0));
end helice_leds;
architecture Behavioral of helice_leds is
component decimal_updown_counter is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
op : in STD_LOGIC;
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en : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component fullseq
Port ( clk : in STD_LOGIC;
INI : in STD_LOGIC;
EN : in STD_LOGIC;
B : in STD_LOGIC_VECTOR (7 downto 0);
Q : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component relogio
Port ( clk : in STD_LOGIC;
hold : in STD_LOGIC;
reset : in STD_LOGIC;
t64 : out STD_LOGIC;
t16 : out STD_LOGIC;
t8 : out STD_LOGIC;
t1 : out STD_LOGIC);
end component;
signal t64, c15, ENseq, hold, resetseq, t16, t8, t1, en_next, cooking, op :
std_logic;
signal ledcooking, A, B, dout, din : std_logic_vector(7 downto 0);
begin
genREG : for i in 0 to 7 generate
dout(i) <= din(i) when rising_edge(clk);
end generate;
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25 | P á g i n a
din <= B;
A <= V when c15='1' else
dout;
--Um multiplexer escolhe se os leds estão apagados (se fora de um estado
cooking) ou a representar a sequência (num estado cooking)
led <= "00000000" when cooking='0' else
ledcooking;
dec : decimal_updown_counter Port Map (
A(7 downto 0) => A(7 downto 0),
op => op,
en => EN,
S(7 downto 0) => B(7 downto 0));
sequencia : fullseq Port Map (
clk => clk,
INI => '0',
EN => ENseq,
B(7 downto 0) => "00000000",
Q(7 downto 0) => ledcooking(7
downto 0)
);
op <= '0';
c15 <= not(B(7)) and not(B(6)) and not(B(5)) and B(4) and not(B(3)) and B(2)
and not(B(1)) and B(0);
ENseq <= c15;
cooking <= (not(E(0)) and not(E(1)) and E(3));
end Behavioral;
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CountEtapas is
Port (enet : in STD_LOGIC;
enT : in std_logic;
R : in STD_LOGIC_vector(3 downto 0);
clk : in std_logic;
Start : in std_logic;
FimdeEtapa : in std_logic;
FimdeReceita : in std_logic;
EsperaIngrediente : in std_logic;
t1 : in std_logic;
es : out STD_LOGIC_vector(3 downto 0));
end CountEtapas;
architecture Behavioral of CountEtapas is
component decimal_updown_counter is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
op : in STD_LOGIC;
en : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component bcd_updown_counter
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
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op : in STD_LOGIC;
en : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0);
en_next : out STD_LOGIC);
end component;
signal op, transcooking, en_next : std_logic;
signal dout, din, ese, et, A : std_logic_vector(3 downto 0);
signal Sele : std_logic_vector(4 downto 0);
signal Cout2, dout2, din2, T : std_logic_vector(7 downto 0);
signal SelT : std_logic_vector(9 downto 0 );
begin
genREG7 : for i in 0 to 7 generate
dout2(i) <= din2(i) when rising_edge(clk);
end generate;
din2 <= Cout2;
genREG3 : for i in 0 to 3 generate
dout(i) <= din(i) when rising_edge(clk);
end generate;
din <= ese;
bcdcounter : bcd_updown_counter Port Map (
A(3 downto 0) => et(3 downto 0),
op => op,
en => enet,
S(3 downto 0) => ese(3 downto 0),
en_next => en_next);
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decimalcounter : decimal_updown_counter Port Map (
A(7 downto 0) => T(7 downto 0),
op => op,
en => enT,
S(7 downto 0) => Cout2(7 downto 0));
op <= '1';
et(3 downto 0) <= dout(3 downto 0);
T(7 downto 0) <= dout2(7 downto 0);
es <= ese;
Sele <= transcooking & R(3) & R(2) & R(1) & R(0);
SelT <= FimdeEtapa & transcooking & R(3) & R(2) & R(1) & R(0) & et(3) & et(2)
& et(1) & et(0);
et(3 downto 0) <= "0011" when Sele="10001" else
"0001" when Sele="10010" else
"0000" when Sele="10011" else
"0100" when Sele="10100" else
"0101" when Sele="10101" else
"0110" when Sele="10110" else
"1000" when Sele="10111" else
"0111" when Sele="11000" else
"0010" when Sele="11001" else
es;
T <= "00100000" when SelT="0100010011" else
"00100000" when SelT="0100010010" else
"00100000" when SelT="0100010001" else
"00100000" when SelT="0100010000" else
"00100000" when SelT="1100010011" else
"00100000" when SelT="1100010010" else
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"00100000" when SelT="1100010001" else
"00100000" when SelT="1100010000" else
"00000101" when SelT="1000010011" else
"00000101" when SelT="1000010010" else
"00010000" when SelT="1000010001" else
"00000101" when SelT="1000010000" else
"00000101" when SelT="0100100001" else
"00000101" when SelT="0100100000" else
"00000101" when SelT="1100100001" else
"00000101" when SelT="1100100000" else
"00000101" when SelT="1000100001" else
"00100000" when SelT="1000100000" else
"00100000" when SelT="0100110000" else
"00100000" when SelT="1100110000" else
"00110000" when SelT="1000110000" else
"00110000" when SelT="0101000100" else
"00110000" when SelT="0101000011" else
"00110000" when SelT="0101000010" else
"00110000" when SelT="0101000001" else
"00110000" when SelT="0101000000" else
"00110000" when SelT="1101000100" else
"00110000" when SelT="1101000011" else
"00110000" when SelT="1101000010" else
"00110000" when SelT="1101000001" else
"00110000" when SelT="1101000000" else
"00010000" when SelT="1001000100" else
"01100000" when SelT="1001000011" else
"00010000" when SelT="1001000010" else
"00000101" when SelT="1001000001" else
"01000000" when SelT="1001000000" else
"01000000" when SelT="0101010101" else
"01000000" when SelT="0101010100" else
"01000000" when SelT="0101010011" else
"01000000" when SelT="0101010010" else
"01000000" when SelT="0101010001" else
"01000000" when SelT="0101010000" else
"01000000" when SelT="1101010101" else
"01000000" when SelT="1101010100" else
"01000000" when SelT="1101010011" else
"01000000" when SelT="1101010010" else
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"01000000" when SelT="1101010001" else
"01000000" when SelT="1101010000" else
"00010000" when SelT="1001010101" else
"01000000" when SelT="1001010100" else
"00010000" when SelT="1001010011" else
"00000101" when SelT="1001010010" else
"00100000" when SelT="1001010001" else
"00010000" when SelT="1001010000" else
"00010000" when SelT="0101100110" else
"00010000" when SelT="0101100101" else
"00010000" when SelT="0101100100" else
"00010000" when SelT="0101100011" else
"00010000" when SelT="0101100010" else
"00010000" when SelT="0101100001" else
"00010000" when SelT="0101100000" else
"00010000" when SelT="1101100110" else
"00010000" when SelT="1101100101" else
"00010000" when SelT="1101100100" else
"00010000" when SelT="1101100011" else
"00010000" when SelT="1101100010" else
"00010000" when SelT="1101100001" else
"00010000" when SelT="1101100000" else
"00110000" when SelT="1001100110" else
"00010000" when SelT="1001100101" else
"00010000" when SelT="1001100100" else
"00100000" when SelT="1001100011" else
"00010000" when SelT="1001100010" else
"00010000" when SelT="1001100001" else
"00000101" when SelT="1001100000" else
"00000101" when SelT="0101111000" else
"00000101" when SelT="0101110111" else
"00000101" when SelT="0101110110" else
"00000101" when SelT="0101110101" else
"00000101" when SelT="0101110100" else
"00000101" when SelT="0101110011" else
"00000101" when SelT="0101110010" else
"00000101" when SelT="0101110001" else
"00000101" when SelT="0101110000" else
"00000101" when SelT="1101111000" else
"00000101" when SelT="1101110111" else
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"00000101" when SelT="1101110110" else
"00000101" when SelT="1101110101" else
"00000101" when SelT="1101110100" else
"00000101" when SelT="1101110011" else
"00000101" when SelT="1101110010" else
"00000101" when SelT="1101110001" else
"00000101" when SelT="1101110000" else
"00010000" when SelT="1001111000" else
"00110000" when SelT="1001110111" else
"00010000" when SelT="1001110110" else
"00110000" when SelT="1001110101" else
"00000101" when SelT="1001110100" else
"00100000" when SelT="1001110011" else
"00100000" when SelT="1001110010" else
"00010000" when SelT="1001110001" else
"00010000" when SelT="1110000111" else
"00010000" when SelT="1110000110" else
"00010000" when SelT="1110000101" else
"00010000" when SelT="1110000100" else
"00010000" when SelT="1110000011" else
"00010000" when SelT="1110000010" else
"00010000" when SelT="1110000001" else
"00010000" when SelT="1110000000" else
"00010000" when SelT="0110000111" else
"00010000" when SelT="0110000110" else
"00010000" when SelT="0110000101" else
"00010000" when SelT="0110000100" else
"00010000" when SelT="0110000011" else
"00010000" when SelT="0110000010" else
"00010000" when SelT="0110000001" else
"00010000" when SelT="0110000000" else
"00010000" when SelT="1001110000" else
"00100000" when SelT="1010000111" else
"00010000" when SelT="1010000110" else
"00110000" when SelT="1010000101" else
"00010000" when SelT="1010000100" else
"01100000" when SelT="1010000011" else
"01100000" when SelT="1010000010" else
"00100000" when SelT="1010000001" else
"00100000" when SelT="1010000000" else
32. SISTEMAS DIGITAIS
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32 | P á g i n a
"00100000" when SelT="0110010010" else
"00100000" when SelT="0110010001" else
"00100000" when SelT="0110010000" else
"00100000" when SelT="1110010010" else
"00100000" when SelT="1110010001" else
"00100000" when SelT="1110010000" else
"00100000" when SelT="1010010010" else
"10010000" when SelT="1010010001" else
Cout2;
transcooking <= ((E(0) and not(E(1)) and E(2) and E(3)) and Start) or ((not(E(0))
and E(1) and E(2) and E(3)) and FimdeReceita) or ((not(E(0)) and E(1) and
not(E(2)) and E(3)) and EsperaIngrediente) or ((E(0) and E(1) and not(E(2)) and
E(3)) and Start);
FimdeReceita <= FimdeEtapa and (not(et(3)) and not(et(2)) and not(et(1)) and
not(et(0)));
FimdeEtapa <= (not(T(7)) and not(T(6)) and not(T(5)) and not(T(4)) and
not(T(3)) and not(T(2)) and not(T(1)) and not(T(0))) and ((not(E(0)) and not(E(1))
and E(2) and E(3)) or (not(E(0)) and not(E(1)) and not(E(2)) and E(3)));
EsperaIngrediente <= ((not(R(3)) and not(R(2)) and not(R(1)) and R(0)) and
FimdeEtapa and ((not(et(3)) and not(et(2)) and et(1) and et(0)) or (not(et(3))
and not(et(2)) and not(et(1)) and et(0)))) or ((not(R(3)) and R(2) and not(R(1))
and not(R(0)) and FimdeEtapa and (not(et(3)) and not(et(2)) and et(1) and
not(et(0)))) or ((not(R(3)) and R(2) and not(R(1)) and R(0)) and FimdeEtapa and
(not(et(3)) and not(et(2)) and et(1) and et(0))) or ((not(R(3)) and R(2) and R(1)
and not(R(0))) and FimdeEtapa and (not(et(3)) and not(et(2)) and not(et(1)) and
et(0)))) or ((not(R(3)) and R(2) and R(1) and R(0)) and FimdeEtapa and
((not(et(3)) and et(2) and et(1) and et(0)) or (not(et(3)) and et(2) and not(et(1))
and et(0)) or (not(et(3)) and not(et(2)) and et(1) and not(et(0)))) or (R(3) and
not(R(2)) and not(R(1)) and not(R(0))) and FimdeEtapa and ((not(et(3)) and
not(et(2)) and et(1) and not(et(0))) or (not(et(3)) and not(et(2)) and not(et(1))
and et(0)))) or (R(3) and not(R(2)) and not(R(1)) and R(0)) and FimdeEtapa and
((not(et(3)) and not(et(2)) and et(1) and not(et(0))) or (not(et(3)) and not(et(2))
and not(et(1)) and et(0))));
end Behavioral;
33. SISTEMAS DIGITAIS
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33 | P á g i n a
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity helice_speed is
Port ( E : in STD_LOGIC_vector(3 downto 0);
et : in STD_LOGIC_vector(3 downto 0);
R : in STD_LOGIC_vector(3 downto 0);
FimdeEtapa : in STD_LOGIC;
transcooking : in STD_LOGIC;
V : out STD_LOGIC_vector(7 downto 0));
end helice_speed;
architecture Behavioral of helice_speed is
signal CookingRecipe : std_logic;
signal Esel : std_logic_vector(3 downto 0);
signal Vr, Ve, Vm : std_logic_vector(7 downto 0);
signal SelVr : std_logic_vector(8 downto 0);
begin
Vr <= "00000010" when SelVr="100010011" else
"00010010" when SelVr="100010010" else
"00000111" when SelVr="100010001" else
"00001000" when SelVr="100010000" else
"00000101" when SelVr="100100001" else
"00010000" when SelVr="100100000" else
"00010101" when SelVr="100110000" else
"00010000" when SelVr="101000100" else
"00010101" when SelVr="101000011" else
34. SISTEMAS DIGITAIS
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34 | P á g i n a
"00000101" when SelVr="101000010" else
"00000111" when SelVr="101000001" else
"00000011" when SelVr="101000000" else
"00010011" when SelVr="101010101" else
"00010101" when SelVr="101010100" else
"00000111" when SelVr="101010011" else
"00010000" when SelVr="101010010" else
"00010101" when SelVr="101010001" else
"00010000" when SelVr="101010000" else
"00010000" when SelVr="101100110" else
"00010101" when SelVr="101100101" else
"00000101" when SelVr="101100100" else
"00010000" when SelVr="101100011" else
"00000101" when SelVr="101100010" else
"00010100" when SelVr="101100001" else
"00010100" when SelVr="101100000" else
"00010011" when SelVr="101111000" else
"00010000" when SelVr="101110111" else
"00000111" when SelVr="101110110" else
"00000101" when SelVr="101110101" else
"00001000" when SelVr="101110100" else
"00010000" when SelVr="101110011" else
"00000110" when SelVr="101110010" else
"00010000" when SelVr="101110001" else
"00000101" when SelVr="101110000" else
"00010000" when SelVr="110000111" else
"00000101" when SelVr="110000110" else
"00000111" when SelVr="110000101" else
"00010000" when SelVr="110000100" else
"00000101" when SelVr="110000011" else
"00010000" when SelVr="110000010" else
"00000111" when SelVr="110000001" else
"00000111" when SelVr="110000000" else
"00010000" when SelVr="110010010" else
"00010101" when SelVr="110010001" else
"00000101" when SelVr="110010000" else
"00000000";
Ve <= Vr when Esel="1100" else
Vm when Esel="1000" else
35. SISTEMAS DIGITAIS
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35 | P á g i n a
"00000000";
Esel <= E(3) & E(2) & E(1) & E(0);
SelVr <= CookingRecipe & R(3) & R(2) & R(1) & R(0) & et(3) & et(2) & et(1) &
et(0);
CookingRecipe <= E(3) and E(2) and not(E(1)) and not(E(0));
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DisplaySelect is
Port ( T : in STD_LOGIC_vector(7 downto 0);
Tm : in std_logic_vector(7 downto 0);
V : in STD_LOGIC_vector(7 downto 0);
R : in std_logic_vector(3 downto 0);
TL : in STD_LOGIC_vector(11 downto 0);
et : in STD_LOGIC_vector(3 downto 0);
Sel : in std_logic_vector(1 downto 0);
disp : out STD_LOGIC_vector(11 downto 0));
end DisplaySelect;
architecture Behavioral of DisplaySelect is
--Tm é tempo de etapa manual e Vm é velocidade de hélice de etapa manual
signal T11, V11, et11, dispe, R11, Tm11, Vm11 : std_logic_vector(11 downto 0);
signal Idle, SetupTime, SetupSpeed : std_logic;
signal Seldisp : std_logic_vector(4 downto 0);
begin
36. SISTEMAS DIGITAIS
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36 | P á g i n a
Seldisp <= SetupTime & SetupSpeed & Idle & Sel(1) & Sel(0);
dispe <= T11 when Seldisp="00000" else
V11 when Seldisp="00001" else
TL when Seldisp="00010" else
et11 when Seldisp="00011" else
R11 when Seldisp="00100" else
R11 when Seldisp="00101" else
R11 when Seldisp="00110" else
R11 when Seldisp="00111" else
Vm11 when Seldisp="01000" else
Vm11 when Seldisp="01001" else
Vm11 when Seldisp="01010" else
Vm11 when Seldisp="01011" else
Tm11 when Seldisp="01000" else
Tm11 when Seldisp="01001" else
Tm11 when Seldisp="01010" else
Tm11 when Seldisp="01011" else
"00000000000";
SetupSpeed <= not(E(3)) and E(2) and E(1) and not(E(0));
SetupTime <= not(E(3)) and E(2) and not(E(1)) and not(E(0));
Idle <= not(E(3)) and not(E(2)) and E(1) and not(E(0));
Tm11 <= "0000" & Tm(7 downto 0);
Vm11 <= "0000" & Vm(7 downto 0);
T11 <= "0000" & T(7 downto 0);
--Só intersessamos primeiros 8 bits, ou seja, 2 digitos decimais
V11 <= "0000" & V(7 downto 0);
--Só intersessamos primeiros 8 bits, ou seja, 2 digitos decimais
e11 <= "00000000" & et(3 downto 0);
--Só intersessamos primeiros 4 bits, ou seja, 1 digito decimal
37. SISTEMAS DIGITAIS
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37 | P á g i n a
R11 <= "00000000" & R(3 downto 0);
disp <= dispe;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ManualT is
Port ( A : in STD_LOGIC_vector(7 downto 0);
Start : in std_logic;
up : in STD_LOGIC;
down : in STD_LOGIC;
enMT : in std_logic;
T : out STD_LOGIC(7 downto 0));
end ManualT;
architecture Behavioral of ManualT is
component decimal_updown_counter is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
op : in STD_LOGIC;
en : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal op : std_logic;
signal Cout : std_logic(7 downto 0);
begin
genREG : for i in 7 to 0 generate
dout(i) <= din(i) when rising_edge(clk);
38. SISTEMAS DIGITAIS
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38 | P á g i n a
din(i) <= Cout(i);
end generate;
decimal_updown_counter Port Map (
A(7 downto 0) => A(7 downto 0),
op => op,
en => enMT,
S(7 downto 0) => Cout(7 downto 0));
enMT <= not(E(0)) and not(E(1)) and E(2) and not(E(3)) and not(Start);
op <= (down and not(up)) and (up xor down);
T(7 downto 0) <= Cout(7 downto 0);
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ManualV is
Port ( A : in STD_LOGIC_vector(7 downto 0);
up : in STD_LOGIC;
down : in STD_LOGIC;
R : in STD_LOGIC_vector(3 downto 0);
Vm : out STD_LOGIC_vector(7 downto 0));
end ManualV;
architecture Behavioral of ManualV is
component decimal_updown_counter is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
39. SISTEMAS DIGITAIS
2014-2015, MEEC
39 | P á g i n a
op : in STD_LOGIC;
en : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component selecReceita is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
up : in STD_LOGIC;
en : in STD_LOGIC;
down : in STD_LOGIC;
R : out std_logic_vector(3 downto 0));
end component;
signal op, uprec, enrec, downrec, clk, en : std_logic;
signal Arec, Rrec: std_logic_vector(3 downto 0);
signal dout, din, Cout, Vme : std_logic_vector(7 downto 0);
begin
genREG : for i in 0 to 7 generate
dout(i) <= din(i) when rising_edge(clk);
din(i) <= Cout(i);
dout(i) <= Vme(i);
end generate;
dec : decimal_updown_counter Port Map (
A(7 downto 0) => A(7 downto 0),
op => op,
en => en,
40. SISTEMAS DIGITAIS
2014-2015, MEEC
40 | P á g i n a
S(7 downto 0) => Cout(7 downto 0));
sR : selecReceita Port Map (
A(3 downto 0) => Arec(3 downto 0),
up => uprec,
en => enrec,
down => downrec,
R => Rrec);
Vm(7 downto 0) <= Vme(7 downto 0);
enMV <= not(E(0)) and E(1) and E(2) and not(E(3)) and not(Start);
op <= (down and not(up)) and (up xor down);
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ReceTimeLeft is
Port ( et : in STD_LOGIC_vector(3 downto 0);
ene : in STD_LOGIC;
enT : in std_logic;
FimdeCentena : in std_logic;
Start : in std_logic;
FimdeEtapa : in std_logic;
FimdeReceita : in std_logic;
EsperaIngrediente : in std_logic;
t1 : in std_logic;
R : in STD_LOGIC_vector(3 downto 0);
41. SISTEMAS DIGITAIS
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41 | P á g i n a
Td : in std_logic_vector(7 downto 0);
clk : in std_logic;
TL : out std_logic_vector(11 downto 0);
es : out STD_LOGIC_vector(3 downto 0));
end ReceTimeLeft;
architecture Behavioral of ReceTimeLeft is
component decimal_updown_counter is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
op : in STD_LOGIC;
en : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component bcd_updown_counter
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
op : in STD_LOGIC;
en : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0);
en_next : out STD_LOGIC);
end component;
signal op, transcooking, en_next : std_logic;
signal dout, din, ese, ete : std_logic_vector(3 downto 0);
signal Sele : std_logic_vector(4 downto 0);
signal Cout2, dout2, din2, T : std_logic_vector(7 downto 0);
signal SelT : std_logic_vector(10 downto 0);
42. SISTEMAS DIGITAIS
2014-2015, MEEC
42 | P á g i n a
begin
genREG7 : for i in 7 to 0 generate
dout2(i) <= din2(i) when rising_edge(clk);
end generate;
din2 <= Cout2;
genREG3 : for i in 3 to 0 generate
dout(i) <= din(i) when rising_edge(clk);
end generate;
din <= ese;
bcdcounter : bcd_updown_counter Port Map (
A(3 downto 0) => et(3 downto 0),
op => op,
en => ene,
S(3 downto 0) => es(3 downto 0),
en_next => en_next);
decimalcounter : decimal_updown_counter Port Map (
A(7 downto 0) => T(7 downto 0),
op => op,
en => enT,
S(7 downto 0) => Cout2(7 downto 0));
op <= '1';
es <= ese;
ete <= et;
ete(3 downto 0) <= dout(3 downto 0);
43. SISTEMAS DIGITAIS
2014-2015, MEEC
43 | P á g i n a
T(7 downto 0) <= dout2(7 downto 0);
Sele <= transcooking & R(3) & R(2) & R(1) & R(0);
SelT <= FimdeCentena & FimdeEtapa & transcooking & R(3) & R(2) & R(1) &
R(0) & et(3) & et(2) & et(1) & et(0);
with Sele select
e(3 downto 0) <= "0011" when "10001",
e(3 downto 0) <= "0001" when "10010",
e(3 downto 0) <= "0000" when "10011",
e(3 downto 0) <= "0100" when "10100",
e(3 downto 0) <= "0101" when "10101",
e(3 downto 0) <= "0110" when "10110",
e(3 downto 0) <= "1000" when "10111",
e(3 downto 0) <= "0111" when "11000",
e(3 downto 0) <= "0010" when "11001",
e(3 downto 0) <= es(3 downto 0) when others;
--Algumas etapas de algumas receitas têm um tempo restante superior a 99s,
obrigando à existência de um sinal FimdeCentena que, quando 1, quer dizer
que se decrementa o digito das centenas
with SelT select
TL(11 downto 7) <= "0001" when "00101000100",
TL(11 downto 7) <= "0001" when "00001000100",
TL(11 downto 7) <= "0001" when "00101010101",
TL(11 downto 7) <= "0001" when "00001010101",
TL(11 downto 7) <= "0001" when "00101100110",
TL(11 downto 7) <= "0001" when "00001100110",
TL(11 downto 7) <= "0001" when "00101111000",
TL(11 downto 7) <= "0001" when "00001111000",
TL(11 downto 7) <= "0001" when "00001110111",
TL(11 downto 7) <= "0001" when "00001110110",
TL(11 downto 7) <= "0001" when "00010000101",
TL(11 downto 7) <= "0001" when "00010000100",
TL(11 downto 7) <= "0001" when "00010000011",
TL(11 downto 7) <= "0001" when "00010000010",
TL(11 downto 7) <= "0001" when "00010010010",
TL(11 downto 7) <= "0001" when "00010010001",
44. SISTEMAS DIGITAIS
2014-2015, MEEC
44 | P á g i n a
TL(11 downto 7) <= "0002" when "00110000111",
TL(11 downto 7) <= "0002" when "00010000111",
TL(11 downto 7) <= "0002" when "00010000110",
TL(11 downto 7) <= "0000" when others;
with SelT select
T(7 downto 0) <= "01000000" when "00100010011",
T(7 downto 0) <= "01000000" when "00100010010",
T(7 downto 0) <= "01000000" when "00100010001",
T(7 downto 0) <= "01000000" when "00100010000",
T(7 downto 0) <= "01000000" when "01100010011",
T(7 downto 0) <= "01000000" when "01100010010",
T(7 downto 0) <= "01000000" when "01100010001",
T(7 downto 0) <= "01000000" when "01100010000",
T(7 downto 0) <= "00100000" when "01000010011",
T(7 downto 0) <= "00010101" when "01000010010",
T(7 downto 0) <= "00010000" when "01000010001",
T(7 downto 0) <= "00010000" when "01000010000",
T(7 downto 0) <= "00010000" when "00100100001",
T(7 downto 0) <= "00010000" when "00100100000",
T(7 downto 0) <= "00010000" when "01100100001",
T(7 downto 0) <= "00010000" when "01100100000",
T(7 downto 0) <= "00000101" when "01000100001",
T(7 downto 0) <= "00100000" when "01000100000",
T(7 downto 0) <= "00100000" when "00100110000",
T(7 downto 0) <= "00100000" when "01100110000",
T(7 downto 0) <= "01010000" when "01000110000",
T(7 downto 0) <= "10011001" when "11000110000",
T(7 downto 0) <= "01010000" when "00101000100",
T(7 downto 0) <= "01010000" when "00101000011",
T(7 downto 0) <= "01010000" when "00101000010",
T(7 downto 0) <= "01010000" when "00101000001",
T(7 downto 0) <= "01010000" when "00101000000",
T(7 downto 0) <= "01010000" when "01101000100",
T(7 downto 0) <= "01010000" when "01101000011",
T(7 downto 0) <= "01010000" when "01101000010",
T(7 downto 0) <= "01010000" when "01101000001",
T(7 downto 0) <= "01010000" when "01101000000",
45. SISTEMAS DIGITAIS
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45 | P á g i n a
T(7 downto 0) <= "10000101" when "01001000100",
T(7 downto 0) <= "01110101" when "01001000011",
T(7 downto 0) <= "00010101" when "01001000010",
T(7 downto 0) <= "00000101" when "01001000001",
T(7 downto 0) <= "00100101" when "01001000000",
T(7 downto 0) <= "00100101" when "00101010101",
T(7 downto 0) <= "00100101" when "00101010100",
T(7 downto 0) <= "00100101" when "00101010011",
T(7 downto 0) <= "00100101" when "00101010010",
T(7 downto 0) <= "00100101" when "00101010001",
T(7 downto 0) <= "00100101" when "00101010000",
T(7 downto 0) <= "00100101" when "01101010101",
T(7 downto 0) <= "00100101" when "01101010100",
T(7 downto 0) <= "00100101" when "01101010011",
T(7 downto 0) <= "00100101" when "01101010010",
T(7 downto 0) <= "00100101" when "01101010001",
T(7 downto 0) <= "00100101" when "01101010000",
T(7 downto 0) <= "10011001" when "11001010101",
T(7 downto 0) <= "10000101" when "01001010101",
T(7 downto 0) <= "01110101" when "01001010100",
T(7 downto 0) <= "00110101" when "01001010011",
T(7 downto 0) <= "00100101" when "01001010010",
T(7 downto 0) <= "00100000" when "01001010001",
T(7 downto 0) <= "00000000" when "01001010000",
T(7 downto 0) <= "00000000" when "00101100110",
T(7 downto 0) <= "00000000" when "00101100101",
T(7 downto 0) <= "00000000" when "00101100100",
T(7 downto 0) <= "00000000" when "00101100011",
T(7 downto 0) <= "00000000" when "00101100010",
T(7 downto 0) <= "00000000" when "00101100001",
T(7 downto 0) <= "00000000" when "00101100000",
T(7 downto 0) <= "00000000" when "01101100110",
T(7 downto 0) <= "00000000" when "01101100101",
T(7 downto 0) <= "00000000" when "01101100100",
T(7 downto 0) <= "00000000" when "01101100011",
T(7 downto 0) <= "00000000" when "01101100010",
T(7 downto 0) <= "00000000" when "01101100001",
T(7 downto 0) <= "00000000" when "01101100000",
T(7 downto 0) <= "10011001" when "11001100110",
T(7 downto 0) <= "10010000" when "01001100110",
46. SISTEMAS DIGITAIS
2014-2015, MEEC
46 | P á g i n a
T(7 downto 0) <= "01100000" when "01001100101",
T(7 downto 0) <= "01010000" when "01001100100",
T(7 downto 0) <= "01000000" when "01001100011",
T(7 downto 0) <= "00100000" when "01001100010",
T(7 downto 0) <= "00010000" when "01001100001",
T(7 downto 0) <= "01000000" when "01001100000",
T(7 downto 0) <= "01000000" when "00101111000",
T(7 downto 0) <= "01000000" when "00101110111",
T(7 downto 0) <= "01000000" when "00101110110",
T(7 downto 0) <= "01000000" when "00101110101",
T(7 downto 0) <= "01000000" when "00101110100",
T(7 downto 0) <= "01000000" when "00101110011",
T(7 downto 0) <= "01000000" when "00101110010",
T(7 downto 0) <= "01000000" when "00101110001",
T(7 downto 0) <= "01000000" when "00101110000",
T(7 downto 0) <= "01000000" when "01101111000",
T(7 downto 0) <= "01000000" when "01101110111",
T(7 downto 0) <= "01000000" when "01101110110",
T(7 downto 0) <= "01000000" when "01101110101",
T(7 downto 0) <= "01000000" when "01101110100",
T(7 downto 0) <= "01000000" when "01101110011",
T(7 downto 0) <= "01000000" when "01101110010",
T(7 downto 0) <= "01000000" when "01101110001",
T(7 downto 0) <= "01000000" when "01101110000",
T(7 downto 0) <= "00110101" when "01001111000",
T(7 downto 0) <= "00100101" when "01001110111",
T(7 downto 0) <= "10011001" when "11001110111",
T(7 downto 0) <= "10010101" when "01001110110",
T(7 downto 0) <= "10000101" when "01001110101",
T(7 downto 0) <= "01010101" when "01001110100",
T(7 downto 0) <= "01010000" when "01001110011",
T(7 downto 0) <= "00110000" when "01001110010",
T(7 downto 0) <= "00010000" when "01001110001",
T(7 downto 0) <= "00100000" when "01110000111",
T(7 downto 0) <= "00100000" when "01110000110",
T(7 downto 0) <= "00100000" when "01110000101",
T(7 downto 0) <= "00100000" when "01110000100",
T(7 downto 0) <= "00100000" when "01110000011",
T(7 downto 0) <= "00100000" when "01110000010",
T(7 downto 0) <= "00100000" when "01110000001",
47. SISTEMAS DIGITAIS
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47 | P á g i n a
T(7 downto 0) <= "00100000" when "01110000000",
T(7 downto 0) <= "00100000" when "00110000111",
T(7 downto 0) <= "00100000" when "00110000110",
T(7 downto 0) <= "00100000" when "00110000101",
T(7 downto 0) <= "00100000" when "00110000100",
T(7 downto 0) <= "00100000" when "00110000011",
T(7 downto 0) <= "00100000" when "00110000010",
T(7 downto 0) <= "00100000" when "00110000001",
T(7 downto 0) <= "00100000" when "00110000000",
T(7 downto 0) <= "00100000" when "01001110000",
T(7 downto 0) <= "00010000" when "01010000111",
T(7 downto 0) <= "10011001" when "11010000110",
T(7 downto 0) <= "10010000" when "01010000110",
T(7 downto 0) <= "10010000" when "01010000101",
T(7 downto 0) <= "01010000" when "01010000100",
T(7 downto 0) <= "01000000" when "01010000011",
T(7 downto 0) <= "10011001" when "11010000010",
T(7 downto 0) <= "10000000" when "01010000010",
T(7 downto 0) <= "00100000" when "01010000001",
T(7 downto 0) <= "00110000" when "01010000000",
T(7 downto 0) <= "00110000" when "00110010010",
T(7 downto 0) <= "00110000" when "00110010001",
T(7 downto 0) <= "00110000" when "00110010000",
T(7 downto 0) <= "00110000" when "01110010010",
T(7 downto 0) <= "00110000" when "01110010001",
T(7 downto 0) <= "00110000" when "01110010000",
T(7 downto 0) <= "00010000" when "01010010010",
T(7 downto 0) <= "10011001" when "11010010010",
T(7 downto 0) <= "10010000" when "01010010001",
T(7 downto 0) <= Cout2(7 downto 0) when others;
enT <= t1 and (not(esperaingrediente) or start);
ene <= (not(E(0)) and not(E(1)) and E(2) and E(3)) and not(transcooking) and
(T(3) and not(T(2)) and not(T(1)) and T(0)) and (not(esperaingrediente) or
start);
transcooking <= ((E(0) and not(E(1)) and E(2) and E(3)) and Start) or ((not(E(0))
and E(1) and E(2) and E(3)) and FimdeReceita) or ((not(E(0)) and E(1) and
48. SISTEMAS DIGITAIS
2014-2015, MEEC
48 | P á g i n a
not(E(2)) and E(3)) and EsperaIngrediente) or ((E(0) and E(1) and not(E(2)) and
E(3)) and Start);
FimdeReceita <= FimdeEtapa and (not(e(3)) and not(e(2)) and not(e(1)) and
not(e(0)));
FimdeEtapa <= (not(T(7)) and not(T(6)) and not(T(5)) and not(T(4)) and
not(T(3)) and not(T(2)) and not(T(1)) and not(T(0))) and ((not(E(0)) and not(E(1))
and E(2) and E(3)) or (not(E(0)) and not(E(1)) and not(E(2)) and E(3)));
EsperaIngrediente <= ((not(R(3)) and not(R(2)) and not(R(1)) and R(0)) and
FimdeEtapa and ((not(e(3)) and not(e(2)) and e(1) and e(0)) or (not(e(3)) and
not(e(2)) and not(e(1)) and e(0)))) or ((not(R(3)) and R(2) and not(R(1)) and
not(R(0)) and FimdeEtapa and (not(e(3)) and not(e(2)) and e(1) and not(e(0))))
or ((not(R(3)) and R(2) and not(R(1)) and R(0)) and FimdeEtapa and (not(e(3))
and not(e(2)) and e(1) and e(0))) or ((not(R(3)) and R(2) and R(1) and not(R(0)))
and FimdeEtapa and (not(e(3)) and not(e(2)) and not(e(1)) and e(0)))) or
((not(R(3)) and R(2) and R(1) and R(0)) and FimdeEtapa and ((not(e(3)) and e(2)
and e(1) and e(0)) or (not(e(3)) and e(2) and not(e(1)) and e(0)) or (not(e(3))
and not(e(2)) and e(1) and not(e(0)))) or (R(3) and not(R(2)) and not(R(1)) and
not(R(0))) and FimdeEtapa and ((not(e(3)) and not(e(2)) and e(1) and not(e(0)))
or (not(e(3)) and not(e(2)) and not(e(1)) and e(0)))) or (R(3) and not(R(2)) and
not(R(1)) and R(0)) and FimdeEtapa and ((not(e(3)) and not(e(2)) and e(1) and
not(e(0))) or (not(e(3)) and not(e(2)) and not(e(1)) and e(0))));
--Será preciso colocar os estados cooking no fimdeetapa?
FimdeCentena <= ((not(R(3)) and R(2) and not(R(1)) and not(R(0))) and
(not(e(3))) and e(2) and not(e(1)) and not(e(0)) and (not(T(7)) and not(T(6)) and
not(T(5)) and not(T(4)) and not(T(3)) and not(T(2)) and not(T(1)) and not(T(0))))
or ((not(R(3)) and R(2) and not(R(1)) and R(0)) and (not(e(3)) and e(2) and
not(e(1)) and e(0)) and (not(T(7)) and not(T(6)) and not(T(5)) and not(T(4)) and
not(T(3)) and not(T(2)) and not(T(1)) and not(T(0)))) or ((not(R(3)) and R(2) and
R(1)and not(R(0))) and (not(e(3)) and e(2)and e(1)and not(e(0))) and (not(T(7))
and not(T(6)) and not(T(5)) and not(T(4)) and not(T(3)) and not(T(2)) and
not(T(1)) and not(T(0)))) or ((not(R(3)) and R(2)and R(1)and R(0))and (not(e(3))
and e(2) and e(1) and not(e(0))) and (not(T(7)) and not(T(6)) and not(T(5)) and
not(T(4)) and not(T(3)) and not(T(2)) and not(T(1)) and not(T(0)))) or (R(3) and
not(R(2)) and not(R(1)) and not(R(0))) and ((not(e(3)) and e(2) and e(1) and
not(e(0))) or (not(e(3)) and not(e(2)) and e(1) and not(e(0)))) and (not(T(7)) and
not(T(6)) and not(T(5)) and not(T(4)) and not(T(3)) and not(T(2)) and not(T(1))
49. SISTEMAS DIGITAIS
2014-2015, MEEC
49 | P á g i n a
and not(T(0)))) or ((R(3)and not(R(2)) and not(R(1)) and R(0))and (not(e(3)) and
not(e(2)) and not(e(1)) and e(0)) and (not(T(7)) and not(T(6)) and not(T(5)) and
not(T(4)) and not(T(3)) and not(T(2)) and not(T(1)) and not(T(0))));
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RobotCompleto is
Port ( E : in STD_LOGIC_vector(3 downto 0);
clk : in std_logic;
ManualMode : in std_logic;
Start : in std_logic;
Cancel : in std_logic;
FimdeEtapa : in std_logic;
FimdeReceita : in std_logic;
EsperaIngrediente : in std_logic;
up : in std_logic;
down : in std_logic;
Sel : in std_logic_vector(1 downto 0);
leds : out std_logic_vector(7 downto 0);
disp : out STD_LOGIC_vector(11 downto 0)
);
end RobotCompleto;
architecture Behavioral of RobotCompleto is
component MaquinadeEstadosBimbi
Port ( clk : in std_logic;
ManualMode : in std_logic;
Start : in std_logic;
Cancel : in std_logic;
FimdeEtapa : in std_logic;
FimdeReceita : in std_logic;
EsperaIngrediente : in std_logic;
50. SISTEMAS DIGITAIS
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50 | P á g i n a
ES0 : out STD_LOGIC_vector(3 downto 0);
ES1 : out STD_LOGIC_vector(3 downto 0);
ES : out std_logic_vector(3 downto 0);
Teste : out STD_LOGIC_vector(2 downto 0)
);
end component;
component selecReceita
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
up : in STD_LOGIC;
clk : in std_logic;
en : in STD_LOGIC;
down : in STD_LOGIC;
R : out std_logic_vector(3 downto 0));
end component;
component helice_leds
Port ( clk : in STD_LOGIC;
EN : in STD_LOGIC;
V : in STD_LOGIC_vector(7 downto 0);
E : in std_logic_vector(3 downto 0);
led : out STD_LOGIC_vector(7 downto 0));
end component;
component CountEtapas
Port (et : in STD_LOGIC_vector(3 downto 0);
enet : in STD_LOGIC;
enT : in std_logic;
R : in STD_LOGIC_vector(3 downto 0);
T : in std_logic_vector(7 downto 0);
clk : in std_logic;
Start : in std_logic;
FimdeEtapa : in std_logic;
FimdeReceita : in std_logic;
EsperaIngrediente : in std_logic;
es : out STD_LOGIC_vector(3 downto 0));
51. SISTEMAS DIGITAIS
2014-2015, MEEC
51 | P á g i n a
end component;
component ReceTimeLeft
Port ( et : in STD_LOGIC_vector(3 downto 0);
ene : in STD_LOGIC;
enT : in std_logic;
R : in STD_LOGIC_vector(3 downto 0);
Td : in std_logic_vector(7 downto 0);
TL : out std_logic_vector(11 downto 0);
es : out STD_LOGIC_vector(3 downto 0));
end component;
component helice_speed
Port ( E : in STD_LOGIC_vector(3 downto 0);
et : in STD_LOGIC_vector(3 downto 0);
R : in STD_LOGIC_vector(3 downto 0);
FimdeEtapa : in STD_LOGIC;
transcooking : in STD_LOGIC;
V : out STD_LOGIC_vector(7 downto 0));
end component;
component DisplaySelect
Port ( T : in STD_LOGIC_vector(7 downto 0);
V : in STD_LOGIC_vector(7 downto 0);
TL : in STD_LOGIC_vector(11 downto 0);
et : in STD_LOGIC_vector(3 downto 0);
Sel : in std_logic_vector(1 downto 0);
disp : out STD_LOGIC_vector(11 downto 0));
end component;
component relogio is
Port ( clk : in STD_LOGIC;
hold : in STD_LOGIC;
reset : in STD_LOGIC;
t64 : out STD_LOGIC;
52. SISTEMAS DIGITAIS
2014-2015, MEEC
52 | P á g i n a
t16 : out STD_LOGIC;
t8 : out STD_LOGIC;
t1 : out STD_LOGIC);
end component;
signal R : std_logic_vector(3 downto 0);
begin
MaquinadeEstados : MaquinadeEstadosBimbi Port Map(
clk => clk,
ManualMode => ManualMode,
Start => Start,
Cancel => Cancel,
FimdeEtapa => FimdeEtapa,
FimdeReceita => FimdeReceita,
EsperaIngrediente => ,EsperaIngrediente
ES0 => ES0,
ES1 => ES1,
ES => ES,
Teste => Teste );
IdleReceita : selecReceita Port Map(
A => SelReceita,
up => up,
clk => clk,
en => ENselectreceita,
down => down,
R => R );
heliceleds : helice_leds Port Map(
clk => clk,
EN => ENheliceleds,
V => V,
E => E,
op => op,
53. SISTEMAS DIGITAIS
2014-2015, MEEC
53 | P á g i n a
led => led );
countetapas : CountEtapas Port Map(
et => et,
enet => enet,
enT => enT,
R => R,
T => T,
es => es );
recetimeleft : ReceTimeLeft Port(
et => et,
ene => ene,
enT => enT,
R => R,
Td => Td,
TL => TL,
es => es );
helicespeed : helice_speed Port Map (
E => E,
et => et,
R => R,
FimdeEtapa => FimdeEtapa,
transcooking => transcooking,
V => V );
display : DisplaySelect Port Map(
T => T,
V => V,
TL => TL,
et => et,
Sel => Sel,
disp => disp );
relogio : relogio Port Map(
clk => clk,
hold => hold,
54. SISTEMAS DIGITAIS
2014-2015, MEEC
54 | P á g i n a
reset => reset,
t64 => t64,
t16 => t16,
t8 => t8,
t1 => t1 );
enT <= t1 and (not(esperaingrediente) or start);
enet <= (not(E(0)) and not(E(1)) and E(2) and E(3)) and not(transcooking) and
(T(3) and not(T(2)) and not(T(1)) and T(0)) and (not(esperaingrediente) or
start);
op <= (down and not(up)) and (up xor down);
ENselectreceita <= not(E(0)) and E(1) and not E(2) and not(E(3));
ENheliceleds <= t64;
transcooking <= ((E(0) and not(E(1)) and E(2) and E(3)) and Start) or ((not(E(0))
and E(1) and E(2) and E(3)) and FimdeReceita) or ((not(E(0)) and E(1) and
not(E(2)) and E(3)) and EsperaIngrediente) or ((E(0) and E(1) and not(E(2)) and
E(3)) and Start);
FimdeReceita <= FimdeEtapa and (not(e(3)) and not(e(2)) and not(e(1)) and
not(e(0)));
FimdeEtapa <= (not(T(7)) and not(T(6)) and not(T(5)) and not(T(4)) and
not(T(3)) and not(T(2)) and not(T(1)) and not(T(0))) and ((not(E(0)) and not(E(1))
and E(2) and E(3)) or (not(E(0)) and not(E(1)) and not(E(2)) and E(3)));
esperaingrediente <= ((not(R(3)) and not(R(2)) and not(R(1)) and R(0)) and
FimdeEtapa and ((not(e(3)) and not(e(2)) and e(1) and e(0)) or (not(e(3)) and
not(e(2)) and not(e(1)) and e(0)))) or ((not(R(3)) and R(2) and not(R(1)) and
not(R(0)) and FimdeEtapa and (not(e(3)) and not(e(2)) and e(1) and not(e(0))))
or ((not(R(3)) and R(2) and not(R(1)) and R(0)) and FimdeEtapa and (not(e(3))
and not(e(2)) and e(1) and e(0))) or ((not(R(3)) and R(2) and R(1) and not(R(0)))
and FimdeEtapa and (not(e(3)) and not(e(2)) and not(e(1)) and e(0)))) or
55. SISTEMAS DIGITAIS
2014-2015, MEEC
55 | P á g i n a
((not(R(3)) and R(2) and R(1) and R(0)) and FimdeEtapa and ((not(e(3)) and e(2)
and e(1) and e(0)) or (not(e(3)) and e(2) and not(e(1)) and e(0)) or (not(e(3))
and not(e(2)) and e(1) and not(e(0)))) or (R(3) and not(R(2)) and not(R(1)) and
not(R(0))) and FimdeEtapa and ((not(e(3)) and not(e(2)) and e(1) and not(e(0)))
or (not(e(3)) and not(e(2)) and not(e(1)) and e(0)))) or (R(3) and not(R(2)) and
not(R(1)) and R(0)) and FimdeEtapa and ((not(e(3)) and not(e(2)) and e(1) and
not(e(0))) or (not(e(3)) and not(e(2)) and not(e(1)) and e(0))));
end Behavioral;
----------------------------------------------------------------------------------
-- Company: IST
-- Engineer: Pedro Tomas
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rom_memory1 is