1. Patents (Lead and co-inventor)
• 7,472,323 Mechanism to stop instruction execution at a microprocessor
• 6,546,531 Automatic delay element insertion system for addressing holdtime problems
• 6,499,123 Method and apparatus for debugging an integrated circuit
• 6,212,629 Method and apparatus for executing string instructions
• 6,185,711 Methods and apparatus for synchronizing asynchronous test structures and eliminating clock skew considerations
• 6,006,312 Cachability attributes of virtual addresses for optimizing performance of virtually and physically indexed caches in maintaining multiply
aliased physical addresses
• 5,920,889 Apparatus and method for write miss processing in a copy-back data cache with an allocating load buffer and a non-allocating store buffer
• 5,904,732 Dynamic priority switching of load and store buffers in superscalar processor
• 5,881,265 Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining
precise interrupts
• 5,802,575 Hit bit for indicating whether load buffer entries will hit a cache when they reach buffer head
• 5,781,753 Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a
processor having distributed pipeline control for speculative and out-of-order execution of complex instructions
• 5,768,575 Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a
processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions
• 5,761,469 Method and apparatus for optimizing signed and unsigned load processing in a pipelined processor
• 5,745,729 Methods and apparatuses for servicing load instructions
• 5,715,425 Apparatus and method for prefetching data into an external cache
• 5,682,492 Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining
precise interrupts
• 5,442,757 Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining
precise interrupts
• 5,226,126 Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags