1. Athmanathan Vaidyanathan
Amit Varde
Sudarshan Iyengar
Srikanth Settikere
Swetha Athmanathan

2.  Traditional ECO Method
 Proposed Method
 3 phase methodology
 Advantages
 Questions & Answers

3.  ECO = Engineering Change Order
 Fix a logical bugs in a design
 Metal ONLY EDIT
 Adequate spare logic cells present on silicon to do
the design
 Clock Tree does not need rework

4.  Translate Design Change (usually described in
HDL) to Boolean logic
 Implement the Boolean logic using from spare
cells
 Verify the design change
 Implement the design change in the layout
(Changes are made only to metal layer(s))

5.  Larger the design change more difficult to
translate it to Boolean logic
 Error prone
 Time consuming
 Designer needs to “know” the design

6.  Semi-automatic technique
 Uses standard synthesis tool
 Ability to handle complex and larger ECOs
than traditional approach
 Less time is required to implement the
design change
 Reduces several cycles of formal analysis
and/or verification.
 The “fix” is not driven by the knowledge
and/or experience of the designer on the
design issue/fix.

7.  The ECO is to be implemented using
 Enough spare cells are available to implement
design change
 Metal Only Edits
 Type and Count of logic cells is established well in
advance

8. 1. RTL Design Re-Synthesis
 Use a Synthesis Engine to re-synthesize design
1. Clock Tree Retention Phase
2. Automatic Placement and Routing

9. Figure 1: Three Phase ECO Technique
Phase 1
Phase 2
Phase 3

10. Figure 1: Three Phase ECO Technique
Phase 1

11.  Iteratively Constrain the Synthesis Engine to
produce a netlist of the design with logical edits
such that it ONLY uses
 Cells used in the original design
 Cells in the spare cell pool
 Use synthesis tool features to set synthesis
constrains:
 dont_touch
 prefered_cells
 dont_use
GOAL:
Generated netlist has cells
that are available on silicon
present on silicon = cells in original
design + cells in spare pool

12. ECO GOAL:
Generated netlist has cells that
are available on silicon

13. Figure 1: Three Phase ECO Technique
Phase 2

15. Figure 1: Three Phase ECO Technique
Phase 3

16.  APR synthesized logic and Clock Tree Network
 Run with “silicon freeze” options.
 APR tool functions:
 Maintain the Cell Mapping from previous revision
 Map the undedicated physical instances (spare
gates) to the newly synthesized ECO netlist.
 Use the available metals (as specified by the
designer) to do a metal-only routing for the new
netlist.
 If FlipFlops are added to logic - Clock Tree balancing
needs to be taken care of maually

17.  Semi-Automated Methodology to perform ECOs:
 Using the same RTL-synthesis and APR tools
used to synthesize the design.
 The principle and operational success of the
methodology is proven by experiments
performed on a set of industry-standard EDA
tools.

20. To begin:
Set the cells
available on silicon
as “preferred gates”
ECO GOAL:
Generated netlist has cells that
are available on silicon

22.  Depends on design
 Example used

23.  Use synthesis tool features to set constrains
 dont_touch
 prefered_cells
 dont_use

24. Reference eco_rev0 eco_rev1 DELTA
AND2X2 15 15 0
AND2X4 2 1 1
AND3X1 2 3 -1
… … … …
OAI221X4 0 1 -1
Total 594 591
Exact Number of Gates Used:
Constraint For Next Iteration:
Set dont_touch on 15 (all) instances

25. Reference eco_rev0 eco_rev1 DELTA
AND2X2 15 15 0
AND2X4 2 1 1
AND3X1 2 3 -1
… … … …
OAI221X4 0 1 -1
Total 594 591
Extra in New revision
Constraint For Next Iteration:
Set preference on this gate

26. Reference eco_rev0 eco_rev1 DELTA
AND2X2 15 15 0
AND2X4 2 1 1
AND3X1 2 3 -1
… … … …
OAI221X4 0 1 -1
Total 594 591
One Gate Needed for the ECO
Constraint For Next iteration:
• Set don’t_touch on 3 instances of AND3X1
• Set don’t use on AND3X1
(provided we have 3 cells - spare cells included)