• Senior DFT engineer with 3+ years’ experience in full chip DfT implementation and verification of scan architectures, JTAG, memory BIST, ATPG. • The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools.

1. SARACA is looking for a DFT Engineer for Bangalore location.
Interested candidates can share their resume on sanjay@saracasolutions.com.
Looking for immediate joiners only!!
Experience - Freshers - 10 years
Job Description-
• Senior DFT engineer with 6+ years’ experience in full chip DfT implementation and
verification of scan architectures, JTAG, memory BIST, ATPG.
• The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using
Mentor DfT tools and Cadence tools.
• The engineer needs to have hands on experience in scan insertion, JTAG, ATPG DRC
and coverage analysis, Simulation debug with timing/SDF.
• Should work independently with minimal support and good communication skills.
• Should be willing to take up new challenges in the project and be a team player.
• The engineer should be able to debug and root cause problem in simulation failures.