General concepts of digital electronics and

2
(Basic Electronics)
• Contents :
– Gates (OR, AND, NOR, NAND, XOR & XNOR),
– Boolean Algebra,
– Combinational and sequential circuits
– Gate Minimization

3
Logic
• It provides us a way to support our claims to
truth.
• It is a formal method of reasoning.
• It can be represented in many ways :
– Propositional logic,
– Digital logic and
– hardware.

4
Propositional Logic
• Represents logic through propositions and
logical connectives (operator).
• It is an elementary atomic sentence that may
take either true or false value but may not
take any other value.

5
examples...
• It is raining.
– It is a proposition as it may either be true or false.
• Australia have won ICC World Cup 2007
– It is also proposition as it is true.
• India is a continent.
– It is a proposition as it is false.
• What did you eat?
– It is not a proposition as it does not result in true or false.
• How are your?
– Not a proposition for the similar reason as above.

6
Types of Propositions
• A simple proposition is one that does not
contain any other proposition as a part.
• A compound proposition is one with two or
more simple proposition as parts or
components. For example :
– It is raining and wind is blowing.
– Take it or leave it.
– If you work hard then you will be rewarded.

7
Connectives
• A connective (or operator) joins simple propositions into
compounds, and joins compounds into larger compounds.
• They are called sentential connectives because they join
sentences (or what we are calling statement or
propositions).
• + .  and  symbols are used to designate the
sentential connectives .
• The symbol ‘~’ is the only operator that is not a
connective because it affects single statement only and
does not join statements into compounds.

8
Different types of connectives (operators)
• Disjunctive (OR)
– Represented by symbol ‘ + ’ or ‘  ’
– Means one of the two arguments is true or both.
– Eg. p + q ( or p  q) means p OR q.
• It means either p is true, or q is true, or both.
• Conjuntive (AND)
– Represented by symbol ‘ . ’ or ‘ & ‘ or ‘  ’
– Means both arguments are true.
– Eg. p . q ( or p & q) ( or p  q) means p AND q.
• It means both p and q are true.

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• Conditional (If...Then or Implication)
– Represented by symbol ‘’ or ‘’ or ‘  ‘
– Means if one argument is true then other argument is true.
• Bi-conditional (If and only if or Equivalence)
– Represented by symbol ‘’ or ‘  ‘
– Means either both argument are true or both are false.
• Negation (NOT)
– Represented by symbol ‘ ~ (tilde)’ or ‘ (apostrophe) or ‾ (bar)
– It is an operator that affects a single statement only and does not
join two or more statements.
– Eg. ~p ( or p’ or p ) means NOT p.
• It means p is false.

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Summary
• Simple statements
– p “p is true” assertion
– ~p “p is false” negation
• Compounds and connectives
– p + q “either p is true, or q is true, or both disjunction
– p . q “both p and q are true” conjunction
– p  q “if p is true then q is true” implication
– p  q “p and q are either both true or both false” equivalence

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Truth Values and
Well-formed Formulae (Wff)
• Every simple or compound proposition may take an either
true value or false value.
• These true (denoted by 1) or false (denoted by 0) are also
called truth values.
• Truth value is defined as truth or false of a proposition.
• All meaningful statements have truth values, whether they
are simple or compound, asserted or negated. i.e. ‘p’ is
either true or false, ~p is either true or false, p+q is either
true or false, and so on.
• A compound statement is truth-functional if its truth value as
a whole can be figured out solely on the basis of the truth
values of its parts or components.

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Negation (NOT)
• The NOT operator works on single proposition.
• It is also called unary connective.
• It ‘p’ denotes a proposition, then its negation will be
denoted by ~p or p’ or p.
• If p is 0 (false) then ~p is 1 (true) and If p is 1 (true) then
~p is 0 (false).
• Also note that : NOT(NOT p) results into p itself i.e.
• p = p
• (p’)’ = p Truth table for Negation
(NOT)
~(~p) = p
p ~p
0 1
1 0

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Disjunction (OR)
• OR connective works with more than one
proposition.
• The compound p+q has two component
propositions (p and q), each of which can be true
or false.
• So, there are four (22
) possible combinations.
• The disjunction of p with q (denoted as p+q or
pq) will be true whenever p is true or q is true
or both are true.

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Truth table for Disjunction (OR)
Note : if a compound has ‘n’ distinct components, there
will be 2n
rows in its truth table.
p q p + q
0 0 0
0 1 1
1 0 1
1 1 1

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Conjunction (AND)
• AND connective also works with more than
one proposition.
• The compound p.q (or p&q or pq) will be
true whenever both p and q are true.
Truth table for Conjunction (AND)
p q p . q
0 0 0
0 1 0
1 0 0
1 1 1

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Implication (If..then / Conditional)
• In the conditional pq, the first proposition
(the if clause) p here, is called the antecedent
and the second proposition (then clause) q
here, is called the consequent.
• The condition pq will be false when p is true
and q is false. For all other combinations, it
will be true.

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Truth table for Implication(If..then)
• The conditional pq may be expressed as :
pq = p’ + q
p q p  q
0 0 1
0 1 1
1 0 0
1 1 1

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Equivalence (If and only If / Bi-Conditonal)
• The bi-conditional results into false when one
of its component proposition is true and the
other is false.
• That is, pq will be 0 (false) when p is 0 and q
is 1 or p is 1 and q is 0. For all other inputs,
pq is 1.

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Truth table for Equivalence (If and only If)
• The bi-conditional pq may be expressed as :
pq = pq + p’ . q’
p q p  q
0 0 1
0 1 0
1 0 0
1 1 1

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S.No. Expression Equivalence Law
1
0 +p = p
0 . p = 0 Properties of 0
2
1 +p = 1
1 . p = p
Properties of 1
3 p + pq = p
p (p + q)= p
Absorption Law
4 p = p Double Negation
5 p + p = p
p . p = p Idempotent Law
Some Equivalence Propositional
Laws
• Two sentences are equivalent if they have the same
truth value under every interpretation i.e. both the
sentences possess the same truth set.

21
6
p + p = 1
p . p = 0
Complementary Law
7 p + q = q + p
p . q = q . p
Commutative Law
8 (p + q) + r = p + (q + r)
(p . q) . r = p . (q . r) Associative Law
9 p . (q + r) = (p . q) + (p . r)
p + (q . r) = (p + q) . (p + r) Distributive Law
10
(p + q) = p . q
(p . q) = p + q De Morgan’s Law
11 p  q = p + q Conditional Elimination
12 p  q = (p  q) . (q  p) Bi-conditional Elimination

22
practice...
• Construct a truth table for the expression (A.(A+B)).
What single term is the expression equivalent to?
Solution :
– Looking at the table, we find that columns (A.(A+B)) and
A are identical. That is, they possess the same truth set.
Hence the given expression (A.(A+B)) is equivalent to A.
A B A + B (A.(A+B))
0 0 0 0
0 1 1 0
1 0 1 1
1 1 1 1

23
• Using truth table, prove that pq is equivalent
to ~q  ~p.
– This rule is also called Transposition.
p q ~q ~p p  q ~q ~p
0 0 1 1 1 1
0 1 0 1 1 1
1 0 1 0 0 0
1 1 0 0 1 1

24
• Prove that p  q = p+ q
p q ~p p  q ~p + q
0 0 1 1 1
0 1 1 1 1
1 0 0 0 0
1 1 0 1 1

25
• Prove that p  q = q  p
p q p  q q  p
0 0 1 1
0 1 0 0
1 0 0 0
1 1 1 1

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• Prove that p  q = (p  q). (q  p)
p q p  q p  q q  p (p  q).(q  p)
0 0 1 1 1 1
0 1 0 1 0 0
1 0 0 0 1 0
1 1 1 1 1 1

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• Consider some simple propositions given below :
– A : It is raining.
– B : Wind is blowing.
– C : I am not driving.
– From these, create the following compound propositions.
(i) A  B (ii) ~B (iii) ~A.C (iv) A .~C (v) A + B.C
• Solution :
(i) A  B : It is raining OR wind is blowing
(ii) ~B : Wind is NOT blowing
(iii) ~A.C : It is NOT raining AND I am not driving
(iv) A.~C : It is raining AND I am driving
(v) A + B.C : It is raining OR wind is blowing AND I am
not driving.

28
Binary Valued Quantities
– Should I carry the book or not?
– Should I use calculator or not?
– Should I miss TV programme or not?
• Each of the above mentioned is a binary decision.
• Each of these questions requires a YES or NOT answer as
there are only two possible answers.
• Binary decision making also applies to formal logic. For
e.g.
– Indira Gandhi was the only woman Prime Minister of India.
– 13 – 2 = 11
– What did I say yesterday?
– Delhi is the biggest state in India.
– What do you say?

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• Sentences which can be determined to be true or
false are called Logical Statements or Truth
Functions and the results TRUE or FALSE are called
truth values and the variables which can store these
truth values are called logical variable or binary
valued variable.
• Truth Table is a table which represents all the
possible values of logical variables/statements along
with all the possible results of the given
combinations of values.
• If the result of any logical statement or expression is
always TRUE or 1, it is called Tautology and if the
result is always FALSE or 0 it is called Fallacy.

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Assignment #1
• Prepare a table of combinations for the following
Boolean algebra expression:
– X + (XZ)’
– X’Y’ + X’Y
– XYZ’ + X’Y’Z
– X’YZ’ + XY’
– X(Y’ + Z’) + XY’
– XY’(Z+YZ’)+Z’
– A[(B’+C)+C’]
• Verify:
– X + XY = X
– (X + Y)’ = X’Y’

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LOGIC GATES
• A Gate is simply an electronic circuit which operates
on one or more signals to produce an output signal.
• Gates are digital (two-state) circuits because the input
and output signals are either low voltage(denotes 0) or
high voltage(denotes 1).
• Gates are often called logic circuits because they can
be analyzed with Boolean algebra.
• There are three types of logic gates :
– Inverter (NOT) Gate
– OR Gate
– AND Gate

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Inverter (NOT) Gate
• An inverter (NOT) gate is a gate with one input
signal and one output signal.
• The output state is always the opposite of the
input state.
• It is called NOT gate because the output is not
the same as the input.
• The output is sometimes called the complement
(opposite) of the input.

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Truth Table for NOT Gate Alternative truth table for NOT gate
X ~X X ~X
Low High 0 1
High Low 1 0
A A
NOT Gate

34
OR Gate
• The OR Gate has two or more input signals but
only one output signal.
• If any of the input signal is 1(high), the output
signal is 1(high).
• If all inputs are 0 then output is also 0.

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Two input OR Gate Three Input OR Gate
X Y F X Y Z F
0 0 0 0 0 0 0
0 1 1 0 0 1 1
1 0 1 0 1 0 1
1 1 1 0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
Two Input OR Gate
Three Inputs OR Gate
F = X + Y
F = X + Y + Z

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AND Gate
• The AND Gate can have two or more input
signals but only one output signal.
• When all the input signals are 1(high), the output
signal is 1(high).
• If any of the inputs is 0 then output is also 0.

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Two input AND Gate Three Input AND Gate
X Y F X Y Z F
0 0 0 0 0 0 0
0 1 0 0 0 1 0
1 0 0 0 1 0 0
1 1 1 0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
Three Inputs AND Gate
F = X . Y
F = X . Y . Z
Two Input AND Gate

38
Basic Postulates of Boolean Algebra
• If X  0 then X = 1 and if X  1 then X = 0
• OR Relations (Logical Addition)
– 0 + 0 = 0
– 0 + 1 = 1
– 1 + 0 = 1
– 1 + 1 = 1
0
0
0
OR
0
1
1
OR
1
0
1
OR
1
1
1
OR

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• AND Relations (Logical Multiplication)
– 0 . 0 = 0
– 0 . 1 = 0
– 1 . 0 = 0
– 1 . 1 = 1
• Compliment Rules (Logical NOT)
– ~0 = 1
– ~1 = 0
0
0
0
AND
0
1
0
AND
1
0
0
AND
1
1
1
AND
0 1
NOT
1 0
NOT

40
Principal of Duality
• It states that – starting with a boolean
relation, another boolean relation can be
derived by :
– changing each OR sign (+) to an AND sign (.)
– changing each AND sign (.) to an OR sign (+)
– replacing each ‘0’ by ‘1’ and each ‘1’ by ‘0’
• The derived relation using duality principle is
called dual of original expression.

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• For instance, we have:
0 + 0 = 0 1 . 1 = 1
0 + 1 = 1 1 . 0 = 0
1 + 0 = 1 0 . 1 = 0
1 + 1 = 1 0 . 0 = 0
changing + with . & 0
with 1 and vice versa,
the postulate II become
postulate III
postulate II postulate III

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Basic Theorems of Boolean Algebra
• Properties of 0 and 1 :
(a) 0 + X = X
(b) 1 + X = 1
(c) 0 . X = 0
(d) 1 . X = X
0
X
X
OR
1
X
1
OR
0
X
0
AND
1
X
X
AND
Gate representation of (a), (b), (c) and (d)

43
Proof using (Truth Table) –
(a) 0 + X = X
(b) 1 + X = 1
(c) 0 . X = 0
(d) 1 . X = X
0 X R
0 0 0
0 1 1
1 X R
1 0 1
1 1 1
0 X R
0 0 0
0 1 0
1 X R
1 0 0
1 1 1
R signifies the output
Tautology
Fallacy

44
• Indempotence Law
a) X + X = X
(b) X . X = X
Proof using (Truth Table) –
(a) X + X = X
(b) X . X = X
X
X
X
OR
X
X
X
AND
X X R
0 0 0
1 1 1
X X R
0 0 0
1 1 1

45
• Involution Law
(X’)’ = X
– Here, first column represents possible values of X,
second column represents complement of X (i.e.
X’) and the third column represents complement
of X’ (i.e. (X’)’ which is same as that of X.
– This law is also called double inversion law.
X
X’
(X’)’ = X
X X’ (X’)’
0 1 0
1 0 1

46
• Complementarity Law
(a) X + X’ = 1
(b) X . X’ = 0
X X’ X + X’
0 1 1
1 0 1
OR
X
X’ X + X’ = 1
X X’ X . X’
0 1 0
1 0 0
X
X’ X . X’ = 0
AND
Tautology
Fallacy

47
• Commutative Law
(a) X + Y = Y + X
(b) X . Y = Y . X
X Y X + Y Y + X
0 0 0 0
0 1 1 1
1 0 1 1
1 1 1 1
X
Y
R
OR
Y
X
R
OR
X
Y
R
AND
Y
X
R
AND
X Y X . Y Y . X
0 0 0 0
0 1 0 0
1 0 0 0
1 1 1 1

48
• Associative Law
(a) X + (Y+ Z) = (X + Y) + Z
(b) X . (Y . Z) = (X . Y) . Z
X
Y
OR
Y
Z
OR
X
R
OR
Y + Z
R
OR
X + Y
Z
Y
Z
AND
X
R
AND
Y . Z
X
Y
AND
Z
R
AND
X . Y

49
X Y Z Y + Z X + Y X + (Y + Z) (X + Y) + Z
0 0 0 0 0 0 0
0 0 1 1 0 1 1
0 1 0 1 1 1 1
0 1 1 1 1 1 1
1 0 0 0 1 1 1
1 0 1 1 1 1 1
1 1 0 1 1 1 1
1 1 1 1 1 1 1

50
• Distribution Law
(a) X . (Y+ Z) = X . Y + X . Z
(b) X + Y . Z = (X + Y) . (X + Z)
Y
OR
Y
Z
OR
X
R
OR
Y + Z
R
OR
X + Y
Z
Y
Z
AND
X
R
AND
Y . Z
Y
AND
Z
AND
X . Y
X . Z
R
X
Z
OR
X + Y
X
AND
Note : Rule (b) is the dual of rule (a) or vice-versa

51
X Y Z Y + Z X . Y X . Z X . (Y + Z) X.Y + X.Z
0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 1 0 0 0 0
0 1 1 1 0 0 0 0
1 0 0 0 0 0 0 0
1 0 1 1 0 1 1 1
1 1 0 1 1 0 1 1
1 1 1 1 1 1 1 1

52
Algebraic proof of law X + Y . Z = (X + Y) . (X + Z)
R.H.S. = (X + Y) (X + Z)
= XX + XZ + XY + YZ
= X + XZ + XY + YZ (XX = X Indempotence Law)
= X + XY + XZ + YZ
= X (1 + Y) + Z (X + Y)
= X . 1 + Z (X + Y) (1+Y = 1 property of 0 and 1)
= X+ XZ + YZ (X.1 = X property of 0 and 1)
= X (1 + Z) + YZ
= X . 1 + YZ (1 + Z = 1 property of 0 and 1)
= X + YZ (X . 1 = X property of 0 and 1)
= L.H.S.

53
• Absorption Law
(a) X + X . Y = X
(b) X . (X + Y) = X
X
X
OR
Y
AND
X . Y
Note : Rule (b) is the dual of rule (a) or vice-versa
X
X
OR
Y
AND
X + Y
X Y X . Y X + XY
0 0 0 0
0 1 0 0
1 0 0 1
1 1 1 1

54
1 0 + X = X
0 . X = 0 Properties of 0
2
1 + X = 1
1 . X = X
Properties of 1
3
X + XY = X
X . (X + Y) = X Absorption Law
4 X = X Involution
5
X + X = X
X . X = X Idempotence Law
Boolean Algebra Rules

55
6 X + X = 1
X . X = 0
Complementarity Law
7
X + Y = Y + X
X . Y = Y . X Commutative Law
8 X + (Y + Z) = (X + Y) + Z
X . (Y . Z) = (X. Y) . Z Associative Law
9 X . (Y + Z) = (X . Y) + (X . Z)
X + (Y . Z) = (X + Y) . (X + Z)
Distributive Law
10 X + X.Y = X + Y

• Augustus DeMorgan had paved the way to boolean algebra
by discovering these two important theorems –
• First Theorem : X + Y = X . Y
• Second Theorem : X . Y = X + Y
De Morgan’s Theorems
OR
X
R
Y
NOT
NOT
NOT
X
Y
Y’
AND R
X’
OR
X
R
Y
NOT
NOT
NOT
X
Y
Y’
AND R
X’
X + Y
X . Y

57
• DeMorgan’s First Theorem
Proof : According to complementarity law –
X + X’ = 1 and X.X’ = 0
i.e. a logical variable/expression when added with its
complement produces the output as ‘1’ and when multiplied
with its complement produces the output as ‘0’.
Let, P = X + Y where P, X, Y are logical
variables
Then according to complementarity law –
P + P’ = 1 and P.P’ = 0
That means, if P, X, Y are boolean variable then this
complementarity law must also hold for variable P. In other
words, if P’ i.e. (X+Y)’ = X’Y’ then
(X + Y) + X’Y’ must be equal to 1 and
(X + Y) . X’Y’ must be equal to 0

58
• Let us prove the first part, i.e.(X + Y) + X’Y’ = 1
L.H.S. = (X + Y) + X’Y’
= ((X + Y) + X’) . ((X + Y) + Y’) (X + YZ = (X+Y).
(X+Z))
= (X + X’ + Y) . (Y + Y’ + X)
= (1 + Y) . (1 + X) (X + X’ = 1)
= 1 . 1 (1 + X = 1)
= 1 (R.H.S.) Hence proved
• Let us prove the second part, i.e. (X + Y) .X’Y’ = 0
L.H.S. = (X + Y) . X’Y’
= X’Y’ . (X + Y)
= X’Y’X + X’Y’Y
= XX’Y’ + X’YY’
= 0 . Y’ + X’ . 0
= 0 + 0
= 0 (R.H.S.) Hence Proved

59
• DeMorgan’s Second Theorem
Proof : According to complementarity law –
X + X’ = 1 and X.X’ = 0
i.e. a logical variable/expression when added with its
complement produces the output as ‘1’ and when multiplied
with its complement produces the output as ‘0’.
Let, P = X . Y where P, X, Y are logical
variables
Then according to complementarity law –
P + P’ = 1 and P.P’ = 0
That means, if P, X, Y are boolean variable then this
complementarity law must also hold for variable P. In other
words, if P’ i.e. (X . Y)’ = X’ + Y’ then
XY + (X’ + Y’) = 1 and
XY . (X’ + Y’) = 0

60
• Let us prove the first part, i.e.XY + (X’ + Y’) = 1
L.H.S. = XY + (X’ + Y’)
= (X’ + Y’) + XY
= (X’ + Y’ + X) . (X’ + Y’ + Y) (X + YZ =
(X+Y).(X+Z))
= (X + X’ + Y’) . (X’ + Y + Y’)
= (1 + Y’) . (X’ + 1)
= 1 . 1
= 1 (R.H.S.) Hence proved
• Let us prove the second part, i.e. XY . (X’ + Y’) = 0
L.H.S. = XY . (X’ + Y’)
= XYX’ + XYY’
= XX’Y + XYY’
= 0 . Y + X . 0
= 0 + 0
= 0 (R.H.S.) Hence Proved

61
Assignment #2
• Prepare truth table for the following boolean algebra expressions –
(a) X (Y’ + Z’) + XY’ (b) XY’ (Z + YZ’) + Z’ (c) A[(B’ + C) + C’]
• Give the dual of the boolean expression –
(X + Y) . (X’ + Z’) . (Y + Z)
• Select the boolean expression that is not equivalent to : x . x + x . x’
(a) x . (x + x’) (b) (x + x’) . x (c) x’ (d) x
• Select the boolean expression that is equivalent to: (x + y) . (x + y’)
(a) y (b) y’ (c) x (d) x’
• Which of the following relationships represents the dual of the Boolean property:
x + x’y = x + y
(a) x’ (x + y’) = x’y’ (b) x(x’y) = xy (c) x.x’ + y = xy (d) x’ (xy’) = x’y’
(e) x (x’ + y) = xy
• Give duals for the following –
(a) X + X’Y (b) XY + XY’ + X’Y (c) (A + 0).(A . 1 . A’) (d) AB + A’B
(e) ABC + AB’C + A’BC’
• Find the complement of the following boolean function –
AB’ + C’D’
• Find the complement of F = x + yz; then show that F.F’ = 0 and F+F’ = 1
• Using DeMorgan’s Theorem, convert the following Boolean expressions to equivalent
expressions that have only OR and complement operations –
(a) F = x’y’ + x’z + y’z (b) F = (y + z’) (x + y) (y’ + z)

62
Minterms (SOP)
• Minterm is the sum of products (sop) of all the literals (with or without bar)
within the logic system.
• For eg. if X = 0, Y = 1, Z = 0 then minterm will be X’YZ’ i.e. for variable with a
value 0, take its complement and the one with value 1, multiply it as it is.
• Steps involved in minterm expansion of expression –
– First convert the given expression in sum of product forms.
– In each term, if any variable is missing, multiply that term with (missing
term + complement of missing term) factor
– Expand the expression
– Remove all duplicate terms and we will have minterm form of an
expression.
• For eg. Convert X + Y to minterms
X + Y = X . (Y + Y’) + Y . (X + X’)
= X.Y + X.Y’ + Y.X + Y.X’
= X.Y + X.Y + X.Y’ + X’.Y
= X.Y + X.Y’ + X’.Y
This process is called expansion of expression.

63
• An Another way of finding minterm.
Qs. : Find the minterm of AB + C.
Sol : It is a 3 variable expression, so a product term must have all
three letters A, B and C.
Steps involved :
• Write down all the terms
AB + C
• Insert X’s where letters are missing
ABX + XXC
• Write down all the combinations of X’s in first term
ABC , ABC’
• Write down all the combinations of X’s in second term
A’B’C, AB’C ABC, A’BC
• Add all of them. Therefore,
AB + C = ABC’ + ABC + A’B’C + AB’C + ABC + A’BC
• Now, remove all duplicate terms
= ABC’ + ABC + A’B’C + AB’C + A’BC
• The expression obtained is the desired minterm.

64
• Shorthand minterm notation :
– Following steps are to be followed :
• First of all, copy original terms
• Substitute 0’s for barred letters and 1’s for non-barred letters.
• Express the decimal equivalent of binary word as a subscript of
‘m’.
– Example : To find the minterm designation of XY’Z’.
– Solution :
• Copy original form = XY’Z’
• Substitute 1’s for non-barred and 0’s for barred letters
i.e. binary equivalent = 100 (putting 1 for X and 0 for Y’ and Z’)
• Decimal equivalent of 100
= 1 x 22
+ 0 x 21
+ 0 x 20
= 4 + 0 + 0 = 4
• Express as decimal subscript of m = m4
• Thus XY’Z’ = m4

65
Maxterm (POS)
• A Maxterm is the product of sums (pos) of all the literals (with or without the
bar) within the logic system.
• For eg. if X = 0, Y = 1, Z = 1 then maxterm will be XY’Z’ i.e. for variable with a
value 1, its complement is added and the one with value 0, take it as it is.
• Steps involved in maxterm expansion of expression –
– First convert the given expression in product of sum forms.
– In each term, if any variable is missing, add that term with (missing term .
complement of missing term) factor
– Remove all duplicate terms and we will have maxterm form of an
expression.
• For eg. Convert X . Y to maxterms
X . Y = X + (Y . Y’) . Y + (X . X’)
= (X+Y) . (X+Y’) . (Y+X) . (Y+X’)
=(X + Y) . (X + Y’) . (Y + X’)
• Maxterm can also be written as ‘M’ with a subscript which is decimal equivalent
of given input combination. For eg. X’+Y+Z+W’whose input combination is 1001
can be written as M9 as decimal equivalent of 1001 is 9.

66
Canonical Expression
• Boolean expression composed entirely either of
minterms or maxterms is referred to as Canonical
Expression.
• Represented in following two forms –
– Sum-of-Products (SOP)
• When a boolean expression is represented purely as sum of
minterms, it is said to be in Canonical Sum-of-Products form.
– Product-of-Sums(POS)
• When a boolean expression is represented purely as product
of Maxterms, it is said to be in Canonical Product-of-Sum
form.

67
• Deriving SOP expression from Truth Table
– For a given expression, prepare truth table for all possible
combinations of inputs.
– Add a new column for minterms and list the minterms for all
the combinations.
– Add all the minterms for which there is output as ‘1’. This
gives you the desired canonical SOP expression.
• Deriving SOP expression from Algebric Method
– First convert the given expression in sum of product forms.
– In each term, if any variable is missing, multiply that term
with (missing term + complement of missing term) factor
– Remove all duplicate terms and we will have minterm form
of an expression.

68
• Example : A logical network has two inputs X & Y and an output Z. The
relationship between inputs and outputs is to be as follows –
– When X = 0, Y = 0 then Z = 1
– When X = 0, Y = 1 then Z = 0
– When X = 1, Y = 0 then Z = 1
– When X = 1, Y = 1 then Z = 1
Truth table for product terms (2 input)
– Here we have added one more column to the table consisting list of product terms or
minterms.
– Adding all the terms for which the output is 1 i.e. Z = 1, we get an expression containing
only minterms, this type of expression is called canonical sum-of-products form of
expression:
X’Y’ + XY’ + XY = Z
X Y Z Product Terms
0 0 1 X’Y’
0 1 0 X’Y
1 0 1 XY’
1 1 1 XY

69
Example : Convert [(X’Y) + (X’Z’)]’ into canonical sum of product form.
Solution :
• Rule 1 : Simplify the given expression using appropriate theorem/rules :
[(X’Y) + (X’Z’)]’ = (X + Y’) (X + Z) (using Demorgans Theorem)
= X + Y’Z [X + YZ = (X+Y).(X+Z)]
Since it is a 3 variable expression, a product term must have all 3 variables.
• Rule 2 : Wherever a literal is missing, multiply that term with missing term +
complement of missing term) factor, i.e.
= X + Y’Z
= X(Y+Y’)(Z+Z’) + (X+X’)Y’Z
= (XY + XY’)(Z+Z’) + (X+X’)Y’Z
= XYZ + XYZ’ + XY’Z + XY’Z’ + XY’Z + X’Y’Z
• Rule 3 : Remove all duplicate terms i.e.
= XYZ + XY’Z + XYZ’ + XY’Z’ + X’Y’Z
This is the desired Canonical Sum-of-Products form.
– Above SOP expression can also be represented by following shorthand notation i.e.
F = (1, 4, 5, 6, 7) or F =  m(1, 4, 5, 6, 7)
where, ‘F’ is a variable function and ‘m’ is a notation for minterm.
i.e. F = m1 + m4 + m5 + m6 + m7

70
• Example : Convert the following three input function ‘F’
denoted as F = (0, 1, 2, 5) into its canonical sum-of-
products form.
• Solution : If three inputs we take as X, Y and Z then
F = m0 + m1 + m2 + m5
where , m0 = 0 0 0 = X’ Y’ Z’
m1 = 0 0 1 = X’ Y’ Z
m2 = 0 1 0 = X’ Y Z’
m5 = 1 0 1 = X Y’ Z
So, Canonical SOP form of the expression is –
X’ Y’ Z’ + X’ Y’Z + X’ Y Z’ + X Y’ Z

71
• Deriving POS expression from Truth Table
– prepare truth table of inputs and outputs.
– Add one additional column of sum terms. For each row of a
table, a sum term is formed by adding all the variable in
complemented or un-complemented form i.e. if input value
for a given variable is ‘1’, variable is complemented and if
‘0’, variable is not complemented.
i.e. for X=0, Y=1, Z=1, sum term will be X + Y’ + Z’
– The desired expression is product of the sums (POS) from
the rows in which the output is ‘0’.

72
• Example : Express in the product of sum form, the
boolean function f(x, y, z), the truth table for which is
given below –
X Y Z F
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1

73
• Sol : Add a new column containing Maxterms. Now the
table is as follows :
• Now by multiplying Maxterms for the output 0’s, we get
the desired product-of-sums expression which is –
(X + Y + Z’) (X + Y’ + Z’) (X’ + Y + Z’)
X Y Z F Maxterm
0 0 0 1 X + Y + Z
0 0 1 0 X + Y + Z’
0 1 0 1 X + Y’ + Z
0 1 1 0 X + Y’ + Z’
1 0 0 1 X’ + Y + Z
1 0 1 0 X’ + Y + Z’
1 1 0 1 X’ + Y’ + Z
1 1 1 1 X’ + Y’ + Z’

74
• Express X’Y + Y(Z’(Z’ + Y)) into canonical product-of-sums form.
• Rule 1 : Simplify the given expression using appropriate theorems/rules.
X’Y + Y(Z’(Z’ + Y)) = X’Y + Y(Z’Z’ + YZ’)
= X’Y + Y(Z’ + YZ’)
= X’Y + Y.Z’(1 + Y)
= X’Y + YZ’.1
= X’Y + YZ’
• Rule 2 : To convert into product of sums form, apply the boolean algebra rule which states that
X + YZ = (X + Y) . (X + Z)
• Now applying this rule we get,
X’Y + YZ’ = (X’Y + Y).(X’Y + Z’)
= (Y + X’Y).(Z’ + X’Y)
= (Y + X’) . (Y + Y) . (Z’ + X’) . (Z’ + Y)
= (X’ + Y) . (Y) . (X’ + Z’) . (Y + Z’)
• Now, this is in product of sums form but not in canonical product of sums form (in canonical
expression all the sum terms are Maxterms).
• Rule 3 : After converting into product of sum terms, in a sum term for missing variable add
[(missing variable ). (complement of missing variable)] e.g. if variable Y is missing then add Y.Y’
i.e. (X’ + Y) . (Y) . (X’ + Z’) . (Y + Z’)
• Terms 1 2 3 4
= (X’ + Y + ZZ’) . (XX’ + Y + ZZ’) . (X’ + YY’ + Z’) . (XX’ + Y + Z’)

75
• Rule 4 : Keep on simplifying the expression (using the rule, X + YZ =
(X+Y).(X+Z)) until you get product of sum terms which are Maxterms.
= (X’ + Y + ZZ’) . (XX’ + Y + ZZ’) . (X’ + YY’ + Z’) . (XX’ + Y + Z’)
= (X’ + Y + Z). (X’ + Y + Z’) . (XX’ + Y + Z) . (XX’ + Y + Z’) . (X’ + Y + Z’) .
(X’ + Y’ + Z’) . (X + Y + Z’) . (X’ + Y + Z’)
= (X’ + Y + Z). (X’ + Y + Z’) . (X + Y + Z) . (X’ + Y + Z) . (X + Y + Z’) .
(X’ + Y + Z’) . (X’ + Y + Z’) . (X’ + Y’ + Z’) . (X + Y + Z’) . (X’ + Y + Z’)
• Rule 5 : Removing all duplicate terms, we get the desired canonical
product of sums form of expression.
= (X’ + Y + Z) . (X’ + Y + Z’) . (X + Y + Z) . (X + Y + Z’) . (X’ + Y’ + Z’)
or
= (X + Y + Z) . (X + Y + Z’) . (X’ + Y + Z) . (X’ + Y + Z’) . (X’ + Y’ + Z’)
• Above POS expression can also be represented by following shorthand
notation i.e.
F = (0, 1, 4, 5, 7) or F = M(0, 1, 4, 5, 7)
where, ‘F’ is a variable function and ‘M’ is a notation for maxterm.
i.e. F = M0 . M1 . M4 . M5 . M7

76
Minimization of Boolean Expression
• Minimized boolean expression means less number of
gates which means simplified circuitry.
• Two ways of simplification –
– using Algebraic Method
• makes use of boolean postulates, rules and theorems to
simplify the expression.
– using Karnaugh Maps (or K-Map)
• named after its originator Maurice Karnaugh)
• it is a graphical display of the fundamental products in a
truth table
• it is nothing but a rectangle made up of certain number of
squares, each square representing a Maxterm or Minterm.

77
• using Algebraic Method
Example 1 : Simplify AB’CD’ + AB’CD + ABCD’ + ABCD
Solution : = AB’CD’ + AB’CD + ABCD’ + ABCD
= AB’C(D’ + D) + ABC(D’+D)
= AB’C + ABC
= AC(B + B’)
= AC
Example 2 : Reduce the expression (XY)’ + X’ + XY
Solution : = (XY)’ + X’ + XY
= X’ + Y’ + X’ + XY
= X’ + Y’ + XY
= X’ + XY + Y’
= (X’ + X).(X’ + Y) + Y’
= X’ + Y + Y’
= X’ + 1
= 1

78
Sum-of-products reduction using K-Map
• In SOP reduction each square of K-map represents
a minterm of the given function.
• for a function of ‘n’ variables, there would be a
map of 2n
squares, each representing a minterm.
• for SOP reduction the map is filled in by placing 1’s
in squares whose minterms lead to 1 as output.
• In every square a number is written. These
subscripted numbers denote that this square
corresponds to that number’s minterm.
• Note that the squares are numbered as (eg. for 3
variable input) 0, 1, 3, 2 then 4, 5, 7, 6 and so on.

79
Y
X
[0] Y’ [1] Y
[0] X’ X’Y’
0
X’Y
1
[1] X XY’
2
XY
3
Y
X
[0] Y’ [1] Y
[0] X’
0 1
[1] X
2 3
YZ
X
[00] Y’Z’ [01] Y’Z [11]YZ [10]YZ’
[0] X’ X’Y’Z’
0
X’Y’Z
1
X’YZ
3
X’YZ’
2
[1] X XY’Z’
4
XY’Z
5
XYZ
7
XYZ’
6
YZ
X
[00] Y’Z’ [01] Y’Z [11]YZ [10]YZ’
[0] X’
0 1 3 2
[1] X
4 5 7 6
2-variable K-map representing minterms 3-variable K-map representing minterms

80
YZ
WX [00] Y’Z’ [01] Y’Z [11]YZ [10]YZ’
[00] W’X’ W’X’Y’Z’
0
W’X’Y’Z
1
W’X’YZ
3
W’X’YZ’
2
[01] W’X W’XY’Z’
4
W’XY’Z
5
W’XYZ
7
W’XYZ’
6
[11] WX WXY’Z’
12
WXY’Z
13
WXYZ
15
WXYZ’
14
[10] WX’ WX’Y’Z’
8
WX’Y’Z
9
WX’YZ
11
WX’YZ’
10
YZ
WX [00] Y’Z’ [01] Y’Z [11]YZ [10]YZ’
[00] W’X’
0 1 3 2
[01] W’X
4 5 7 6
[11] WX
12 13 15 14
[10] WX’
8 9 11 10
4-variable K-map
representing minterms
The binary code 00, 01, 11, 10 is
called Gray Code. Gray Code is
the binary code in which each
successive number differs only in
one place. That is why box
numbering scheme follows above
order only.

81
• How to map in K-map?
• Suppose, we have been given with the following truth table for mapping -
• Canonical SP expression for this table is
F = AB’ + AB or F = (2, 3)
• The blank K-map for 2-variable will be
• For minterm m2 and m3 the output is 1. Thus, mark 1 in the squares for m2 and m3 i.e. square
numbered as 2 and 3.
• After entering 1’s for all ‘1’ output, enter 0’s in all blank squares. The K-map will now look like as –
• Same is the method for mapping 3-variable, 4-variable etc.
A B F
0 0 0
0 1 0
1 0 1
1 1 1
B
A
[0] B’ [1] B
[0] A’ 0 1
[1] A 2 3
B
A
[0] B’ [1] B
[0] A’ 0 0
[1] A 1 1

82
• How to reduce boolean expressio in SOP form using K-
map?
• First we have to mark pairs, quads and octets.
– adjacent 1’ are encircled.
– if 2 adjacent 1’s are encircled it makes a pair, if 4 adjacent 1’s
are encircled it makes a quad, if 8 adjacent 1’s are encircled it
makes a octet.
• While encircling groups of 1’s, firstly search for octets,
then for quads and lastly go for pair. This is because a
bigger group removes more variable thereby making the
resultant expression simpler.
• Remove the variable which changes its state from
complemented to un-complemented state or vice-versa.
• Pair removes one variable only.

83
• Reduction of a Pair –
• In the K-map shown below, after mapping a
given function F(W, X, Y Z) two pairs have been
marked. Pair-1 is m0 + m4 (group of 0th
minterm
and 4th
minterm). Pair-2 is m14 + m15.
YZ
WX [00] Y’Z’ [01] Y’Z [11]YZ [10]YZ’
[00] W’X’ 1
0
0
1
0
3
0
2
[01] W’X 1
4
0
5
0
7
0
6
[11] WX 0
12
0
13
1
15
1
14
[10] WX’ 0
8
0
9
0
11
0
10

84
• Observe that Pair-1 is a vertical pair. Moving vertically in pair-1,
see one variable ‘X’ is changing its state from X’ to X as m0 is
W’X’Y’Z’ and m4 is W’XY’Z’. Compare the two and we see
W’X’Y’Z’ changes to W’XY’Z’. So the variable ‘X’ can be
removed.
• Thus reduced expression for Pair-1 is W’Y’Z’.
• We can prove the same algebraically also as follows –
Pair – 1 = m0 + m4
= W’X’Y’Z’ + W’XY’Z’
= W’Y’Z’ (X’ + X)
= W’Y’Z’ . 1
= W’Y’Z’
• Similarly, reduced expression for Pair-2 (m14 + m15) will be WXY
as WXYZ (m14) changes to WXYZ’(m15). ‘Z’ will be removed as it
is changing its state from Z’ to Z.

85
• Reduction of a Quad –
• In the K-map shown below, after mapping a
given function F(W, X, Y Z) two quads have been
marked. Quad-1 is m0+m4+m12+m8 and Quad-2 is
m7+m6+m15+m14.
YZ
WX [00] Y’Z’ [01] Y’Z [11]YZ [10]YZ’
[00] W’X’ 1
0
0
1
0
3
0
2
[01] W’X 1
4
0
5
1
7
1
6
[11] WX 1
12
0
13
1
15
1
14
[10] WX’ 1
8
0
9
0
11
0
10

86
• Remove the two variables which changes their
states.
• A Quad removes two variables.
• In the above example we see that –
– In Quad-1 two variables changes their states i.e. W
and X are changing their states, so these two
variables will be removed.
– Thus reduced expression for Quad-1 is Y’Z’.
– Similarly in Quad-2, W and Z are removed as these
two variables are changing their states.
– Thus reduced expression for Quad-2 is XY.
– Final reduced expression is :
Y’Z’ + XY

87
• Reduction of an Octect –
• Suppose we have K-map with an octet marked as
shown below -
YZ
WX [00] Y’Z’ [01] Y’Z [11]YZ [10]YZ’
[00] W’X’ 0
0
0
1
0
3
0
2
[01] W’X 0
4
0
5
0
7
0
6
[11] WX 1
12
1
13
1
15
1
14
[10] WX’ 1
8
1
9
1
11
1
10

88
• Remove the three variables which changes
their states.
• A Octet removes three variables.
• In the above example we see that –
– While moving horizontally in the octet two
variables Y and Z are removed and moving
vertically one variable X is removed.
– Thus eliminating X, Y and Z, the reduced
expression for the octet is W only.
– Final reduced expression is :
W

89
Other things to be taken care of before arriving
at the final expression -
• Map Rolling
– This is a special property of K-Map that its opposite
edges squares and corner squares are considered
contiguous.
– map rolling means roll the map i.e. consider the
map as if its left edges are touching the right edges
and top edges are touching the bottom edges.
– Following pairs, quads and octets are marked after
rolling the map.

90
YZ
WX [00] Y’Z’ [01] Y’Z [11]YZ [10]YZ’
[00] W’X’
0 1
1
3 2
[01] W’X 1
4 5 7
1
6
[11] WX
12 13 15 14
[10] WX’
8 9
1
11 10
YZ
WX [00] Y’Z’ [01] Y’Z [11]YZ [10]YZ’
[00] W’X’
0
1
1
1
3 2
[01] W’X 1
4 5 7
1
6
[11] WX 1
12 13 15
1
14
[10] WX’
8
1
9
1
11 10

91
YZ
WX [00] Y’Z’ [01] Y’Z [11]YZ [10]YZ’
[00] W’X’ 1
0 1 3
1
2
[01] W’X
4 5 7 6
[11] WX
12 13 15 14
[10] WX’ 1
8 9 11
1
10
YZ
WX [00] Y’Z’ [01] Y’Z [11]YZ [10]YZ’
[00] W’X’ 1
0
1
1
1
3
1
2
[01] W’X
4 5 7 6
[11] WX
12 13 15 14
[10] WX’ 1
8
1
9
1
11
1
10

92
• Overlapping Groups
– Overlapping means same ‘1’ can be encircled
more than once.
– For eg. consider the following K-map -
YZ
WX
[00] Y’Z’ [01] Y’Z [11]YZ [10]YZ’
[00] W’X’
0 1 3 2
[01] W’X
4
1
5
1
7
1
6
[11] WX
12 13
1
15
1
14
[10] WX’
8 9 11
1
10

93
• Observe that ‘1’ for m7 has been encircled
twice.
– Once for Pair-1 (m5 + m7) and again for Quad (m7
+ m6 + m15 + m14).
• Also ‘1’ for m14 has been encircled twice.
– For the Quad and for Pair-2 (m14 + m10).
• Reduced expression for –
– Pair-1 is W’XZ
– Quad is XY
– Pair-2 is WYZ’
• Thus, final reduced expression for this map is -
W’XZ + XY + WYZ’

• Redundant Groups
– Redundant group is a group whose all 1’s are overlapped by
other groups (i.e. pairs, quads, octets).
– Redundant groups must be removed.
– For eg. consider the following K-map –
with redundant group without redundant group
94
YZ
WX
[00] Y’Z’ [01] Y’Z [11]YZ [10]YZ’
[00] W’X’
0 1 3 2
[01] W’X 1
4
1
5 7 6
[11] WX
12
1
13
1
15 14
[10] WX’
8 9 11 10
YZ
WX
[00] Y’Z’ [01] Y’Z [11]YZ [10]YZ’
[00] W’X’
0 1 3 2
[01] W’X 1
4
1
5 7 6
[11] WX
12
1
13
1
15 14
[10] WX’
8 9 11 10

95
• There are three pairs :
– Pair-1 (m4 + m5)
– Pair-2 (m5 + m13)
– Pair-3 (m13+ m15)
• Pair-2 is a redundant group as its all 1’s are marked
by other groups.
• With this redundant group the reduced expression
will be –
W’XY’ + XY’Z + WXZ
• After removing the redundant group, we get the
required K-map.
• The reduced expression for required K-map is-
W’XY’ + WXZ

96
Product-of-Sum reduction using K-Map
• In POS each square of K-map represents a Maxterm.
• The map is just the same as that of the used in SOP
reduction.
• For POS reduction the map is filled by placing 0’s in
squares whose Maxterm lead to output 0.
• In POS complemented letters represent 1’s and un-
complemented letters represent 0’s.
• For POS expression adjacent 0’s are encircled in the form
of pairs, quads and octets.
• Following are 2, 3, 4 variable K-maps for POS reduction

97
Y
X
[0] Y [1] Y’
[0] X X+Y
0
X+Y’
1
[1] X’ X’+Y
2
X’+Y’
3
Y
X
[0] Y [1] Y’
[0] X
0 1
[1] X’
2 3
YZ
X
[00] Y+Z [01] Y+Z’ [11]Y’+Z’ [10]Y’+Z
[0] X X+Y+Z
0
X+Y+Z’
1
X+Y’+Z’
3
X+Y’+Z
2
[1] X’ X’+Y+Z
4
X’+Y+Z’
5
X’+Y’+Z’
7
X’+Y’+Z
6
YZ
X
[00] Y+Z [01] Y+Z’ [11]Y’+Z’ [10]Y’+Z
[0] X
0 1 3 2
[1] X’
4 5 7 6
2-variable K-map representing Maxterms 3-variable K-map representing Maxterms

98
YZ
WX [00] Y+Z [01] Y+Z’ [11]Y’+Z’ [10]Y’+Z
[00] W+X W+X+Y+Z
0
W+X+Y+Z’
1
W+X+Y’+Z’
3
W+X+Y’+Z
2
[01] W+X’ W+X’+Y+Z
4
W+X’+Y+Z’
5
W+X’+Y’+Z’
7
W+X’+Y’+Z
6
[11] W’+X’ W’+X’+Y+Z
12
W’+X’+Y+Z’
13
W’+X’+Y’+Z’
15
W’+X’+Y’+Z
14
[10] W’+X W’+X+Y+Z
8
W’+X+Y+Z’
9
W’+X+Y’+Z’
11
W’+X+Y’+Z
10
YZ
WX [00] Y+Z [01] Y+Z’ [11]Y’+Z’ [10]Y’+Z
[00] W+X
0 1 3 2
[01] W+X’
4 5 7 6
[11] W’+X’
12 13 15 14
[10] W’+X
8 9 11 10
4-variable
K-map
representing
Maxterms

99
Assignment #3
• Reduce
F(a, b, c, d) = m(0, 2, 7, 8, 10, 15)
using Karnaugh map.
• What is the simplified Boolean equation for the
function –
F(A,B,C,D) = (7,9,10,11,12,13,14,15)
• Find the minimum POS expression of –
F(A,B,C,D) = (0,1,3,5,6,7,10,14,15)

100
NOR Gate
• If either of the two input is 1 (high) the output
will be 0 (low).
• NOR gate is nothing but inverted OR gate i.e. If all
the inputs are 0 (low) then the output signal is
1(high).

101
Two input NOR Gate Three Input NOR Gate
X Y F X Y Z F
0 0 1 0 0 0 1
0 1 0 0 0 1 0
1 0 0 0 1 0 0
1 1 0 0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
Two Input NOR Gate
Three Inputs NOR Gate
Y = A + B
F = A + B + C

102
NAND Gate
• NAND gate is nothing but inverted AND gate i.e.
If all the inputs are 1 (high) then the output
signal is 0(low), otherwise for all other
combination, it produces a 1 (high) output..

103
Two input NAND Gate Three Input NAND Gate
X Y F X Y Z F
0 0 1 0 0 0 1
0 1 1 0 0 1 1
1 0 1 0 1 0 1
1 1 0 0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Three Inputs NAND Gate
F = A . B
F = A . B . C
Two Input NAND Gate

104
XOR Gate (Exclusive OR Gate)
• Can have two or more input signals but
produces one output signal.
• It produces output 1 for only those input
combinations that have odd number of 1’s.
• In Boolean algebra  sign stands for XOR
operation. Thus A XOR B can be written as
AB.
• Also, AB = AB’ + A’B.

105
Two input XOR Gate Three Input XOR Gate
X Y F X Y Z F
0 0 0 0 0 0 0
0 1 1 0 0 1 1
1 0 1 0 1 0 1
1 1 0 0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
F = A  B
Two Input XOR Gate

106
XNOR Gate (Exclusive NOR Gate)
• Can have two or more input signals but produces one output
signal.
• It is logical equivalent to inverted XOR Gate i.e. XOR gate followed
by NOT gate.
• It produces output 1 for only those input combinations that have
even number of 1’s.
• In Boolean algebra  sign stands for XNOR operation. Thus A
XNOR B can be written as AB.
• Also, A  B = AB + A’B’ OR A  B = (A’+B) . (A +
B’)

107
Two input XNOR Gate Three Input XNOR Gate
X Y F X Y Z F
0 0 1 0 0 0 1
0 1 0 0 0 1 0
1 0 0 0 1 0 0
1 1 1 0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
X = A  B
Two Input XNOR Gate

108
• Design a circuit to realize the following –
– F(A,B,C) = AB + AC’ + B’A’C
– F(X,Y,Z)= (X+Y).(X’+Z’).(Y+Z)
Assignment #4

109
NAND, NOR as Universal Gates
• NAND, NOR gates are also referred to as
Universal Gates because other functions like
AND, OR can easily be implemented.
• NAND-to-NAND Logic
– Derive simplified sum-of-products expression.
– Draw a circuit diagram using AND, OR gates.
– Just replace AND and OR gates with NAND gates.
• AND, OR and NOT operations from NAND gates
are shown below -

111
• AND Operation –
X . Y = (X NAND Y) NAND (X NAND Y)
• Proof - X NAND Y = (X.Y)’
= X’ + Y’
(X NAND Y) NAND (X NAND Y)
= (X’ + Y’) NAND (X’ + Y’)
= [(X’ + Y’) . (X’ + Y’)]’
= (X’ + Y’)’ + (X’ + Y’)’
= (X’’ . Y’’) + (X’’ . Y’’)
= (X . Y) + (X . Y)
= X . Y

112
• OR Operation –
X + Y = (X NAND X) NAND (Y NAND Y)
• Proof - X NAND X = (X.X)’
= X’ + X’
= X’
Similarly Y NAND Y = Y’
Therefore,
(X NAND X) NAND (Y NAND Y)
= (X’) NAND (Y’)
= (X’ . Y’)’
= X’’ + Y’’
= X + Y

113
• NOT Operation –
NOT X = X NAND X
= (X . X)’
= X’ i.e. NOT X

114
• NOR-to-NOR Logic
– Derive simplified product-of-sum expression.
– Draw a circuit diagram using OR, AND gates.
– Just replace OR and AND gates with NOR gates.
• OR Operation
• AND Operation
• NOT Operation
• AND, OR and NOT operations from NOR gates are
shown below -
A + B = (A NOR B) NOR (A NOR B)
A . B = (A NOR A) NOR (B NOR B)
A = A NOR A

116
• Draw the circuit diagram for the functions given
below using NAND gates only –
– XYZ’ + ZX’
– YZ + XZ
– AB + BC + CD
– AB’C + C’B
• Draw the circuit diagram for the functions given
below using NOR gates only –
– (X + Y) . (Y + Z) . (Z + X)
– (A’ + B’ + C’) . (A + B’ + C). (A + B + C’)
– A . (B’ + C)
Assignment #5

117
(Combinational Building Blocks)
• Contents :
– Multiplexer
– Decoder
– Encoder
– Adder
– Subtracter

118
Application of Logic Gates
• Logic Gates are used in following useful applications-
– Adders
• Half Adder
• Full Adder
–Subtractors
• Half Subtractor
• Full Subtractor
– Encoder
– Decoder

119
• Adders
Before getting into details, we know that –
C S
0 + 0 = 0 0
0 + 1 = 0 1
1 + 0 = 0 1
1 + 1 = 1 0
1 + 1 + 1 = 1 1
See, the result is having two bits, right bit gives you
the SUM and left bit gives your the CARRY.

120
• Half Adder :
– It is a logic circuit that adds two bits.
– It produces the outputs : SUM and CARRY
– The Boolean equation for SUM and CARRY are :
SUM = x  y OR S = x’y+ xy’
CARRY = x . y
– Therefore, SUM produces 1 when ‘x’ and ‘y’ are different and
CARRY is ‘1’ when both ‘x’ and ‘y’ both are ‘1’.
– Truth Table & Circuit Diagram for Half Adder is given below :
X Y Carry Sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

121
• Full Adder :
– Application of Half Adder are limited as only two bits can be added.
– It is a logic circuit that can add three bits.
– It produces two outputs : SUM and CARRY
– The Boolean equation for SUM and CARRY are :
SUM = x  y  z (SUM is x XOR y XOR z)
CARRY = xy + yz + zx (CARRY is xy OR yz OR zx)
– Truth Table for Full Adder is given below :
X Y Z Carry Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

122
– Therefore, SUM produces 1 when input is containing
odd number of 1’s and CARRY is ‘1’ when there are
two or more 1’s in input.
– Circuit Diagram of Full Adder :

123
• Maps for Full Adder
SUM
S = x’y’z + x’yz’ + xy’z’ + xyz
CARRY
C = xy + xz + yz
YZ
X
[00] Y’Z’ [01] Y’Z [11]YZ [10]YZ’
[0] X’
1
1
[1] X 1 1
YZ
X
[00] Y’Z’ [01] Y’Z [11]YZ [10]YZ’
[0] X’ 1
[1] X 1 1 1

124
• A Full Adder can be implemented with two Half Adders and one OR
Gate.
• The Sum ‘S’ output from the second half-adder is the exclusive-OR
(XOR) of ‘z’ and the output of the first half-adder, giving :
S = z  (x  y)
= z’(xy’ +x’y) + z(xy’ + x’y)’
= z’(xy’ + x’y) + z(xy + x’y’)
= xy’z’ + x’yz’ + xyz + x’y’z
• The Carry output is :
C = z(xy’ + x’y) + xy
= xy’z + x’yz + xy
y
x
z

125
• Half Subtractor
– A combination circuit that subtracts two bits and produces their difference.
– Needs two outputs:
• One output generates the difference and designated by ‘D’
• Second output generates the binary signal that a ‘1’ has been borrowed.
– Truth table for half subtractor :
x y B D
0 - 0 = 0 0
0 - 1 = 1 1
1 - 0 = 0 1
1 - 1 = 0 0
– The output borrow ‘B’ is a ‘0’ as long as x>=y. It is a ‘1’ when x = 0 and y = 1.
– The Boolean function for ‘B’ and ‘D’ are :
D = x’y + xy’
B = x’y
– Note that the logic for ‘D’ is exactly the same as the logic for ‘S’ in the half
adder.

126
• Full Subtractor
– Performs a subtraction between two bits, taking into account that a ‘1’ may
have been borrowed by a lower significant stage.
– has three input and two outputs
– The three inputs (here x, y, z) denote the minuend, subtrahend and previous
borrow respectively.
– The two outputs (here D, B) represents the difference and borrow
respectively.
– The truth table is as under :
x y z = B D
(x – y – z)
0 0 0 = 0 0
0 0 1 = 1 1
0 1 0 = 1 1
0 1 1 = 1 0
1 0 0 = 0 1
1 0 1 = 0 0
1 1 0 = 0 0
1 1 1 = 1 1

127
• Maps for Full Subtractor
Difference
D = x’y’z + x’yz’ + xy’z’ + xyz
Borrow
B = x’y + x’z + yz
YZ
X
[00] Y’Z’ [01] Y’Z [11]YZ [10]YZ’
[0] X’
1
1
[1] X 1 1
YZ
X
[00] Y’Z’ [01] Y’Z [11]YZ [10]YZ’
[0] X’ 1 1 1
[1] X 1

128
• Encoder
– Process of converting signals from one type to another
type is called encoding e.g. decimal to binary, decimal to
hexadecimal etc.
– The logic circuit which performs this job is called encoder.
• Decimal to Binary Encoder
– Converts decimal numbers to equivalent binary numbers.
– Number of output lines required is determined as-
• 2n
must be >= I, where ‘I’ represents the total numbers to be
encoded. for eg. to convert numbers (0-9) i.e. 10 numbers into
binary, then number of output of lines of the encoder will be 4
because 2n
>= 10, to make it true, ‘n’ must be 4 i.e. 24
>= 10.

130
• The switches used are push button which on pressing
provide a high ‘1’ input to attached OR gates.
• Notice,
– Gates Y3, Y2, Y1 and Y0 are connected to inputs wherever
there are 1’s. For eg.
• when 6th
push button is pressed then Y2 and Y1 OR
gates get high ‘1’ inputs, hence produce high ‘1’
output, therefore the output is
Y3Y2Y1Y0 = 0 1 1 0 = 6
• Similary, when 4th
push button is pressed, only Y2 gets
high ‘1’ inputs, therefore only Y2’s output is high ‘1’,
therefore the output is
Y3Y2Y1Y0 = 0 1 0 0 = 4

131
• Hexadecimal to Binary Encoder : This encoder converts a
hexadecimal number to its binary equivalent.
F3
F2
F1 F0

132
• When a push button is pressed, its binary equivalent is
generated. For instance, if push button ‘A’ (decimal 10) is
pressed, F3 and F1 produces ‘1’ as outputs as they get ‘1’
(high) inputs. Thus the output word is :
10102 =1010 =A16
• For push button D (1310) the output word is :
11012 = 1310 = D16

133
• Decoder
– A decoder is a circuit which converts binary number
into its equivalent decimal form.
– In a decoder if there are 3 input lines, it ill be capable
of producing 8 distinct outputs.

134
• Notice here when input is
00 F0 produces 1 output
i.e. whenever there is a ‘0’ in the input , line is
connected to the inverted input and, for every ‘1’ in
the input, line is connected to un-complemented
input.

136
• Implementing a Full Adder circuit with a decoder
• We know that the functions for full adder in the sum-of-minterm
form is written as : S(x, y, z) = (1, 2, 4, 7)
C(x, y, z) = (3, 5, 6, 7)
• Now to implement these, we need a 3-to-8 line decoder as there
are 3-inputs and 8 minterms (23
) outputs.
• Now, we required two OR gates for outputs sum ‘S’ and carry ‘C’.
• The OR gate for output ‘S’ forms the sum of minterms 1, 2, 4 & 7.
The OR gate for output ‘C’ forms the sum of minterms 3, 5, 6 & 7.

139
Multiplexer
• Multiplex means many-to-one.
• It is a circuit with many inputs but only one output.
• It means transmitting a large number of information
units over a small number of channels or lines.
• A multiplexer (abbreviated MUX) is used when a
complex logic circuit is to be shared by a number of
input signals. This process is called multiplexing.
• Normally, there are 2n
input lines whose bit
combinations determine which input is selected.
• It is also called data selector as it selects one of the
several input and then feeds it through to a single
output.

140
Boolean function implementation using MUX
• A Boolean function of ‘n’ variables can be
implemented with 2n-1
to 1 multiplexer.
• If we have a Boolean function of ‘n’ variables, we
take (n-1) of these variables and connect them to
the selection lines of a multiplexer.
• The remaining single variable of the function is
used for the inputs of the multiplexer i.e. if the left
out variable is X, the inputs of the multiplexer are
chosen to be either X or X’ or 1 or 0.

141
For eg. : Consider the function F(x, y, z) = (1,3,5,6)
here, n =3 2n-1
= 23-1
= 22
= 4
Truth table for the above function –
This 3 variable Boolean function can be implemented
using 4-to-1 multiplexer by following the steps
described below :
X Y Z F minterm
0 0 0 0 X’ Y’ Z’
0 0 1 1 X’ Y’ Z
0 1 0 0 X’ Y Z’
0 1 1 1 X’ Y Z
1 0 0 0 X Y’ Z’
1 0 1 1 X Y’ Z
1 1 0 1 X Y Z’
1 1 1 0 X Y Z

142
• Express the function in its sum-of-minterms form.
• Single out the leftmost variable from the ordered set of
variables.
– i.e. if three variables are written in order xyz, the left most
variable ‘x’ is singled out. If the variables are written in order
yzx, then ‘y’ is singled out. Similarly from zxy, ‘z’ is singled
out.
• Connect the (n-1) variables to the selection lines of the
multiplexer.
– Make sure that the higher order variable is connected to
higher order selection line (the left most variable is the
highest order variable). Thus, the lowest-order variable is
connected to the lowest-order selection line (S0), the next
order variable is connected to the next order selection line
(S1) and so on.

143
• Now, consider the single variable (highest order variable) which in our case is
‘x’. If you have a look at the truth table of F(x, y, z), ‘x’ is ‘0’ for the first half of
the minterms (i.e. for m0, m1, m2, m3 ‘x’ is ‘0’) and it is ‘1’ for the second half
of the minterm (i.e. for m4, m5, m6, m7 ‘x’ is ‘1’). Thus ‘x’ is complemented in
the minterms 0 to (2n
/2 – 1) i.e. for m0, m1, m2, m3 in our case (0 to (23
/2 – 1)
means 0 to 8/2 – 1 i.e. 0 to 3) and ‘x’ remains un-complemented for rest of
the minterms 2n
/2 to 2n
– 1 i.e. m4, m5, m6, m7 (i.e. n = 3, 23
/2 to 23
– 1 mean
4 to 7).
• Now, list the inputs of the multiplexer and under them list all the minterms in
two rows. The first row lists all those minterms where ‘x’ is complemented,
and the second row all the minterms with ‘x’ un-complemented.
• Circle all the minterms of the function and inspect each column separated as
explained in the next step.
Io I1 I2 I3
X’ 0 1 2 3
X 4 5 6 7

144
• This step decides the values to be applied to inputs according to following
rules :
– Rule 1 : If the two minterms in a column are not circled, apply 0 to the
corresponding multiplexer input.
– Rule 2 : If the two minterms are circled, apply 1 to the corresponding
multiplexer input.
– Rule 3 : If the bottom minterms is circled and the top minterms is not
circled, apply x (in un-complemented form) to the corresponding
multiplexer input.
– Rule 4 : If the top minterms is circled and the bottom minterms is not
circled, apply x’ (in complemented form) to the corresponding
multiplexer input.
– That is, Io I1 I2 I3
X’ 0 1 2 3
X 4 5 6 7
0 1 x x’

145
• Thus,
I0 is applied 0 (Rule 1)
I2 is applied x (Rule 3)
I3 is applied x’ (Rule 4)
• Now the given function can be implemented using MUX as shown below:
• The equation for a 4 x 1 MUX is :
S’0S’1 I0 + S’0S1 I1 + S0S’1 I2 + S0S1 I3

146
• Example : Implement the following function with a multiplexer :
F(a, b, c, d)= (0, 1, 3, 4, 8, 9, 15)
• Solution : It is a four variable function i.e. n = 4. Thus it will be implemented using 2n–1
to 1
multiplexer i.e. 8 to 1 multiplexer.
The selection lines would be 4 – 1 = 3.
Ordered Sequence = abcd
Singled out variable = a
The variables to be applied to the selection lines= bcd
Implementation table is:
I2, I5, I6 is applied 0 (Rule 1)
I3 , I4 is applied a’ (Rule 4)
I7 is applied a (Rule 3)
Io I1 I2 I3 I4 I5 I6 I7
a’ 0 1 2 3 4 5 6 7
a 8 9 10 11 12 13 14 15
1 1 0 a’ a’ 0 0 a

147
Io
I1
I2
I3
I4
I5
I6
I7
S2 S1 S0
1
0
a’
a
b
c
d
8 x 1
MUX
Y F
The equation for a 8 x 1 MUX is :
F = S’0S’1S’2 I0 + S’0S’1S2 I1 + S’0S1S’2 I2 + S’0S1S2 I3 + S0S’1S’2 I4 + S0S’1S2 I5 + S0S1S’2 I6 + S0S1S2 I7

148
• Implementation through scaled down MUX
• For a given function, decide how many selection lines are needed. For 2x1 MUX, we need
one selection line as 21
= 2 so 1 variable is needed for selection line.
• Select one variable selection line, say we selected variable a.
Now the possible inputs through this selection line (S0) would be 0 and 1 i.e. a’ and a.
• Now factor out given function so that the function be represented in terms of factors
multiplied by a’ and a (the inputs to selection line).
Example : Let us assume that the given function is F(a, b, c) = ab’ + bc’ + c’a’
The selection variable chosen is a.
Factoring out ab’ + bc’ + c’a’, we get
= ab’ + (a+a’)bc’ + c’a’
= ab’ + abc’ +a’bc’ + c’a’
= a(b’ + bc’) + a’(c’(b+1)) (b’ + bc’ = b’ + c)
= a(b’ + c) + a’c’ (1 + b = 1)
Now we have factored out the given function in terms of selection input a and a’.
• Finally show them (i.e. b’ + c and c’) as Inputs i.e., as:
I0 = c’ (because of a’ i.e. S’0)
I1 = b’ + c (because of a i.e. S0)
F = S’0 I0 + S0 I1
Io
I1
S0
c’
b’
c
2 x 1
MUX F
a

149
Sequential Building Blocks
–Flip-Flop
• RS, D, JK, Master Slave, T – Flip-Flops
–Registers & Shift Registers

150
Sequential Logic
• In combinational circuit the outputs at any instant
of time are entirely dependent upon the inputs
present at that time.
• A sequential circuit consists of a combinational
circuit to which memory elements are connected to
form a feedback path.
• The binary information stored in the memory
elements at any given time defines the state of the
sequential circuit.
• A sequential circuit is specified by a time sequence
of inputs, outputs and internal states.

152
Types of Sequential Circuits
• Classification depends on the timing of their signals.
• A synchronous sequential circuit is a system whose
behavior can be defined from the knowledge of its signals
at discrete instants of time.
• The behavior of an asynchronous sequential circuit
depends upon the order in which its input signals change
and can be affected at any instant of time.
• Synchronization is achieved by a timing device called a
master-clock generator which generates a periodic train of
clock pulses.
• The clock pulses are distributed throughout the system in
such a way that memory elements are affected only with
the arrival of the synchronization pulse.

153
• Synchronous sequential circuits that use clock pulses in the inputs
of memory elements are called clocked sequential circuits.
• The memory elements used in clocked sequential circuits are
called flip-flops.
• These circuits are binary cells capable of storing one bit of
information, binary 1 or binary 0.
• A flip-flop circuit has two outputs, one for the normal value and
one for the complement value of the bit stored in it.
• A number of flip-flops put together constitute a register, which
can store multi-bit word.
• A flip-flop circuit can maintain a binary state indefinitely (as long
as power is delivered to the circuit) until directed by an input
signal to switch states.
• The major differences among various types of flip-flops are in the
number of inputs they posses and in the manner in which the
inputs affect the binary state.

154
Basic Flip-Flop or S-R Flip Flop
• A basic flip-flop circuit can be constructed from
two NAND gates or two NOR gates.
• The cross coupled connection from the output of
one gate to the input of the other gate constitutes
a feedback path.
• Each flip-flop has two outputs, Q and Q’, and two
inputs, set and reset.
• This type of flip-flop is sometimes called a direct-
coupled RS flip-flop or SR-Latch.

156
• From the diagram it is evident that the flip flop has
mainly four states. They are
– S=1, R=0—Q=1, Q’=0
• This state is also called the SET state.
– S=0, R=1—Q=0, Q’=1
• This state is known as the RESET state.
– In both the states you can see that the outputs are just
compliments of each other and that the value of Q follows
the value of S.
– S=0, R=0—Q & Q’ = Remember
• If both the values of S and R are switched to 0, then the circuit
remembers the value of S and R in their previous state.
– S=1, R=1—Q=0, Q’=0 [Invalid]
• This is an invalid state because the values of both Q and Q’ are 0.
They are supposed to be compliments of each other. Normally, this
state must be avoided.

158
• Like the NOR Gate S-R flip flop, this one also has four
states. They are
– S=1, R=0—Q=0, Q’=1
• This state is also called the SET state.
– S=0, R=1—Q=1, Q’=0
• This state is known as the RESET state.
– In both the states you can see that the outputs are just
compliments of each other and that the value of Q follows
the compliment value of S.
– S=0, R=0—Q=1, & Q’ =1 [Invalid]
• If both the values of S and R are switched to 0 it is an invalid state
because the values of both Q and Q’ are 1. They are supposed to be
compliments of each other. Normally, this state must be avoided.
– S=1, R=1—Q & Q’= Remember
• If both the values of S and R are switched to 1, then the circuit
remembers the value of S and R in their previous state.

159
Clocked S-R Flip Flop
• It is also called a Gated S-R flip flop.
• It is sometimes desirable in sequential logic circuits to have
a bistable SR flip-flop that only changes state when certain
conditions are met regardless of the condition of either the
Set or the Reset inputs.
• By connecting a 2-input AND gate in series with each input
terminal of the SR Flip-flop a Gated SR Flip-flop can be
created.
• This extra conditional input is called an “Enable” input and
is given the prefix of “EN“. The addition of this input means
that the output at Q only changes state when it is HIGH
and can therefore be used as a clock (CLK) input making it
level-sensitive.

160
• When the Enable input “EN” is at logic level “0”, the outputs
of the two AND gates are also at logic level “0”, (AND Gate
principles) regardless of the condition of the two inputs S and
R, latching the two outputs Q and Q into their last known
state.
• When the enable input “EN” changes to logic level “1” the
circuit responds as a normal SR bistable flip-flop with the two
AND gates becoming transparent to the Set and Reset signals.
• This additional enable input can also be connected to a clock
timing signal (CLK) adding clock synchronisation to the flip-
flop creating what is sometimes called a “Clocked SR Flip-
flop“.
• So a Gated Bistable SR Flip-flop operates as a standard
bistable latch but the outputs are only activated when a logic
“1” is applied to its EN input and deactivated by a logic “0”.

161
• The operation of an SR flip-flop is as follows:
• The Set input will make Q goto 1 i.e. will 'set' the output. The Reset input will make the
output Q goto 0 i.e. reset the output. The scenerio of having both Set and Reset at logic 1
is not allowed as this is not a logical pair of inputs.
• Knowing the above, we can layout the operating characteristics and the state change
table:
Operating Characteristics State Change Diagram
• There are a few different ways SR flip-flops can be made. They can be pulse driven or
clock (and therefore level are used) driven. For the state change diagram above either a
pulse or level input can be implied. When using the state change table to describe
pulses, a '1' implies a pulse should be applied, where '0' implies that no pulse should
exist at this state.
• For either a pulse driven circuit or a clock driven circuit, the following applies:
– An 'X' means a pulse / level may or may not be applied. The reason behind this is
because no matter of the input (0 or 1), the output will always goto the same value.
It is because of this fact that this is considered a 'don't care' input. Hence 's' and 'r'
are 'don't care' sets of 'S' and 'R' respectivly ('s' leads to the same output as 'S' and
that is why 's' is a subset of 'S').

162
SR
Q 00 01
S
11 10
0 X 1
Q 1 1 X 1
R
Q(t + 1) = S + R’Q
(c) Characteristic Equation

163
D Flip Flop
• D flip flop is actually a slight modification of the
above explained clocked SR flip-flop. From the
figure you can see that the D input is connected to
the S input and the complement of the D input is
connected to the R input. The D input is passed on
to the flip flop when the value of CP is ‘1’. When
CP is HIGH, the flip flop moves to the SET state. If
it is ‘0’, the flip flop switches to the CLEAR state.

164
D
Q 0
D
1
0 1
Q 1 1
Q(t + 1) = D
(d) Characteristic
Equation

165
J-K Flip Flop
• A J-K flip flop can also be defined as a modification of the S-R flip flop. The only difference
is that the intermediate state is more refined and precise than that of a S-R flip flop.
• The behavior of inputs J and K is same as the S and R inputs of the S-R flip flop. The letter
J stands for SET and the letter K stands for CLEAR.
• When both the inputs J and K have a HIGH state, the flip-flop switch to the complement
state. So, for a value of Q = 1, it switches to Q=0 and for a value of Q = 0, it switches to
Q=1.
• The circuit includes two 3-input AND gates. The output Q of the flip flop is returned back
as a feedback to the input of the AND along with other inputs like K and clock pulse [CP].
So, if the value of CP is ‘1’, the flip flop gets a CLEAR signal and with the condition that
the value of Q was earlier 1. Similarly output Q’ of the flip flop is given as a feedback to
the input of the AND along with other inputs like J and clock pulse [CP]. So the output
becomes SET when the value of CP is 1 only if the value of Q’ was earlier 1.
• The output may be repeated in transitions once they have been complimented for J=K=1
because of the feedback connection in the JK flip-flop. This can be avoided by setting a
time duration lesser than the propagation delay through the flip-flop. The restriction on
the pulse width can be eliminated with a master-slave or edge-triggered construction.

167
T Flip Flop
• This is a much simpler version of the J-K flip
flop. Both the J and K inputs are connected
together and thus are also called a single input
J-K flip flop. When clock pulse is given to the
flip flop, the output begins to toggle. Here also
the restriction on the pulse width can be
eliminated with a master-slave or edge-
triggered construction. Take a look at the
circuit and truth table below.

169
Master-Slave Flip Flop
• The Master-Slave Flip-Flop is basically two gated JK flip-flops
connected together in a series configuration with the slave having
an inverted clock pulse. The outputs from Q and Q’ from the “Slave”
flip-flop are fed back to the inputs of the “Master” with the outputs
of the “Master” flip flop being connected to the two inputs of the
“Slave” flip flop. This feedback configuration from the slave’s output
to the master’s input gives the characteristic toggle of the JK flip
flop as shown below.

170
The Master-Slave JK Flip Flop

171
• From the above figure we can see that both the
J-K flip flops are presented in a series
connection.
• The output of the master J-K flip flop is fed to
the input of the slave J-K flip flop.
• The output of the slave J-K flip flop is given as a
feedback to the input of the master J-K flip flop.
• The clock pulse [Clk] is given to the master J-K
flip flop and it is sent through a NOT Gate and
thus inverted before passing it to the slave J-K
flip flop.

172
Truth table for JK Master Slave flip-flop having Preset (PR) and Clear (CLR) functions

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