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Dr. M.S. Saravanan, DivyaBaskaran / International Journal of Engineering Research and
                   Applications (IJERA) ISSN: 2248-9622 www.ijera.com
                    Vol. 3, Issue 1, January -February 2013, pp.1147-1149
 Managing the Traffic in Multipath Switching system using Flow
                             Slice
                             Dr. M.S. Saravanan*,DivyaBaskaran**
                *(
                  Professor, Dept. of IT, Vel Tech Dr. RR & Dr. SR Technical University, Chennai.)
     **(
           Final Year Student, M.Tech.IT,Vel Tech Dr. RR & Dr. SR Technical University, Avadi, Chennai.)


ABSTRACT
         Multipath switching system are used in            the additional resequencing mechanisms should
as core routers.These routers provide terabit or           work fast enough to catch up with the switch fabric’s
even petabit switching capacity. The most                  line rate.
difficult issues in designing the multipath
switching system is how to manage the traffic
across its multipath. On the same way that is not
disturbing the flow packet orders.Resulting of the
previous solution was suffer from delay penalities
or load hardware algorithm was used
previouslythey perform badly due to the heavy-
failed flow size distribution.In this paper,we
develop a novel schemeNamely flow slice that
cuts the each flow into flow slice at every
intraflow interval larger than the slicing
threshold and manages the traffic on a finer
granularity.The flow slice scheme achieves
comparative managing the traffic to a optimal
one . it also limits the probability of out-of-order       Fig. 1: Architecture for multi path switching
packet to a negligible level, on three popular
Mpsec at the cost of little hardware complexity
and an internal speedupto two. In this paper the           III.FLOW SLICE
resultsare proven by theoretical analyses and also                   A flow-slice is a sequence of packets in a
validated        through       trace-drivenprotype         flow, whereevery intra-flow interval between two
simulation.                                                consecutive packets issmaller than or equal to a
                                                           slicing threshold ST [2].Flow slices can be seen as
Keywords:                             Flowslice,traffic    miniflows created by cutting off every intraflow
management,switching system.                               interval larger than .we depict the Cumulative
                                                           Distribution Functions (C.D.F) of intraflow intervals
I. INTRODUCTION                                            in our traces [3].Flow-slices can be seen as mini-
         The MultipathSwitching systems (MPS)              flows created by cutting off everyintra-flow interval
plays a major rolein fabricating the high                  larger than ST. Compared with the original 5-tuple
performance corerouters. A well-known paradigm is          flows, three specific properties are observed for
the deployment of Benes multistage switches in             flow-slice in all the traces.
Cisco CRS-1 . Other examples include the Vitesse             Small Size). Both the average packet count
switch chip family implementing the Parallel Packet              (FC) and the average size (FS) of flow slice are
Switch (PPS), and the Load-balanced Birkhoff-von                 much smaller than those of the original flow.
Neumann (LBvN) switches [1]. In general, MPS is              (Light-Tailed Size Distribution). Flow-slice
built by aggregating several lower speed switches                packet count/size distributions are light tailed
and,therefore, exhibits multiple internal data paths.            while it is well-known that original flow-size
                                                                 distribution is heavy tailed. (Fewer Active
II. LITERATURE SURVEY                                            Flow Slices). The active flow-slice number is
          The various findings say the following                 1-2 magnitudes smaller than that of active flow
types of methods are used for managing the traffic in
multipath switching systems. They are uniform load
sharing, it has the traffic destined for each output
should be dispatched to all the switching paths
uniformly; intraflow packet ordering,it has the
packets in the same flow should depart MPS as their
arrival orders;low complexitythe load-balancing and



                                                                                                1147 | P a g e
Dr. M.S. Saravanan, DivyaBaskaran / International Journal of Engineering Research and
                           Applications (IJERA) ISSN: 2248-9622 www.ijera.com
                            Vol. 3, Issue 1, January -February 2013, pp.1147-1149
                                                                  backbone links of one of the largest commercial
                                                                  backbones worldwide [4].
                                                                           The disadvantages are our major
                                                                  improvement over the existing works is to tailor the
                                                                  FS approach in the MPS scenario by introducing the
                                                                  offline delay bound.

                                                                  VI.MANAGINGTHE                            TRAFFIC
                                                                  PERFORMANCE
                                                                            In this paper a novel load-balancing
                                                                  scheme, namely, Flow Slice, based on the fact that
                                                                  the intraflow packet interval is often, larger than the
                                                                  [5]. Due to three positive properties of flow slice,
                                                                  our scheme achieves good load-balancing uniformity
                                                                  with little hardware overhead and                timing
                                                                  complexity. By calculating delay bounds at three
Fig         3.1:      Flow      Slice      Packet       Count     popular, we show that when the slicing threshold is
                                                                  set to the smallest admissible value at, the FS
                                                                  scheme can achieve optimal performance while
                                                                  keeping the intraflow packet out-of-order probability
                                                                  negligible given an internal speedup up to two. Our
                                                                  results are also validated through trace-driven
                                                                  prototype simulations under traffic patterns.The
                                                                  advantages are immune to packet loss, while other
                                                                  solutions like the resequencer require additional loss
                                                                  detection Mechanisms.The Load Balancing can be
                                                                  deployed using the following modules.
                                                                       1. Load-Balancing Scheme
                                                                       2. MULTIPATH SWITCHING SYSTEM
                                                                       3. Multistage Multiplane Clos Switches

                                                                  1)Load-Balancing Scheme: Interflow packet order
                                                                  is natively preserved besetting slicing threshold to
      Fig          3.2:       Flow          Slice         Size    the delay upper bound at any two packets in the
                                                                  same flow slice cannot be disordered as they are
                                                                  dispatched to the same switching path where
                                                                  processing is guaranteed; and two packets in the
                                                                  same flow but different flow slices will be in order at
                                                                  departure, as the earlier packet will have depart from
                                                                  before the latter packet arrives [6]. Due to the fewer
                                                                  number of active flow slices, the only additional
                                                                  overhead in, the hash table, can be kept rather small,
                                                                  , and placed on-chip to provide ultrafast access
                                                                  speed. This table size depends only on system line
                                                                  rate and will stay unchanged even if scales to more
                                                                  than thousand external ports, thus guarantees system
                                                                  scalability.

                                                                  2) Multipath switching system: Through lay-aside
       Fig 3.3:Active Flow Slice Number                           Buffer Management module, all packets are virtually
                                                                  queued at the output according to the flow group and
                                                                  the priority class in a hierarchical manner. The
       V. SWITCHING SYSTEM                                        output scheduler fetches packets to the output line
                 Our major improvement over the existing          using information provided by. Packets in the same
       works is to tailor the approach in the scenario by         flow will bevirtually buffered in the same queue and
       introducing the offline delay bound calculation,           scheduled in discipline. Hence, intraflow packet
       while the previous solutions either use an empirical       departure orders holdas their arriving orders at the
       slicing threshold or maintain flow context to              multiplexer. Central-stage parallel switches adopt an
       facilitate the slicing. The traces here are collected at   output-queued model [7]. By Theorem, we derive
                                                                  packet delay bound at firststage. We then study


                                                                                                        1148 | P a g e
Dr. M.S. Saravanan, DivyaBaskaran / International Journal of Engineering Research and
                   Applications (IJERA) ISSN: 2248-9622 www.ijera.com
                    Vol. 3, Issue 1, January -February 2013, pp.1147-1149
delay at second-stage switches. Define native packet                for InternetLoad Balancing,” Proc. IEEE
delay at stage m of an be delay experienced at stage                INFOCOM,pp. 332-341, 2000.
m on the condition that all the preceding stages              [5]   L. Carter and M. Wegman, “Universal
immediately send all arrival packets out without                    Classes of HashingFunctions,” J. Computer
delay.                                                              and System Sciences, vol. 18, no. 2,pp.
                                                                    143-154, 1979.
3) Multistage Multiplane Clos Switches: We                    [6]   C.S. Chang, D.S. Lee, and Y.S. Jou, “Load
consider the Multistage Multiplane Clos-                            Balanced Birkhoff-von Neumann Switch,
networkbased switch by Chao et a . It is constructed                Part II: Multi-Stage Buffering,” Computer
of five stages of switchmodules with top-level                      Comm., vol. 25, pp. 623-634, 2002.
architecture similar to a external input/output ports         [7]   C.S. Chang, D.S. Lee, and Y.S. Jou, “Load
[8]. The first and last stages Clos are composed of                 Balanced Birkhoff-von Neumann Switches,
inputdemultiplexers and output multiplexers,                        Part I: One-Stage Buffering,” Computer
respectively, having similar internal structures as                 Comm., vol. 25, pp. 611-622, 2002.
those in PPS. Stages 2-4 of M2Clos are constructed            [8]   C.S. Chang, D.S. Lee, and Y.J. Shih,
by parallel switching planes; however, each plane is                “Mailbox Switch: A Scalable Two-Stage
no longer formed by a basic switch, but by a three-                 Switch Architecture for Conflict Resolution
stage Clos Network to support large port count.                     of Ordered Packets,” Proc. IEEE
Inside each Clos Network, the first stage is                        INFOCOM, 2004.
composed by k identical Input Modules [9]. Each IM            [9]   C.S. Chang, D.S. Lee, and C.Y. Yue,
is an packet switch, with each output link connected                “Providing Guaranteed Rate Services in the
to a Central Module. Thus, there are a total of m                   Load Balanced Birkhoff-von Neumann
identical in second stage of the Close networks                     Switches,” IEEE/ACM Trans. Networking,
                                                                    vol. 14, no. 3, pp. 644-656, June 2006.
VIII.CONCLUSION
                                                          *
          We propose a novel load-balancing scheme,        Author: Dr. M.S. Saravanan, received B.Sc degree
namely, FlowSlice, based on the fact that the             incomputer science from Madras University in 1996,
intraflow packet interval isoften, say in 40-50           the MCA degree from Bharathidasan University in
percent, larger than the delay upperbound at MPS.         2001, the M.Phil degree from Madurai Kamaraj
Due to three positive properties of flow slice,our        University in 2004, M.Tech degree from IASE
scheme achieves good load-balancing uniformity            University in 2005. and PhD degree fromBharathiar
withlittle hardware overhead and O(1) timing              University in 2012.His current research interests
complexity. Bycalculating delay bounds at three           include Process Mining, Business Process modeling,
popular MPSes, we showthat when the slicing               Workflow management systems and Exception
threshold is set to the smallestadmissible value at 1-4   handling etc. He is a professor in the Department of
ms, the FS scheme can achieveoptimal performance          Information Technology in VEL TECH Dr, RR &
while keeping the intraflowpacketout-of-order             Dr. SR Technical University, Avadi, Chennai, India.
probability negligible, given aninternal speedup up       M.S. Saravanan has published twenty eight
to two. Our results are also validatedthrough trace-      international publications and presented twelve
driven prototype simulations under highlybursty           research papers in international and national
traffic patterns.                                         conferences, having 13 years of teaching experience
                                                          in various institutions in India.
REFERENCES
  [1]    A. Aslam and K. Christensen, “Parallel           **Author: DivyaBaskaran, received B.Tech degree
         Packet Switching UsingMultiplexors with          in Information Technology from PeriyarManiammai
         Virtual Input Queues,” Proc. Ann. IEEE           University, Thanjavur, India in 2011, Currently
         Conf.Local Computer Networks (LCN), pp.          pursuing M.Tech degree in Information Technology
         270-277, 2002.                                   from VelTechDr.RR& Dr.SR Technical University,
  [2]    J. Bennett, C. Partridge, and N. Shectman,       Avadi, Chennai, India.
         “Packet Reordering IsNot Pathological
         Network Behavior,” IEEE/ACM Trans.
         Networking,vol. 7, no. 6, pp. 789-798, Dec.
         1999.
  [3]    N. Brownlee and K. Claffy, “Understanding
         Internet Traffic Streams: Dragonflies and
         Tortoises,” IEEE Comm. Magazine,vol. 40,
         no. 10, pp. 110-117, Oct. 2002.
  [4]    Z. Cao, Z. Wang, and E. Zegura,
         “Performance of Hashing-BasedSchemes




                                                                                               1149 | P a g e

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  • 1. Dr. M.S. Saravanan, DivyaBaskaran / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 3, Issue 1, January -February 2013, pp.1147-1149 Managing the Traffic in Multipath Switching system using Flow Slice Dr. M.S. Saravanan*,DivyaBaskaran** *( Professor, Dept. of IT, Vel Tech Dr. RR & Dr. SR Technical University, Chennai.) **( Final Year Student, M.Tech.IT,Vel Tech Dr. RR & Dr. SR Technical University, Avadi, Chennai.) ABSTRACT Multipath switching system are used in the additional resequencing mechanisms should as core routers.These routers provide terabit or work fast enough to catch up with the switch fabric’s even petabit switching capacity. The most line rate. difficult issues in designing the multipath switching system is how to manage the traffic across its multipath. On the same way that is not disturbing the flow packet orders.Resulting of the previous solution was suffer from delay penalities or load hardware algorithm was used previouslythey perform badly due to the heavy- failed flow size distribution.In this paper,we develop a novel schemeNamely flow slice that cuts the each flow into flow slice at every intraflow interval larger than the slicing threshold and manages the traffic on a finer granularity.The flow slice scheme achieves comparative managing the traffic to a optimal one . it also limits the probability of out-of-order Fig. 1: Architecture for multi path switching packet to a negligible level, on three popular Mpsec at the cost of little hardware complexity and an internal speedupto two. In this paper the III.FLOW SLICE resultsare proven by theoretical analyses and also A flow-slice is a sequence of packets in a validated through trace-drivenprotype flow, whereevery intra-flow interval between two simulation. consecutive packets issmaller than or equal to a slicing threshold ST [2].Flow slices can be seen as Keywords: Flowslice,traffic miniflows created by cutting off every intraflow management,switching system. interval larger than .we depict the Cumulative Distribution Functions (C.D.F) of intraflow intervals I. INTRODUCTION in our traces [3].Flow-slices can be seen as mini- The MultipathSwitching systems (MPS) flows created by cutting off everyintra-flow interval plays a major rolein fabricating the high larger than ST. Compared with the original 5-tuple performance corerouters. A well-known paradigm is flows, three specific properties are observed for the deployment of Benes multistage switches in flow-slice in all the traces. Cisco CRS-1 . Other examples include the Vitesse  Small Size). Both the average packet count switch chip family implementing the Parallel Packet (FC) and the average size (FS) of flow slice are Switch (PPS), and the Load-balanced Birkhoff-von much smaller than those of the original flow. Neumann (LBvN) switches [1]. In general, MPS is  (Light-Tailed Size Distribution). Flow-slice built by aggregating several lower speed switches packet count/size distributions are light tailed and,therefore, exhibits multiple internal data paths. while it is well-known that original flow-size distribution is heavy tailed. (Fewer Active II. LITERATURE SURVEY Flow Slices). The active flow-slice number is The various findings say the following 1-2 magnitudes smaller than that of active flow types of methods are used for managing the traffic in multipath switching systems. They are uniform load sharing, it has the traffic destined for each output should be dispatched to all the switching paths uniformly; intraflow packet ordering,it has the packets in the same flow should depart MPS as their arrival orders;low complexitythe load-balancing and 1147 | P a g e
  • 2. Dr. M.S. Saravanan, DivyaBaskaran / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 3, Issue 1, January -February 2013, pp.1147-1149 backbone links of one of the largest commercial backbones worldwide [4]. The disadvantages are our major improvement over the existing works is to tailor the FS approach in the MPS scenario by introducing the offline delay bound. VI.MANAGINGTHE TRAFFIC PERFORMANCE In this paper a novel load-balancing scheme, namely, Flow Slice, based on the fact that the intraflow packet interval is often, larger than the [5]. Due to three positive properties of flow slice, our scheme achieves good load-balancing uniformity with little hardware overhead and timing complexity. By calculating delay bounds at three Fig 3.1: Flow Slice Packet Count popular, we show that when the slicing threshold is set to the smallest admissible value at, the FS scheme can achieve optimal performance while keeping the intraflow packet out-of-order probability negligible given an internal speedup up to two. Our results are also validated through trace-driven prototype simulations under traffic patterns.The advantages are immune to packet loss, while other solutions like the resequencer require additional loss detection Mechanisms.The Load Balancing can be deployed using the following modules. 1. Load-Balancing Scheme 2. MULTIPATH SWITCHING SYSTEM 3. Multistage Multiplane Clos Switches 1)Load-Balancing Scheme: Interflow packet order is natively preserved besetting slicing threshold to Fig 3.2: Flow Slice Size the delay upper bound at any two packets in the same flow slice cannot be disordered as they are dispatched to the same switching path where processing is guaranteed; and two packets in the same flow but different flow slices will be in order at departure, as the earlier packet will have depart from before the latter packet arrives [6]. Due to the fewer number of active flow slices, the only additional overhead in, the hash table, can be kept rather small, , and placed on-chip to provide ultrafast access speed. This table size depends only on system line rate and will stay unchanged even if scales to more than thousand external ports, thus guarantees system scalability. 2) Multipath switching system: Through lay-aside Fig 3.3:Active Flow Slice Number Buffer Management module, all packets are virtually queued at the output according to the flow group and the priority class in a hierarchical manner. The V. SWITCHING SYSTEM output scheduler fetches packets to the output line Our major improvement over the existing using information provided by. Packets in the same works is to tailor the approach in the scenario by flow will bevirtually buffered in the same queue and introducing the offline delay bound calculation, scheduled in discipline. Hence, intraflow packet while the previous solutions either use an empirical departure orders holdas their arriving orders at the slicing threshold or maintain flow context to multiplexer. Central-stage parallel switches adopt an facilitate the slicing. The traces here are collected at output-queued model [7]. By Theorem, we derive packet delay bound at firststage. We then study 1148 | P a g e
  • 3. Dr. M.S. Saravanan, DivyaBaskaran / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 3, Issue 1, January -February 2013, pp.1147-1149 delay at second-stage switches. Define native packet for InternetLoad Balancing,” Proc. IEEE delay at stage m of an be delay experienced at stage INFOCOM,pp. 332-341, 2000. m on the condition that all the preceding stages [5] L. Carter and M. Wegman, “Universal immediately send all arrival packets out without Classes of HashingFunctions,” J. Computer delay. and System Sciences, vol. 18, no. 2,pp. 143-154, 1979. 3) Multistage Multiplane Clos Switches: We [6] C.S. Chang, D.S. Lee, and Y.S. Jou, “Load consider the Multistage Multiplane Clos- Balanced Birkhoff-von Neumann Switch, networkbased switch by Chao et a . It is constructed Part II: Multi-Stage Buffering,” Computer of five stages of switchmodules with top-level Comm., vol. 25, pp. 623-634, 2002. architecture similar to a external input/output ports [7] C.S. Chang, D.S. Lee, and Y.S. Jou, “Load [8]. The first and last stages Clos are composed of Balanced Birkhoff-von Neumann Switches, inputdemultiplexers and output multiplexers, Part I: One-Stage Buffering,” Computer respectively, having similar internal structures as Comm., vol. 25, pp. 611-622, 2002. those in PPS. Stages 2-4 of M2Clos are constructed [8] C.S. Chang, D.S. Lee, and Y.J. Shih, by parallel switching planes; however, each plane is “Mailbox Switch: A Scalable Two-Stage no longer formed by a basic switch, but by a three- Switch Architecture for Conflict Resolution stage Clos Network to support large port count. of Ordered Packets,” Proc. IEEE Inside each Clos Network, the first stage is INFOCOM, 2004. composed by k identical Input Modules [9]. Each IM [9] C.S. Chang, D.S. Lee, and C.Y. Yue, is an packet switch, with each output link connected “Providing Guaranteed Rate Services in the to a Central Module. Thus, there are a total of m Load Balanced Birkhoff-von Neumann identical in second stage of the Close networks Switches,” IEEE/ACM Trans. Networking, vol. 14, no. 3, pp. 644-656, June 2006. VIII.CONCLUSION * We propose a novel load-balancing scheme, Author: Dr. M.S. Saravanan, received B.Sc degree namely, FlowSlice, based on the fact that the incomputer science from Madras University in 1996, intraflow packet interval isoften, say in 40-50 the MCA degree from Bharathidasan University in percent, larger than the delay upperbound at MPS. 2001, the M.Phil degree from Madurai Kamaraj Due to three positive properties of flow slice,our University in 2004, M.Tech degree from IASE scheme achieves good load-balancing uniformity University in 2005. and PhD degree fromBharathiar withlittle hardware overhead and O(1) timing University in 2012.His current research interests complexity. Bycalculating delay bounds at three include Process Mining, Business Process modeling, popular MPSes, we showthat when the slicing Workflow management systems and Exception threshold is set to the smallestadmissible value at 1-4 handling etc. He is a professor in the Department of ms, the FS scheme can achieveoptimal performance Information Technology in VEL TECH Dr, RR & while keeping the intraflowpacketout-of-order Dr. SR Technical University, Avadi, Chennai, India. probability negligible, given aninternal speedup up M.S. Saravanan has published twenty eight to two. Our results are also validatedthrough trace- international publications and presented twelve driven prototype simulations under highlybursty research papers in international and national traffic patterns. conferences, having 13 years of teaching experience in various institutions in India. REFERENCES [1] A. Aslam and K. Christensen, “Parallel **Author: DivyaBaskaran, received B.Tech degree Packet Switching UsingMultiplexors with in Information Technology from PeriyarManiammai Virtual Input Queues,” Proc. Ann. IEEE University, Thanjavur, India in 2011, Currently Conf.Local Computer Networks (LCN), pp. pursuing M.Tech degree in Information Technology 270-277, 2002. from VelTechDr.RR& Dr.SR Technical University, [2] J. Bennett, C. Partridge, and N. Shectman, Avadi, Chennai, India. “Packet Reordering IsNot Pathological Network Behavior,” IEEE/ACM Trans. Networking,vol. 7, no. 6, pp. 789-798, Dec. 1999. [3] N. Brownlee and K. Claffy, “Understanding Internet Traffic Streams: Dragonflies and Tortoises,” IEEE Comm. Magazine,vol. 40, no. 10, pp. 110-117, Oct. 2002. [4] Z. Cao, Z. Wang, and E. Zegura, “Performance of Hashing-BasedSchemes 1149 | P a g e