UIET MDU DSD FILE.

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1:- Design All logical Gates Using VHDL.
VHDL PROGARM FOR OR GATE
Sample WaveFormOutput:-

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VHDL PROGARM FOR AND GATE
Sample WaveFormOutput:-

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VHDL PROGARM FOR NOT GATE
Sample WaveFormOutput:-

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VHDL PROGARM FOR NAND GATE
Sample WaveFormOutput:-

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VHDL PROGARM FOR NOR GATE
Sample WaveFormOutput:-

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VHDL PROGARM FOR XOR GATE
Sample WaveFormOutput:-

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VHDL PROGARM FOR XNOR GATE
Sample WaveFormOutput:-

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2:- VHDL Programs For the following and check the Simulation
1) Half Adder
2) Full Adder.
VHDL PROGARM FOR HALF ADDER
Sample WaveFormOutput:-

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VHDL PROGARM FOR FULL ADDER
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fulladder is
port( a, b, cin : in STD_LOGIC;
sum, cout : out STD_LOGIC );
end fulladder;
architecture Behavioral of fulladder is
signal s1,s2,s3: STD_ULOGIC;
constant gate_delay:Time :=100 ps;
begin
s1<=(a xor b) after gate_delay;
s2<=(cin and s1) after gate_delay;
s3<=(a and b) after gate_delay;
sum<=(s1 xor cin) after gate_delay;
cout<=(s2 or s3) after gate_delay;
end Behavioral;
Sample WaveFormOutput:-

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3:- VHDL Programs For the following and check the Simulation
1. Multiplexer
2. Demultiplexer
VHDL PROGARM FOR MULTIPLEXER(4 X 1)
Sample WaveFormOutput:-

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VHDL PROGARM FOR DEMULTIPLEXER(2X4)
Sample WaveFormOutput:-

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4:- VHDL Program For a Comparator and check the Simulation
Sample WaveFormOutput:-

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5:- VHDL Program For a Code Converter and check the Simulation
Sample WaveFormOutput:-

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6:- VHDL Program For a JK flip flop and check the Simulation
Sample WaveFormOutput:-

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7:- VHDL Program For a Counter and check the Simulation
Sample WaveFormOutput:-