This document discusses the design of an HDLC protocol controller for sensor data processing. It aims to model an efficient sensor data processing system that provides ease of integration with packet-based data communication, data buffering management, data security and compression, and RF-based wireless communication. The design and implementation of HDLC procedures are described, including the HDLC frame structure with fields for flag, address, control, information, and CRC. The HDLC modules designed include an encoding and sending module using a finite state machine, and a receiving and decoding module also using a finite state machine. Potential applications are in fields like mineral processing, patient monitoring, and sensor data instrumentation.

1. HDLC PROTOCOL CONTROLLER FOR SENSOR
DATA PROCESSING

2. HDLC PROTOCOL CONTROLLER FOR SENSOR
DATA PROCESSING
AIM:
 To model and design an efficient sensor data
processing system.
 Provides ease of integration with other technologies
and techniques like
I. Packet based data communication
II. Data buffering management
III. Data security& compression
IV. Rf based wireless communication

3. TRANSMITTING UNIT
MULTI SENSOR DATA
MULTIPLEXER
A/D CONVERTOR
ENCODING AND SENDING MODULE

4. RECEIVING UNIT
RECEIVING AND DECODING MODULE
D/A CONVERTOR
DE MULTIPLEXER
RECEIVER

5. DESIGN AND IMPLEMENTATION OF HDLC
PROCEDURES
 High level data link control procedures
 Established by international organization for standardization(ISO)
 Widely used in digital communications
 HDLC procedures are bit oriented
 More flexible
 More efficient
 Basic transfer unit is a frame.

6. HDLC FRAME STRUCTURE
 Flag is 8 bit field
 Address is an 8 bit field
 Control is an 8 bit field
 Info or data is an 8 bit
field
 CRC is a frame check
sequence and uses16/32
bit.

7. The first field is for frame synchronization flag
and is ‘01111110’ for both header and frame end.
The second is address of the receiving station.
The third field is a control code
The fourth field is the information and is a
multiple of 8 bits.
The fifth field is Frame Check Sequence.

8. HDLC MODULES DESIGN

9. • ENCODING-AND-SENDING MODULE:
 Adopts finite state machine in VHDL consisting of five
stages:
 Idle state
 Frame header sending state
 User data sending state
 CRC codes sending state
 Frame end sending state

10. • RECEIVING-AND-DECODING MODULE
 Adopts finite state machine and consists of
 Frame header detecting state
 User data processing state
 CRC verifying and comparing state
 Storage flag generation state
 Data storing state

11. • APPLICATIONS:
Sensor data processing in fields like
I. mineral processing
II. Patient monitoring
III. Sensor data instrumentation
IV. Bio medical instrumentation
V. Radar sensor data processing

12. Thank you