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Conferencia
- 1. Digital Integrated Circuits A Design Perspective José Leonardo Simancas García Electronic Engineer Introduction to Design March 4, 2010 1 © Digital Integrated EE141 Circuits2nd Introduction
- 2. What is thisconference all about? Introduction to digital integrated circuits. CMOS devices and manufacturing technology. CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Sequential circuits. Arithmetic, interconnect, and memories. Programmable logic arrays. Design methodologies. What will you learn? Understanding, designing, and optimizing digital circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability 2 © Digital Integrated EE141 Circuits2nd Introduction
- 3. Digital Integrated Circuits Issues in digital design The CMOS inverter Combinational logic structures Sequential logic gates Design methodologies Interconnect: R, L and C Timing Arithmetic building blocks Memories and array structures 3 © Digital Integrated EE141 Circuits2nd Introduction
- 4. Introduction Why is designing digital ICs different today than it was before? Will it change in future? 4 © Digital Integrated EE141 Circuits2nd Introduction
- 5. The First Computer The Babbage Difference Engine (1832) 25,000 parts cost: £17,470 5 © Digital Integrated EE141 Circuits2nd Introduction
- 6. ENIAC - Thefirst electronic computer (1946) 6 © Digital Integrated EE141 Circuits2nd Introduction
- 7. The Transistor Revolution First transistor Bell Labs, 1948 7 © Digital Integrated EE141 Circuits2nd Introduction
- 8. The First IntegratedCircuits Bipolar logic 1960’s ECL 3-input Gate Motorola 1966 8 © Digital Integrated EE141 Circuits2nd Introduction
- 9. Intel 4004 Micro-Processor 1971 1000 transistors 1 MHz operation 9 © Digital Integrated EE141 Circuits2nd Introduction
- 10. Intel Pentium (IV)microprocessor 10 © Digital Integrated EE141 Circuits2nd Introduction
- 11. Moore’s Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months 11 © Digital Integrated EE141 Circuits2nd Introduction
- 12. EE141 © Digital Integrated LOG2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FUNCTION 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Circuits2nd 1959 1960 Moore’s Law 1961 1962 Electronics, April 19, 1965. 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 12 Introduction
- 13. Evolution in Complexity 13 © Digital Integrated EE141 Circuits2nd Introduction
- 14. Transistor Counts 1 Billion K Transistors 1,000,000 100,000 Pentium® III 10,000 Pentium® II Pentium® Pro 1,000 Pentium® i486 100 i386 80286 10 8086 Source: Intel 1 1975 1980 1985 1990 1995 2000 2005 2010 Projected 14 © Digital Integrated EE141 Circuits2nd Courtesy, Intel Introduction
- 15. Moore’s law inMicroprocessors 1000 100 2X growth in 1.96 years! Transistors (MT) 10 P6 Pentium® proc 1 486 386 0.1 286 8085 8086 Transistors on Lead Microprocessors double every 2 years Transistors on Lead Microprocessors double every 2 years 0.01 8080 8008 4004 0.001 1970 1980 1990 2000 2010 Year 15 © Digital Integrated EE141 Circuits2nd Courtesy, Intel Introduction
- 16. Die Size Growth 100 Die size (mm) P6 486 Pentium ® proc 10 386 286 8080 8086 8085 ~7% growth per year 8008 4004 ~2X growth in 10 years 1 1970 1980 1990 2000 2010 Year Die size grows by 14% to satisfy Moore’s Law Die size grows by 14% to satisfy Moore’s Law 16 © Digital Integrated EE141 Circuits2nd Courtesy, Intel Introduction
- 17. Frequency 10000 Doubles every 1000 2 years Frequency (Mhz) 100 P6 Pentium ® proc 486 10 8085 386 8086 286 1 8080 8008 4004 0.1 1970 1980 1990 2000 2010 Year Lead Microprocessors frequency doubles every 2 years Lead Microprocessors frequency doubles every 2 years 17 © Digital Integrated EE141 Circuits2nd Courtesy, Intel Introduction
- 18. Power Dissipation 100 P6 Power (Watts) Pentium ® proc 10 486 8086 286 386 8085 1 8080 8008 4004 0.1 1971 1974 1978 1985 1992 2000 Year Lead Microprocessors power continues to increase Lead Microprocessors power continues to increase 18 © Digital Integrated EE141 Circuits2nd Courtesy, Intel Introduction
- 19. Power will bea major problem 100000 18KW 10000 5KW 1.5KW Power (Watts) 1000 500W Pentium® proc 100 286 486 10 8086 386 8085 8080 8008 1 4004 0.1 1971 1974 1978 1985 1992 2000 2004 2008 Year Power delivery and dissipation will be prohibitive Power delivery and dissipation will be prohibitive 19 © Digital Integrated EE141 Circuits2nd Courtesy, Intel Introduction
- 20. Power density 10000 Power Density (W/cm2) Rocket Nozzle 1000 Nuclear Reactor 100 8086 10 4004 Hot Plate P6 8008 8085 386 Pentium® proc 8080 286 486 1 1970 1980 1990 2000 2010 Year Power density too high to keep junctions at low temp Power density too high to keep junctions at low temp 20 © Digital Integrated EE141 Circuits2nd Courtesy, Intel Introduction
- 21. Not Only Microprocessors Cell Phone Small Power Signal RF RF Digital Cellular Market (Phones Shipped) Power Management 1996 1997 1998 1999 2000 Analog Units 48M 86M 162M 260M 435M Baseband Digital Baseband (DSP + MCU) (data from Texas Instruments) 21 © Digital Integrated EE141 Circuits2nd Introduction
- 22. Challenges in DigitalDesign ∝ DSM ∝ 1/DSM “Microscopic Problems” “Macroscopic Issues” • Ultra-high speed design • Time-to-Market • Interconnect • Millions of Gates • Noise, Crosstalk • High-Level Abstractions • Reliability, Manufacturability • Reuse & IP: Portability • Power Dissipation • Predictability • Clock distribution. • etc. Everything Looks a Little Different …and There’s a Lot of Them! ? 22 © Digital Integrated EE141 Circuits2nd Introduction
- 23. Productivity Trends Logic Transistor per Chip (M) 10,000 10,000,000 100,000 100,000,000 1,000 Logic Tr./Chip 10,000 1,000,000 10,000,000 (K) Trans./Staff - Mo. Tr./Staff Month. 100 1,000 Complexity 100,000 1,000,000 Productivity 10 58%/Yr. compounded 100 10,000 Complexity growth rate 100,000 1,0001 10 10,000 x x 0.1 100 1 1,000 xx x 21%/Yr. compound xx Productivity growth rate x 0.01 10 0.1 100 0.001 1 0.01 10 1981 1983 1985 1987 1989 1991 1993 1995 1999 2001 2005 2007 1997 2003 2009 Source: Sematech Complexity outpaces design productivity 23 © Digital Integrated EE141 Circuits2nd Courtesy, ITRS Roadmap Introduction
- 24. Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per chip; chip cost does not increase significantly Cost of a function decreases by 2x But … How to design chips with more and more functions? Design engineering population does not double every two years… Hence, a need for more efficient design methods Exploit different levels of abstraction 24 © Digital Integrated EE141 Circuits2nd Introduction
- 25. Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT DEVICE G S D n+ n+ 25 © Digital Integrated EE141 Circuits2nd Introduction
- 26. Design Metrics How to evaluate performance of a digital circuit (gate, block, …)? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function 26 © Digital Integrated EE141 Circuits2nd Introduction
- 27. Cost of IntegratedCircuits NRE (non-recurrent engineering) costs design time and effort, mask generation one-time cost factor Recurrent costs silicon processing, packaging, test proportional to volume proportional to chip area 27 © Digital Integrated EE141 Circuits2nd Introduction
- 28. NRE Cost isIncreasing 28 © Digital Integrated EE141 Circuits2nd Introduction
- 29. Die Cost Single die Wafer Going up to 12” (30cm) From http://www.amd.com 29 © Digital Integrated EE141 Circuits2nd Introduction
- 30. Cost per Transistor cost: ¢-per-transistor per- 1 0.1 Fabrication capital cost per transistor (Moore’s law) 0.01 0.001 0.0001 0.00001 0.000001 0.0000001 1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012 30 © Digital Integrated EE141 Circuits2nd Introduction
- 31. Yield No. of good chips per wafer Y= ×100% Total number of chips per wafer Wafer cost Die cost = Dies per wafer × Die yield π × (wafer diameter/2)2 π × wafer diameter Dies per wafer = − die area 2 × die area 31 © Digital Integrated EE141 Circuits2nd Introduction
- 32. Defects −α defects per unit area × die area die yield = 1 + α α is approximately 3 die cost = f (die area)4 32 © Digital Integrated EE141 Circuits2nd Introduction
- 33. Some Examples (1994) Chip Metal Line Wafer Def./ Area Dies/ Yield Die layers width cost cm2 mm2 wafer cost 386DX 2 0.90 $900 1.0 43 360 71% $4 486 DX2 3 0.80 $1200 1.0 81 181 54% $12 Power PC 4 0.80 $1700 1.3 121 115 28% $53 601 HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73 DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149 Super Sparc 3 0.70 $1700 1.6 256 48 13% $272 Pentium 3 0.80 $1500 1.5 296 40 9% $417 33 © Digital Integrated EE141 Circuits2nd Introduction
- 34. Reliability― Noise in Digital Integrated Circuits v(t) V DD i(t) Inductive coupling Capacitive coupling Power and ground noise 34 © Digital Integrated EE141 Circuits2nd Introduction
- 35. DC Operation Voltage TransferCharacteristic V(y) VOH = f(VOL) V f OH V(y)=V(x) VOL = f(VOH) VM = f(VM) VM Switching Threshold V OL V OL V V(x) OH Nominal Voltage Levels 35 © Digital Integrated EE141 Circuits2nd Introduction
- 36. Mapping between analogand digital signals V V out “ 1” OH V Slope = -1 V OH IH Undefined Region V IL Slope = -1 “ 0” V V OL OL V V V IL IH in 36 © Digital Integrated EE141 Circuits2nd Introduction
- 37. Definition of NoiseMargins "1" V OH NM H Noise margin high V IH Undefined Region NM L V V OL IL Noise margin low "0" Gate Output Gate Input 37 © Digital Integrated EE141 Circuits2nd Introduction
- 38. Noise Budget Allocates gross noise margin to expected sources of noise Sources: supply noise, cross talk, interference, offset Differentiate between fixed and proportional noise sources 38 © Digital Integrated EE141 Circuits2nd Introduction
- 39. Key Reliability Properties Absolute noise margin values are deceptive a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage) Noise immunity is the more important metric – the capability to suppress noise sources Key metrics: Noise transfer functions, Output impedance of the driver and input impedance of the receiver; 39 © Digital Integrated EE141 Circuits2nd Introduction
- 40. Regenerative Property out out v3 v3 f (v) fin v(v) v1 v1 v3 fin v(v) f (v) v2 v0 in v0 v2 in Regenerative Non-Regenerative 40 © Digital Integrated EE141 Circuits2nd Introduction
- 41. Regenerative Property v0 v1 v2 v3 v4 v5 v6 A chain of inverters 5 V (Volt) v0 3 1 v1 v2 21 Simulated response 0 2 4 6 8 10 t (nsec) 41 © Digital Integrated EE141 Circuits2nd Introduction
- 42. Fan-in and Fan-out M N Fan-out N Fan-in M 42 © Digital Integrated EE141 Circuits2nd Introduction
- 43. The Ideal Gate V out Ri = ∞ Ro = 0 Fanout = ∞ g=∞ NMH = NML = VDD/2 V in 43 © Digital Integrated EE141 Circuits2nd Introduction
- 44. An Old-time Inverter 5.0 4.0 NM L 3.0 ( V) V o u t 2.0 VM NM H 1.0 0.0 1.0 2.0 3.0 4.0 5.0 V in (V) 44 © Digital Integrated EE141 Circuits2nd Introduction
- 45. Delay Definitions V in 50% t tpHL tpLH V out 90% 50% 10% t tf tr 45 © Digital Integrated EE141 Circuits2nd Introduction
- 46. Ring Oscillator v0 v1 v2 v3 v4 v5 v0 v1 v5 T = 2 × tp × N 46 © Digital Integrated EE141 Circuits2nd Introduction
- 47. A First-Order RCNetwork R vout vin C tp = ln (2) τ = 0.69 RC Important model – matches delay of inverter 47 © Digital Integrated EE141 Circuits2nd Introduction
- 48. Power Dissipation Instantaneous power: p(t) = v(t)i(t) = Vsupplyi(t) Peak power: Ppeak = Vsupplyipeak Average power: 1 t +T Vsupply t +T Pave = ∫ T t p (t )dt = T ∫t isupply (t )dt 48 © Digital Integrated EE141 Circuits2nd Introduction
- 49. Energy and Energy-Delay Power-Delay Product (PDP) = E = Energy per operation = Pav × tp Energy-Delay Product (EDP) = quality metric of gate = E × tp 49 © Digital Integrated EE141 Circuits2nd Introduction
- 50. A First-Order RCNetwork R vout vin CL T T Vdd E 0 1 = ∫ P ( t ) dt = V dd ∫ i sup ply( t ) dt = Vdd ∫ CL dV out = C L • V dd 2 → 0 0 0 T T Vdd 1 2 E ca p = ∫ P cap ( t ) dt = ∫ V out i ca p( t ) dt = ∫ C L Vout dVout = -- C • V dd - 2 L 0 0 0 50 © Digital Integrated EE141 Circuits2nd Introduction
- 51. Summary Digital integrated circuits have come a long way and still have quite some potential left for the coming decades Some interesting challenges ahead Getting a clear perspective on the challenges and potential solutions is the purpose of this book Understanding the design metrics that govern digital design is crucial Cost, reliability, speed, power and energy dissipation 51 © Digital Integrated EE141 Circuits2nd Introduction