COA RKGITM #sem education purpose ppt good for student

Computer Organization and
Architecture
04-09-2023 Faculty Name :Dr.Sharmila Unit -2 1
Raj Kumar Goel Institute of Technology
Ghaziabad
Faculty Name
Dr.Sharmila
Unit: 2
Course Core: BCS 302

Faculty Information
Dr.Sharmila received B.E. degree in Electronics and
Communication Engineering from the Annamalai
University, the M.E degree in Computer and
Communication engineering from Anna University,
Tamil Nadu, and the Ph.D. degree in Electronics &
Communication Engineering from Pondicherry
University. She is an eminent academician having more
than 14 years of teaching experience. She has
published widely in International Journals and
Conferences, her research findings related to Wireless
Sensor Networks, Digital image Processing,
Cryptography and Information Security, and Block
chain. She has authored/co-authored more than 20
research papers and 5 chapters in six other books,
published by IET, Springer and Elsevier. She also
contributes as an Editor of Books in CRC publication &
River Publishers.

Evaluation Scheme
Subject L T P CT TA TOTA
L
PS TE PE TOTA
L
CREDI
T
Computer
Organization
and
Architecture
(BCS 302)
3 1 0 20 10 30 70 100 4

SUBJECT SYLLABUS
Unit- I: Introduction: Functional units of digital system and their interconnections, buses, bus
architecture, types of buses and bus arbitration. Register, bus and memory transfer. Processor
organization, general registers organization, stack organization and addressing modes.
Unit-II: Arithmetic and logic unit: Look ahead carries adders. Multiplication: Signed operand
multiplication, Booths algorithm and array multiplier. Division and logic operations. Floating
point arithmetic operation, Arithmetic & logic unit design. IEEE Standard for Floating Point
Numbers
Unit -III: Control Unit: Instruction types, formats, instruction cycles and sub cycles (fetch and
execute etc), micro operations, execution of a complete instruction. Program Control, Reduced
Instruction Set Computer, Pipelining. Hardwire and micro programmed control: micro programme
sequencing, concept of horizontal and vertical microprogramming.
Unit-IV: Memory: Basic concept and hierarchy, semiconductor RAM memories, 2D & 2 1/2D
memory organization. ROM memories. Cache memories: concept and design issues &
performance, address mapping and replacement Auxiliary memories: magnetic disk, magnetic
tape and optical disks ,Virtual memory: concept implementation.
Unit V: Input / Output: Peripheral devices, I/O interface, I/O ports, Interrupts: interrupt
hardware, types of interrupts and exceptions. Modes of Data Transfer: Programmed I/O, interrupt
initiated I/O and Direct Memory Access., I/O channels and processors. Serial Communication:
Synchronous & asynchronous communication, standard communication interfaces..

04-09-2023
Faculty Name :Dr.Sharmila Unit -2
5
Course Objective
The objective of this course is to discuss the basic concepts and structure of
computers. Students will understand the concepts of register transfer logic,
arithmetic operations, and different types of addressing modes. They will also
learn the memory organization, different types of serial communication
techniques, and Instruction execution stages of processor.

Course Outcome
CO1 :Study of the basic structure and operation of a digital
computer system.
CO2: Analysis of the design of arithmetic & logic unit and
understanding of the fixed point and floating point arithmetic
operations.
CO3: Implementation of control unit techniques and the concept of
Pipelining
CO4: Understanding the hierarchical memory system, cache
memories and virtual memory.
CO5:Understanding the different ways of communicating with I/O
devices and standard I/O interfaces.
04-09-2023 6

Program Outcomes
1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics,
natural sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate consideration
for the public health and safety, and the cultural, societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities with
an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.
04-09-2023 7

Program Outcomes
7. Environment and Sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need
for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader
in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive
clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage
in independent and life-long learning in the broadest context of technological change
04-09-2023 8

CO-PO Mapping
04-09-2023 9

End Semester Question Paper Template
https://docs.google.com/document/d/1BveHJiCZscr81UoFnzuw2o_kuL2bH
qcM/edit?usp=drive_link&ouid=113601798732220097258&rtpof=true&sd=
true
04-09-2023 10

Brief Introduction about the Subject with Videos
This course is designed with an aim of educating students to understand the basic
concepts of computer architecture and organization that can help the students to have a
clear view as to how a computer system works. Computer architecture and
Organization focuses on the function and design of various components necessary to
process information digitally. The study of computer architecture and organization
focuses on the interface between hardware and software, and emphasizes the structure
and behavior of the system. Students will understand the concepts of register transfer
logic, arithmetic operations, and different types of addressing modes. They will also
learn the memory organization, different types of serial communication techniques,
and Instruction execution stages of processor.
04-09-2023 11

Prerequisite and Recap
Pre-requisites of course: Basic concepts in digital circuit design,
Components of computer
04-09-2023 12

Unit content
• Unit- II: Arithmetic and logic unit: Look ahead carries
adders. Multiplication: Signed operand multiplication, Booths
algorithm and array multiplier. Division and logic operations.
Floating point arithmetic operation, Arithmetic & logic unit
design. IEEE Standard for Floating Point Numbers
04-09-2023 13

04-09-2023
14
Unit Objective
1. Student will be able to understand the Arithmetic and logic
unit of Central processing Unit.
2. Students will be able to understand how the signed operand
multiplication is carried out using Booths Algorithm and array
multiplier.
3. Students will be able to understand the Division and logic
operations.
4. Students will be able to Floating point arithmetic operation, and
IEEE Standard for Floating Point Numbers

04-09-2023
15
Topic Objective
Analysis of the design of arithmetic & logic unit and understanding of the fixed
point and floating point arithmetic operations.

Notes
• Introduction
• What does an Adder mean?
• Types of Adders
– Half Adder
– Full Adder
– How are they different?
– Applications of Full Adders
– Parallel Adders
• Carry Look Ahead (CLA) or Look Ahead Carry
Adder
• Important Questions

Introduction
• Digital computers perform various arithmetic
operations.
• One of the basic operations is Addition of two
binary digits.
• The first 3 operations produce a sum whose
length is 1 digit but when the last operation is
performed sum is two digits.

Introduction
04-09-2023 Faculty Name :Dr.Sharmila Unit -2
Source: https://www.jaincolab.com/4-bit-binary-full-adder-and-subtractor
18

Introduction
• The higher bit is called carry and lower bit is
called sum.
• This operation is called a half – adder operation.
• The circuit which performs this is known as a
Full Adder.

So what does an “adder” mean?
• It’s a digital circuit that performs addition of
numbers.
• For CPU, it is used to calculate addresses, table
indices and similar operations.
• It can be constructed for many numerical
representations.
– Such as – Binary – Coded Decimal (BCD) or Excess-3
(XS3) - the most common adders which operate on
binary numbers

Types of Adders
• Half Adder
• Full Adder
• Look Ahead Carry or Carry Look-Ahead (CLA)
Adder
• & many more…

Half Adder
• The half adder adds two
single binary digits A and
B
• It has two outputs, sum
(S) and carry (C).
– Sum = AB’ + A’B
– Carry = A * B
• Requires XOR & AND
gates for design.

Full Adder
• A combinational circuit
that adds 3 input bits
to generate a Sum bit
and a Carry bit.
– Where X, Y, Cin are
inputs; C & S are
outputs.
Sum = X + Y + Cin
Carry = XY’ + YCin’ + CinX’

How are they different?
Criterion Half Adder Full Adder
Definition Adds two single bit digits Adds two 1-bit digits
Input Two data bits (a and b)
Two data bits (a and b)
and a carry from the
previous class (Cin)
Output Sum (S) and a Carry (C) Sum (S) and a Carry (Cout)
Carry Previous carry is not used Previous carry is used.
Componen
ts
XOR and an AND gate
Two XOR and two AND
gates, one OR gate
Usage Calculators, Computers Digital processors

Applications of a Full Adder
• Fundamental building block of on-chip libraries.
• Configured according to desired complexity of
arithmetic and numeric computations.
• In processors and other kinds of computing
devices, adders are used in the arithmetic logic
unit.
• Adders also use in other parts of the processor,
where they are used to calculate addresses, table
indices, & similar operations.

Look – Ahead Carry Adder
• A Look – Ahead Carry or Carry Look – Ahead (CLA) Adder is a fast
adder which improves speed by reducing the amount of time
required to determine carry bits. It reduces the time which are
delayed at each stage

Carry Generation & Propagation

Input Output
Row A B Cin Sum Cout Condition
0 0 0 0 0 0 No Carry
Generation
Cout = 0
1 0 0 1 1 0
2 0 1 0 1 0
Carry Propagation
Cout = Cin
3 0 1 1 0 1
4 1 0 0 1 0
5 1 0 1 0 1
6 1 1 0 0 1 Carry Generation
Cout = 1
7 1 1 1 1 1
28

• From truth table, carry generation in row 6
and 7 is given by:
Gi = AiBi
• Similarly the carry propagation Pi occurs with
either Ai = 1 and Bi = 0 or vice - versa:
Pi = Ai ⊕ Bi
Gi is known as the Carry Generate Signal
PI is known as the Carry Propagate Signal
29

• The new expressions for the output sum
and the carry out are given by:
Si = Pi ⊕ Ci
Ci+1 = Gi + Pi Ci

C1 = G0 + P0C0
C2 = G1 + P1C1 = G1 + P1 (G0 + P0C0) = G1 + P1G0 +
P1P0C0
C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0
C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 +
P3P2P1P0C0
• The general expression is :
Ci+1= Gi + PiGi-1 + PiPi-1Gi-2 + … PiPi-1…P2P1G0 + PiPi-1
….P1P0C0.

Carry Look Ahead - Structure
Fig. 3:
Look-
Ahead
Carry
generator
32

4-bit Carry Look-Ahead Adder
Adding all three figures from
the previous slide, we get a
4-bit Carry Look-Ahead
Adder
33

Merits & Demerits
• Merits:
– Reduced Propagation Time (Delay)
– Fastest Addition Logic
• Demerits:
– CLA is that the carry logic block gets very
complicated for more than 4 bits.
• CLAs are usually implemented as 4-bit modules and are
used in a hierarchical structure to realize adders that
have multiples of 4 bits.

Important Questions
• How do the computers add numbers?
• Explain half adder and full adder circuits with
suitable diagram.
• Design a 4-bit Carry Look-Ahead (CLA) adder and
explain its operation with examples.

Lecture 1 of Unit 2 is over…
• In the next lecture, we’ll see…
– Multiplication of signed binary numbers

– Multiplication of signed binary numbers

Lecture 2 – Multiplication
• Binary Multiplication
– Unsigned
– Signed

Binary Multiplication
• More complicated than addition
– A straightforward implementation will involve
shifts and adds
• More complex operation can lead to
– More area (on silicon) and/or
– More time (multiple cycles or longer clock cycle
time)
• Let’s begin from a simple, straightforward
method

Human way of multiplication
Each method has some pros and cons,
If we choose first it is quite
complicated to implement
the same in processor as
everything in processor is
Logic High and Logic Low.
For the second one, it take
O(n) times and you need to
take care in choosing lower
value as multiplier.
Third method shows
multiplication done
using Logic High(1’s)
and Logic Low(0’s).
If closely, every time 1’s and 0’s are multiplied with
the multiplicand and shifted left (2n) times.
Where n is the position of bit used by multiplier.
40

Straightforward Algorithm
01010010 (multiplicand)
01101101 (multiplier)
x
01010010
00000000
01010010
01010010
00000000
01010010
01010010
00000000
010001011101
010

x
000000000000000
(partial sum)

x
000000001010010
(partial sum)

000000001010010
(partial sum)
x
00000000

000000001010010
(partial sum)
x

000000001010010
(partial sum)
x
01010010

x
000000110011010
(partial sum)

000000110011010
(partial sum)
x
01010010

x
000010000101010
(partial sum)

000010000101010
(partial sum)
x
00000000

x
000010000101010
(partial sum)

000010000101010
(partial sum)
x
01010010

x
000111001101010
(partial sum)

x
01010010
000111001101010
(partial sum)

x
010001011101010
(partial sum)

010001011101010
(partial sum)
x
00000000

010001011101010 (full
sum)
x
This algorithm is also known as Shift – Add Multiplication.

Unsigned Number Multiplication
1 0 1 1 Multiplicand (11)
× 1 1 0 1 Multiplier (13)
1 0 1 1 Partial Product (PP)
0 0 0 0 PP
1 0 1 1 PP
1 0 1 1 PP
1 0 0 0 1 1 1 1 Product (143)

Unsigned Number Multiplication
• Note: if the multiplier bit is 1, then copy
multiplicand, otherwise 0
• We need a double length result

Algorithm
• M = 1011 Q = 1101 (q3 q2 q1 q0)
• Let a variable x be initialized to 0000 [4 bit
binary number]
– Since the bit q0 of multiplier is 1
• x = x + 1011 = 0000 + 1011 = 1011
• Right shift x 🡺 0 1 0 1 | 1
• x = x + 0000 = 0 1 0 1 | 1
• Right shift x 🡺 0 0 1 0 | 1 1

Algorithm
• x = x + 1011 =
• Right shift x 🡺 0 1 1 0 | 1 1 1
– x = x + 1011 =
• Right shift x 🡺 1 0 0 0 | 1 1 1 1 🡺 Result
(Product)
0 0 1 0 | 1 1
1 0 1 1
1 1 0 1 | 1 1
0 1 1 0 | 1 1 1
1 0 1 1
1 0 0 0 1 | 1 1 1
61

Second Example
10 x 5
1010 (M) 101 (Q)
X= 0000
• Since q0 is 1
• X= X + 1010 = 1010
• RS 🡺 0101 | 0
• Since q0 is 0
• X=X + 0000 = 0101 | 0
• RS 🡺 0010 | 10
• Since q0 is 1
• X = X + 1010
0010 | 10
1010
1100 | 10
• RS 🡺 0110 | 010
•Product – 0110010 (50)
62

Flowchart for Unsigned Binary
Multiplication

Try to understand this example…

Signed Multiplication
• Considering 2’s complement signed
operands, what will happen to (-13) × (+11) if
we follow the same method of unsigned
multiplication?

Sign extension of negative
multiplicand.
1 0 0 1 1 ( 13)
0 1 0 1 1
( +
11)
1 1 1 1 1 1 0 0 1 1
1 1 1 1 1 0 0 1 1
0 0 0 0 0 0 0 0
1 1 1 0 0 1 1
0 0 0 0 0 0
1 1 0 1 1 1 0 0 0 1 (143)
Sign
extension
is shown in
red
66

⚫For a negative multiplier, a straightforward solution is to
form the 2’s-complement of both the multiplier and the
multiplicand and proceed as in the case of a positive
multiplier.
⚫This is possible because complementation of both
operands does not change the value or the sign of the
product.
⚫A technique that works equally well for both negative
and positive multipliers – Booth algorithm.

Hardware Implementation:
68

Hardware Implementation
69

Example of a multiplier
• A Walther
WSR160 arithmometer from
1960.
• Each turn of the crank handle
adds (up) or
subtracts (down) the operand
set to the top register from the
value in the accumulator
register at the bottom.
• Shifting the adder left or right
multiplies the effect by ten.
70

Important Questions
• How do the computers multiply numbers?
• Why multiplication is tougher to implement
than addition in computer architecture?

Lecture 3 – Booth’s Multiplication
• Why we need another algorithm for binary
signed multiplication?
• What does the algorithm say?

Who is Booth?
The algorithm was invented
by Andrew Donald Booth in
1951 while doing research on
crystallography in London.
Source: https://history.computer.org/pioneers/booth-ad.html
73

Why do we need another algo?
• The previous methods do not work in
multiplying negative numbers.
• Solution 1
– Convert to positive if required
– Multiply as before
– If signs were different, negate answer
• Solution 2
– Booth’s algorithm

Booth’s Multiplication Algorithm
• Objective:
– To allow the multiplication of two signed binary
numbers in 2’s complement form.
• Advantage:
– This algorithm facilitates the process of multiplying
signed numbers.

Booth’s Multiplication Algorithm
• Booth’s analysis led him to conclude that
– The ALU which can add or subtract can be used to
get the same result in more than one way.
– Examples – 3 + 4 = 7 and 8 – 1 = 7
• At this time, shifting was faster than the
addition.
• Hence, reducing the no. of additions increased
performance.

Points to remember (for unsigned)
• Possible arithmetic actions:
– 00 🡺 no arithmetic operation
– 01 🡺 add multiplicand to left half of product
– 10 🡺 subtract multiplicand from left half of product
– 11 🡺 no arithmetic operation

Booth’s algo: (7) × (3)
A Q Q-1 M
3 7
0000 0011 0 0111
1001 0011 0 0111
A <- (A – M) 1st
cycle
1100 1001 1 0111 Shift
1110 0100 1 0111 Shift
0101 0100 1 0111
A <- (A + M) 2nd
cycle
0010 1010 0 0111 Shift
0001 0101 0 0111 Shift
78

Booth’s algo: (7) × (−3)
A Q Q-1 M
(-3) 7
0000 1101 0 0111
1001 1101 0 0111 A <- (A – M) 1st cycle
1100 1110 1 0111 Shift
0011 1110 1 0111 A <- (A + M) 2nd cycle
0001 1111 0 0111 Shift
1010 1111 0 0111 A <- (A – M) 3rd cycle
1101 0111 1 0111 Shift
1110 1011 1 0111 Shift
79

Flowchart
80

Truth Table
Q0 Q-1
(Add)’ /
Sub
Add / Subtract
Enable
Shift
0 0 × 0 1
0 1 0 1 1
1 0 1 1 1
1 1 × 0 1

Important Questions
• Show the multiplication process using Booth’s
algorithm when the following numbers are
multiplied : (+14) × (+13)
• Explain Booth’s algorithm with its flow chart and
hardware configuration. Multiply (-7) and (+3)
using Booth’s algorithm.

– Array Multiplier

Background & Motivation
• One of the most critical functions carried out
by ALU.
• Digital multiplication is the most extensively
used operation (especially in signal
processing), people who design digital signal
processors sacrifice a lot of chip area in order
to make the multiply as fast as possible
• Innumerable schemes have been proposed
for realization of the operation.

Multiplication Schemes
• Serial Multiplication (Shift-Add)
– Computing a set of partial products, and then
summing the partial products together.
– The implementations are primitive with simple
architectures (used when there is a lack of a
dedicated hardware multiplier)

Multiplication Schemes
• Parallel Multiplication
– Partial products are generated simultaneously.
– Parallel implementations are used for high
performance machines, where computation latency
needs to be minimized.

Principles of Array Multiplier
a3 a2 a1 a0
× b3 b2 b1 b0
a3b0 a2b0 a1b0 a0b0
a3b1 a2b1 a1b1 a0b1
a3b2 a2b2 a1b2 a0b2
a3b3 a2b3 a1b3 a0b3
p7 p6 p5 p4 p3 p2 p1 p0
• 4 × 4 bit multiplication
88

• For 4 × 4 Array Multiplier:
• 16 AND gates
• 4 HAs
• 8 FAs
• Total 12 Adders
• For m × n Array Multiplier:
• m × n AND gates
• n HAs
• (m – 2) × n FAs
• Total (m – 1) × n Adders
89

Advantages & Disadvantages
• Advantages:
– Minimum complexity
– Easily scalable &
pipelined
– Regular shape, easy to
place & route.
• Disadvantages:
– High power
consumption
– More digital gates
resulting in large chip
area.

Conclusions
• Array multiplier is implemented and verified in
Verilog.
• Although it utilizes more gates, the performance
can easily be increased using pipeline technique.
• As a parallel multiplication method, array
multiplier outperforms serial multiplication
schemes in terms of speed.

Important Questions
• What are array multipliers?
• How array multipliers are implemented? What
are the components required to build an 8 × 8
Array Multiplier?

– Division and Logic Operation

Lecture 5 – Division Operation
• Binary Division
• Division algorithms
– Restoring Division
– Non-restoring Division
• Important Questions

Binary Division
• Division of two fixed-point binary numbers in signed-
magnitude representation is done with paper and
pencil
• by a process of successive compare, shift and
subtract operations.
• Binary division is simpler than decimal division
• because the quotient digits are either 0 or 1 and,
• there is no need to estimate how many times the
dividend or partial remainder fits into the divisor.
97

Hardware Implementation
• It is identical to
multiplication.
• Register EAQ is now
shifted to the left
with 0 inserted into
Qn and the previous
value of E lost.

Restoring Division
• Positive divisor = Register M
• Positive dividend = Register Q
• Register A = 0
• After division is complete,
– Quotient = Q and Remainder = A

Restoring Division
• A ‘0’ bit is added at the left end of both A and M
to serve as a sign bit for subtraction.
• Algorithm:
– Do ‘n’ times (where n is no. of bits in Q)
• Shift A and Q left one binary position.
• Subtract M from A, placing the answer back in A (A = A –
M)
• If the sign of A is 1, set Q0 to 0 and add M back to A
(restore A); otherwise, set Q0 to 1.

Non-Restoring Division
• It is complex than the restoring one because
simpler operation are involved i.e. addition and
subtraction, also now restoring step is
performed.
• We rely on the sign bit of the register which
initially contains 0 named as A.

• Step 1: Q = Dividend, M = Divisor, A = 0, N = no. of bits in
dividend.
• Step 2: Check the sign bit (MSB) of register A.
• Step 3: If it is 1, then shift left contents of AQ and perform the
operation A = A + M, otherwise shift left AQ and perform the
operation A = A – M (means add 2’s complement of M to A and
store it to A).
• Step 4: Again check the sign bit of register A.

• Step 5: If sign bit is 1, then Q[0] becomes 0, otherwise 1 (Q[0]
means LSB of register Q)
• Step 6: Decrement value of N by 1.
• Step 7: If N not equal to 0, then go to Step 2, otherwise go to
next step.
• Step 8: If sign bit of A is 1, then perform A = A + M.
• Step 9: Register Q contains quotient and A contains remainder.

Important Questions
• Perform the division of following numbers using
restoring division algorithm:
– Dividend = 1 0 1 0
– Divisor = 0 0 1 1
• Similar questions using non-restoring division
algorithm can be asked.

Daily Quiz
1. The logic operations are simpler to implement using logic circuits.
a) True
b) False
Answer: a
2. The logic operations are implemented using _______ circuits.
a) Bridge
b) Logical
c) Combinatorial
d) Gate
Answer: c
3. In full adders the sum circuit is implemented using ________
a) And & or gates
b) NAND gate
c) XOR
d) XNOR
Answer: c

Daily Quiz
4. A _______ gate is used to detect the occurrence of an overflow.
a) NAND
b) XOR
c) XNOR
d) AND
Answer: b
5. We make use of ______ circuits to implement multiplication.
a) Flip flops
b) Combinatorial
c) Fast adders
d) None of the mentioned
Answer: c
6. The multiplier is stored in ______
a) PC Register
b) Shift register
c) Cache
Answer: b

Daily Quiz
7. The decimal numbers represented in the computer are called as floating point
numbers, as the decimal point floats through the number.
a) True
b) False
Answer: a
8. If the decimal point is placed to the right of the first significant digit, then the
number is called ________
a) Orthogonal
b) Normalized
c) Determinate
Answer: b
9. . ________ constitute the representation of the floating number.
a) Sign
b) Significant digits
c) Scale factor
d) All of the mentioned
Answer: d

Daily Quiz
10. The sign followed by the string of digits is called as ______
a) Significant
b) Determinant
c) Mantissa
d) Exponent
Answer: c
Explanation: The mantissa also consists of the decimal point.
11. In IEEE 32-bit representations, the mantissa of the fraction is said to occupy
______ bits.
a) 24
b) 23
c) 20
d) 16
Answer: b
12. The 32 bit representation of the decimal number is called as ___________
a) Double-precision
b) Single-precision
c) Extended format
Answer: b

Weekly assignment
1. Write a program to evaluate the arithmetic statement
X = (A+B*C) / (D-E/F+G)
• using a general register computer with three address instruction.
• using a general register computer with two address instruction.
• using an accumulator type computer with one address instruction.
• using a stack organized computer with zero address instruction.
2. A computer uses a memory unit with 128K words of 32 bits each. A binary
instruction code is stored in one word of memory. The instruction has four parts:
an indirect bit, an operation code, a register code part to specify one of 37
registers and an address part.
• How many bits are there in the operation code, the register code part and
the address part?
• Draw the instruction word format and indicate the number of bits in each
part?
• How many bits are there in the data and address inputs of the memory?

Faculty Video Links, Youtube & NPTEL Video
Links and Online Courses Details
• https://archive.nptel.ac.in/courses/106/105/10
6105163/

References
Text books:
1. Computer System Architecture - M. Mano
2. Carl Hamacher, Zvonko Vranesic, Safwat Zaky Computer Organization,
McGraw-Hill, Fifth Edition, Reprint 2012
3. John P. Hayes, Computer Architecture and Organization, Tata McGraw Hill,
Third Edition, 1998. Reference books
4. William Stallings, Computer Organization and Architecture-Designing for
Performance, Pearson Education, Seventh
edition, 2006.
5. Behrooz Parahami, “Computer Architecture”, Oxford University Press,
Eighth Impression, 2011.
6. David A. Patterson and John L. Hennessy, “Computer Architecture-A
Quantitative Approach”, Elsevier, a division of
reed India Private Limited, Fifth edition, 2012
7. Structured Computer Organization, Tannenbaum(PHI)

Old Question Paper
1. Explain Booth’s multiplication algorithm. Multiply (+15) and (+10) using
Booth’s algorithm.
2. Show the contents of the registers E, A, Q, SC during the process of
multiplication of two binary numbers 11111 (multiplicand) & 10101
(multiplier). The signs are not included.
3. Discuss the advantages and disadvantages of using a variable length
instruction format?
4. Design a 4-bit Carry-Look ahead Adder and explain its operation with an
example.
5. Make & Explain Arithmetic & Logic Unit design?
Represent the following decimal numbers in IEEE standard floating point
format :-
a) -1.75
b) 21
6. Differentiate between fixed point representation and floating point
representation. Explain with suitable examples?
7. Show the multiplication process using Booth’s algorithm when the
following numbers are multiplied : (+14) X (+13)

Old Question Paper
8. Represent (1460.125)10 in Single Precision and Double Precision formats.
9. Explain Booth’s algorithm with its flow chart and hardware configuration.
Multiply (-7) and (+3) using Booth’s algorithm.
10. Why does increasing the amount of data that can stored in a processor’s
register file, generally increase the performance of the processor?
11. What are the four essential elements of a number in floating point
notation?

Expected Questions for Exam
1. Explain Booth’s multiplication algorithm. Multiply (+15) and (+10) using Booth’s
algorithm.
2. Show the contents of the registers E, A, Q, SC during the process of multiplication of
two binary numbers 11111 (multiplicand) & 10101 (multiplier). The signs are not
included.
3. Discuss the advantages and disadvantages of using a variable length instruction
format?
4. Design a 4-bit Carry-Look ahead Adder and explain its operation with an example.
5. Make & Explain Arithmetic & Logic Unit design?
Represent the following decimal numbers in IEEE standard floating point format :-
a) -1.75
b) 21
6. Differentiate between fixed point representation and floating point representation.
Explain with suitable examples?
7. Show the multiplication process using Booth’s algorithm when the following numbers
are multiplied : (+14) X (+13)

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