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![List of tables PM3533
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. Operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Electrical characteristics of SMPS full power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Electrical characteristics of SMPS section mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. SMPS operation parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. SMPS inductor specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Information classified Company restricted - Do not copy (See last page for obligations)
Table 8. SMPS capacitor specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. SMPS performance with critical components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 10. Boost full power mode general electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. Boost converter operation parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 12. Inductor specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Company restricted
Table 13. Capacitor specification for Boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 14. DC-DC closed-loop mode electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 15. Buck DC-DC converter operating parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 16. Inductor specification for closed-loop mode DC-DC converter usage . . . . . . . . . . . . . . . . 38
Table 17. Capacitor specification for closed-loop mode DC-DC converter usage . . . . . . . . . . . . . . . 38
Table 18. Current output capability / nominal voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 19. Regulator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 20. Power-up timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 21. D/A-converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 22. PADAC coding table by setting ‘48’ [in dec] for fused values . . . . . . . . . . . . . . . . . . . . . . . 43
Table 23. I/O pad accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 24. RF control voltage output parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 25. Thermal shutdown parameter table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 26. Battery monitoring characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 27. Under Voltage Lockout characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 28. MUX1 register writings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 29. PM3533 Kelvin nodes for self test purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 30. Power up timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 31. Power down timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 32. Data interface timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 33. SPI control signal timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 34. PM3533 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 35. Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 36. Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 37. Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 38. Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 39. Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 40. Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 41. Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 42. Register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 43. Register 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 44. Register 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 45. Register 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 46. Register 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 47. Register 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 48. Register 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
8/77 CD00271682 Rev 3](https://image.slidesharecdn.com/cd00271682pm3533datasheetrev31968-111011021759-phpapp01/85/CD00271682_PM3533_datasheet_rev3-8-320.jpg)
![PM3533 SMPS for PA
5.3 Operating parameters for SMPS converter
Characteristics to be met over the operating temperature range specified in Table 3:
Operation conditions unless otherwise stated.
Table 6. SMPS operation parameters
Symbol Parameter Min Typ Max Unit Notes
Voltage levels and regulation
Operating input voltage Accuracy: +/- 3%
Vi_oper1 5.82 6 6.18 V
Information classified Company restricted - Do not copy (See last page for obligations)
(full power mode) BOOST OUTPUT
Operating input voltage Accuracy: +/- 3%
Vi_oper2 5.15 5.3 5.45 V
(full power mode) BOOST OUTPUT
Operating input voltage Accuracy: +/- 3%
Vi_oper3 3.88 4 4.12 V
Company restricted
(full power mode) BOOST OUTPUT
Operating input voltage Accuracy: +/- 3%
Vi_oper4 4.18 4.3 4.42 V
(full power mode) BOOST OUTPUT
Lowest power levels
Boost-converter is in by-
Operating input voltage Vbat min pass mode when SMPS
Vi_oper_low Vbat min V
(low power mode) - 350 mV input voltage is VBAT.
NOTE: Depends on the
application usage
smps_ctrl at (default gain setting)
0.023 0.066 0.073 0.080 Accuracy: +10.0/- 9.5%
0.03 0.088 0.095 0.103 Accuracy: +8.0/- 7.9%
0.1 0.326 0.318 0.311 Accuracy: +2.6/- 2.3%
0.4 1.269 1.272 1.277 Accuracy: +0.4/-0.2%
Vout
0.75 2.385 V (used as a ratio reference)
-[-30;+85]°C
1.00 3.195 3.243 Accuracy: +0.2/+0.05%
1.25 3.982 4.001 Accuracy: +0.65/+0.2%
1.55 4.964 5.097 Accuracy: +3.4/+0.7%
1.59 5.097 5.446 Accuracy: +7.7/+0.8%
1.62 5.198 5.461 Accuracy: +6.0/+0.9%
Look at smps_ctrl = 0.75V /
g1 3.18
Gain, Vout Vout = 2.385V above
g2 3.38 Optional (via bit control)
Iload=1.25A @Vi_oper2
Dropout Switching freq 9.5 MHz.
Included LC DCR/ACR
voltage at room Note: Minimum delay setting 370 420 mV
temp used @ Vi_oper2. values (see Section 5.4
values)
Iload=1.25A @Vi_oper2
Dropout
Switching frequency typ of Included LC DCR/ACR
voltage 270 350 mV
5.0 MHz @ Vi_oper2. (1) values (see Section 5.4
-[-30;+85]°C
values)
CD00271682 Rev 3 21/77](https://image.slidesharecdn.com/cd00271682pm3533datasheetrev31968-111011021759-phpapp01/85/CD00271682_PM3533_datasheet_rev3-21-320.jpg)
![SMPS for PA PM3533
Table 6. SMPS operation parameters (continued)
Symbol Parameter Min Typ Max Unit Notes
@Vout max= 4.7 V
Note: Max currents are
Iload Load current 1.2 1.7 A defined during the GSM
burst. MAX value includes
PA current consumption in
worst case VSWR case.
Load current in GSM mode @Vout max= 3.6 V
when Boost-converter is by-
Information classified Company restricted - Do not copy (See last page for obligations)
Note: Max currents are
Iload_mode passed or PA max power is 2.5 A
defined during the GSM
achieved lower than
nominal SMPS Vout value. burst.
Note: PA is in power-down
mode.
Company restricted
No load current Includes internal clock and
Inol drivers and internal
consumption 3 3.5 mA
-[-30;+85]°C regulator quiescent
Switching freq 9.5MHz currents.
Converter in full power
mode
Note: PA is in power-down
mode and PM3533 is in
Iidle
Idle current 0.6 0.8 mA idle mode.
-[-30;+85]°C
Regulators are on.
Clock and drivers are off.
Clock range can be tuned with 5+
1-bit
6.5 13.5
Adjustable Internal clock (with the 1stset of reduction /
f_osc (4.7/7.9) (11.7 /14.9) MHz
increment bits)
(typical values) [2.1/5.3] [8.2/10.5]
[with the 2nd set of reduction /
increment bits]
7.1 10.0 Tuning range over temp, vbat and
f_osc_tuning_ corners.
[5.7, [9.3,
range OTP tuning range MHz [extended range available
4.2, 5.8,
dedicated control bits:
-[-30;+85]°C 3.3] 5.45] set 1, set2, set3]
f_osc_tuning_ Can be tuned with OTP
memory and with 4+1-bit
acc 160 230 350 kHz
current bias. Absolute
-[-30;+85]°C
accuracy.
Delta
Tuned OTP freq shift over
f_osc_shift 450 ΔkHz
vbat and temp.
-[-30;+85]°C
f_osc_d1 Selectable 2MHz dither
Dither deviation 1 1.9 2 MHz
-[-30;+85]°C deviation
f_osc_d2 Selectable 4MHz dither
Dither deviation 2 3.7 4 MHz
-[-30;+85]°C deviation
Vin 300mVpp perturbation.
Line_tr (2) Line transient response mVpp Trise/tfall=10 µs.
Iload = 1.25 A DC
22/77 CD00271682 Rev 3](https://image.slidesharecdn.com/cd00271682pm3533datasheetrev31968-111011021759-phpapp01/85/CD00271682_PM3533_datasheet_rev3-22-320.jpg)
![PM3533 SMPS for PA
Table 6. SMPS operation parameters (continued)
Symbol Parameter Min Typ Max Unit Notes
Vin=Vbat range
Transients from 10 mA to
Load_tr (2) Load transient response (3)
mVpp
1250 mA.
Trise = Tfall = 13 µs.
PSRR sine wave perturbation
Mode1 Iout = 1200 mA 35 dB
[-30;+85]°C <10 kHz
Information classified Company restricted - Do not copy (See last page for obligations)
Efficiency in GSM-mode
Vin = 5 V. Iload 1.25 A @ Iload = 1.25A (GSM burst
[-30;+85]°C Vout, typ = 4.6 V 93 95 % rms current value). Full
Switching freq 9.5 MHz power mode
Company restricted
Vin = 3.6 V. Iload 0.52A @ SMPS full power mode,.
[-30;+85]°C Vout = 2 V, 89 92 % Boost converter by-passed
Switching freq 9.5 MHz (active mode)
Vin = 3.6 V. Iload 0.17 A @ SMPS Section mode,.
[-30;+85]°C Vout = 1.1 V, 79 83 % Boost converter by-passed
Switching freq 9.5 MHz (active mode)
Vin = 5.0 V. Iload 0.52 A @
SMPS full power mode in
[-30;+85]°C Vout = 2 V, 87.5 90.5 %
VUSB case
Switching freq 9.5 MHz
Vin = 5.0 V. Iload 0.17 A @
Vout = 1.1 V, SMPS section mode in
[-30;+85]°C 74 77 %
VUSB case
Switching freq 9.5 MHz
Efficiency in WCDMA-mode
Vin = 3.6 V. Iload 0.5 A @ SMPS Section power
[-30;+85]°C Vout, typ = 3.37 V 93 94.5 % mode, Boost by-passed
Switching freq 2.1 MHZ (active mode)
Vin = 3.6 V. Iload 0.15 @ SMPS section mode,
[-30;+85]°C Vout = 1.6V, 85 88 % Boost by-passed (passive
Switching freq 2.1 MHZ mode)
Vin = 3. 6V. Iload 0.045 @ SMPS section mode,
[-30;+85]°C Vout = 0.77 V, 62 68 % Boost by-passed (passive
Switching freq 2.1 MHZ mode) (4)
Vin = 5.0 V. Iload 0.5 A @
Vout, typ = 3.37 V SMPS section power mode
[-30;+85]°C 92 93.5 %
in VUSB case
Switching freq 2.1 MHZ
Vin = 5.0 V. Iload 0.15 @
SMPS section mode in
[-30;+85]°C Vout = 1.6V, 81 84 %
VUSB case
Switching freq 2.1 MHZ
Vin = 5.0 V. Iload 0.045 @
SMPS section mode in
[-30;+85]°C Vout = 0.77 V, 56 62 %
VUSB case
Switching freq 2.1 MHZ
CD00271682 Rev 3 23/77](https://image.slidesharecdn.com/cd00271682pm3533datasheetrev31968-111011021759-phpapp01/85/CD00271682_PM3533_datasheet_rev3-23-320.jpg)
![PM3533 Boost DC-DC converter
Table 11. Boost converter operation parameters (continued)
Symbol Parameter Min Typ Max Unit Remarks
Note: PA is in power-down mode and
PM3533 is thus in idle mode
Quiescent current (no (i.e.SMPS_ctrl=0V).
Iq1 load) Full power mode 14 26 mA Includes internal clock & control blocks
Switching freq 7 MHz and boost trap capacitor circuitry & power
stages, and also internal regulator
quiescent currents
Adjustable Internal
Information classified Company restricted - Do not copy (See last page for obligations)
f_osc 4.5 11.4 MHz Clock range can be tuned with 5-bit
clock (typical values)
f_osc_tuning
Tuning range over temp, vbat and
_range OTP tuning range 6.8 8.0 MHz
corners.
[30; +85°C]
Company restricted
f_osc_tuning
Can be tuned with OTP memory and with
_acc 160 220 330 kHz
4-bit current bias. Absolute accuracy.
[30; +85°C]
Delta
f_osc_shift 450 ΔkHz Tuned OTP freq shift over vbat and temp.
[-30; +85°C]
f_osc_d1
Dither deviation1 1.9 2 MHz Selectable 2 MHz dither deviation
[-30; +85°C]
f_osc_d2
Dither deviation2 3.7 4 MHz Selectable 4 MHz dither deviation
[-30; +85°C]
Vin 300 mVpk perturbation.
Line_tr(1) Line transient (2) Trise/tfall=10 µs. Iload = 1200 mA.
mVpp
[-30; +85°C] response(1). In the application SMPS and BOOST
blocks are in series.
Vin= 3.6 V
Load_tr Load transient
250 mVpp Transients from 10 mA to 1250 mA
[-30; +85°C] response(1)
Trise = Tfall = 13.3 µs.
Line_tr
Line regulation(1). 0.1 0.2 mV Vin 2.7 – 5.3V, Iload 1200 mA
[-30; +85°C]
Load_tr Iload 10 mA – 1200 mA, Vin 5 V,
Load regulation(1) 20 mV
[-30; +85°C] Vin 2.7 V
PSRR Mode Boost+ SMPS
35 dB sine wave perturbation <10 kHz
[-30; +85°C] Iout = 1250 mA
Efficiency - condition Vbat = 3.6 V
Vbatt = 3.6 V
Iload 1.2 A
η @ Vout = 5.3 V, 89 92 % Boost in full power mode
switching freq 7 MHz
over full Temp. range
CD00271682 Rev 3 29/77](https://image.slidesharecdn.com/cd00271682pm3533datasheetrev31968-111011021759-phpapp01/85/CD00271682_PM3533_datasheet_rev3-29-320.jpg)
![PM3533 BUCK DC-DC converter
7 BUCK DC-DC converter
The BUCK DC-DC-converter design topology used is similar to the SMPS one. DC-DC-
converter control is performed via the reference voltage.
Figure 13. Buck DC-DC-converter simplified block diagram
Information classified Company restricted - Do not copy (See last page for obligations)
Company restricted
7.1 DC-DC closed-loop mode, critical electrical parameters
The most critical parameters are collected in Table 14.
Table 14. DC-DC closed-loop mode electrical characteristics
Symbol Parameter Min Typ Max Unit
VBAT Input voltage range 2.3 4.4 V
Vout1 Output voltage, programmable 1.35 V
Vout2 Output voltage, programmable 1.45 V
Vout3 Output voltage, programmable 1.65 V
Vout4 Output voltage, programmable 1.55 V
Vout5 Output voltage, programmable 1.85 V
Iout Output current range 400 mA
Active current consumption (no load
Iq 3.5 4.5 mA
current (1);
Efficiency with 100mA load
[-30;+85]°C VBAT 3.6V, switching freq 2.1 MHz, 87 88 %
Vout 1.45 V (coil 3u3, case 2520)
CD00271682 Rev 3 33/77](https://image.slidesharecdn.com/cd00271682pm3533datasheetrev31968-111011021759-phpapp01/85/CD00271682_PM3533_datasheet_rev3-33-320.jpg)
![BUCK DC-DC converter PM3533
Table 14. DC-DC closed-loop mode electrical characteristics (continued)
Symbol Parameter Min Typ Max Unit
Efficiency with 150mA load
[-30;+85]°C VBAT 3.6V, switching freq 2.1 MHz, 89 90 %
Vout 1.45 V (coil 3u3, case 2520)
Efficiency with 200mA load
[-30;+85]°C VBAT 3.6V, switching freq 2.1 MHz, 89 90 %
Vout 1.45 V (coil 3u3, case 2520)
Efficiency with 300mA load
Information classified Company restricted - Do not copy (See last page for obligations)
[-30;+85]°C VBAT 3.6V, switching freq 2.1 MHz, 88 89.5 %
Vout 1.45 V (coil 3u3, case 2520)
Max continuous load current 400 mA
Programmable switching frequency
1.8 4.5 MHz
Company restricted
(5-bit)
Startup time (function of load LC
10(2) µs
circuitry)
1. In the continuous conduction mode of coil current
2. For example, C=10 µF, L=2.2 µH
7.2 Operating requirements for BUCK DC-DC converter
The following characteristics are to be met over the operating temperature range specified
in Table 3: Operation conditions, unless otherwise stated.
Table 15. Buck DC-DC converter operating parameters
Symbol Parameter Min Typ Max Unit Notes
Voltage levels and regulation
Operating input
Vi_oper 2.3 4.4 V
voltage
Accuracy +/- 3%. Including
Output voltage 1) 1.309 1.350 1.390 V ripple voltage and line/load
Output voltage 2) 1.406 1.450 1.493 V regulation.
Vout1,2,3,4,5 Output voltage 3) 1.600 1.650 1.699 V Output voltage can be
Output voltage 4) 1.504 1.550 1.596 V programmed based on
Output voltage 5) 1.795 1.850 1.905 V battery voltage information
from base band.
Reference voltage External band-gap
Vref 1.182 1.200 1.218 V
accuracy reference voltage
RF IC is also included in
Iload Load current 10 400 mA
maximum Iload
Max. Iload and VBAT at
2.7 V
Ibatt VBAT input current 250 mA
Note: 1.45 V output
voltage used.
34/77 CD00271682 Rev 3](https://image.slidesharecdn.com/cd00271682pm3533datasheetrev31968-111011021759-phpapp01/85/CD00271682_PM3533_datasheet_rev3-34-320.jpg)
![PM3533 BUCK DC-DC converter
Table 15. Buck DC-DC converter operating parameters (continued)
Symbol Parameter Min Typ Max Unit Notes
Note: the RF IC is in
power-down mode and
PM3533 is in idle mode.
Quiescent current
(no load) Includes internal clock &
Iq 3.5 4.5 mA control blocks and boost
Switching frequency
trap capacitor
2 MHz
circuitry/power stages.Also
internal regulator
Information classified Company restricted - Do not copy (See last page for obligations)
quiescent currents.
Adjustable Internal Clock range can be tuned
f_osc 1.8 4.5 MHz
clock (typical values) with 5-bit
f_osc_
Tuning range over temp,
tuning_range OTP tuning range 2.5 2.8 MHz
Company restricted
vbat and corners.
[-30;+85]°C
f_osc_tuning_ Can be tuned with OTP
memory and with 4-bit
acc 60 120 kHz
current bias. Absolute
-[-30;+85]°C
accuracy.
Delta
f_osc_shift Tuned OTP freq shift over
250 kHz
vbat and temp.
-[-30;+85]°C
f_osc_d1 Selectable 1 MHz dither
Dither deviation1 0.8 1 MHz
-[-30;+85]°C deviation
f_osc_d2 Selectable 2 MHz dither
Dither deviation2 1.8 2 MHz
-[-30;+85]°C deviation
Vin 300 mVpk
Line_tr Line transient perturbation.
2 4 mVpp
Figure 14 response. Trise/tfall=10 µs
Iload = 400 mA.
Vin=2.3/3.6/ 4.4 V
Load_tr
Load transient Transients from 10 mA to
[-30;+85]°C 10 20 mVpp
response 400 mA
Figure 14
Trise = Tfall = 10 µs.
Line_tr
Vin 2.3 V – 4.4 V,
[-30;+85]°C Line regulation. 0.1 0.2 mV
Iload 400 mA
Figure 14
Load_tr
Iload 10 mA – 400 mA,
[-30;+85]°C Load regulation 1 2 mV
Vin 4.4 V, Vin 2.3 V
Figure 14
PSRR Mode1 sine wave perturbation
58 dB
[-30;+85]°C Iout = 400mA <10 kHz
CD00271682 Rev 3 35/77](https://image.slidesharecdn.com/cd00271682pm3533datasheetrev31968-111011021759-phpapp01/85/CD00271682_PM3533_datasheet_rev3-35-320.jpg)
![BUCK DC-DC converter PM3533
Table 15. Buck DC-DC converter operating parameters (continued)
Symbol Parameter Min Typ Max Unit Notes
Efficiency measured with coil 3u3 case2520, condition: Vbat 3.6 V closed-loop mode
Vin = 3.6 V.
Iload 300 mA
DC-DC in normal power
[-30;+85]°C @ Vout = 1.45 V 88 89.5 %
mode
Switching freq.
2.1MHz
Vin = 3.6 V.
Information classified Company restricted - Do not copy (See last page for obligations)
Iload 200 mA
DC-DC in normal power
[-30;+85]°C @ Vout = 1.45V 89 90 %
mode
Switching freq
2.1MHz
Vin = 3.6 V.
Company restricted
Iload 150 mA
DC-DC in normal power
[-30;+85]°C @ Vout = 1.45 V 89 90 %
mode
Switching freq
2.1MHz
Vin = 3.6 V.
Iload 100 mA
DC-DC in normal power
[-30;+85]°C @ Vout = 1.45 V 87 88 %
mode
Switching freq
2.1 MHz
Vin = 3.6 V.
Iload 60 mA
DC-DC in normal power
[-30;+85]°C @ Vout = 1.45 V 82 84 %
mode
Switching freq
2.1 MHz
Efficiency measured with coil 3u3 case2520, condition: VUSB 5.0 V closed-loop mode
Vbatt =5.0 V.
Iload 300 mA
Buck DC-DC in VUSB
[-30;+85]°C @ Vout = 1.45 V 86.5 88 %
case
Switching freq.
2.1MHz
Vin = 5.0 V.
Iload 200 mA
Buck DC-DC in VUSB
[-30;+85]°C @ Vout = 1.45V 87 89 %
case
Switching freq
2.1MHz
Vin = 5.0 V.
Iload 150 mA
Buck DC-DC in VUSB
[-30;+85]°C @ Vout = 1.45 V 86 87 %
case
Switching freq
2.1MHz
Vin = 5.0 V.
Iload 100 mA
Buck DC-DC in VUSB
[-30;+85]°C @ Vout = 1.45 V 83 84 %
case
Switching freq
2.1 MHz
36/77 CD00271682 Rev 3](https://image.slidesharecdn.com/cd00271682pm3533datasheetrev31968-111011021759-phpapp01/85/CD00271682_PM3533_datasheet_rev3-36-320.jpg)
![PM3533 BUCK DC-DC converter
Table 15. Buck DC-DC converter operating parameters (continued)
Symbol Parameter Min Typ Max Unit Notes
Vin = 5.0 V.
Iload 60 mA
Buck DC-DC in VUSB
[-30;+85]°C @ Vout = 1.45 V 77 79 %
case
Switching freq
2.1 MHz
Timing (refer to start-up and mode change section)
Initial condition:
Information classified Company restricted - Do not copy (See last page for obligations)
t_idle_dcdc Regulators on DC-DC-
Idle to operation
6 12 μs converter off, output
[-30;+85]°C Sampled soft-start
capacitor charged but not
loaded.
Power-off to
T_on_dcdc
Company restricted
DC-DC-converter power-
operation 35 55 μs
[-30;+85]°C up, output at 0V.
Sampled soft-start
Figure 14. Transient response requirement
tr<XXmV
overshoot
Vout Vout +/-tolerance
overshoot
tr<XXmV Note: During rise or fall recovery times,
there must be no unstable behaviour.
T_rec The fall recovery time is dependant on
Cout and load current
Load transient Load rise time = fall = 10us Vin = Vout = constant.
Load step = Iload max.
Line transient Line fall time = rise = 10us Line step: 300mV. Iload = constant
= Ilaod max
CD00271682 Rev 3 37/77](https://image.slidesharecdn.com/cd00271682pm3533datasheetrev31968-111011021759-phpapp01/85/CD00271682_PM3533_datasheet_rev3-37-320.jpg)
![PM3533 Digital to analog converter
Table 21. D/A-converter characteristics (continued)
Symbol Characteristics Condition Min Typ Max Unit Note
Monotonic
behavior
INL1 Integral non-linearity 1.5 LSB
required @
VHI = 2.5 V
Monotonic
behavior
INL2 Integral non-linearity 0.9 LSB
required @
VHI = 2.6 V
Information classified Company restricted - Do not copy (See last page for obligations)
DNL Differential non-linearity 0.5 LSB
Maximum output voltage 2.2 V
DAC output voltage in PD 100 mV
Company restricted
Internal mux switch
Mux_res (use external resistor of 47ohm 35 55 mΩ
to get max of 100ohm as worst
case)
In addition to normal usage of the current mode PADAC it is possible to use extra added
feature in order to use a coded output current to have a better accuracy of PADAC output
current. During a mass-production phase and its OTP fusing phase PADAC output current
by a certain code of 48 [in dec] is read/saved to certain register bits so this information can
be taken into use by combining dedicated bits. Look at the register table in the end part of
this datasheet for further details of registers available.
The application sw is able to read these dedicated bits in the following way:
After a normal power-up, read reg15.bit_numbers of [10,5,0] + reg2.bit[7] = MSB…LSB
order of bits for saved value and by looking at the accurate measured output current
value like it is coded in the table below.
Table 22. PADAC coding table by setting ‘48’ [in dec] for fused values
Coded value [in decimal] Corresponding value [mA]
0 1.600
1 1.645
2 1.690
3 1.735
4 1.780
5 1.825
6 1.870
7 1.915
8 1.960
9 2.005
10 2.050
11 2.095
CD00271682 Rev 3 43/77](https://image.slidesharecdn.com/cd00271682pm3533datasheetrev31968-111011021759-phpapp01/85/CD00271682_PM3533_datasheet_rev3-43-320.jpg)
![Digital to analog converter PM3533
Table 22. PADAC coding table by setting ‘48’ [in dec] for fused values
Coded value [in decimal] Corresponding value [mA]
12 2.140
13 2.185
14 2.230
15 2.275
The following kind of an accuracy can be achieved through setting of reg9.bits[15...9] i.e.
‘1100001’ which equals to 48 [in dec] + enable_bit_of_padac. This setting is used while the
Information classified Company restricted - Do not copy (See last page for obligations)
coded value is saved like informed for corresponding output current values in the table
above, thus being saved during the fusing phase of the mass-production testing
Table 23. I/O pad accuracy
Company restricted
I/O PAD Parameter Min Typ Max Unit
PADAC1 or
Accuracy by ‘1100001’- value -50 +50 μΑ
PADAC2
Then it is straightforward to use this information like matching a linear equation with the
following characteristic equation:
PADAC_output_current(Padac_output_code_wanted)
= (y_offset / (48 - 1)) * (Padac_output_code_wanted - 1) + min_LSB_size
In which
min_LSB_size = 33uA
y_offset = Coded_value - min_LSB_size
* Coded_value (in μA) is read from the table PADAC coding table
With this added feature the following kind of an accuracy of
PADAC_output_current (Padac_output_code_wanted)
can be achieved as a function of different PADAC control bits in Reg9[15...10]:
Figure 17. Output current accuracy of PADAC coded characteristic equation
44/77 CD00271682 Rev 3](https://image.slidesharecdn.com/cd00271682pm3533datasheetrev31968-111011021759-phpapp01/85/CD00271682_PM3533_datasheet_rev3-44-320.jpg)
![PM3533 register description for closed-loop mode PM3533
Table 36. Register 1 (continued)
Register 1 Valid state Name Bit functional description
Enables functional measurement in test
bit 6 1 ENa_TEMP
mode
TSD_temp_ctrl => 00 150C;10 140C; 01
bit 7 1 TSD_fuse1
160C; 11 170C (used in test mode)
TSD_temp_ctrl => 00 150C;10 140C; 01
bit 8 1 TSD_fuse0
160C; 11 170C (used in test mode)
bit 9 1 Mux_VREG_ctrl_C2 (used only in test phase)
Information classified Company restricted - Do not copy (See last page for obligations)
bit 10 1 Mux_VREG_ctrl_C1 (used only in test phase)
bit 11 1 Mux_VREG_ctrl_C0 (used only in test phase)
bit 12 1 Mux_HV_ctrl C2 (used only in test phase)
Company restricted
bit 13 1 Mux_HV_ctrl C1 (used only in test phase)
bit 14 1 Mux_HV ctrl_C0 (used only in test phase)
bit 15 1 OTP_prog_ena Enables OTP signal paths in test phase
Table 37. Register 2
Register2 Valid state Name Bit functional description
Internal AFForce_bit[15].Frequency
bit 0 1 AFForce_bit[15]; RETKU reduction enable; 1.79MHz minus offset to
the SMPS value in register 14.
Internal AFForce_bit[16].Frequency
bit 1 1 AFForce_bit[16]; ITKU increasing enable; 1.35MHz plus offset to
the SMPS value in register 14.
bit 2 1 AFForce_bit[17] Internal AFForce_bit[17]
bit 3 1 AFForce_bit[18] Internal AFForce_bit[18]
bit 4 1 AFForce_bit[19] Internal AFForce_bit[19]
FuseData[15]; Programmed OTP RETKU
bit 5 read only FuseData[15]
bit. To read it keep reg15.bit='0'.
FuseData[16]; Programmed OTP ITKU bit.
bit 6 read only FuseData[16]
To read it keep reg15.bit='0'.
FuseData[39]. This is used for in serial
read-out of OTP memory. Keep
FuseData[39]/AFForce_bit[ reg14.bit15='0' to see this serial clocked
bit 7 read only data stream output i.e. D39.
17]
PADAC coded bit number 0 (LSB), others
look at register 15.
FuseData[18]. Programmed THSD Fuse0
bit 8 read only FuseData[18]
bit. To read it keep reg15.bit='0'.
FuseData[19]. Lower OTP mem MSB bit.
bit 9 read only FuseData[19] Programmed THSD Fuse1 bit. To read it
keep reg15.bit='0'.
62/77 CD00271682 Rev 3](https://image.slidesharecdn.com/cd00271682pm3533datasheetrev31968-111011021759-phpapp01/85/CD00271682_PM3533_datasheet_rev3-62-320.jpg)
![PM3533 PM3533 register description for closed-loop mode
Table 37. Register 2
Register2 Valid state Name Bit functional description
‘0' for enable sr_latch to output tsd_out
bit 10 0/1 tsd_mux1_ena state in pwmreg1.bit15; '1' reset sr_latch
output node to low state in pwmreg1.bit15.
In test mode smps rds_on low/high side
bit 11 0/1 rds_smps_low_high_ena sw can be set; '0' for low side; '1' for high
side
In test mode boost rds_on low/high side
Information classified Company restricted - Do not copy (See last page for obligations)
bit 12 0/1 rds_boost_low_high_ena sw can be set; '0' for low side; '1' for high
side
In test mode dcdc rds_on low/high side sw
bit 13 0/1 rds_dcdc_low_high_ena
can be set; '0' for low side; '1' for high side
In test_mode: '1'->'0' sequence to
bit 14 0/1 test_otp_reset
Company restricted
manually set otp_reset_pulse for OTP_cell
SMPS: the 5th delay tune for very high
bit 15 1 long_delay load impedances; when used set
reg3.bit[3...0]='1000'
Table 38. Register 3
Register3 Valid state Name Bit functional description
Delay tune for low side of driver chain;
bit 0 1 SMPS_ast_l beneficial for having minimum dropout
voltage (used ext coil res affects)
Delay tune for low side of driver chain;
bit 1 1 SMPS_ast_l beneficial at larger range of power levels
(GSM)
Delay tune for low side of driver chain;
beneficial at larger range of power level
bit 2 1 SMPS_ast_l
(GSM) but with larger dropout voltage
(used ext coil res affects)
Delay tune for low side of driver chain;
bit 3 1 SMPS_ast_l beneficial mid-to-low-power range loads
(WCDMA)
bit 4 1 Dither bandwidth 0 for 2.8MHz; 1 for 5.6MHz
bit 5 1 SMPS_Dither_ena SMPS dither enable
bit 6 1 SMPS_drw_inout SMPS drw in/out enable
SMPS_CTRL_bias/comp/ Enable for smps_ctrl bias. Enable for
bit 7 1
sawt smps_ctrl comparator/sawtooth
SMPS mode selection 00=PD, 01=bypass,
10=section, 11 normal (bits as bit '9', bit '8'
bit 8 1 SMPS mode selection
order) Cdoup_SMPS is enabled also with
01=bypass
bit 9 1 SMPS mode selection (used with bit 8)
CD00271682 Rev 3 63/77](https://image.slidesharecdn.com/cd00271682pm3533datasheetrev31968-111011021759-phpapp01/85/CD00271682_PM3533_datasheet_rev3-63-320.jpg)
![PM3533 register description for closed-loop mode PM3533
Table 41. Register 6 (continued)
Register 6 Valid state Name Bit functional description
bit 6 1 Batman_ENA Enable control for Batman_out
('0' for res_div (set bit8 to '0'); '1' for
bit 7 1 Batman_KelvinH
res_meas (set bit8 to '0'); test structures)
('0' for res_div (set bit7 to '0'); '1' for hi-Z
bit 8 1 Batman_KelvinL
state (set bit7 to '1'); test structures)
(‘00’ = PD, '10'=DC-DC_clock '01' =
bit 9 1 Clock divider enable SMPS_CLOCK, 11 = Boost_clock (bits
Information classified Company restricted - Do not copy (See last page for obligations)
9,10 order); used only in test phase)
bit 10 1 Clock divider enable (used only in test phase)
Enabling digital buffers for ANT_T1,
ANT_T2, RFCTRL3 I/Os,
Company restricted
1= Digital buffers enabled in application
ANT_T1_T2_RFCTRL3_
bit 11 1 mode,
ctrl
0= OTP_clock @ANT_T1 and
TSD_testsense @ANT_T2 enabled in test
mode.
Enable switch for RFCTRL3, 1=digital high
bit 12 1 RFCTRL3_set
state, 0=digital low_state
ANTENNA tuning switch control, 1=digital
bit 13 1 ANT_T1_antsw_set
high state, 0=digital low_state
ANTENNA tuning switch control, 1=digital
bit 14 1 ANT_T2_antsw_set
high state, 0=digital low_state
(0 = mux outputs 8- 13,
bit 15 1 MUX switch
1 = mux outputs 1-7; used in test phase)
Table 42. Register 7
Register 7 Valid state Name Bit functional description
SMPS feedback setting control: linked to
0x5C01 setting (and alternatively 0x5C0D
with reg2.bit0=’1’ and reg14.bit15=’1’ for
bit 0 1 SMPS_loop_fb3 lowest switching freq), additionally 0x5C05
or 0x5C09 (=recommended) with
reg2.bit0='1' and reg14.bit15='1' for the
semi-lowest switching frequency
Enables open loop gain increment option
bit 1 1 Open_gain_inc
(especially in EER/ET architecture)
Additional smps freq reduction (bits of
[3...2] combines 4 selections); can be used
bit 2 1 Freq_red1
in GSM/WCDMA (in OTP or in free-
running OSC modes)
Additional smps freq reduction (bits of
[3...2] combines 4 selections); can be used
bit 3 1 Freq_red2
in GSM/WCDMA (in OTP or in free-
running OSC modes)
66/77 CD00271682 Rev 3](https://image.slidesharecdn.com/cd00271682pm3533datasheetrev31968-111011021759-phpapp01/85/CD00271682_PM3533_datasheet_rev3-66-320.jpg)
![PM3533 register description for closed-loop mode PM3533
Table 43. Register 8 (continued)
Register 8 Valid state Name Bit functional description
Enable for DC-DC soft start; starts at
DCDC_ sampled output voltage; this bit is left for
bit 12 1
sampled_start_control sw compatibility (because it was like
fast_start before)
bit 13 1 DC-DCmux (DC-DC mux C0; used in test phase)
bit 14 1 DC-DCmux (DC-DC mux C1; used in test phase)
bit 15 1 DC-DCmux (DC-DC mux C2; used in test phase)
Information classified Company restricted - Do not copy (See last page for obligations)
Table 44. Register 9
Register 9 Valid state Name Bit functional description
bit 0 1 DC-DC_loop_fb1 DC-DC feedback setting control
Company restricted
bit 1 1 DC-DC_loop_fb1 DC-DC feedback setting control
bit 2 1 DC-DC_loop_fb1 DC-DC feedback setting control
bit 3 1 DC-DC_loop_fb2 DC-DC feedback setting control
bit 4 1 DC-DC_loop_fb2 DC-DC feedback setting control
bit 5 Reserved
bit 6 1 DC-DC_C_shunt Adds shunt capacitor into feedback loop
(Adds parallel resistor into feedback loop;
bit 7 1 DC-DC_paraR
used only in test phase)
(Enables 2.5V @Vref=1.2V; normally not
bit 8 1 OVER2VENA used in the closed-loop configuration of
SMPS usage in the rf subsystem)
bit 9 1 PA_DAC_XPD Enable for PA_DAC
bit 10 1 PA_DAC bit0 PA DAC control
bit 11 1 PA_DAC bit1 PA DAC control
bit 12 1 PA_DAC bit2 PA DAC control
bit 13 1 PA_DAC bit3 PA DAC control
bit 14 1 PA_DAC bit4 PA DAC control
bit 15 1 PA_DAC bit5 PA DAC control
Table 45. Register 12
Register 12 Valid state Name Bit functional description
bit 0 read only FuseDR[0] FuseDR[0] (Upper OTP mem LSB bit)
bit 1 read only FuseDR[1] FuseDR[1]
bit 2 read only FuseDR[2] FuseDR[2]
bit 3 read only FuseDR[3] FuseDR[3]
bit 4 read only FuseDR[4] FuseDR[4]
bit 5 read only FuseDR[5] FuseDR[5]
68/77 CD00271682 Rev 3](https://image.slidesharecdn.com/cd00271682pm3533datasheetrev31968-111011021759-phpapp01/85/CD00271682_PM3533_datasheet_rev3-68-320.jpg)
![PM3533 PM3533 register description for closed-loop mode
Table 45. Register 12
Register 12 Valid state Name Bit functional description
bit 6 read only FuseDR[6] FuseDR[6]
bit 7 read only FuseDR[7] FuseDR[7]
bit 8 read only FuseDR[8] FuseDR[8]
bit 9 read only FuseDR[9] FuseDR[9]
bit 10 read only FuseDR[10] FuseDR[10]
bit 11 read only FuseDR[11] FuseDR[11]
Information classified Company restricted - Do not copy (See last page for obligations)
bit 12 read only FuseDR[12] FuseDR[12]
bit 13 read only FuseDR[13] FuseDR[13]
bit 14 read only FuseDR[14] FuseDR[14]
Company restricted
bit 15 read only FuseDR[15] FuseDR[15]
Table 46. Register 13
Register 13 Valid state Name Bit functional description
bit 0 read only FuseDR[16] FuseDR[16]
bit 1 read only FuseDR[17] FuseDR[17]
bit 2 read only FuseDR[18] FuseDR[18]
bit 3 read only FuseDR[19] FuseDR[19] (Upper OTP mem MSB bit)
bit 4 read only Version_bit0 Coding of versions as follows (bit3...bit0)
PM3533: ‘001’ for v1.0
bit 5 read only Version_bit1
PM3533: ‘010’ for v1.0B
bit 6 read only Version_bit2
bit 7 read only Version_bit3
bit 8 read only Family_bit0 Coding of RF PM IC family
bit 9 read only Family_bit1 PM3533: ‘010’
bit 10 read only Family_bit2
bit 11 read only Man_bit0 Coding of RF PM IC manufacturer
bit 12 read only Man_bit1 PM3533: ‘111’
bit 13 read only Man_bit2
bit 14 Reserved
bit 15 Reserved
Table 47. Register 14
Register 14 Valid state Name Bit functional description
These bits adjust switching frequency so
bit 0 1 SMPS_clock_freq
that bits 00000 gives minimum freq
bit 1 1 SMPS_clock_freq and 11111 gives max freq.
CD00271682 Rev 3 69/77](https://image.slidesharecdn.com/cd00271682pm3533datasheetrev31968-111011021759-phpapp01/85/CD00271682_PM3533_datasheet_rev3-69-320.jpg)
![PM3533 register description for closed-loop mode PM3533
Table 47. Register 14
Register 14 Valid state Name Bit functional description
For SMPS: '00000': 6.48 MHz; '01101':
bit 2 1 SMPS_clock_freq
9.54 MHz; '01110': 9.77 MHz;
bit 3 1 SMPS_clock_freq '11111': 13.59 MHz (typical values)
(SMPS: Calibration range in the OTP used
bit 4 1 SMPS_clock_freq mode is 7.1 - 10.1 MHz when
reg7.bit[3...2]=’00’)
These bits adjust switching frequency so
Information classified Company restricted - Do not copy (See last page for obligations)
bit 5 1 BOOST_clock_freq
that bits 00000 gives minimum freq
bit 6 1 BOOST_clock_freq and 11111 gives max freq.
For Boost: '00000': 4.51 MHz; '01101':
bit 7 1 BOOST_clock_freq
7.52 MHz; '01110': 7.74 MHz;
Company restricted
bit 8 1 BOOST_clock_freq '11111':11.42 MHz (typical values)
(Boost: Calibration range in the OTP used
bit 9 1 BOOST_clock_freq
mode is 6.8 - 8.0 MHz)
These bits adjust switching frequency so
bit 10 1 DC-DC_clock_freq
that bits 0000 gives minimum freq
bit 11 1 DC-DC_clock_freq and 1111 gives max freq.
For RF-IC DCDC: '00000': 1.62 MHz;
bit 12 1 DC-DC_clock_freq
'01110'': 2.75 MHz;
'01111':2.83 MHz; '11111': 4.09 MHz
bit 13 1 DC-DC_clock_freq
(typical values)
(DCDC: Calibration range in the OTP used
bit 14 1 DC-DC_clock_freq
mode is 2.45 - 2.84 MHz)
0' sets OTP mode which uses trimmed
bit 15 1 DATA_ENA
values; '1' is for user set values.
Table 48. Register 15
Reg 15 Valid state Name Bit functional description
FuseData[0] (Lower OTP mem LSB bit) /
bit 0 read only FuseData[0]
PADAC coded bit number 1
1 read only FuseData[1] FuseData[1]
2 read only FuseData[2] FuseData[2]
3 read only FuseData[3] FuseData[3]
4 read only FuseData[4] FuseData[4]
5 read only FuseData[5] FuseData[5] / PADAC coded bit number 2
6 read only FuseData[6] FuseData[6]
7 read only FuseData[7] FuseData[7]
8 read only FuseData[8] FuseData[8]
9 read only FuseData[9] FuseData[9]
70/77 CD00271682 Rev 3](https://image.slidesharecdn.com/cd00271682pm3533datasheetrev31968-111011021759-phpapp01/85/CD00271682_PM3533_datasheet_rev3-70-320.jpg)
![PM3533 PM3533 register description for closed-loop mode
Table 48. Register 15 (continued)
Reg 15 Valid state Name Bit functional description
FuseData[10] / PADAC coded bit number
10 read only FuseData[10]
3
11 read only FuseData[11] FuseData[11]
12 read only FuseData[12] FuseData[12]
13 read only FuseData[13] FuseData[13]
14 read only FuseData[14] FuseData[14] (bits[19...15] in Reg2)
Information classified Company restricted - Do not copy (See last page for obligations)
15 read only FUSE_OK Internal Fuse_ok
Company restricted
CD00271682 Rev 3 71/77](https://image.slidesharecdn.com/cd00271682pm3533datasheetrev31968-111011021759-phpapp01/85/CD00271682_PM3533_datasheet_rev3-71-320.jpg)
More Related Content
CD00271682_PM3533_datasheet_rev3
- 1. PM3533 All-in-one energy management for smart phone RF solutions Preliminary Data Description PM3533 is an all-in-one solution for RF energy Information classified Company restricted - Do not copy (See last page for obligations) management and RF front-end control for GSM/EDGE/WCDMA/TD-SCDMA/LTE RF solutions. It is designed specifically to support Multi-Mode and Multi-Band Power Amplifier (MMMB PA); with >90% efficiency and 2.6 V cut- Company restricted off voltage support, PM3533 enable improved efficiency for PA and RF IC to maximizes the battery life time of smart phones. The PM3533 includes DCDC converters for transceiver and PA, PA bias DAC, linear regulated low noise supply for RF FE, GPIOs for antenna control of tunable antennas and SPI RF FE Features control. • All-in-one RF PMU • Supports 2.6 V to 5.5 V battery voltage range Applications • High efficiency 400 mA DCDC converter for RF • Multi-Mode and Multi-Band PA solutions transceiver • Mobile phones – five level programmable output voltage • Portable communication equipment • High efficiency 600 mA/1.5 A Buck DCDC converter for PA with analog control voltage • Navigation systems and connected devices • Boost DCDC converter for PA – BOOST by-pass mode – Enables support for low VBAT cut-off: 2.6 V • Line regulated low noise 2.5 V supply for RF FE components • PA bias DAC • Three GPIO signals for RF FE control • Battery voltage monitoring circuitry • Under-voltage-lockout circuitry • Thermal shutdown circuitry • Green product: lead-free/RoHs compliant. • VFBGA 3.4 mm x 3.4 mm x 1.0 mm with 0.4 mm pitch December 2010 CD00271682 Rev 3 1/77 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to www.stericsson.com 4 change without notice.
- 2. PM3533 Device summary Table 1. Device summary Features Range Temperature range -20°C to +85°C All specifications fulfilled Temperature range -30°C to +85°C Functional Information classified Company restricted - Do not copy (See last page for obligations) Battery voltage range 2.6 V to 5.5 V Package VFBGA 3.4 mm x 3.4 mm x 1.0 mm, 64 F8x8 DCDC1 - GSM PA operation Output voltage range 50 mV to 5.5 V Company restricted Control voltage range 0 to 1.5 V Maximum output current 1.5 A Efficiency 90% (combined efficiency of Boost-Buck) Efficiency 95% (Buck) Large signal loop BW 230 kHz DCDC1 – WCDMA PA operation Output voltage range 50 mV to Vin-150 mV Control voltage range 0 to 1.5 V Maximum output current 600 mA Efficiency 96% (Buck) Large signal loop BW 230 kHz DCDC2 for TRX Output voltage (Vout) 1.35 V, 1.45 V or 1.65 V Maximum output current 400 mA Efficiency 90% (Buck) PSRR ≤ 100 kHz 63 dB Start-up time 10 μs IDAC Resolution 6 bits Output current range 0 to 2.3 mA (Vout < 2.3 V) 2.5 V linear regulator Output voltage 2.5 V Maximum output current 60 mA PSRR ≤ 100kHz 40 dB 2/77 CD00271682 Rev 3
- 3. PM3533 Figure 1. DCDC1 GSM operation - Combined Boost-Buck DCDC 1 GSM PA operation (Buck/Boost) - VBAT= 3.6V DCDC 1 GSM PA operation (Buck/Boost) - VBAT= 3.6V 100 100 90 90 80 80 70 70 60 60 Eff (%) Eff (%) 50 50 40 40 30 30 20 20 Information classified Company restricted - Do not copy (See last page for obligations) 10 10 0 0 0.0 1.0 2.0 3.0 4.0 5.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Vout (V) Iload (A) Figure 2. DCDC1 GSM PA operation - Buck Company restricted DCDC 1 GSM PA operation (Buck) - VBAT= 3.6V DCDC 1 GSM PA operation (Buck) - VBAT= 3.6V 100 100 90 90 80 80 70 70 60 60 Eff (%) Eff (%) 50 50 40 40 30 30 20 20 10 10 0 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.2 0.4 0.6 0.8 1.0 Vout (V) Iload (A) Figure 3. DCDC1 WCDMA PA operation - Buck DCDC 1 WCDMA PA operation (Buck) - VBAT= 3.6V DCDC 1 WCDMA PA operation (Buck) - VBAT= 3.6V 100 100 90 90 80 80 70 70 60 60 Eff (%) Eff (%) 50 50 40 40 30 30 20 20 10 10 0 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.1 0.2 0.3 0.4 0.5 0.6 Vout (V) Iload (A) 3/77 CD00271682 Rev 3
- 4. PM3533 Figure 4. DCDC2 in TRX operation DCDC 2 TRX operation - VBAT= 3.6V, Vout= 1.45V 100 90 80 70 60 Eff (%) 50 40 30 20 Information classified Company restricted - Do not copy (See last page for obligations) 10 0 50 100 150 200 250 300 350 400 Iload (mA) Company restricted 4/77 CD00271682 Rev 3
- 5. PM3533 Contents Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 1.1.1 Special power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 General specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Information classified Company restricted - Do not copy (See last page for obligations) 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Company restricted 4 Reference design schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 SMPS for PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1 Closed-loop mode SMPS full power critical electrical parameters . . . . . . 19 5.2 Closed-loop mode SMPS section mode, critical electrical parameters . . 20 5.3 Operating parameters for SMPS converter . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 Critical external components for SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4.1 SMPS performance with critical components . . . . . . . . . . . . . . . . . . . . 26 6 Boost DC-DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1 Boost full power electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.2 Operating requirements for Boost DC-DC converter . . . . . . . . . . . . . . . . 28 6.3 Critical external components for Boost DC-DC converter . . . . . . . . . . . . 31 7 BUCK DC-DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.1 DC-DC closed-loop mode, critical electrical parameters . . . . . . . . . . . . . 33 7.2 Operating requirements for BUCK DC-DC converter . . . . . . . . . . . . . . . . 34 7.3 Critical external components for BUCK DC-DC converter . . . . . . . . . . . . 38 7.3.1 Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.3.2 Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8 Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.1 VHI regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 CD00271682 Rev 3 5/77
- 6. Contents PM3533 8.1.1 Power up for VHI regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9 Digital to analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10 RF controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Information classified Company restricted - Do not copy (See last page for obligations) 12 OTP memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13 Battery monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Company restricted 14 Under-voltage-lockout block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 15 Mux structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 15.1 MUX 1 controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 15.1.1 PM3533 self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 16 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 16.1 Power UP/DOWN sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 17 Control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 17.1 Data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 18 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 18.1 PM3533 ball-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 18.2 PM3533 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 19 PM3533 register description for closed-loop mode . . . . . . . . . . . . . . . 61 20 Example of WCDMA output power distribution curve . . . . . . . . . . . . . 72 21 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 21.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 21.2 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 22 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6/77 CD00271682 Rev 3
- 7. PM3533 Contents 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Information classified Company restricted - Do not copy (See last page for obligations) Company restricted CD00271682 Rev 3 7/77
- 8. List of tables PM3533 List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3. Operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4. Electrical characteristics of SMPS full power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 5. Electrical characteristics of SMPS section mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 6. SMPS operation parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 7. SMPS inductor specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Information classified Company restricted - Do not copy (See last page for obligations) Table 8. SMPS capacitor specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 9. SMPS performance with critical components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 10. Boost full power mode general electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 11. Boost converter operation parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 12. Inductor specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Company restricted Table 13. Capacitor specification for Boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 14. DC-DC closed-loop mode electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 15. Buck DC-DC converter operating parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 16. Inductor specification for closed-loop mode DC-DC converter usage . . . . . . . . . . . . . . . . 38 Table 17. Capacitor specification for closed-loop mode DC-DC converter usage . . . . . . . . . . . . . . . 38 Table 18. Current output capability / nominal voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 19. Regulator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 20. Power-up timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 21. D/A-converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 22. PADAC coding table by setting ‘48’ [in dec] for fused values . . . . . . . . . . . . . . . . . . . . . . . 43 Table 23. I/O pad accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 24. RF control voltage output parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 25. Thermal shutdown parameter table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 26. Battery monitoring characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 27. Under Voltage Lockout characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 28. MUX1 register writings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 29. PM3533 Kelvin nodes for self test purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 30. Power up timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 31. Power down timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 32. Data interface timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 33. SPI control signal timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 34. PM3533 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 35. Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 36. Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 37. Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 38. Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 39. Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 40. Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 41. Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 42. Register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 43. Register 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 44. Register 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 45. Register 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 46. Register 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 47. Register 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 48. Register 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 8/77 CD00271682 Rev 3
- 9. PM3533 List of tables Table 49. VFBGA 3.4 mm x 3.4 mm x 1.0 mm with 0.4 mm pitch and 0.25 mm ball . . . . . . . . . . . . . 73 Table 50. Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 51. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 52. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Information classified Company restricted - Do not copy (See last page for obligations) Company restricted CD00271682 Rev 3 9/77
- 10. List of figures PM3533 List of figures Figure 1. DCDC1 GSM operation - Combined Boost-Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. DCDC1 GSM PA operation - Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 3. DCDC1 WCDMA PA operation - Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 4. DCDC2 in TRX operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 5. PM3533 functional block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. PM3533 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Information classified Company restricted - Do not copy (See last page for obligations) Figure 7. Reference design schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8. USB application reference design schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 9. Step-down switching regulator based on Buck converter with voltage-mode control . . . . . 19 Figure 10. Transient response requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 11. Boost converter simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Company restricted Figure 12. Transient response requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 13. Buck DC-DC-converter simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 14. Transient response requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 15. Power up sequence timing diagram for VHI regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 16. DA-converter block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 17. Output current accuracy of PADAC coded characteristic equation . . . . . . . . . . . . . . . . . . 44 Figure 18. RF control connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 19. Thermal shutdown functional of modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 20. Simplified OTP bits connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 21. Under-voltage-lockout block overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 22. PM3533 multiplexer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 23. Power up sequence timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 24. Power down sequence timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 25. Timing waveform of writes cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 26. Timing waveform of read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 27. Serial data input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 28. PM3533 ball-out diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 29. DG09 WCDMA output power distribution curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 30. VFBGA 3.4 mm x 3.4 mm x 1.0 mm, 0.4 mm pitch, 0.25 mm ball . . . . . . . . . . . . . . . . . . . 74 Figure 31. Marking composition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10/77 CD00271682 Rev 3
- 11. PM3533 Overview 1 Overview PM3533 is RF energy management and RF FE control device that contains following functionalities: SMPS (Switched Mode Power Supply), Boost DC-DC converter, Buck DC- DC converter, several regulators for internal use and one regulator for external use. PM3533 also contains two antenna control IOs and two PA bias DAC outputs with the possibility to use the second DAC output also as third GPIO. Figure 5. PM3533 functional block diagram Information classified Company restricted - Do not copy (See last page for obligations) Company restricted 1.1 Main features • Antenna controls and PA control signals – Two antenna-tuning controls. Controls are programmable via the Serial Peripheral Interface (SPI). – One adjustable current reference for PA, with two multiplexed outputs. – One of the outputs can also be used a static control output • SMPS converter – SMPS converter optimized for both GSM and WCDMA power amplifiers – GSM mode bursts ramp-up/ramp-down capability – Two different operating modes, which are controlled via Serial Peripheral Interface (SPI). The operating modes are used to optimize SMPS efficiency at lower power levels. Operation modes are explained in Section 1.1.1. – Internal adjustable switching clock – Dithering. Dithering adds deviation to switching frequency, which lowers switching harmonic at output of SMPS. The deviation of the dithering is adjustable between two different frequencies. – Adjustable delay control for SMPS power switch drivers. – Adjustable integrated loop-filter. • Boost DC-DC converter – Boost DC-DC converter regulates the battery voltage up to 4.0 V, 4.3 V, 5.3 V or 6 V. CD00271682 Rev 3 11/77
- 12. Overview PM3533 – Three different operating modes are controlled by the Serial Peripheral Interface (SPI). The operating modes are used to optimize the power converter efficiency at lower power levels. The operation modes are explained in Section 1.1.1. – Sampled soft-start, to enable smooth transient behavior on Boost DC-DC converter output when starting the device or to continue from earlier idle (with its output already at the correct level) – Internal adjustable switching clock. – Dithering. Dithering adds deviation to switching frequency, which lowers switching harmonic at the output of the boost DC-DC converter. The deviation of the dithering is adjustable between two different frequencies Information classified Company restricted - Do not copy (See last page for obligations) • Buck DC-DC converter – The buck DC-DC converter down-regulates the battery voltage to 1.45 V. The output voltage is adjustable also to 1.65 V or 1.35 V, another normal usage set is 1.85 V or 1.55 V. – Sampled soft-start, to enable smooth transient behavior on Buck DC-DC converter Company restricted output when starting the device or to continue from earlier idle (with its output already at the correct level). – Internal adjustable switching clock. – Dithering. Dithering adds deviation to switching frequency, which lowers switching harmonic at the output of the buck DC-DC converter. The deviation of the dithering is adjustable between two different frequencies. • External regulators – PM3533 has one regulator for external use. VHI regulates the battery voltage to 2.6 V or 2.5 V. VHI is enabled automatically after power-up with default output voltage of 2.5V. • Multiplexer – PM3533 has one programmable multiplexer used to switch several analog node voltages to PM3533 MUX1 I/O. The battery-monitoring block is also connected to the multiplexer. Additionally MUX1 I/O can be used for self-testing purposes.Multiplexer structure is shown in Figure 22. • Serial Peripheral Interface (SPI) for PM3533 control. • Battery monitoring block. This block enables battery voltage monitoring during the operation and can also be used for self-testing purposes in production line. • Under Voltage Lockout block. This block adds special protection by automatically powering-down the boost power converter if abnormal power-downs occur at full power mode. • 40-bit OTP memory. One time programmable memory is needed to switch the frequency tuning for all three converters. Also TSD (Thermal shutdown cell) can be tuned with OTP memory. • Thermal shutdown – Thermal shutdown circuitry monitors the die temperature and fulfills a shutdown when a specified temperature is reached. Thermal protection is enabled automatically after power-up. 12/77 CD00271682 Rev 3
- 13. PM3533 Overview 1.1.1 Special power saving modes DCDC converters have “low power” operation modes, which reduce the current consumption in low power mode. The modes are controlled through the serial control interface. SMPS converter 1. “Low power” mode means that the size of power switches including the drivers are reduced at lower power levels. 2. Power switches are divided into two parts. In high power levels both parts are used Information classified Company restricted - Do not copy (See last page for obligations) while in low power levels only 1/3 part of the switches and their drivers are used. The decision on which mode is used comes from the base-band. Boost DC_DC converter Boost DC_DC converter includes two different power saving modes. Company restricted 1. “Full power” mode means that the boost DCDC converter at normal operational mode with the full output power capability. Enabling of this is coming from the base-band. 2. The boost converter has also a “By-Pass” mode, which corresponds to 100% duty cycle operation. In that mode the converter upper switch is turned on while the converter lower switch is turned off. The boost by-pass function can be used in low power levels by shutting down the boost-converter. CD00271682 Rev 3 13/77
- 14. General specifications PM3533 2 General specifications 2.1 Absolute maximum ratings Note: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Always use the operating conditions mentioned below when using the PM3533 in the application usage or similar kind of, to achieve the correct functionality and performance (look at Section 2.2: Operating conditions for further details). Information classified Company restricted - Do not copy (See last page for obligations) Table 2. Absolute maximum ratings Symbol Parameter Min Typ Max Unit IND_BOOST, INPUT_SMPS, Company restricted Supply voltage level -0.3 9 V VBATT, VBB_VRX SMPS_CTRL, DATA, ENABLE, Supply voltage level / control voltage level -0.3 2.7 V SCLK, XRESET, VREF, VXO Tj Junction temperature 150 °C TS Storage temperature -50 125 °C Electrostatic discharge integrity for pins connected to battery, ESDHBM -1000 +1000 V HBM(1) ESDCDM Electrostatic discharge protection, Charge device Model(2) -500 +500 V 1. Test conditions according to JESD22-A114. 2. Test conditions according to JESD22-C101. 2.2 Operating conditions Table 3. Operation conditions Symbol Parameter Min Typ Max Unit General electrical characteristics TOP Operating ambient temperature, all specifications fulfilled -20 +85 °C TOPF Operating ambient temperature, functional -30 +85 °C TJA Thermal resistance 50 °C/W VBAT Battery voltage in normal operation mode 2.6(1) 5.5 V VBATMAX Maximum battery voltage (due to charging) 4.8 5.5 V VBAT1 Battery voltage in normal operation mode with Vbuck_boost 2.3 5.5 V VBOOSTMAX Maximum up-converted voltage 6.5 V 14/77 CD00271682 Rev 3
- 15. PM3533 General specifications Table 3. Operation conditions (continued) Symbol Parameter Min Typ Max Unit VUSB USB supply voltage 4.75 5 5.25 V (2) (3) IAD Admissible current per ball 800 mA PMAX (4) Power dissipation 800 mW VBAT_Iload Battery current for PM3533 3 A Information classified Company restricted - Do not copy (See last page for obligations) VXO Digital power supply 2.1 2.5 V VXO_Iload Digital power supply current load (UVL enabled) 120 µA VIO Driver stage supply voltage 1.7 1.8 1.9 V VIO_Iload Driver stage supply current Iload 3.5 18 mA Company restricted Analog power supply DC 3.339 3.4 3.461 Vbuck_boost V TRAN -0.1 +0.1 Vbuck_boost_Iload Analog power supply current load 25 mA VREF Reference voltage 1.176 1.2 1.224 V VLOW Digital input/output low 0 0.67 V VINPUT,HIGH Digital input high 1.1 1.88 V VOUTPUT,HIGH Digital output high 1.5 1.88 V Ileak_vbat Leakage current from Vbat supply 120 µA 1. Analog power supply can be supplied from the Baseband Vbuck_boost or directly from the battery. When the Analog supply is fed from battery, PM3533 cut-off voltage is 2.6 V (typical) otherwise cut-off is 2.3 V 2. Analog power supply range in the USB mode is according to the USB standard specification. 3. USB supply voltage as low as 4.0 V is allowed and even under transient conditions minimum of 3.67 V is possible for a short period of time in the USB 3.0 specification. 4. Maximum that is allowed while taking into account internal losses at applicable load condition CD00271682 Rev 3 15/77
- 16. Block diagram PM3533 3 Block diagram PM3533 block diagram in the closed-loop mode environment is shown below. Figure 6. PM3533 block diagram Information classified Company restricted - Do not copy (See last page for obligations) Company restricted 16/77 CD00271682 Rev 3
- 17. PM3533 Reference design schematic 4 Reference design schematic Figure 7. Reference design schematic Information classified Company restricted - Do not copy (See last page for obligations) Company restricted CD00271682 Rev 3 17/77
- 18. Company restricted 18/77 Figure 8. Reference design schematic USB application reference design schematic CD00271682 Rev 3 PM3533 Information classified Company restricted - Do not copy (See last page for obligations)
- 19. PM3533 SMPS for PA 5 SMPS for PA Figure 9 shows the simplified schematic of PM3533 step-down switching regulator with basic functionality. The converter itself is a Buck converter with synchronous rectification. The control is realized using the so-called voltage-mode control. Figure 9. Step-down switching regulator based on Buck converter with voltage-mode control Information classified Company restricted - Do not copy (See last page for obligations) Company restricted 5.1 Closed-loop mode SMPS full power critical electrical parameters The most critical parameters are collected in Table 4. Table 4. Electrical characteristics of SMPS full power mode Symbol Parameter Min Typ Max Unit Vin Input voltage range 2.3 6 V Iout Max.output current range, bursted 2.5 A Active current consumption with no Iq 2.8 mA load current, 9.5 MHz clock, Vctrl 0V Efficiency with Iload1.2 A Vinput=3.6V , Vout=3.2V 92 94 % Freq 9.5MHz (coil loss included) Max continuous load current in 2 A +85 °C ambient temperature CD00271682 Rev 3 19/77
- 20. SMPS for PA PM3533 Table 4. Electrical characteristics of SMPS full power mode (continued) Symbol Parameter Min Typ Max Unit Programmable switching frequency 2.1 12 MHz (5-bit) Power-up time 10 µs 5.2 Closed-loop mode SMPS section mode, critical electrical parameters Information classified Company restricted - Do not copy (See last page for obligations) Table 5. Electrical characteristics of SMPS section mode Symbol Parameter Min Typ Max Unit Output current range. Continuous Company restricted Iout current over temp range and over life- 600 mA time Active current consumption with no Iq load current, switching freq 9.5 MHz. 2.8 mA SMPS_cntrl at 0 V Efficiency with VBAT=3.6 V, Iout = 80 mA, Vout = 0.95 V, 82 % f = 2.2 MHz Efficiency with VBAT=3.6V, Iout = 285 mA,Vout=3.4 V, 95 % f = 2.2 MHz Max load current, continuous at 500 (TBD) mA application level 20/77 CD00271682 Rev 3
- 21. PM3533 SMPS for PA 5.3 Operating parameters for SMPS converter Characteristics to be met over the operating temperature range specified in Table 3: Operation conditions unless otherwise stated. Table 6. SMPS operation parameters Symbol Parameter Min Typ Max Unit Notes Voltage levels and regulation Operating input voltage Accuracy: +/- 3% Vi_oper1 5.82 6 6.18 V Information classified Company restricted - Do not copy (See last page for obligations) (full power mode) BOOST OUTPUT Operating input voltage Accuracy: +/- 3% Vi_oper2 5.15 5.3 5.45 V (full power mode) BOOST OUTPUT Operating input voltage Accuracy: +/- 3% Vi_oper3 3.88 4 4.12 V Company restricted (full power mode) BOOST OUTPUT Operating input voltage Accuracy: +/- 3% Vi_oper4 4.18 4.3 4.42 V (full power mode) BOOST OUTPUT Lowest power levels Boost-converter is in by- Operating input voltage Vbat min pass mode when SMPS Vi_oper_low Vbat min V (low power mode) - 350 mV input voltage is VBAT. NOTE: Depends on the application usage smps_ctrl at (default gain setting) 0.023 0.066 0.073 0.080 Accuracy: +10.0/- 9.5% 0.03 0.088 0.095 0.103 Accuracy: +8.0/- 7.9% 0.1 0.326 0.318 0.311 Accuracy: +2.6/- 2.3% 0.4 1.269 1.272 1.277 Accuracy: +0.4/-0.2% Vout 0.75 2.385 V (used as a ratio reference) -[-30;+85]°C 1.00 3.195 3.243 Accuracy: +0.2/+0.05% 1.25 3.982 4.001 Accuracy: +0.65/+0.2% 1.55 4.964 5.097 Accuracy: +3.4/+0.7% 1.59 5.097 5.446 Accuracy: +7.7/+0.8% 1.62 5.198 5.461 Accuracy: +6.0/+0.9% Look at smps_ctrl = 0.75V / g1 3.18 Gain, Vout Vout = 2.385V above g2 3.38 Optional (via bit control) Iload=1.25A @Vi_oper2 Dropout Switching freq 9.5 MHz. Included LC DCR/ACR voltage at room Note: Minimum delay setting 370 420 mV temp used @ Vi_oper2. values (see Section 5.4 values) Iload=1.25A @Vi_oper2 Dropout Switching frequency typ of Included LC DCR/ACR voltage 270 350 mV 5.0 MHz @ Vi_oper2. (1) values (see Section 5.4 -[-30;+85]°C values) CD00271682 Rev 3 21/77
- 22. SMPS for PA PM3533 Table 6. SMPS operation parameters (continued) Symbol Parameter Min Typ Max Unit Notes @Vout max= 4.7 V Note: Max currents are Iload Load current 1.2 1.7 A defined during the GSM burst. MAX value includes PA current consumption in worst case VSWR case. Load current in GSM mode @Vout max= 3.6 V when Boost-converter is by- Information classified Company restricted - Do not copy (See last page for obligations) Note: Max currents are Iload_mode passed or PA max power is 2.5 A defined during the GSM achieved lower than nominal SMPS Vout value. burst. Note: PA is in power-down mode. Company restricted No load current Includes internal clock and Inol drivers and internal consumption 3 3.5 mA -[-30;+85]°C regulator quiescent Switching freq 9.5MHz currents. Converter in full power mode Note: PA is in power-down mode and PM3533 is in Iidle Idle current 0.6 0.8 mA idle mode. -[-30;+85]°C Regulators are on. Clock and drivers are off. Clock range can be tuned with 5+ 1-bit 6.5 13.5 Adjustable Internal clock (with the 1stset of reduction / f_osc (4.7/7.9) (11.7 /14.9) MHz increment bits) (typical values) [2.1/5.3] [8.2/10.5] [with the 2nd set of reduction / increment bits] 7.1 10.0 Tuning range over temp, vbat and f_osc_tuning_ corners. [5.7, [9.3, range OTP tuning range MHz [extended range available 4.2, 5.8, dedicated control bits: -[-30;+85]°C 3.3] 5.45] set 1, set2, set3] f_osc_tuning_ Can be tuned with OTP memory and with 4+1-bit acc 160 230 350 kHz current bias. Absolute -[-30;+85]°C accuracy. Delta Tuned OTP freq shift over f_osc_shift 450 ΔkHz vbat and temp. -[-30;+85]°C f_osc_d1 Selectable 2MHz dither Dither deviation 1 1.9 2 MHz -[-30;+85]°C deviation f_osc_d2 Selectable 4MHz dither Dither deviation 2 3.7 4 MHz -[-30;+85]°C deviation Vin 300mVpp perturbation. Line_tr (2) Line transient response mVpp Trise/tfall=10 µs. Iload = 1.25 A DC 22/77 CD00271682 Rev 3
- 23. PM3533 SMPS for PA Table 6. SMPS operation parameters (continued) Symbol Parameter Min Typ Max Unit Notes Vin=Vbat range Transients from 10 mA to Load_tr (2) Load transient response (3) mVpp 1250 mA. Trise = Tfall = 13 µs. PSRR sine wave perturbation Mode1 Iout = 1200 mA 35 dB [-30;+85]°C <10 kHz Information classified Company restricted - Do not copy (See last page for obligations) Efficiency in GSM-mode Vin = 5 V. Iload 1.25 A @ Iload = 1.25A (GSM burst [-30;+85]°C Vout, typ = 4.6 V 93 95 % rms current value). Full Switching freq 9.5 MHz power mode Company restricted Vin = 3.6 V. Iload 0.52A @ SMPS full power mode,. [-30;+85]°C Vout = 2 V, 89 92 % Boost converter by-passed Switching freq 9.5 MHz (active mode) Vin = 3.6 V. Iload 0.17 A @ SMPS Section mode,. [-30;+85]°C Vout = 1.1 V, 79 83 % Boost converter by-passed Switching freq 9.5 MHz (active mode) Vin = 5.0 V. Iload 0.52 A @ SMPS full power mode in [-30;+85]°C Vout = 2 V, 87.5 90.5 % VUSB case Switching freq 9.5 MHz Vin = 5.0 V. Iload 0.17 A @ Vout = 1.1 V, SMPS section mode in [-30;+85]°C 74 77 % VUSB case Switching freq 9.5 MHz Efficiency in WCDMA-mode Vin = 3.6 V. Iload 0.5 A @ SMPS Section power [-30;+85]°C Vout, typ = 3.37 V 93 94.5 % mode, Boost by-passed Switching freq 2.1 MHZ (active mode) Vin = 3.6 V. Iload 0.15 @ SMPS section mode, [-30;+85]°C Vout = 1.6V, 85 88 % Boost by-passed (passive Switching freq 2.1 MHZ mode) Vin = 3. 6V. Iload 0.045 @ SMPS section mode, [-30;+85]°C Vout = 0.77 V, 62 68 % Boost by-passed (passive Switching freq 2.1 MHZ mode) (4) Vin = 5.0 V. Iload 0.5 A @ Vout, typ = 3.37 V SMPS section power mode [-30;+85]°C 92 93.5 % in VUSB case Switching freq 2.1 MHZ Vin = 5.0 V. Iload 0.15 @ SMPS section mode in [-30;+85]°C Vout = 1.6V, 81 84 % VUSB case Switching freq 2.1 MHZ Vin = 5.0 V. Iload 0.045 @ SMPS section mode in [-30;+85]°C Vout = 0.77 V, 56 62 % VUSB case Switching freq 2.1 MHZ CD00271682 Rev 3 23/77
- 24. SMPS for PA PM3533 Table 6. SMPS operation parameters (continued) Symbol Parameter Min Typ Max Unit Notes Idle start-up Initially: regulators on and t_idle 5 μs From idle to operation SMPS is off. Device start-up Initially: PM3533 is t_on From shutdown to 15 μs shutdown. operation. 1. Minimum delay setting used 2. Transient response requirement clarification is illustrated in Figure 10. Information classified Company restricted - Do not copy (See last page for obligations) 3. These parameters are verified in system measurements in closed-loop mode RF engine platform. It should not inhibit GSMK modulation for burst power-up/down sequences 4. BOOST by-passed active mode means that BOOST serial switch is open by having charge pump activated. BOOST by- passed passive mode means that also charge pump is disabled. Company restricted 24/77 CD00271682 Rev 3
- 25. PM3533 SMPS for PA Figure 10. Transient response requirement tr<(mV) overshoot Vout Vout +/-tolerance overshoot Tr (mV) Note: During rise or fall recovery times, there must be no unstable behaviour. The fall T_rec recovery time is dependant on Cout and load current Information classified Company restricted - Do not copy (See last page for obligations) Load rise time = fall = Xus Vin = Vout = constant. Load transient Load step = Iload min to Iloadmax Line transient Line fall time = rise = Xus Line step: 300mV. xV < Vin < xV Company restricted Iload = constant = Mode1/Mode2 5.4 Critical external components for SMPS Inductor Table 7. SMPS inductor specification Symbol Parameter Min Typ Max Notes L Inductance (µH) 1 Peak current value when inductance is within Ira Rated current 1 (A) 1.5 ± 20 % tolerance, compared to measured typical value at 50% Irated. Rdc DC resistance (mohm) 60 Rdc is measured with Ira bias current Coil inductance compared to nominal value in Inductance tolerance nominal temperature should not change more Ltemp over temperature -5 +5 than specified over the operating temp. range. range (%) Measured with Ira bias current Measured with Ira bias current and Sf switching PL Power Loss (mW) 160 freq. Magnetic shielding TBD CD00271682 Rev 3 25/77
- 26. SMPS for PA PM3533 Capacitors Table 8 lists the specification for SMPS capacitor. Table 8. SMPS capacitor specification Parameter Specifications Size (target) 0603 Dielectric X5R/X7R Temperature range –30°C to +85°C Information classified Company restricted - Do not copy (See last page for obligations) Rated voltage 10 V DC Capacitance (typical) 0V Bias 470 nF +/-10 % Max. Capacitance change 0-5V DC Bias, over From initial value +/-10% temperature range, after aging Company restricted ESR @ 9 MHz (max) 20 mohm Maximum operating voltage 5.5 V DC Serial Inductance max. 1.8 nH 5.4.1 SMPS performance with critical components Table 9. SMPS performance with critical components Symbol Parameter Typ Unit Notes Cout ESR < 20 mohm, L=1 µH, Iload 10 mA to 1200 mA, Vo_ripple Ripple voltage 3.1 mVpp Switching frequency 9 MHz 26/77 CD00271682 Rev 3
- 27. PM3533 Boost DC-DC converter 6 Boost DC-DC converter Boost DC-DC-converter’s design topology is the same as SMPS. DC-DC-converter’s output voltage control is done with reference voltage and dedicated control bits. Figure 11. Boost converter simplified block diagram Information classified Company restricted - Do not copy (See last page for obligations) Company restricted 6.1 Boost full power electrical parameters Note: The most critical parameters are collected in Table 10 and Table 13. These tables are shown separately to ease the reading and best define the converter most critical parameters. Table 10. Boost full power mode general electrical characteristics Symbol Parameter Min Typ Max Unit Vin Input voltage range 2.3 4.4 V Vout1 Output voltage range, no load 5.3 V Vout2 Output voltage range, no load 4.0 V Vout3 Output voltage range, no load(1) 6.0 V Vout4 Output voltage range, no load 4.3 V Iout Boost input current range, bursted 3 A Active current consumption with no load current, full power Iq mode, 7 MHz clock, over temperature and Vbat range 14 26 mA (smps_ctrl=0V) CD00271682 Rev 3 27/77
- 28. Boost DC-DC converter PM3533 Table 10. Boost full power mode general electrical characteristics (continued) Symbol Parameter Min Typ Max Unit Efficiency with Iload=1.2 A VBAT=2.7 V, Vout=5.3 V, Switching frequency 7 MHz, over 80 83 % temperature Efficiency with Iload=1.2 A VBAT=3.6 V, Vout=5.3 V, Switching frequency 7 MHz, over 89 92 % temperature Efficiency with Iload=700 mA Information classified Company restricted - Do not copy (See last page for obligations) VBAT=3.6 V, Vout=5.3 V 92 94 % Switching freq 7 MHz, over temperature Max continuous input current in +85°C ambient temperature 2 A Programmable switching frequency (4-bit) 4.5 11.4 MHz Company restricted Output settling time (function of load LC circuitry) 10(2) µs 1. Restricted usage only during production calibration 2. For example L=1 µH C=10 µF 6.2 Operating requirements for Boost DC-DC converter Characteristics are to be met over the operating temp range specified in Table 3: Operation conditions unless otherwise stated. Table 11. Boost converter operation parameters Symbol Parameter Min Typ Max Unit Remarks Voltage levels and regulation Operating input Vi_oper 2.3 4.4 V voltage Accuracy +/- 3%. Including ripple voltage Vout_b1 Output voltage 5.15 5.3 5.45 V and line/load regulation Accuracy +/- 3%. Including ripple voltage Vout_b2 Output voltage 4 V and line/load regulation Accuracy +/- 3%. Including ripple voltage Vout_b3 Output voltage 6 V and line/load regulation Accuracy +/- 3%. Including ripple voltage Vout_b4 Output voltage 4.3 V and line/load regulation Normal mode means that PA is active. Max value includes also PA VSWR Load current in Iload 1 1250 1700 mA current. normal mode Note: Max current is defined during the GSM burst. Includes power coil ripple current Ibatt Vbatt Input current 3450 mA Note: Max current is defined during the GSM burst. 28/77 CD00271682 Rev 3
- 29. PM3533 Boost DC-DC converter Table 11. Boost converter operation parameters (continued) Symbol Parameter Min Typ Max Unit Remarks Note: PA is in power-down mode and PM3533 is thus in idle mode Quiescent current (no (i.e.SMPS_ctrl=0V). Iq1 load) Full power mode 14 26 mA Includes internal clock & control blocks Switching freq 7 MHz and boost trap capacitor circuitry & power stages, and also internal regulator quiescent currents Adjustable Internal Information classified Company restricted - Do not copy (See last page for obligations) f_osc 4.5 11.4 MHz Clock range can be tuned with 5-bit clock (typical values) f_osc_tuning Tuning range over temp, vbat and _range OTP tuning range 6.8 8.0 MHz corners. [30; +85°C] Company restricted f_osc_tuning Can be tuned with OTP memory and with _acc 160 220 330 kHz 4-bit current bias. Absolute accuracy. [30; +85°C] Delta f_osc_shift 450 ΔkHz Tuned OTP freq shift over vbat and temp. [-30; +85°C] f_osc_d1 Dither deviation1 1.9 2 MHz Selectable 2 MHz dither deviation [-30; +85°C] f_osc_d2 Dither deviation2 3.7 4 MHz Selectable 4 MHz dither deviation [-30; +85°C] Vin 300 mVpk perturbation. Line_tr(1) Line transient (2) Trise/tfall=10 µs. Iload = 1200 mA. mVpp [-30; +85°C] response(1). In the application SMPS and BOOST blocks are in series. Vin= 3.6 V Load_tr Load transient 250 mVpp Transients from 10 mA to 1250 mA [-30; +85°C] response(1) Trise = Tfall = 13.3 µs. Line_tr Line regulation(1). 0.1 0.2 mV Vin 2.7 – 5.3V, Iload 1200 mA [-30; +85°C] Load_tr Iload 10 mA – 1200 mA, Vin 5 V, Load regulation(1) 20 mV [-30; +85°C] Vin 2.7 V PSRR Mode Boost+ SMPS 35 dB sine wave perturbation <10 kHz [-30; +85°C] Iout = 1250 mA Efficiency - condition Vbat = 3.6 V Vbatt = 3.6 V Iload 1.2 A η @ Vout = 5.3 V, 89 92 % Boost in full power mode switching freq 7 MHz over full Temp. range CD00271682 Rev 3 29/77
- 30. Boost DC-DC converter PM3533 Table 11. Boost converter operation parameters (continued) Symbol Parameter Min Typ Max Unit Remarks Vbatt = 3.6 V Iload 0.7 A η @ Vout = 5.3 V, 92 94 % Boost in full power mode switching freq 7 MHz over full Temp range Vin = 2.7V Iload 1.2A η @ Vout = 5.3V 80 83 % Boost in full power mode Information classified Company restricted - Do not copy (See last page for obligations) switching freq 7 MHz over full Temp range Vin = 2.7 V Iload 0.35 A η @ Vout = 5.3 V, 91 94 % Boost in full power mode Company restricted Switching freq 7 MHz Over full temp range Timing (refer to start-up and mode change section) Initial condition: Regulators on Boost- Idle to operation 10 15 µs converter idle mode. Output capacitor Sampled soft-start charged but not loaded. Power-off to operation Boost converter initial power-up. Output 25 45 µs Sampled soft-start starts from Vbat - 350mV (typical). 1. Transient response requirement is illustrated in Figure 12. 2. These parameters are verified in system measurements on the close-loop mode RF engine platform. It should not inhibit GSMK modulation for burst power-up/down sequences 30/77 CD00271682 Rev 3
- 31. PM3533 Boost DC-DC converter Figure 12. Transient response requirement overshoot tr<XXmV Vout Vout +/-tolerance overshoot tr<XXmV Note: During rise or fall recovery times, there must be no unstable behaviour. The fall T_rec recovery time is dependant on Cout and load current Load rise time = fall = 10us Vin = Vout = constant. Load transient Information classified Company restricted - Do not copy (See last page for obligations) Load step = Iload max. Line transient Line fall time = rise = 10us Line step: 300mV. Iload = constant =Ilaod max Company restricted 6.3 Critical external components for Boost DC-DC converter Inductor Table 12. Inductor specification Symbol Parameter Min Typ Max Unit Notes L Inductance 1 µH Peak current value when inductance is within Ira Rated current 1 3 A ± 20 % tolerance, compared to measured typical value at 50% Irated. Rdc is measured with Ira Rdc DC resistance 50 mΩ bias current Coil inductance compared to nominal value in nominal temperature Inductance tolerance over should not change more Ltemp -5 +5 % temperature range than specified over the operating temp. range. Measured with Ira bias current Measured with Ira bias PL Power loss TBD W current and Sf switching freq. CD00271682 Rev 3 31/77
- 32. Boost DC-DC converter PM3533 Capacitor Table 13. Capacitor specification for Boost converter Parameter Specification Size (target) 0805 Dielectric X5R / X7R Temperature range –30°C to +85°C Rated voltage 10 V DC Information classified Company restricted - Do not copy (See last page for obligations) Capacitance (typical) 0V Bias 11 µF +/-10% or +/-20%, Min capacitance @ 6 V DC Bias 4 µF ESR @ 7.5 MHz (max) 20 mΩ Maximum operating voltage 6 V DC Company restricted 32/77 CD00271682 Rev 3
- 33. PM3533 BUCK DC-DC converter 7 BUCK DC-DC converter The BUCK DC-DC-converter design topology used is similar to the SMPS one. DC-DC- converter control is performed via the reference voltage. Figure 13. Buck DC-DC-converter simplified block diagram Information classified Company restricted - Do not copy (See last page for obligations) Company restricted 7.1 DC-DC closed-loop mode, critical electrical parameters The most critical parameters are collected in Table 14. Table 14. DC-DC closed-loop mode electrical characteristics Symbol Parameter Min Typ Max Unit VBAT Input voltage range 2.3 4.4 V Vout1 Output voltage, programmable 1.35 V Vout2 Output voltage, programmable 1.45 V Vout3 Output voltage, programmable 1.65 V Vout4 Output voltage, programmable 1.55 V Vout5 Output voltage, programmable 1.85 V Iout Output current range 400 mA Active current consumption (no load Iq 3.5 4.5 mA current (1); Efficiency with 100mA load [-30;+85]°C VBAT 3.6V, switching freq 2.1 MHz, 87 88 % Vout 1.45 V (coil 3u3, case 2520) CD00271682 Rev 3 33/77
- 34. BUCK DC-DC converter PM3533 Table 14. DC-DC closed-loop mode electrical characteristics (continued) Symbol Parameter Min Typ Max Unit Efficiency with 150mA load [-30;+85]°C VBAT 3.6V, switching freq 2.1 MHz, 89 90 % Vout 1.45 V (coil 3u3, case 2520) Efficiency with 200mA load [-30;+85]°C VBAT 3.6V, switching freq 2.1 MHz, 89 90 % Vout 1.45 V (coil 3u3, case 2520) Efficiency with 300mA load Information classified Company restricted - Do not copy (See last page for obligations) [-30;+85]°C VBAT 3.6V, switching freq 2.1 MHz, 88 89.5 % Vout 1.45 V (coil 3u3, case 2520) Max continuous load current 400 mA Programmable switching frequency 1.8 4.5 MHz Company restricted (5-bit) Startup time (function of load LC 10(2) µs circuitry) 1. In the continuous conduction mode of coil current 2. For example, C=10 µF, L=2.2 µH 7.2 Operating requirements for BUCK DC-DC converter The following characteristics are to be met over the operating temperature range specified in Table 3: Operation conditions, unless otherwise stated. Table 15. Buck DC-DC converter operating parameters Symbol Parameter Min Typ Max Unit Notes Voltage levels and regulation Operating input Vi_oper 2.3 4.4 V voltage Accuracy +/- 3%. Including Output voltage 1) 1.309 1.350 1.390 V ripple voltage and line/load Output voltage 2) 1.406 1.450 1.493 V regulation. Vout1,2,3,4,5 Output voltage 3) 1.600 1.650 1.699 V Output voltage can be Output voltage 4) 1.504 1.550 1.596 V programmed based on Output voltage 5) 1.795 1.850 1.905 V battery voltage information from base band. Reference voltage External band-gap Vref 1.182 1.200 1.218 V accuracy reference voltage RF IC is also included in Iload Load current 10 400 mA maximum Iload Max. Iload and VBAT at 2.7 V Ibatt VBAT input current 250 mA Note: 1.45 V output voltage used. 34/77 CD00271682 Rev 3
- 35. PM3533 BUCK DC-DC converter Table 15. Buck DC-DC converter operating parameters (continued) Symbol Parameter Min Typ Max Unit Notes Note: the RF IC is in power-down mode and PM3533 is in idle mode. Quiescent current (no load) Includes internal clock & Iq 3.5 4.5 mA control blocks and boost Switching frequency trap capacitor 2 MHz circuitry/power stages.Also internal regulator Information classified Company restricted - Do not copy (See last page for obligations) quiescent currents. Adjustable Internal Clock range can be tuned f_osc 1.8 4.5 MHz clock (typical values) with 5-bit f_osc_ Tuning range over temp, tuning_range OTP tuning range 2.5 2.8 MHz Company restricted vbat and corners. [-30;+85]°C f_osc_tuning_ Can be tuned with OTP memory and with 4-bit acc 60 120 kHz current bias. Absolute -[-30;+85]°C accuracy. Delta f_osc_shift Tuned OTP freq shift over 250 kHz vbat and temp. -[-30;+85]°C f_osc_d1 Selectable 1 MHz dither Dither deviation1 0.8 1 MHz -[-30;+85]°C deviation f_osc_d2 Selectable 2 MHz dither Dither deviation2 1.8 2 MHz -[-30;+85]°C deviation Vin 300 mVpk Line_tr Line transient perturbation. 2 4 mVpp Figure 14 response. Trise/tfall=10 µs Iload = 400 mA. Vin=2.3/3.6/ 4.4 V Load_tr Load transient Transients from 10 mA to [-30;+85]°C 10 20 mVpp response 400 mA Figure 14 Trise = Tfall = 10 µs. Line_tr Vin 2.3 V – 4.4 V, [-30;+85]°C Line regulation. 0.1 0.2 mV Iload 400 mA Figure 14 Load_tr Iload 10 mA – 400 mA, [-30;+85]°C Load regulation 1 2 mV Vin 4.4 V, Vin 2.3 V Figure 14 PSRR Mode1 sine wave perturbation 58 dB [-30;+85]°C Iout = 400mA <10 kHz CD00271682 Rev 3 35/77
- 36. BUCK DC-DC converter PM3533 Table 15. Buck DC-DC converter operating parameters (continued) Symbol Parameter Min Typ Max Unit Notes Efficiency measured with coil 3u3 case2520, condition: Vbat 3.6 V closed-loop mode Vin = 3.6 V. Iload 300 mA DC-DC in normal power [-30;+85]°C @ Vout = 1.45 V 88 89.5 % mode Switching freq. 2.1MHz Vin = 3.6 V. Information classified Company restricted - Do not copy (See last page for obligations) Iload 200 mA DC-DC in normal power [-30;+85]°C @ Vout = 1.45V 89 90 % mode Switching freq 2.1MHz Vin = 3.6 V. Company restricted Iload 150 mA DC-DC in normal power [-30;+85]°C @ Vout = 1.45 V 89 90 % mode Switching freq 2.1MHz Vin = 3.6 V. Iload 100 mA DC-DC in normal power [-30;+85]°C @ Vout = 1.45 V 87 88 % mode Switching freq 2.1 MHz Vin = 3.6 V. Iload 60 mA DC-DC in normal power [-30;+85]°C @ Vout = 1.45 V 82 84 % mode Switching freq 2.1 MHz Efficiency measured with coil 3u3 case2520, condition: VUSB 5.0 V closed-loop mode Vbatt =5.0 V. Iload 300 mA Buck DC-DC in VUSB [-30;+85]°C @ Vout = 1.45 V 86.5 88 % case Switching freq. 2.1MHz Vin = 5.0 V. Iload 200 mA Buck DC-DC in VUSB [-30;+85]°C @ Vout = 1.45V 87 89 % case Switching freq 2.1MHz Vin = 5.0 V. Iload 150 mA Buck DC-DC in VUSB [-30;+85]°C @ Vout = 1.45 V 86 87 % case Switching freq 2.1MHz Vin = 5.0 V. Iload 100 mA Buck DC-DC in VUSB [-30;+85]°C @ Vout = 1.45 V 83 84 % case Switching freq 2.1 MHz 36/77 CD00271682 Rev 3
- 37. PM3533 BUCK DC-DC converter Table 15. Buck DC-DC converter operating parameters (continued) Symbol Parameter Min Typ Max Unit Notes Vin = 5.0 V. Iload 60 mA Buck DC-DC in VUSB [-30;+85]°C @ Vout = 1.45 V 77 79 % case Switching freq 2.1 MHz Timing (refer to start-up and mode change section) Initial condition: Information classified Company restricted - Do not copy (See last page for obligations) t_idle_dcdc Regulators on DC-DC- Idle to operation 6 12 μs converter off, output [-30;+85]°C Sampled soft-start capacitor charged but not loaded. Power-off to T_on_dcdc Company restricted DC-DC-converter power- operation 35 55 μs [-30;+85]°C up, output at 0V. Sampled soft-start Figure 14. Transient response requirement tr<XXmV overshoot Vout Vout +/-tolerance overshoot tr<XXmV Note: During rise or fall recovery times, there must be no unstable behaviour. T_rec The fall recovery time is dependant on Cout and load current Load transient Load rise time = fall = 10us Vin = Vout = constant. Load step = Iload max. Line transient Line fall time = rise = 10us Line step: 300mV. Iload = constant = Ilaod max CD00271682 Rev 3 37/77
- 38. BUCK DC-DC converter PM3533 7.3 Critical external components for BUCK DC-DC converter 7.3.1 Inductor Table 16. Inductor specification for closed-loop mode DC-DC converter usage Symbol Parameter Min Typ Max Unit Notes L Inductance 3.3 µH Peak current value when inductance is Information classified Company restricted - Do not copy (See last page for obligations) Ira Rated current 1 0.6A A within ± 20 % tolerance, compared to measured typical value at 50% Irated. Rdc DC resistance 140 mΩ Rdc is measured with Ira bias current Coil inductance compared to nominal Company restricted value in nominal temperature should Inductance tolerance over Ltemp -5 +5 % not change more than specified over temperature range the operating temp. range. Measured with Ira bias current Measured with Ira bias current and Sf PL Power loss 1) TBD W switching freq. 7.3.2 Capacitor Table 17. Capacitor specification for closed-loop mode DC-DC converter usage Parameter Value Size (target) 0603 Dielectric X5R / X7R Temperature Range –30°C to +85°C Rated voltage 6.3 V DC Capacitance (typical) 0V Bias 10 µF +/-10% or +/-20%, Min Capacitance @ 2.8V DC Bias 6 µF Max capacitance @ 0V DC Bias 12 µF ESR @ 100 kHz (max) 20 mΩ Maximum operating voltage 5.5 V DC 38/77 CD00271682 Rev 3
- 39. PM3533 Regulators 8 Regulators PM3533 includes one linear regulator that can be used to supply low-power functions inside PM3533, RFIC and RF FE components. 8.1 VHI regulator The VHI regulator provides 2.6 V / 2.5 V output voltage. 2.6 V is a default value and 2.5 V can be selected via SPI interface. Information classified Company restricted - Do not copy (See last page for obligations) Note: 1 For 2.5 V mode: Full_perf (full performance) Vin>2.7 V, Reduced_perf (reduced performance) Vin between 2.6 V and 2.7 V; For 2.6V mode: Full_perf Vin>2.8V, Reduced_perf Vin between 2.7 V and 2.8 V Company restricted Table 18. Current output capability / nominal voltage Parameter Min Typ Max Unit Notes VHI output current 30 60 mA Table 19. Regulator specifications(1) Parameter Min Typ Max Unit Notes 0.02< ESR < 0.1 Ω External compensation capacitance 0.47 1 µF Iout=<60 mA Device to device output voltage variation. Output voltage device to device 2.510 2.605 2.69 V variation Over full temperature range, 2.425 2.500 2.575 V input voltage range, load range and Vref range (see Note 1) One sample. Over full 2.530 2.670 temperature range, input Output voltage: one sample variation V 2.445 2.555 voltage range and load range (see Note 1) 30/ Line regulation (1) /(PSRR) dB F < 10 kHz, Vin>Full_perf (50) 30/ Line regulation(2)/(PSRR) dB F < 100 kHz, Vin>Full_perf (40) F < 100 kHz, Vin=Reduced_perf Line regulation 0 10 dB range Over full temperature and load Load regulation 2 6 mV range, Input voltage >Full_perf Over full temperature and load range Load regulation 35 mV Input voltage =Reduced_perf range CD00271682 Rev 3 39/77
- 40. Regulators PM3533 Table 19. Regulator specifications(1) (continued) Parameter Min Typ Max Unit Notes Rise time (1% to 99%) 6 10 µs C = 1uF Voltage reference already On(3) Overshoot 3 % C = 1uF, turn on/off Settling time (0.1% of nominal), 90 mA, C = 1uF, turn on from register depends on load, voltage 20 30 µs write latch enable reference/bias already ON C = 1 µF Information classified Company restricted - Do not copy (See last page for obligations) Total noise density with specified Iload = 10 mA – 60 mA bandwidth, including VREF noise, 155 nVrms @ 1kHz temp, VBAT/Vbuck-boost 50 / √ Hz @ 100kHz 60 @ 1MHz Company restricted Short-circuit current. Note: the device does not tolerate 300 mA Output shorted to ground continuous short-circuit current Quiescent current 230 330 µA ON mode 1. Characteristics above are NOT valid if Vin < Full_perf range (see Note 1). 2. Line regulation is 20 dB for f < 100 kHz when battery voltage is lower than Full_perf range. 3. For 90 % rise time max is 10 µs. Rise time is defined in case when VREF and VXO are already settled. 8.1.1 Power up for VHI regulator VHI regulator’s power-up-timing-sequence is presented in Figure 15. The VXO supply voltage is used as enable signal for the VHI regulator. VHI regulator uses VREF as reference voltage and hence VREF must be activated for VHI to settle to the right output voltage level. The timing diagram below is representative only and therefore real power-up timings are linked to different application use cases and external filtering components (for instance on the external Vref line). Figure 15. Power up sequence timing diagram for VHI regulator 40/77 CD00271682 Rev 3
- 41. PM3533 Regulators Table 20. Power-up timing values Name Time Unit t0 0 µs t1 20 µs t2 30 µs t3 70 µs t4 270 µs t5 300 µs Information classified Company restricted - Do not copy (See last page for obligations) t6 350 µs Company restricted CD00271682 Rev 3 41/77
- 42. Digital to analogconverter PM3533 9 Digital to analog converter There is one 6–bit D/A converter inside PM3533 designed for PA bias control. The converter is supplied from VHI –supply and it provides a maximum output current up to a 2.2 V output voltage level. The DAC output is multiplexed between two different outputs PADAC1 and PADAC2. The DAC value and multiplexing are controlled via SPI. Figure 16. DA-converter block diagram Information classified Company restricted - Do not copy (See last page for obligations) Company restricted Note: Unused PADAC output should be left floating (it is internally pulled-down while at an off state). Operation characteristics are presented in Table 21. Table 21. D/A-converter characteristics Symbol Characteristics Condition Min Typ Max Unit Note N Resolution 6 bits Max output source current I_CTRL=x, Iout, max 2.2 2.5 mA DAC1 Vout<2.3V I_CTRL=0, Iout, min Min output source current 0 mA Vout=0V I_CTRL=x, Iout, LSB step size mA Vo<2.6V max/63 42/77 CD00271682 Rev 3
- 43. PM3533 Digital to analog converter Table 21. D/A-converter characteristics (continued) Symbol Characteristics Condition Min Typ Max Unit Note Monotonic behavior INL1 Integral non-linearity 1.5 LSB required @ VHI = 2.5 V Monotonic behavior INL2 Integral non-linearity 0.9 LSB required @ VHI = 2.6 V Information classified Company restricted - Do not copy (See last page for obligations) DNL Differential non-linearity 0.5 LSB Maximum output voltage 2.2 V DAC output voltage in PD 100 mV Company restricted Internal mux switch Mux_res (use external resistor of 47ohm 35 55 mΩ to get max of 100ohm as worst case) In addition to normal usage of the current mode PADAC it is possible to use extra added feature in order to use a coded output current to have a better accuracy of PADAC output current. During a mass-production phase and its OTP fusing phase PADAC output current by a certain code of 48 [in dec] is read/saved to certain register bits so this information can be taken into use by combining dedicated bits. Look at the register table in the end part of this datasheet for further details of registers available. The application sw is able to read these dedicated bits in the following way: After a normal power-up, read reg15.bit_numbers of [10,5,0] + reg2.bit[7] = MSB…LSB order of bits for saved value and by looking at the accurate measured output current value like it is coded in the table below. Table 22. PADAC coding table by setting ‘48’ [in dec] for fused values Coded value [in decimal] Corresponding value [mA] 0 1.600 1 1.645 2 1.690 3 1.735 4 1.780 5 1.825 6 1.870 7 1.915 8 1.960 9 2.005 10 2.050 11 2.095 CD00271682 Rev 3 43/77
- 44. Digital to analogconverter PM3533 Table 22. PADAC coding table by setting ‘48’ [in dec] for fused values Coded value [in decimal] Corresponding value [mA] 12 2.140 13 2.185 14 2.230 15 2.275 The following kind of an accuracy can be achieved through setting of reg9.bits[15...9] i.e. ‘1100001’ which equals to 48 [in dec] + enable_bit_of_padac. This setting is used while the Information classified Company restricted - Do not copy (See last page for obligations) coded value is saved like informed for corresponding output current values in the table above, thus being saved during the fusing phase of the mass-production testing Table 23. I/O pad accuracy Company restricted I/O PAD Parameter Min Typ Max Unit PADAC1 or Accuracy by ‘1100001’- value -50 +50 μΑ PADAC2 Then it is straightforward to use this information like matching a linear equation with the following characteristic equation: PADAC_output_current(Padac_output_code_wanted) = (y_offset / (48 - 1)) * (Padac_output_code_wanted - 1) + min_LSB_size In which min_LSB_size = 33uA y_offset = Coded_value - min_LSB_size * Coded_value (in μA) is read from the table PADAC coding table With this added feature the following kind of an accuracy of PADAC_output_current (Padac_output_code_wanted) can be achieved as a function of different PADAC control bits in Reg9[15...10]: Figure 17. Output current accuracy of PADAC coded characteristic equation 44/77 CD00271682 Rev 3
- 45. PM3533 RF controls 10 RF controls Two state IOs re designed to control the antenna switches. Figure 18. RF control connection Information classified Company restricted - Do not copy (See last page for obligations) Company restricted Table 24. RF control voltage output parameters Signal Parameter Min Typ Max Unit Notes name Voltage HI 2.43 2.6 V @ 0mA 2.51 LO 0 0.05 V @ -1mA Resistance sink 95 RFC1 ohm ANT1 Resistance source 50 Dynamic load 10 20 pF Switching time 1 us Voltage HI 2.43 2.6 V @ 0mA 2.51 LO 0 0.04 V @ -1mA Resistance sink 95 RFC2 ohm ANT2 Resistance source 50 Dynamic load 10 20 pF Switching time 1 us Voltage HI 2.43 2.6 V @ 0mA 2.51 LO 0 0.04 V @ -1mA Resistance sink 95 RFCTRL3 (other RFC3 ohm Resistance source 50 mode of muxed I/O) Dynamic load 10 20 pF Switching time 1 us CD00271682 Rev 3 45/77
- 46. Thermal shutdown PM3533 11 Thermal shutdown The thermal shutdown block protects the PM3533 from over-heating. The TSD block is used to shutdown functions when the temperature threshold limit is reached. When the temperature level is reached TSD shuts down the power stages of all converters, however all other PM3533 blocks are still active. The TSD function is enabled automatically whenever a power-up sequence is controlled. See the power-up diagrams for futher details in Figure 23. Information classified Company restricted - Do not copy (See last page for obligations) Figure 19. Thermal shutdown functional of modes Company restricted Table 25. Thermal shutdown parameter table Parameter Name Control bit Min Typ Max Unit Temperature Fuse <1:0> Tt170 147 170 183 °C threshold =11 Fuse <1:0> Tt160 137 160 173 °C =10 Fuse <1:0> Tt150 127 150 163 °C =00 Fuse <1:0> Tt140 117 140 153 °C =01 Hysteresis ΔT 13 17 °C Current Temp = 130 14 17 Idd µA consumption Temp = 170 21 35 With Accuracy <10 °C mismatching 46/77 CD00271682 Rev 3
- 47. PM3533 OTP memory 12 OTP memory One time programmable memory cell (OTP) is used for tuning purposes during PM3533 mass-production testing phase. Basic functionality of OTP macro cell: data is programmed serially through SCANIN pin on each CLOCK rising edge. OTP is programmed using an external high voltage HV solder bump at a wafer level. To sense the data stored in cell, a RESET pulse is required after power on. Fuse_ok signal indicates that data is available on D0 to D39 pins. PROG pin is needed to select the 20-bit block for the programming. Information classified Company restricted - Do not copy (See last page for obligations) PM3533 digital cell includes a multiplexer, which needs enabling and Fuse_ok controlling bits. Fuse_ok is generated during the OTP programming procedure, it indicates if the data_set is corrupted. If Fuse_ok is “1” and enable Reg14(15) bit is “0” the data set from antifuse can be used. If Reg14(15) is high and Fuse_ok is low, the multiplexer outputs the data which is programmed in register REG14(15:0). Reg15(15:0), Reg13(3:0) and Company restricted Reg12(15:0) can be used to read the whole OTP(39:0) memory content of two 20-bit memory blocks, these are available through the SPI (Serial Peripheral Interface) access to read all the OTP memory bits. Figure 20. Simplified OTP bits connection diagram CD00271682 Rev 3 47/77
- 48. Battery monitoring PM3533 13 Battery monitoring PM3533 includes a battery monitoring block. This block provides a scaled-down battery voltage information for a transceiver IC ADC through the MUX1 output ball. Table 26. Battery monitoring characteristics Parameter Min Typ Max Unit Notes PM3533 battery information output VBAT_inf VBAT/4 V voltage. Information classified Company restricted - Do not copy (See last page for obligations) 0.1% Battery monitoring accuracy device to Initial accuracy % device over temperature range 0.2% @ 100Meg Battery monitoring accuracy vs. load Load accuracy % 2% @ 10Meg resistance Company restricted 48/77 CD00271682 Rev 3
- 49. PM3533 Under-voltage-lockout block 14 Under-voltage-lockout block PM3533 includes an Under Voltage Lockout block. This block provides special protection mode to PM3533 and especially to its boost power converter while it is working at full-power mode and the modes of operation include sudden or abnormal power-downs (i.e. uncontrolled states of critical supply voltages like those are disappearing suddenly especially VBAT and/or VXO before XRESET signal is set low by an external control see Figure 24.) When UVL triggers it disables the internal control signals of the boost converter block which Information classified Company restricted - Do not copy (See last page for obligations) further disables the power stages of this converter making it disabled. This way boost converter is inhibited to have unwanted overshoots at its output voltage during like out-of- spec (VBAT/VXO uncontrolled power-downs) situations. This function is automatically enabled when normal power-up is controlled, as shown in Figure 23. The function is kept enabled by hard-wired internal control signals. Only the Company restricted Xreset signal asserting to '0' disables this function (at the reset state of PM3533). Figure 21. Under-voltage-lockout block overview Table 27. Under Voltage Lockout characteristics Parameter Min Typ Max Unit Notes UVL_Ena at low state & XRESET at high VBAT_trig 2.35 2.37 2.39 V state Boost_off to Boost_on, that is VBAT level VBAT_trig_hyst 170 mV of 2.54 V before boost_turned_on again UVL_Enal at low state & VXO_Mon_Ena VXO_trig 1.89 1.90 1.92 V at low state & XRESET at high state Boost_off to Boost_on i.e. VXO level of VXO_trig_hyst 60 mV 1.96 V before boost_turned_on again CD00271682 Rev 3 49/77
- 50. Mux structure PM3533 15 Mux structure PM3533 includes several nodes which can be multiplexed to MUX1 output pin or MUX2 output pin. Figure 22. PM3533 multiplexer structure MUX MAP for KAURA20 b_drw_out Information classified Company restricted - Do not copy (See last page for obligations) s_drw_out 1_1 d_drw_out 1_2 Mux_boost Ritsa_drw_out Ol 1_3 8 6mA_Vdig Temp 1_4 THPROTOUT 4_1 9 Company restricted VREG 50BD VIO Mux_smps 2 4_2 15 10 VIO VREG50S Mux dcdc Empty 4_3 11 empty VHI 3 14 D_drw_in 12 4_4 4 Batman 6mA_boost Empty 13 6mA_smps 4_5 5 6mA_dcdc 4_6 B_drw_in 6 4_7 7 IND_BOOST 1 OUT_BOOST 2 MUX1 IND_SMPS MUX2 3 INPUT_SMPS 4 IND_DCDC 5 IND_DCDC 5 Vbb_VRX GND_DCDC 6 7 GND_BOOST GND_SMPS 8 9 50/77 CD00271682 Rev 3
- 51. PM3533 Mux structure 15.1 MUX 1 controls Table 28. MUX1 register writings Switch Reg Bit value Explanation 1 reg6 bits 5,4,3 001 2 Reserved 011 3 Reserved 010 4 Reserved 100 Information classified Company restricted - Do not copy (See last page for obligations) 5 Reserved 101 6 Reserved 110 7 Reserved 111 8 Reg6 bits 2,1,0 001 BOOST_MUX Company restricted 9 Reserved 010 TEMP 10 Reserved 011 SMPS_MUX 11 Reserved 100 DCDC-MUX 12 Reserved 101 (empty) 13 Reserved 110 BATMAN 14 Reg6 bit 15 0/1 1 = Enables sw 1-7 output to sw 14 15 Reg1 bit 0 0/1 1 = Enables sw 1,2 output to sw 15 1_1 Reg06 bit9,10 1/0 01 = CLK DCDC 1_2 Reg06 bit9,10 1/0 10 = CLK SMPS 1_3 Reg06 bit9,10 1/0 11 = CLK Boost 1_4 Reg06 bit7, Reg06bit9,10 Reg06 bit7 =1, Reg06bit9,10 =00 4_1 Reg01 bit 11,10,9 001 4_2 Reserved 010 4_3 Reserved 011 4_4 Reserved 100 4_5 Reserved 101 4_6 Reserved 110 4_7 Reserved 111 CD00271682 Rev 3 51/77
- 52. Mux structure PM3533 15.1.1 PM3533 self test PM3533 has several Kelvin nodes which can be multiplexed to output pin MUX1 (see Figure 22). In closed-loop mode environment PM3533 MUX1 output pin is connected to the RF IC ADC which enables PM3533 self testing measurements. Table 29. PM3533 Kelvin nodes for self test purpose Expected Register setup Register setup Output ball Reg06 voltage Reg01 Reg06 Kelvin node what will be Note value at pin self tested MUX1 Bit 11 Bit 10 Bit 9 Bit 2 Bit 1 Bit 0 Bit 15 Information classified Company restricted - Do not copy (See last page for obligations) Battery voltage Battery Batman VBATT 0 0 0 1 0 0 0 divided by monitoring four Company restricted VBB_VRX, Driver VREF, VIO, stage VIO 0.9 0 1 1 0 0 0 1 GND_VIO, supply VXO voltage VBB_VRX, Driver VREF, VIO, stage VIO 0.9 0 1 0 0 0 0 1 GND_VIO, supply VXO voltage Regulator VHI 1.3 1 0 0 0 0 0 1 output 52/77 CD00271682 Rev 3
- 53. PM3533 Modes of operation 16 Modes of operation The device has several operating modes. There are a few active modes, power–down mode and several test modes. Most of the blocks can be turned on and off individually through the serial interface. The operating modes are described in the following sections. 16.1 Power UP/DOWN sequence Power UP/DOWN sequence described here must always be followed when powering the IC Information classified Company restricted - Do not copy (See last page for obligations) UP or DOWN (an order of external supply voltages and control signals). Mis-use of the IC can lead to shorter lifetime. The timing diagram below is representative only and therefore real power-up timings are linked to different application use cases and external filtering components (for instance on the external Vref line). Company restricted Note: Internal VDIG_int which gives a supply voltage to the digital interface of PM3533 follows approximately a rise time of the Vref line after high state of which (five worst case time constants of RextCext) PM3533 is ready to receive more accesses for controls i.e. external component filtering on the vref line dominates the wake-up time of PM3533 added with max current capability of an external buffer driving this external Vref line during its rising period. After all this Xreset is released and control accesses are allowed. Table 30. Power up timing values Name Time Unit t0 0 μs t1 30 μs t2 270 μs t3 300 μs t4 Figure 23. Power up sequence timing diagram CD00271682 Rev 3 53/77
- 54. Modes of operation PM3533 Table 31. Power down timing values Name Time Unit t5 μs t6 -40 μs t7 -30 μs t8 Reference μs Figure 24. Power down sequence timing diagram Information classified Company restricted - Do not copy (See last page for obligations) Company restricted 54/77 CD00271682 Rev 3
- 55. PM3533 Control interface 17 Control interface 17.1 Data interface PM3533 is programmed via the serial bus (SLE,SDATA,SCLK and RESET). SDATA data is clocked by SCLK rising edge. The data is fed with MSB first and address bits before data bits. PM3533 is in RESET state, when RESET signal is logical low. Table 32. Data interface timings Information classified Company restricted - Do not copy (See last page for obligations) Levels Min Max Unit High 1.5 V Low 0.5 V Company restricted Figure 25. Timing waveform of writes cycle Address Data SCLK SDAT A7 A6 A5 R/W A4 A3 A2 A1 A0 MSB LSB SLE Note: On SCLK rising edge, one bit of data is shifted in the shift register. SLE should be kept high when the interface is not used Figure 26. Timing waveform of read cycle Note: Data should read at the falling edge of SCLK. CD00271682 Rev 3 55/77
- 56. Control interface PM3533 Figure 27. Serial data input timing tslc tsdc tch thcd tcl tlh SCLK tclk SDAT Information classified Company restricted - Do not copy (See last page for obligations) tsll SLE Company restricted Table 33. SPI control signal timing table Symbol Parameter Min Max Unit tclk Clock cycle 52 ns tch SCLK high period 0.4*tclk 0.6*tclk ns tcl SLK low period 0.4*tclk 0.6*tclk ns tslc SLE to SCLK setup time 0.8*tcl 1.2*tcl ns tsdc SDAT to SCLK setup time 0.8*tcl 1.2*tcl ns tsll SLE to last clk setup time 0.8*tcl tcl ns thcd SCLK to SDAT hold time 0.8*tch 1.2*tch ns tlh SLE high period tclk ns Note: Clocking frequency should be approximately 19.2 MHz. 56/77 CD00271682 Rev 3
- 57. PM3533 Pin description 18 Pin description 18.1 PM3533 ball-out Figure 28. PM3533 ball-out diagram Information classified Company restricted - Do not copy (See last page for obligations) Company restricted CD00271682 Rev 3 57/77
- 58. Pin description PM3533 18.2 PM3533 pin description Table 34. PM3533 pin description ESD BGA Pin name Type Ground Supply Function ball Voltage FB_DCDC A1 I GND_DIG DC-DC-converter feedback MUX1 C4 O GND_DIG VXO Multiplexer output FB_BOOST B1 I GND_DIG Boost-converter feedback Information classified Company restricted - Do not copy (See last page for obligations) ANT_T2 B2 O GND_DIG Buffered digital output ANT_T1 C2 O GND_DIG Buffered digital output PA_DAC1 C1 O GND_DIG 1st Current DAC output Company restricted GND_DIG E1 G GND_DIG Ground GND_DIG A2 G GND_DIG Ground GND_DIG B3 G GND_DIG Ground GND_DIG C3 G GND_DIG Ground GND_DIG D3 G GND_DIG Ground GND_DIG D4 G GND_DIG Ground GND_DIG E3 G GND_DIG Ground GND_DIG E2 G GND_DIG Ground GND_DIG F3 G GND_DIG Ground GND_DIG G3 G GND_DIG Ground VXO D2 S GND_DIG 2.5V / 2.15V supply voltage VREF D1 S GND_DIG 1.2V reference voltage SCLK G1 I GND_DIG VXO SPI clock input DATA F1 I GND_DIG VXO SPI data input ENABLE F2 I GND_DIG VXO SPI enable input XRESET E4 I GND_DIG VXO SPI XRESET input SMPS_CTRL G2 I GND_DIG VXO SMPS-converter control voltage FB_SMPS H1 I GND_DIG SMPS-converter feedback VHI H2 O GND_DIG VHI 2.6V / 2.5V regulated output Battery input supply voltage for Vbb_VRX H3 S GND_VIO Vbb_VRX converter regulators and VHI- regulator VIO H4 O GND_VIO VIO 1.8V driver stage supply voltage GND_VIO G4 G GND_VIO Ground for VIO 2nd Current DAC output / Additional PADAC2 / RFCTRL3 F4 S GND_DIG buffered digital output GND_VIO F5 G GND_VIO Ground 58/77 CD00271682 Rev 3
- 59. PM3533 Pin description Table 34. PM3533 pin description (continued) ESD BGA Pin name Type Ground Supply Function ball Voltage CB_SMPS H5 I GND_VIO CB_SMPS SMPS-converter boost-trap input MUX2 G5 O GND_VIO MUX2 High voltage multiplexer output GND_SMPS H6 G SMPS-converter ground GND_SMPS H7 G SMPS-converter ground Information classified Company restricted - Do not copy (See last page for obligations) GND_SMPS H8 G SMPS-converter ground IND_SMPS G6 O SMPS-converter output IND_SMPS G7 O SMPS-converter output IND_SMPS G8 O SMPS-converter output Company restricted INPUT_SMPS F6 I SMPS-converter input INPUT_SMPS F7 I SMPS-converter input INPUT_SMPS F8 I SMPS-converter input OUT_BOOST E5 O Boost-converter output OUT_BOOST E6 O Boost-converter output OUT_BOOST E7 O Boost-converter output OUT_BOOST E8 O Boost-converter output IND_BOOST D5 I Boost-converter input IND_BOOST D6 I Boost-converter input IND_BOOST D7 I Boost-converter input IND_BOOST D8 I Boost-converter input GND_BOOST C5 G Boost-converter ground GND_BOOST C6 G Boost-converter ground GND_BOOST C7 G Boost-converter ground GND_BOOST C8 G Boost-converter ground VBATT B8 S GND_VIO VBATT DC-DC-converter input VBATT A8 S GND_VIO VBATT DC-DC-converter input IND_DCDC A7 O DC-DC-converter output IND_DCDC B7 O DC-DC-converter output GND_DCDC B5 G DC-DC-converter ground GND_DCDC B6 G DC-DC-converter ground CB_BOOST A6 I GND_VIO CB_BOOST Boost-converter boost-trap input GND_VIO A5 G GND_VIO CB_DC-DC B4 I GND_VIO CB_DC-DC DC-DC-converter boost-trap input CD00271682 Rev 3 59/77
- 60. Pin description PM3533 Table 34. PM3533 pin description (continued) ESD BGA Pin name Type Ground Supply Function ball Voltage VIO A4 I GND_VIO VIO 1.8V driver stage supply voltage Vbb_VRX1 A3 S GND_VIO VBB_VRX No connection Information classified Company restricted - Do not copy (See last page for obligations) Company restricted 60/77 CD00271682 Rev 3
- 61. PM3533 PM3533 register description for closed-loop mode 19 PM3533 register description for closed-loop mode PM3533 closed-loop mode control registers are listed in this chapter. SPI device address ID is ‘110’ (in binary format) for address decoding of A7...A5 like in Figure 25. Table 35. Register 0 Register 0 Valid state Name Bit functional description Information classified Company restricted - Do not copy (See last page for obligations) bit 0 Reserved bit 1 Reserved bit 2 Reserved bit 3 Reserved Company restricted bit 4 1 Common BIAS enable Enables common bias OpA bit 5 Reserved bit 6 Reserved bit 7 Reserved bit 8 1 REGU6ma_B_ctrl Enable for boost_ctrl_int.regu6ma bit 9 1 REGU6ma_DC-DC_ctrl Enable for DC-DC_ctrl_int.regu6ma bit 10 1 REGU6ma_s_ctrl Enable for smps_ctrl_int.regu6ma bit 11 1 PADAC_mux_sel 0' for PADAC1; '1' for PADAC2 closed-loop closed-loop mode1='0' VHI=2.6 V, closed- bit 12 0/1 mode_Mode_Sel loop mode2='1' VHI=2.5V Enable for REGU_VHI. bit 13 0 REGU_VHI (This is also an internal supply voltage for the PA_DAC). bit 14 0 REGU_VHI_Vext Enable for REGU_VHI bit 15 Reserved Table 36. Register 1 Register 1 Valid state Name Bit functional description Enable control for the output on MUX1 by bit 0 1 Input_EN '001','010' or '011' selections bit 1 Mux_HV_ctrl C3 (used only in test phase) Thermal shutdown test-enable (‘1’=test bit 2 1 TSD TESTENABLE mode) Thermal protection enable (‘0’ for bit 3 0 TSD THSDENA application mode enable) bit 4 1 Mux_HV_ctrl C3 (used only in test phase) bit 5 1 DIG_load (used only in test phase) CD00271682 Rev 3 61/77
- 62. PM3533 register descriptionfor closed-loop mode PM3533 Table 36. Register 1 (continued) Register 1 Valid state Name Bit functional description Enables functional measurement in test bit 6 1 ENa_TEMP mode TSD_temp_ctrl => 00 150C;10 140C; 01 bit 7 1 TSD_fuse1 160C; 11 170C (used in test mode) TSD_temp_ctrl => 00 150C;10 140C; 01 bit 8 1 TSD_fuse0 160C; 11 170C (used in test mode) bit 9 1 Mux_VREG_ctrl_C2 (used only in test phase) Information classified Company restricted - Do not copy (See last page for obligations) bit 10 1 Mux_VREG_ctrl_C1 (used only in test phase) bit 11 1 Mux_VREG_ctrl_C0 (used only in test phase) bit 12 1 Mux_HV_ctrl C2 (used only in test phase) Company restricted bit 13 1 Mux_HV_ctrl C1 (used only in test phase) bit 14 1 Mux_HV ctrl_C0 (used only in test phase) bit 15 1 OTP_prog_ena Enables OTP signal paths in test phase Table 37. Register 2 Register2 Valid state Name Bit functional description Internal AFForce_bit[15].Frequency bit 0 1 AFForce_bit[15]; RETKU reduction enable; 1.79MHz minus offset to the SMPS value in register 14. Internal AFForce_bit[16].Frequency bit 1 1 AFForce_bit[16]; ITKU increasing enable; 1.35MHz plus offset to the SMPS value in register 14. bit 2 1 AFForce_bit[17] Internal AFForce_bit[17] bit 3 1 AFForce_bit[18] Internal AFForce_bit[18] bit 4 1 AFForce_bit[19] Internal AFForce_bit[19] FuseData[15]; Programmed OTP RETKU bit 5 read only FuseData[15] bit. To read it keep reg15.bit='0'. FuseData[16]; Programmed OTP ITKU bit. bit 6 read only FuseData[16] To read it keep reg15.bit='0'. FuseData[39]. This is used for in serial read-out of OTP memory. Keep FuseData[39]/AFForce_bit[ reg14.bit15='0' to see this serial clocked bit 7 read only data stream output i.e. D39. 17] PADAC coded bit number 0 (LSB), others look at register 15. FuseData[18]. Programmed THSD Fuse0 bit 8 read only FuseData[18] bit. To read it keep reg15.bit='0'. FuseData[19]. Lower OTP mem MSB bit. bit 9 read only FuseData[19] Programmed THSD Fuse1 bit. To read it keep reg15.bit='0'. 62/77 CD00271682 Rev 3
- 63. PM3533 PM3533 register description for closed-loop mode Table 37. Register 2 Register2 Valid state Name Bit functional description ‘0' for enable sr_latch to output tsd_out bit 10 0/1 tsd_mux1_ena state in pwmreg1.bit15; '1' reset sr_latch output node to low state in pwmreg1.bit15. In test mode smps rds_on low/high side bit 11 0/1 rds_smps_low_high_ena sw can be set; '0' for low side; '1' for high side In test mode boost rds_on low/high side Information classified Company restricted - Do not copy (See last page for obligations) bit 12 0/1 rds_boost_low_high_ena sw can be set; '0' for low side; '1' for high side In test mode dcdc rds_on low/high side sw bit 13 0/1 rds_dcdc_low_high_ena can be set; '0' for low side; '1' for high side In test_mode: '1'->'0' sequence to bit 14 0/1 test_otp_reset Company restricted manually set otp_reset_pulse for OTP_cell SMPS: the 5th delay tune for very high bit 15 1 long_delay load impedances; when used set reg3.bit[3...0]='1000' Table 38. Register 3 Register3 Valid state Name Bit functional description Delay tune for low side of driver chain; bit 0 1 SMPS_ast_l beneficial for having minimum dropout voltage (used ext coil res affects) Delay tune for low side of driver chain; bit 1 1 SMPS_ast_l beneficial at larger range of power levels (GSM) Delay tune for low side of driver chain; beneficial at larger range of power level bit 2 1 SMPS_ast_l (GSM) but with larger dropout voltage (used ext coil res affects) Delay tune for low side of driver chain; bit 3 1 SMPS_ast_l beneficial mid-to-low-power range loads (WCDMA) bit 4 1 Dither bandwidth 0 for 2.8MHz; 1 for 5.6MHz bit 5 1 SMPS_Dither_ena SMPS dither enable bit 6 1 SMPS_drw_inout SMPS drw in/out enable SMPS_CTRL_bias/comp/ Enable for smps_ctrl bias. Enable for bit 7 1 sawt smps_ctrl comparator/sawtooth SMPS mode selection 00=PD, 01=bypass, 10=section, 11 normal (bits as bit '9', bit '8' bit 8 1 SMPS mode selection order) Cdoup_SMPS is enabled also with 01=bypass bit 9 1 SMPS mode selection (used with bit 8) CD00271682 Rev 3 63/77
- 64. PM3533 register descriptionfor closed-loop mode PM3533 Table 38. Register 3 Register3 Valid state Name Bit functional description I/O mux control and SMPS opamp enable control (0 = I/O MUX to TSD_testforce, 1 = bit 10 1 SMPS_CTRL_opamp enables SMPS opamp and disables routing to TSD_testforce) bit 11 Reserved bit 12 Reserved bit 13 Reserved Information classified Company restricted - Do not copy (See last page for obligations) bit 14 Reserved bit 15 Reserved Table 39. Register 4 Company restricted Register 4 Valid state Name Bit functional description bit 0 Reserved bit 1 Reserved bit 2 Reserved bit 3 Reserved bit 4 1 Dither bandwidth 0 for 2.8MHz; 1 for 5.4MHz bit 5 1 BOOST_XCLR BOOST dither enable bit 6 1 BOOST_drw_inout BOOST drw in/out enable BOOST_CTRL_bias/comp Enable for boost_ctrl bias. Enable for bit 7 1 /sawt boost_ctrl comparator/sawtooth Boost mode selection 00=PD, 01=bypass, 10=section, 11 normal (bits as bit '9',bit '8' bit 8 1 Boost mode selection order). Cdoup_boost is enabled also with 01=bypass bit 9 1 Boost mode selection (used with bit 8) BOOST_sampled_start_ Enable for BOOST soft start; starts at bit 10 1 control sampled output voltage bit 11 1 BOOST_CTRL_opamp Boost gain opamp enable control Enable for BOOST soft start; starts at BOOST_sampled_start_ sampled output voltage; this bit is left for bit 12 1 control software compatibility (as it was like fast_start before) bit 13 Reserved bit 14 Reserved bit 15 Reserved 64/77 CD00271682 Rev 3
- 65. PM3533 PM3533 register description for closed-loop mode Table 40. Register 5 Register 5 Valid state Name Bit functional description bit 0 Reserved bit 1 Reserved BOOST feedback setting control: enables bit 2 1 BOOST_loopfb1d added parallel resistor to resistor divider bit 3 Reserved bit 4 Reserved Information classified Company restricted - Do not copy (See last page for obligations) Mux Boost control bits bit 5 1 Mux B C0 (used only in test phase) Mux Boost control bits bit 6 1 Mux B C1 (used only in test phase) Company restricted Mux Boost control bits bit 7 1 Mux B C2 (used only in test phase) BOOST feedback setting control: enables bit 8 1 BOOST_loop_fb1a also lim_opamp when _fb1x (x=a or b or c) bits are set BOOST feedback setting control: _fb1a & bit 9 1 BOOST_loop_fb1b _fb1b set output-to-ref gain value to internal decoder BOOST feedback setting control: _fb1c bit 10 1 BOOST_loop_fb1c enables dc path to error opamp. This bit is internally controlled by boost soft_start bit. bit 11 1 BOOST_loop_fb2 BOOST feedback setting control bit 12 1 BOOST_loop_fb2 BOOST feedback setting control Adds 1.5meg resistor into feedback loop bit 13 1 BOOST_1,5meg (used only in test phase) bit 14 1 BOOST_C_shunt Adds shunt capacitor into feedback loop Adds parallel resistor into feedback loop bit 15 1 BOOST_paraR (used only in test phase) Table 41. Register 6 Register 6 Valid state Name Bit functional description Set ‘1’ for Battery Monitor mux output bit 0 1 Mux 1 C0 enable for decoder Set ‘1’ for Battery Monitor mux output bit 1 1 Mux 1 C1 enable for decoder Set ‘1’ for Battery Monitor mux output bit 2 1 Mux 1 C2 enable for decoder bit 3 1 Mux 2 C0 (used only in test phase) bit 4 1 Mux 2 C1 (used only in test phase) bit 5 1 Mux 2 C2 (used only in test phase) CD00271682 Rev 3 65/77
- 66. PM3533 register descriptionfor closed-loop mode PM3533 Table 41. Register 6 (continued) Register 6 Valid state Name Bit functional description bit 6 1 Batman_ENA Enable control for Batman_out ('0' for res_div (set bit8 to '0'); '1' for bit 7 1 Batman_KelvinH res_meas (set bit8 to '0'); test structures) ('0' for res_div (set bit7 to '0'); '1' for hi-Z bit 8 1 Batman_KelvinL state (set bit7 to '1'); test structures) (‘00’ = PD, '10'=DC-DC_clock '01' = bit 9 1 Clock divider enable SMPS_CLOCK, 11 = Boost_clock (bits Information classified Company restricted - Do not copy (See last page for obligations) 9,10 order); used only in test phase) bit 10 1 Clock divider enable (used only in test phase) Enabling digital buffers for ANT_T1, ANT_T2, RFCTRL3 I/Os, Company restricted 1= Digital buffers enabled in application ANT_T1_T2_RFCTRL3_ bit 11 1 mode, ctrl 0= OTP_clock @ANT_T1 and TSD_testsense @ANT_T2 enabled in test mode. Enable switch for RFCTRL3, 1=digital high bit 12 1 RFCTRL3_set state, 0=digital low_state ANTENNA tuning switch control, 1=digital bit 13 1 ANT_T1_antsw_set high state, 0=digital low_state ANTENNA tuning switch control, 1=digital bit 14 1 ANT_T2_antsw_set high state, 0=digital low_state (0 = mux outputs 8- 13, bit 15 1 MUX switch 1 = mux outputs 1-7; used in test phase) Table 42. Register 7 Register 7 Valid state Name Bit functional description SMPS feedback setting control: linked to 0x5C01 setting (and alternatively 0x5C0D with reg2.bit0=’1’ and reg14.bit15=’1’ for bit 0 1 SMPS_loop_fb3 lowest switching freq), additionally 0x5C05 or 0x5C09 (=recommended) with reg2.bit0='1' and reg14.bit15='1' for the semi-lowest switching frequency Enables open loop gain increment option bit 1 1 Open_gain_inc (especially in EER/ET architecture) Additional smps freq reduction (bits of [3...2] combines 4 selections); can be used bit 2 1 Freq_red1 in GSM/WCDMA (in OTP or in free- running OSC modes) Additional smps freq reduction (bits of [3...2] combines 4 selections); can be used bit 3 1 Freq_red2 in GSM/WCDMA (in OTP or in free- running OSC modes) 66/77 CD00271682 Rev 3
- 67. PM3533 PM3533 register description for closed-loop mode Table 42. Register 7 Register 7 Valid state Name Bit functional description DC gain increment: '0'=3.18; '1'=3.40; dgc bit 4 1 dcg_bit equals to smps_out / smps_ctrl bit 5 1 Mux S C0 (Mux SMPS control bits; in test phase) bit 6 1 Mux S C1 (Mux SMPS control bits; in test phase) bit 7 1 Mux S C2 (Mux SMPS control bits; in test phase) SMPS feedback setting control (external bit 8 1 SMPS_loop_fb1 Information classified Company restricted - Do not copy (See last page for obligations) L-C effects on usage) SMPS feedback setting control (external bit 9 1 SMPS_loop_fb1 L-C effects on usage) SMPS feedback setting control (external bit 10 1 SMPS_loop_fb1 L-C effects on usage) Company restricted SMPS feedback setting control (external bit 11 1 SMPS_loop_fb2 L-C effects on usage) SMPS feedback setting control (external bit 12 1 SMPS_loop_fb2 L-C effects on usage) SMPS 1uF cap enable bit. Note: enable bit 13 1 SMPS_1uF also bit numbers 10,11 and 14 for response tuning bit 14 1 SMPS_C_shunt Adds shunt capacitor into feedback loop (Adds parallel resistor into feedback loop; bit 15 1 SMPS_paraR used in test phase) Table 43. Register 8 Register 8 Valid state Name Bit functional description bit 0 Reserved bit 1 Reserved bit 2 Reserved bit 3 Reserved bit 4 1 DC-DC_Dither bandwidth 0' for 1.19MHz; '1' for 2.3MHz bit 5 1 DC-DC_XCLR DC-DC_dither enable bit 6 1 DC-DC_drw_inout DC-DC drw in/out enable Enable for DC-DC_ctrl bias. Enable for bit 7 1 DC-DC_CTRL_bias boost_ctrl comparator/sawtooth. bit 8 1 DRV XPD Driver stage enable DC-DC- Enable for DC-DC soft start; starts at bit 9 1 sampled_start_control sampled output voltage bit 10 Reserved bit 11 1 DC-DC_CTRL_opamp DC-DC control opamp enable CD00271682 Rev 3 67/77
- 68. PM3533 register descriptionfor closed-loop mode PM3533 Table 43. Register 8 (continued) Register 8 Valid state Name Bit functional description Enable for DC-DC soft start; starts at DCDC_ sampled output voltage; this bit is left for bit 12 1 sampled_start_control sw compatibility (because it was like fast_start before) bit 13 1 DC-DCmux (DC-DC mux C0; used in test phase) bit 14 1 DC-DCmux (DC-DC mux C1; used in test phase) bit 15 1 DC-DCmux (DC-DC mux C2; used in test phase) Information classified Company restricted - Do not copy (See last page for obligations) Table 44. Register 9 Register 9 Valid state Name Bit functional description bit 0 1 DC-DC_loop_fb1 DC-DC feedback setting control Company restricted bit 1 1 DC-DC_loop_fb1 DC-DC feedback setting control bit 2 1 DC-DC_loop_fb1 DC-DC feedback setting control bit 3 1 DC-DC_loop_fb2 DC-DC feedback setting control bit 4 1 DC-DC_loop_fb2 DC-DC feedback setting control bit 5 Reserved bit 6 1 DC-DC_C_shunt Adds shunt capacitor into feedback loop (Adds parallel resistor into feedback loop; bit 7 1 DC-DC_paraR used only in test phase) (Enables 2.5V @Vref=1.2V; normally not bit 8 1 OVER2VENA used in the closed-loop configuration of SMPS usage in the rf subsystem) bit 9 1 PA_DAC_XPD Enable for PA_DAC bit 10 1 PA_DAC bit0 PA DAC control bit 11 1 PA_DAC bit1 PA DAC control bit 12 1 PA_DAC bit2 PA DAC control bit 13 1 PA_DAC bit3 PA DAC control bit 14 1 PA_DAC bit4 PA DAC control bit 15 1 PA_DAC bit5 PA DAC control Table 45. Register 12 Register 12 Valid state Name Bit functional description bit 0 read only FuseDR[0] FuseDR[0] (Upper OTP mem LSB bit) bit 1 read only FuseDR[1] FuseDR[1] bit 2 read only FuseDR[2] FuseDR[2] bit 3 read only FuseDR[3] FuseDR[3] bit 4 read only FuseDR[4] FuseDR[4] bit 5 read only FuseDR[5] FuseDR[5] 68/77 CD00271682 Rev 3
- 69. PM3533 PM3533 register description for closed-loop mode Table 45. Register 12 Register 12 Valid state Name Bit functional description bit 6 read only FuseDR[6] FuseDR[6] bit 7 read only FuseDR[7] FuseDR[7] bit 8 read only FuseDR[8] FuseDR[8] bit 9 read only FuseDR[9] FuseDR[9] bit 10 read only FuseDR[10] FuseDR[10] bit 11 read only FuseDR[11] FuseDR[11] Information classified Company restricted - Do not copy (See last page for obligations) bit 12 read only FuseDR[12] FuseDR[12] bit 13 read only FuseDR[13] FuseDR[13] bit 14 read only FuseDR[14] FuseDR[14] Company restricted bit 15 read only FuseDR[15] FuseDR[15] Table 46. Register 13 Register 13 Valid state Name Bit functional description bit 0 read only FuseDR[16] FuseDR[16] bit 1 read only FuseDR[17] FuseDR[17] bit 2 read only FuseDR[18] FuseDR[18] bit 3 read only FuseDR[19] FuseDR[19] (Upper OTP mem MSB bit) bit 4 read only Version_bit0 Coding of versions as follows (bit3...bit0) PM3533: ‘001’ for v1.0 bit 5 read only Version_bit1 PM3533: ‘010’ for v1.0B bit 6 read only Version_bit2 bit 7 read only Version_bit3 bit 8 read only Family_bit0 Coding of RF PM IC family bit 9 read only Family_bit1 PM3533: ‘010’ bit 10 read only Family_bit2 bit 11 read only Man_bit0 Coding of RF PM IC manufacturer bit 12 read only Man_bit1 PM3533: ‘111’ bit 13 read only Man_bit2 bit 14 Reserved bit 15 Reserved Table 47. Register 14 Register 14 Valid state Name Bit functional description These bits adjust switching frequency so bit 0 1 SMPS_clock_freq that bits 00000 gives minimum freq bit 1 1 SMPS_clock_freq and 11111 gives max freq. CD00271682 Rev 3 69/77
- 70. PM3533 register descriptionfor closed-loop mode PM3533 Table 47. Register 14 Register 14 Valid state Name Bit functional description For SMPS: '00000': 6.48 MHz; '01101': bit 2 1 SMPS_clock_freq 9.54 MHz; '01110': 9.77 MHz; bit 3 1 SMPS_clock_freq '11111': 13.59 MHz (typical values) (SMPS: Calibration range in the OTP used bit 4 1 SMPS_clock_freq mode is 7.1 - 10.1 MHz when reg7.bit[3...2]=’00’) These bits adjust switching frequency so Information classified Company restricted - Do not copy (See last page for obligations) bit 5 1 BOOST_clock_freq that bits 00000 gives minimum freq bit 6 1 BOOST_clock_freq and 11111 gives max freq. For Boost: '00000': 4.51 MHz; '01101': bit 7 1 BOOST_clock_freq 7.52 MHz; '01110': 7.74 MHz; Company restricted bit 8 1 BOOST_clock_freq '11111':11.42 MHz (typical values) (Boost: Calibration range in the OTP used bit 9 1 BOOST_clock_freq mode is 6.8 - 8.0 MHz) These bits adjust switching frequency so bit 10 1 DC-DC_clock_freq that bits 0000 gives minimum freq bit 11 1 DC-DC_clock_freq and 1111 gives max freq. For RF-IC DCDC: '00000': 1.62 MHz; bit 12 1 DC-DC_clock_freq '01110'': 2.75 MHz; '01111':2.83 MHz; '11111': 4.09 MHz bit 13 1 DC-DC_clock_freq (typical values) (DCDC: Calibration range in the OTP used bit 14 1 DC-DC_clock_freq mode is 2.45 - 2.84 MHz) 0' sets OTP mode which uses trimmed bit 15 1 DATA_ENA values; '1' is for user set values. Table 48. Register 15 Reg 15 Valid state Name Bit functional description FuseData[0] (Lower OTP mem LSB bit) / bit 0 read only FuseData[0] PADAC coded bit number 1 1 read only FuseData[1] FuseData[1] 2 read only FuseData[2] FuseData[2] 3 read only FuseData[3] FuseData[3] 4 read only FuseData[4] FuseData[4] 5 read only FuseData[5] FuseData[5] / PADAC coded bit number 2 6 read only FuseData[6] FuseData[6] 7 read only FuseData[7] FuseData[7] 8 read only FuseData[8] FuseData[8] 9 read only FuseData[9] FuseData[9] 70/77 CD00271682 Rev 3
- 71. PM3533 PM3533 register description for closed-loop mode Table 48. Register 15 (continued) Reg 15 Valid state Name Bit functional description FuseData[10] / PADAC coded bit number 10 read only FuseData[10] 3 11 read only FuseData[11] FuseData[11] 12 read only FuseData[12] FuseData[12] 13 read only FuseData[13] FuseData[13] 14 read only FuseData[14] FuseData[14] (bits[19...15] in Reg2) Information classified Company restricted - Do not copy (See last page for obligations) 15 read only FUSE_OK Internal Fuse_ok Company restricted CD00271682 Rev 3 71/77
- 72. Example of WCDMAoutput power distribution curve PM3533 20 Example of WCDMA output power distribution curve The most important driver for PM3533 is to increase efficiencies in WCDMA low power levels. Figure 29 presents the DG09 WCDMA output power distribution curve. The power distribution curve shows that in WCDMA system the mobile transmitter is almost all of the time in power level area comprised between 6 dB and -12 dB. Figure 29. DG09 WCDMA output power distribution curve Information classified Company restricted - Do not copy (See last page for obligations) Company restricted 72/77 CD00271682 Rev 3
- 73. PM3533 Package information 21 Package information 21.1 Package mechanical data Table 49. VFBGA 3.4 mm x 3.4 mm x 1.0 mm with 0.4 mm pitch and 0.25 mm ball Ref. Min. Typ. Max. Unit (1) A 1.00 mm A1 0.125 mm Information classified Company restricted - Do not copy (See last page for obligations) A2 0.19 mm A4 0.585 mm b(2) 0.22 0.26 0.30 mm Company restricted D 3.30 3.40 3.50 mm D1 2.80 mm E 3.30 3.40 3.50 mm E1 2.80 mm e 0.40 F mm Z 0.30 mm ddd 0.08 mm eee(3) 0.15 mm fff(4) 0.05 mm 1. VFBGA stands for Very thin profile Fine pitch Ball Grid Array. - Very thin profile:. 0.80 < A ≤ 1.00 mm/Fine pitch:e< 1.00 mm - The total profile height (Dim A) is measured from the seating plane to the top of the component. - The maximum total package height is calculated by the following methodology: 2 2 2 A Max = A1Typ + A2 Typ + ( A1 + A2 + A4 tolerance values ) 2. The typical ball diameter before mounting is 0.25 mm. 3. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. 4. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective zone eee above The axis of each ball must lie simultaneously in both tolerance zones. CD00271682 Rev 3 73/77
- 74. Package information PM3533 Figure 30. VFBGA 3.4 mm x 3.4 mm x 1.0 mm, 0.4 mm pitch, 0.25 mm ball Information classified Company restricted - Do not copy (See last page for obligations) Company restricted See Note 1 1. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. - A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner.The exact shape of each corner is optional. 74/77 CD00271682 Rev 3
- 75. PM3533 Package information 21.2 Package marking The package marking consists of one line. Figure 31. Marking composition PACKAGE FACE : TOP LEGEND Unmarkable Surface Marking Composition Field Information classified Company restricted - Do not copy (See last page for obligations) A A -66669 - MARKING AREA B -66668 - Assy Plant (P) B C D C -66670 - Assy Year (Y) Company restricted D -66667 - Assy Week (WW) E E -66671 - DOT Table 50. Package marking Item Description Format Value A Marking area - Product code 1st line P3533 CD00271682 Rev 3 75/77
- 76. Ordering information PM3533 22 Ordering information Table 51. Ordering information Order code Package Packing VFBGA PM3533BDKT 3.4 mm x 3.4 mm x 1.0 mm, Tape on reel 0.4 mm pitch, 0.25 mm ball Information classified Company restricted - Do not copy (See last page for obligations) 23 Revision history Company restricted Table 52. Document revision history Date Revision Changes 07-May-2010 1 Initial release. Updated – Table 6: SMPS operation parameters – Table 8: SMPS capacitor specification – Table 11: Boost converter operation parameters – Table 14: DC-DC closed-loop mode electrical characteristics – Table 15: Buck DC-DC converter operating parameters – Section 8.1: VHI regulator (first sentence) – Chapter 11: Thermal shutdown (second paragraph) 26-Oct-2010 2 – Chapter 14: Under-voltage-lockout block (third paragraph) – Table 34: PM3533 pin description (update for VHI) – Table 35: Register 0 (bit 5, bit 6, bit 12) – Table 46: Register 13 (bit 5) – Table 51: Ordering information – The Note 1 in Chapter 21: Package information Added – Section 21.2: Package marking Updated – The cover page: document title, description, applications and feature list – Chapter 1: Overview – Chapter 2: General specifications – Table 6: SMPS operation parameters 16-Dec-2010 3 – Section 8.1: VHI regulator – Table 10: Boost full power mode general electrical characteristics – Table 11: Boost converter operation parameters – Table 25: Thermal shutdown parameter table – Table 34: PM3533 pin description – Table 40: Register 5, Table 42: Register 7 76/77 CD00271682 Rev 3
- 77. PM3533 CONFIDENTIALITY OBLIGATIONS: This document contains sensitive information. Its distribution is subject to the signature of an Non-Disclosure Agreement (NDA). It is classified “COMPANY RESTRICTED. At all times you should comply with the following security rules (Refer to NDA for detailed obligations): Do not copy or reproduce all or part of this document Keep this document locked away Further copies can be provided on a “need to know basis”, please contact your local ST-ERICSSON sales office. Information classified Company restricted - Do not copy (See last page for obligations) Company restricted Please Read Carefully: The contents of this document are subject to change without prior notice. ST-Ericsson makes no representation or warranty of any nature whatsoever (neither expressed nor implied) with respect to the matters addressed in this document, including but not limited to warranties of merchantability or fitness for a particular purpose, interpretability or interoperability or, against infringement of third party intellectual property rights, and in no event shall ST-Ericsson be liable to any party for any direct, indirect, incidental and or consequential damages and or loss whatsoever (including but not limited to monetary losses or loss of data), that might arise from the use of this document or the information in it. ST-Ericsson and the ST-Ericsson logo are trademarks of the ST-Ericsson group of companies or used under a license from STMicroelectronics NV or Telefonaktiebolaget LM Ericsson. All other names are the property of their respective owners. © ST-Ericsson, 2010 - All rights reserved Contact information at www.stericsson.com under Contacts www.stericsson.com CD00271682 Rev 3 77/77