This document appears to be an assignment submission for a course on VHDL. It includes the student's name, ID number, professor, and engineer. It lists the components of the assignment such as the block diagram, source code, test bench, and simulation. It then analyzes the results, explaining that if the input is 0001 then the output represents half the input frequency, with each output pulse representing two input pulses. It lists references used including a book, lab, software, and the internet.

1. بسم الله الرحمن الرحيم
Assignment NO.8
Name : Bajes Osama Abu Ammona
ID :120112256
Prof : Ibrahim S. I. Abuhaiba
Eng : Ahmed Eldaly

2. Block Diagrame :
Source Code :

3. Test Bensh :
Simulation :

4. Result Analysis:
if c=0001 then m =21 =2 so f_out =f_in/2 so for every pulse in the output represent two pulse in the input as shown .
References :
Book : Wiley.IEEE.Press.RTL.Hardware.Design.Using.VHDL.Apr.2006.
Lab : VHDL Lab.
Software : Aldec Active-HDL >> HELP >> interactive VHDL Tutorial .
Internet : internet .