Resume

1. Akash Bahetra
Hedgewar Colony,
Rewa 486001
Madhya Pradesh
Final Year B.E.[ECE] | Rewa Engineering College, Rewa
+91 8770517457 | akashbahetra05@gmail.com linkedin.com/in/akash-bahetra-606452152
Education
Bachelor of Engineering – ECE 2016 – Present Rewa Engineering College, Rewa 6.89/10.0
12th
– Senior Secondary (CBSE) 2014 – 2015 Bal Bharti School, Rewa 78.8%
10th
– High School (CBSE) 2012 - 2013 Bal Bharti School, Rewa 8.0/10.0
Publications
Projects
Skills & Interests
Programming Languages : C++ | VHDL | Verilog
Design Tools : SPECTRE ADEL/XL | Cadence Virtuoso Layout XL | Assura Physical Verification
CAD Tools : MATLAB | Xilinx Vivado
FPGA : Spartan 3E Series
Non-Technical Skills : Adobe Photoshop | Presentation Skill | MS Office | Team Work
Dec ‘19 Ultra-low power high gain high speed OTA
IEEE Conference on Information & Communication technologies, IIIT Allahabad
• Replaced current mirror topology with push-pull inverter circuit to decrease the power consumption &
replaced Compensating Capacitor with a small MOSFET and used its drain to source capacitance for
frequency compensation.
• Simulated and analyzed the design in Cadence standard 180nm technology using SPECTRE ADEL/XL
and Layout was generated using Cadence Virtuoso Layout XL tool. DRC, LVS and RC extraction of the
physical layout has also performed using Assura physical verification tool.
• Achieved ultra-low power usage without affecting the gain or speed of the OTA.
Dec ’19 - Present 16-bit Harvard Structure RISC based Processor with modified ALU
Mrs. Samiksha Singh Chauhan | Rewa Engineering College, Rewa |
• Implementing a 16-bit Harvard based RISC processor and using a modified ALU.
• Verilog code will be compiled and layout will be generated using Cadence Encounter tool with its SDC
file.
June – July ‘19 Photolithography modeling with MATLAB
Mr. Rupesh K. Chaudhary | SSPL, DRDO
• Simulated the PLG constraints so as to compare it to experimental values
• Graphs were plotted for different properties like resist thickness & aerial images using MATLAB
• Comparison of experimental values & ideal value was done to check the accuracy

2. Internship & Courses
October ‘18 ASIC design flow using Cadence design tools
Dr. Kishore P. Sarawadekar | IIT BHU
• Chip Designing using Cadence design tools was the main objective
• Used the Encounter and Innovus tools to simulate & Floorplan respectively in gpdk 90nm technology
• Exported gds format file for fabrication was achieved after locating and correcting all the errors
June – July ‘19 MMIC – Photolithography
Dr. D.S. Raval | SSPL, DRDO
• Process of photolithography was carried out under the supervision of senior scientists
• Cleaning, Baking, Coating & Exposure was done under specific atmospheric conditions
• Observation was done under microscope of the exposed wafer to get the correct pattern
June – July ‘18 VLSI design
Mr. Rakesh Gumasta | CRISP, Bhopal
• Learned VHDL coding & FPGA implementation on the Spartan 3E kits
• Various circuits such as counters, MuX etc. were designed using Xilinx ISE Design coded with
VHDL and the implemented to Spartan 3E based FPGAs.
• Implementation and verification of many circuits including 7 segments were carried out successfully
Position Of Responsibility
• Head of Catalyst E-cell | The Entrepreneurship cell, Rewa Engineering College. | 2018 – 2019
• Presented a paper at IEEE CICT 2019, IIIT Allahabad | Dec 2019
• Student Member | MHRD – Institution Innovation Council | 2018 – 2019
• Student Coordinator | Training & Placement Cell, Rewa Engineering College. | 2018 - Present
• Represented REC as a Team Leader at Finals of NEC (National Entrepreneurship Challenge), IIT Bombay. | 2019
• Participant - Swachh Bharat Internship. | 2018
Personal Details
Father’s Name : Mr. Kanhaiya Lal Bahetra Marital Status : Single
Mother’s Name : Smt. Rajni Bahetra Nationality : Indian
Birthday : 13 September, 1997 Gender : Male
Declaration
I, Akash Bahetra, hereby declare that the information contained herein is true and correct to the best of my knowledge and itself.
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Akash Bahetra Rewa, Madhya Pradesh