This document describes a VHDL project to design a calculator ALU. The objectives are to create a calculator that performs addition, subtraction, doubling, and boolean logic functions. It will use push buttons to select the function and DIP switches to set the input data. A controller FSM will control the data flow and outputs will be displayed on 7-segment displays. The design includes subsystems for a frequency divider, debounce process, controller, multiplexer, registers, ALU, output register, debug outputs, and display control. Timing diagrams and test results using a DE1 board are analyzed. The conclusions discuss if the design goals were met and lessons learned.

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Milwaukee School of Engineering
Department of Electrical Engineering
EE3900B‐112 ‐ Design of Logic Systems
Final Design Project ‐ VHDL Calculator ALU
Submitted By: Alexander H. Kremnitzer
Submitted To: Dr. Joshua Carl
Submitted On: 11‐12‐2015

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Table of Contents
Table of Contents ………….……………………………………………………………………………………….…………..…….2
Introduction
Purpose.……………..…………………………….…………..………….……………………………...………....……….3
Objectives………………………………………………………...………………………………….……......….….……..4
Developments
Problem Investigation and Formulation …………………………………………....…..….………..………..6
Functional Block Diagram of system.……………….…………………………………....…..….…….………..7
Input and Output Pin Assignments……….……….……………………………………....…..….…….………..8
Subsystem Functions
Frequency Divider Process...………………………….………...…….……………………………….…….……..12
Debounce Process / Shift Register..……………….………...…..……………………………………….……..13
Controller Process...…………………………………………….…...……….………………………………….……..14
Multiplexer Process...…………………………………….………...……….……………………………..….………17
Input Register Process...…………………………………………...………….…………………………..….………18
Arithmetic Logic Unit………………………………….……………………….………..……...……….….….………20
Output Register Process...………………………………………...………….…………………………..….………23
Debug Output...………………………………..……………………...………….…………………………..….………24
Display Control Process...…………………………………………...………….………………………..…….…….25
7‐Segment Display…………………………………………………………………………………………………………27
Results and Analysis
Simulation Timing Diagrams……….………………….…………………………………...……………….……..29
Test Data Using DE1 Board………………………………………………………………………………..…………32
Analysis of Timing Diagrams, Test Data and DE1 Results………………………………….………….32
Conclusions
Brief reinstatement of objective / purpose…………………………………………..……………..….……33
Were Design Goals Met………………………………………………………………………………………..….…..33
What was learnt from project…………………………………………………………………….……..………….34
Opportunities or ideas to improve on project next time……………………………….……..……….34
Appendices
Assignment Sheet…………………………………………………………………………………….…….…..…………35
Copy of VHDL Code………………………………………………………………………………………….…………….39

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Introduction
Purpose:
The purpose of this project was to design a computing machine that will perform Addition,
Subtraction, Data Doubling, Boolean Logic AND, Boolean Logic OR and Boolean Logic XOR.
The approach is to write a VHDL code for an Arithmetic Logic Unit (ALU) that has the data flow
controlled by enable signals produced from a separate process which is a Finite State Machine
(FSM) Moore model controller. The user is able to select what function the ALU will perform
using push button switches and set the data externally using DIP switches. After these
parameters are set, the user then presses a pushbutton start button that uses shift registers to
perform debounce operations and the denounced signal will starts the Controller and transition
between states on a rising edge clock transition until the output value is done and hold that
value on the display until rested by pressing the start button and the controller state transitions
restart. Data flow is provided by an input multiplexer, input registers and an output register all
controlled by a rising clock edge and the FSM enable control signals. The ALU runs concurrently
independent of the clock signals and will perform the set function and output the final result.
The final results is then output from the C register and displayed by a concurrent processes controlling
the data and performing display control intelligence such as carry bits and overflow to display on both
Light Emitting Diodes (LED) and using a Case statement for the decimal data to display on the seven‐
segment displays. The device used in this lab is the DE1 FPGA development board that uses an Altera
EP2C20F84 Field programmable gate Array (FPGA).

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Introduction Continued:
Objectives:
The objectives of this project was to:
• Create a “calculator” using VHDL that performs set mathematical and Boolean logic
operations.
• Control data flow by a separate controller section that is a model of a Moore Finite
state Machine (FSM) that creates enable signals to control data flow and is started by a
denounced push button.
• Use a frequency divider to provide a clock signal for the FSM, switch debounce (shift
register), multiplexer and all registers.
• Perform mathematical functions and Boolean operations in a concurrent ALU process.
• Use a clock transition and a signal from the controller to output the result from the ALU
through the data output register.
• Display the decimal data on a 7 segment display and also provide the binary result from
the ALU. If addition and doubling also display a “1” if there was a carry flag and if
subtraction display a negative dash if there was an overflow condition.
• In subtraction if the result causes overflow then two’s complement is to be performed
on the ALU data so the displayed decimal data is correct on the 7‐segment display.
• To allow the user to externally set the function that the ALU will perform using three
push buttons and start the controller.
• The available mathematical functions of the ALU are to be:
Set = 000; Addition = DataA + DataB.
Set = 001; Subtraction = DataA – DataB.
Set = 010; Doubling = DataA + DataA.
Set = 011; Boolean Logic AND = DataA AND DataA
Set = 011; Boolean Logic OR = DataA OR DataA
Set = 100; Boolean Logic XOR = DataA XOR DataA
Set = Any other state is invalid and the data display is blanked.

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Introduction Continued:
Objectives Continued:
• To allow the user to manually set using DIP switches the data value of the two 4‐bit
inputs that is to be operated on by the ALU.
• To allow the user to start the controller code by a single push button that used shift
registers to debounce mechanical glitches caused by contact bounce.
• To allow the concated 5‐bit output result from the ALU to be displayed through on
LEDs. The concated MSB will then be used for carry and overflow detection.
• To create a flag bit if performing Addition or Doubling a carry bit occurs and in
subtraction a flag bit if an overflow occurs.
• To allow the 5‐bits output data result from the ALU to be displayed on two seven‐
segment displays. If there is an overflow condition in subtraction to post process the
ALU data using 2’s complement so the decimal display will be correct. The binary coded
data will stay in overflow format.
• To post process the data so a carry flag will display a 1 on a seven segment display and
a negative will cause a dash.
• To let the user know the calculation is complete by lighting a done LED and the data
will stay displayed on the seven segment display until the start button is pressed and
will then perform a new mathematical function.

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Development
Problem Investigation / Formulation:
The functioning of the unit was created by first identifying the four areas to get a basic
overview of how the unit is to perform:
1) Understand the problem – Review the assignment handout and create a basic overview of what I
determined is necessary to do with the code so it will perform as described.
2) Create a state diagram – I determined what states were needed and created a state diagram of the
controller section that provided control signals for enabling the rest of the functionality to perform as
needed to derive the proper output.
3) Create a State Table – From the State Diagram I then created a state table that represented the
functionality of the State Diagram but in table form.
4) Write the VHDL code. I was originally going to do Structural Port Map but for me I felt it was better
to have all processes in the same code.
I found it easier to be able to visualize the functionality and make corrections by not using Port
Map structure and instantiating components. While the main code would have been smaller since
some components such as registers would not have to be repeated, I found it easier to follow by
having it all on one sheet and while some of the individual processes acted concurrently I wrote the
code with the process in order of how I envisioned the data to flow although I knew they were not
sequential operations (excluding processes that were enabled by the controller section). I found this
easier as I later had to add a process to add “intelligence” for the display to correct the decimal value
when subtracting and an overflow occurred. It took some tweaking and when an error occurred
during compiling I could click on the error and it would take me right to the section of code and with it
all in one file I could then make corrections to the code and then if the changes effected some other
section I could then scroll up to that area and make the applicable adjustments to it. Also at times I
changed signal names and would use the find/replace to automatically process the change across the
entire document, versus opening a file separate file I had instantiated if I used port map structure.

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Development Continued:
Functional/Architectural Diagram of the complete system:
Figure 1 – System Diagram

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Development Continued:
Input Pin Assignments:
Table 1 – Input Pin Assignments
Note: Clock_50 is from the on‐board oscillator from DE1 Board and assigned to Pin L1.
Figure 2 – Pin Assignments on DE1 Board

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Development Continued:
Output Pin Assignments:
Pin Assignments ‐ Outputs
Function Output Signal Display Pin
Negative on Hex(3) Display
Neg(0) Hex(3) Segment 0 (a) F4
Neg(1) Hex(3) Segment 1 (b) D5
Neg(2) Hex(3) Segment 2 ( c) D6
Neg(3) Hex(3) Segment 3 (d) J4
Neg(4) Hex(3) Segment 4 (e) L8
Neg(5) Hex(3) Segment 5 (f) F3
Neg(6) Hex(3) Segment 6 (g) D4
Carry bit '1' on Hex(2) Display
carry_bit(0) Hex(2) Segment 0 (a) G5
carry_bit(1) Hex(2) Segment 1 (b) G6
carry_bit(2) Hex(2) Segment 2 (c) C2
carry_bit(3) Hex(2) Segment 3 (d) C1
carry_bit(4) Hex(2) Segment 4 (e) E3
carry_bit(5) Hex(2) Segment 5 (f) E4
carry_bit(6) Hex(2) Segment 6 (g) D3
BCD Data converted to Display on the
Hex(1) and Hex(0) Display
seven_seg() Hex(1) Segment 0 (a) E1
seven_seg(12) Hex(1) Segment 1 (b) H6
seven_seg(11) Hex(1) Segment 2 (c) H5
seven_seg(10) Hex(1) Segment 3 (d) H4
seven_seg(9) Hex(1) Segment 4 (e) G3
seven_seg(8) Hex(1) Segment 5 (f) D2
seven_seg(7) Hex(1) Segment 6 (g) D1
seven_seg(6) Hex(0) Segment 0 (a) J2
seven_seg(5) Hex(0) Segment 1 (b) J1
seven_seg(4) Hex(0) Segment 2 (c) H2
seven_seg(3) Hex(0) Segment 3 (d) H1
seven_seg(2) Hex(0) Segment 4 (e) F2
seven_seg(1) Hex(0) Segment 5 (f) F1
seven_seg(0) Hex(0) Segment 6 (g) E2
State assigned for debug LEDs display
state_assign(2) LEDR(2) U19
state_assign(1) LEDR(1) R19
state_assign(0) LEDR(0) R20
Control signal for debug LEDs display
control_output(3) LEDR(9) R17
control_output(2) LEDR(8) R18
control_output(1) LEDR(7) U18
control_output(0) LEDR(6) Y18
Data in BCD for LED debug
Data_Out(4) LEDG(7) Y21
Data_Out(3) LEDG(6) Y22
Data_Out(2) LEDG(5) W21
Data_Out(1) LEDG(4) W22
Data_Out(0) LEDG(3) V21
Overflow flag over LEDG(1) U21
Done LED done LEDG(0) U22
Table 2 – Output Pin Assignments

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Development Continued:
Output Pin Assignments Continued:
Figure 3 – Red LED Assignments on DE1 Board
Figure 4 – Green LED Assignments on DE1 Board

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Development Continued:
Output Pin Assignments Continued:
Figure 5 – 7‐Segment Display Assignments on DE1 Board
Figure 6 ‐ Input and Output Signals in VHDL code
The input and output signals were assigned in the Entity / Port section of the
VHDL Code. Table 1 defines the input signal names and physical pin assignments used
on the DE1 board. Figure 2 shows the physical switch assignment the inputs are
assigned to. Table 2 defines the output signal names and physical pin assignments used
on the DE1 board. Figure 3 thru 5 shows the physical LEDs or Segments of the 7‐
segment display the outputs are assigned to.

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Development Continued:
Frequency Divider Process:
Figure 7 ‐ VHDL Code for the frequency divider process
The frequency divider is in two sections and outputs two separate clock pulses.
Pin L1 provides an initial 50MHz clock pulse from the DE1 board. In the first frequency
divider section every time a rising edge happens (CLOCK_50’Event and CLOCK_50=’1’) a
count happens and the count is then compared against the CONSTANT max = 5000. If
(count < max) it continues to loops using an “IF” statement and each time increment by
‘1’ until the CONSTANT Max value is reached. This is the whole period. The value is then
50MHz divided by 5 KHz, or 10 KHz. A second Constant (half <= max/2) will for the first
half of the count outputs a ‘0’ and for the second half period will assign a value of ‘1’.
This creates a 10 kHz square wave clock signal called ckl_tenkilo. The process is
repeated a second time with new CONSTANTS max1 and half1 which are set to creates
a second 1 kHz square wave clock signal. All clocked processes use the rising edge of
the clock signal.

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Development Continued:
Switch Debounce / Shift Register Process:
Figure 7 ‐ VHDL Code for the switch debounce process
Figure 8 ‐ Shift Register Diagram
To debounce the switch a 4 bit shift register is used. The register is four D flip flops that transition on a
rising clock edge. Initially the outputs are reset as “0000”and the when the switch is pressed the value
is loaded into the first D flip‐flop. At each clock transition the value is shifted to the next flip flop and
the switch value is put into the place of the prior flip flop input. After four transitions it does a
comparison to see if all the flip flops are ‘0’ bits, equal to ‘0000” indicating that there is no switch
bounce occurring and provide a signal for the controller to start transitioning states

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Development Continued:
Controller Module Process
Figure 9 ‐ VHDL Code for the controller process
The Controller Module is a Finite State Machine (FSM) based on a Moore Model. The
controller section in the VHDL Code will loop in the init state until it sees a signal that the pushbutton
has been pressed. The pushbutton is run through a debounce code (shift register and then compared)
to eliminate glitches from causing the Controller Module to falsely start. After the start pushbutton is
pushed, the debounced signal will start the Controller Module will cycle through each state transition
on a rising clock edge of the 1 KHz clock signal from the frequency divider process. When the
controller is finished it will loop in the init state until it sees another signal from the debounced switch
to start the transitions. The data input, output and the ALU sections are processes independent of the
controller although some require an enable signal. After the init when the start pushbutton is pressed
the state the controller automatically advances to enable the multiplex and first Load DataA then
DataB. There is a ALU state added that I put in symbolically as the ALU is running concurrently
independent of a clock or control signal, so once data is loaded it will perform its operation based on
what data is output from the input registers. The controller then will enable the output register to
pass the result for later display processing.

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Development Continued:
Controller Module Process Continued:
When done it lights the done LED telling the user it is complete. The done LED and 7‐segment display
result remains on until the start button is pressed again and then the controller cycles through
another time and the process repeats
Figure 10– State diagram of the Controller Model

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Development Continued:
Controller Module Process Continued:
Figure 11– ASM Algorithmethic State Machine of the Controller Model
Table 3 – State Table of the Controller Model

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Development Continued:
Input Multiplexer Process:
Figure 12 ‐ VHDL Code for the input multiplexer process
Figure 13 ‐ Physical multiplexer process
Table 4 ‐ Multiplexer process output table
The multiplexer (MUX) is a two input MUX controlled by a single bit and runs independent of
the clock. The two inputs are DataA and DataB. If the control_out(0) bit is = ‘0’ then the output of the
multiplexer is DataA and if the control_out(0) bit is = ‘1’ then the output of the multiplexer is DataB.
Its use tis to control the flow of data that is put on the bus. Otherwise then both input data could
occur at the same time on the data bus causing a corruption of data.

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Development Continued:
Input Data Registers Process:
Figure 14 ‐ VHDL Code for the input data register processes
Figure 15 ‐ Physical Input Data Register process

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Development Continued:
Input Data Registers Process Continued:
Table 5 ‐ Input Data registers process output table
The input data registers control the flow of data and are under both control of the clock and an enable
signal. When a rising edge clock signal occurs the data into the register will pass to the output if an
enable signal ‘1’ is present. There is two 4 bit input data registers. One for DataA and a second for
DataB. While the mux selects which data is on the Buss, the registers control if that data passes to the
ALU. So for DataA to pass that register must be enabled by control_out(1) bit = ‘1’ and see a rising
clock edge and for DataB to pass that register must be enabled by control_out(2) bit = ‘1’ and see a
rising clock edge. If there is no control bit enabling the registers they do not transition.

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Development Continued:
Arithmetic Logic Unit:
Figure 16 ‐ VHDL Code for the ALU ‐ Arithmetic Logic Unit

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Development Continued:
Arithmetic Logic Unit Continued:
ALU
PROCESS
SET
=000
SET
=001
SET
=010
SET
=011
SET
=100
SET
=101
SET
=OTHERS
ADDITION
SUBTRACTION
DOUBLING
AND
OR
XOR
INVALID
Alu_out <= (‘0’ & data_outA) + (‘0’ & data_outB)
over <= ‘0’, Neg_bit <= ‘0’,
Carry_bit <= ((data_outA(3) AND (data_outB(3))
Alu_out <= (‘0’ & data_outA) + (‘0’ & data_outA)
over <= ‘0’, Neg_bit <= ‘0’,
Carry_bit <= ((data_outA(3) AND (data_outA(3))
Alu_out <= (‘0’ & data_outA) AND (‘0’ & data_outA)
over <= ‘0’, Neg_bit <= ‘0’, Carry_bit <= ‘0’
Alu_out <= (‘0’ & data_outA) OR (‘0’ & data_outA)
over <= ‘0’, Neg_bit <= ‘0’, Carry_bit <= ‘0’
Alu_out <= (‘0’ & data_outA) XOR (‘0’ & data_outA)
over <= ‘0’, Neg_bit <= ‘0’, Carry_bit <= ‘0’
Alu_out <= (others => ‘1’,
over <= ‘0’, Neg_bit <= ‘0’, Carry_bit <= ‘0’
data_outB
>
data_outA
Alu_out <= (‘0’ & data_outA) ‐ (‘0’ & data_outB)
over <= ‘1’, Neg_bit <= ‘1’, Carry_bit <= ‘0’
Alu_out <= (‘0’ & data_outA) ‐ (‘0’ & data_outB)
over <= ‘0’, Neg_bit <= ‘0’, Carry_bit <= ‘0’
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
Y
N
Figure 16 –ALU – Arithmetic Logic Unit
Table 6 –Table of ALU Set function

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Development Continued:
Arithmetic Logic Unit Continued:
Figure 17 – Functional diagram of the Arithmetic Logic Unit
The Arithmetic Logic Unit (ALU) will perform either a mathematical or a Boolean logic operation
on the input data based on the function it is set to perform by the push button switch positions.
The possible operations of the ALU are: 000 = Addition, 001 = Subtraction, 010 = Logic AND, 011 =
Logic OR, 100 = Logic XOR. The 4‐bit data is sent to the AUL input terminals when the input registers
are enabled by the controller. A ‘0’ bit is concated as the MSB to create a 5 bit input data value in the
ALU for overflow and carry. The Arithmetic Logic Unit is a combinational circuit and once the data it
present at the input pins the output result will show. Then the controller advances state and enables
the 5‐bit result of the ALU to be displayed on the 5 result LEDs.

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Development Continued:
Output Register C:
Figure 18 ‐ VHDL Code for the output data Register C processes
Figure 19 ‐ Physical Output Data Register C process
Table 7 ‐ Output Data Registers C process output table

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Development Continued:
Output Register C Continued:
The output data register control the flow of data from the ALU and is under both control of the clock
and an enable signal. When a rising edge clock signal occurs the data from the ALU into the output
register will pass through the register if an enable signal is present. There is one 5 bit input data to the
registers as a ‘0’ was concated to the data coming in to allow carry and overflow functions. If the data
is subtraction and an overflow occurs then the value is the 2’s complement and it processed later to
correct for the decimal display.
Debug Output:
Figure 20 ‐ VHDL Code for the debug processes
The Debug Process allow the internal signals assigned at each controller state to be displayed
externally on LEDs to allow a visual indication of what state the controller is in. This was done as I had
for the development process clocked the state transitions at 1Hz to aid in code development and
debug. Then I was able to verify the data flow at each state was correct. Also the internal
control_output (enable signal from the control was also assigned to an external output of 4 LEDS to
visually show the control signal for the debug process. In the final code this was changed to 1 KHz so
the entire process to transition through all the states would not take so long and it then appears that
it is running instantaneously.

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Development Continued:
Display Control:
Figure 21 ‐ VHDL Code for the display control processes
Figure 22 ‐ Display Control Processes

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Development Continued:
Display Control Continued:
The Display Control Process takes the flag signals from the ALU and output them
to external displays. It is based on nested IF statements that are processed if the
control output bit 3 = ‘1’ indicating the output register is enabled and will synchronize
their process with the displayed data. When a carry bit is indicated a digit ‘1’ is
displayed on the Hex2 seven‐segment display. When a negative bit is indicated a
negative dash is displayed on the Hex3 seven‐segment display. And when an overflow
occurs, a LED is lit to indicate the overflow condition. Otherwise each of the displays
are not light.
Figure 23 ‐ VHDL Code for the display control processes in overflow
A second process was created to process of the data out of the ALU for use in the
case statement that controls the decimal display on the seven‐segment display. When
negative and an overflow occurs the result from the ALU is in 2’s complement from and
this process then takes that value and does a 2’s complement of the result so the
correct decimal will display.

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Development Continued:
Seven Segment Display:
Figure 24 ‐ VHDL Code for the Seven‐Segment Display

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Development Continued:
Seven‐Segment Display Continued:
The data result from the ALU after being processed for overflow condition uses a Case
statement process to display the value on the seven‐segment display. The Data is in a 5 bit vector and
as there is a possibility of a maximum input value for DataA and DataB to be 15 decimal the case
statement must be able to cover all cases from 0 thru 30 and also blank the display if an invalid case
occurs as shown in Figure 24. I used a 14 bit vector to control HEX0 and Hex1 to display a “00” decimal
thru “30” decimal representing the binary value. The seven segment displays use a different logic
where a ‘0’ bit will turn on the segment and a ‘1’ bit will turn off the segment which is the opposite
logic of how the LEDs function on the DE1 board. When a case statement that is not “00000” thru
“11110” occurs I used the declaration WHEN OTHERS => seven_seg <= “11111111111111” to turn off
the display.

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Results and Analysis
Simulation Timing Diagrams:
Figure 25 – Addition DataA + DataB; SET = 000

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Figure 26 – Subtraction DataA ‐ DataB; SET = 001
Results and Analysis Continued:
Simulation Timing Diagrams Continued:
Figure 27– Doubling DataA; SET = 010

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Figure 28 – Boolean DataA AND DataB; SET = 011
Results and Analysis Continued:
Simulation Timing Diagrams Continued:
Figure 29 – Boolean DataA OR DataB; SET = 100
Figure 30 – Boolean DataA XOR DataB; SET = 101

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Results and Analysis Continued:
Test Data Using DE1 Board
Using the setting shown in the simulations of Figures 25 thru 30, the code was tested. First the
input data was set using the slide switches as shown in Table 6 to declare the desired 4‐bit input data
values for DataA and DataB. Then the pushbutton switches corresponded to the SET switches on the
DE1 evaluation board as also shown in Figure 2 were pressed to test each individual operation. The
pushbuttons default to a high input through internal circuitry on the DE1 board so when pressed they
were set to a ‘0’ and defaulted to a ‘1’ when not pressed.
Finally the start pushbutton of Figure 2 was pressed to start the controller to cycle through the FSM
States and the output value was displayed on the 5 output LEDs per Figure 4 and verified they match
the simulation results. In addition or doubling a carry state was verified and if a carry occurred the
HEX2 display would display a decimal digit of 1. Also when performing subtraction, if an overflow
occurred it indicated a negative so the HEX3 display would indicate by producing a dash, see Figure 5.
A process control was necessary in the code to correct the ALU output when in overflow as it
produced two’s complement math and would not produce the desired decimal digits output in Figure
24.
Analysis of Timing Diagrams, Test Data and DE1 Results
The testing confirmed the operation of the VHDL controller and ALU model. The user can manually set
the input data and manually select which function the ALU is to perform and have it automatically
cycle the process sequentially and hold the final result until the start pushbutton is pressed. It is not
possible to properly develop and observe the system operations when the circuit it running at a fast
clock speed so I wrote in the code a frequency divider to slow the system operations to first run at an
observable speed of 1Hz clock pulses during the development and debug process and later changed
the frequency divider constants so the state transitions occurred at a 1kHz clock rate making the
result appear to be instantaneous. For simulation the constants assigned to max and max1 were
decreased and the clock pulse input increased in simulation to properly display a simulation waveform
showing all the state transitions and outputs.

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Conclusions
Brief Reinstatement of objective / purpose
The processing of calculating data with an ALU can be controlled automatically by the outputs
of an independent controller. An employer could have independent modules of the design being
worked on separate groups, perhaps in different countries and interface them together remotely (i.e.
Port Map Structure). Several things I learned by this design is to first learn the individual sections of
the code and then in the end make each section an individual separate process. Some are controlled
by a separate FSM controller that outputs a control signals to enable process and therefore control
the flow of data through the system but others run concurrently. I also learned as a system becomes
more complex it can be valuable to incorporate intermediate debugging outputs to see at what
location the system is actual in, by monitoring theses internal states it can be determined if the
controller is actually sequencing in the correct order and at the correct time and the clock speed can
be slowed using a frequency divider to aid in debugging.
Were Design Goals Met
Yes, the code was able to replicate the functionality of the system diagram and data flow. A separate
controller was used for independent control of each processes that were used to control data flow.
The decimal value displayed was corrected and indicates both carry and negative outputs. Also
overflow in subtractions was corrected in a separate process so the correct decimal data was
displayed on the seven‐segment displays.

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Conclusions Continued
What was learnt from project?
There is many ways to implement the processes in the code. I could have in the ALU done control such
as correction of the 2’s complement data and just output flags from the ALU for carry, Negative and
Overflow. When subtracting and in an overflow condition I decided to do the display control as a
separate process. The ability to call out a library that allowed mathematical operations to occur
greatly reduced the code. In theory the separate processes, such as the multiplexer, registers and ALU
could have been a part of the library. Also they could have been done separately done as instantiated
components and the code set up using port maps. I initially was going to use this approach but later
found it more helpful to have all code in one file. On a larger code this is probably not the best
method where repeated processes occur but I found it easier to debug and make small changes in the
code while debugging if all in one VHDL code file.
Opportunities or ideas to improve on project next time
As mentioned if there are repeated processes in a large code, using the structure of port maps and
instantiating the components is probably the preferred method. Also the ALU could have been done
as a complete unit with outputs flags indicating carry, overflow and perform 2’s complement on the
output result if doing subtraction and an overflow occurs. However it was not much more work to do
this in a separate process and in a way I preferred that as I could check the ALU would output the true
value and 2’s complement in overflow and later process the data to control the decimal display
independently.

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Appendices
Assignment Sheet

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