PhoenixIndia Technologies, Karur, 7373885830 7373885630

1. PhoenixIndia Technologies
FOR MORE DETAILS CONTACT: 7373885830 | 7373885630.
MAIL – PHOENIXINDIATECHNOLOGIES@GMAIL.COM
DESIGN FLOW FOR FLIP-FLOP GROUPING IN DATA-DRIVEN
CLOCK GATING
Clock gating is a predominant technique used for power saving. It is observed that the
commonly used synthesis based gating still leaves a large amount of redundant clock pulses. Data-
driven gating aims to disable these. To reduce the hardware overhead involved, flip-flops (FFs)
are grouped so that they share a common clock enabling signal. The question of what is the group
size maximizing the power savings is answered in a previous paper. Here we answer the question
of which FFs should be placed in a group to maximize the power reduction. We propose a practical
solution based on the toggling activity correlations of FFs and their physical position proximity
constraints in the layout. Our data-driven clock gating is integrated into an Electronic Design
Automation (EDA) commercial backend design flow, achieving total power reduction of 15%–
20% for various types of large-scale state-of-the-art industrial and academic designs in 40 and 65
manometer process technologies. These savings are achieved on top of the savings obtained by
clock gating synthesis performed by commercial EDA tools, and gating manually inserted into the
register transfer level design.