Recent advancements in Cache technology a slide prepared for the partial fulfillment of Advanced Computer Architecture Course, MECE II NCIT Balkumari

1. Recent Advancements in
Cache Technology
Paras Nath Chaudhary (192961)
Nepal College of Information Technology

2. Overview
● Idea behind Cache
● Hybrid Cache
● Comparison of Various sorts of Hybrid Caches
● Non-uniform Cache design for Multi-core Processor
● Cache Optimization Trends
● References
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3. Idea Behind Cache
● Why not make all of the computer's memory run at the same speed as the
L1 cache, so no caching would be required?
● Problem: Incredibly expensive
● use a small amount of expensive memory to speed up a large amount of
slower, less-expensive memory
● Locality of Reference
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4. Hybrid Caches
● Static Random-Access Memory ( SRAM )
● Dynamic Random-Access Memory( DRAM )
● Phase Change Random-Access Memory ( PRAM )
○ based on the resistance difference of two phases
● Magnetoresistive Random-Access Memory ( MRAM )
○ Stores data in magnetic domain
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5. Comparison Of Various Sorts Of Hybrid
Caches
Features SRAM DRAM PRAM MRAM
Density Low High High Very High
Speed Very fast Fast Fast read / slow
write
Slow read / very
slow write
Dynamic
Power
Low Medium Low read and
high write
Medium read
and high write
Leakage
Power
High Medium Low Low
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6. Non-uniform Cache Design For Multi-core
Processor
● Non-uniform Cache Access
○ To increase the execution of processors that have many processing cores and require ton
of information transmission capacity
○ Decreases the latency of information access
○ Expands Scalability
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7. Different Non-uniform Cache Architectures
● Uniform Cache Architecture ( UCA )
● Multi-level Uniform Cache Architecture (ML-UCA)
● Statically-Mapped Non-uniform Cache Architecture (S-NUCA)
● Dynamically-Mapped Non-uniform Cache Architecture (D-NUCA)
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8. Uniform Cache Architecture (UCA)
● Similar to tradition cache.
● Uses sub-banks, but limited by number of ports
● Moore’s law scaling leads to increasing wire delay
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9. Multi-level Uniform Cache Architecture
(ML-UCA)
● Cache split into two levels: L2 and L3
● Both levels aggressively banked to support parallel access
● L3 includes everything in L2
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10. Statically-Mapped Non-uniform Cache
Architecture (S-NUCA)
● Aggressively banked and supports non-uniform access
● No inclusion ( avoid duplication)
● Mapping of data into banks is statically pre-determined based on block
index
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11. Dynamically-Mapped Non-uniform Cache
Architecture (D-NUCA)
● Mapping of data into banks is dynamic
● Cache management attempts to have most requests served by faster
banks
● Frequently used data promoted to faster banks
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12. Cache Optimization Trend
● Hybrid Memory Cube
○ for improving the wall in terms of efficiency and performance
○ 15 times better performance than DDR3 module
○ uses 70% less energy per bit than DDR3
● Solid State Device
○ Intel Z68 chipset which allows SATA Solid State Device (SSD) to function as a cache for
the hard disk drive with a much higher speed
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13. References:
● Elarabi T, Bhatt V. 2016. ADVANCEMENTS IN CACHE ARCHITECTURE AND
TECHNOLOGY-A SURVEY. International Journal of Advances in Electronics and Computer
Science. Volume-3. Issue-8. ISSN: 2393-2835
● Alameldeen A. Non-Uniform Cache Architectures. 2018 (Available at
http://web.cecs.pdx.edu/~alaa/ece588/notes/nuca.pdf), Accessed: Feb - 4, 2020
● Lira J, Molina C, Gonzalez A. Performance Analysis of Non-Uniform Cache Architecture Policies
for Chip-Multiprocessors Using the Parsec v2.0 Benchmark Suite (Available at
http://arco.e.ac.upc.edu/wiki/images/1/1f/Lira_jorpar09.pdf), Accessed: Feb - 4, 2020
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14. Thank You
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