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TRƯỜNG ĐẠI HỌC BÁCH KHOA ĐÀ NẴNG

        KHOA ĐIỆN TỬ – VIỄN THÔNG

                   




     BÁO CÁO THÍ NGHIỆM

KỸ THUẬT SIÊU CAO TẦN
LAB 3: Transients on Transmission Lines




                 Student        : Nguyễn Thị Bảo Trâm

                 Group          :      09A

                 Class          :     06DT1




               Đà Nẵng – 2010




               dddDDDASARTETE
Báo cáo TN SIÊU CAO TẦN                                                                        Lab3


1. Introduction:

   We have thus far focused on techniques for understanding transmission lines under sinusoidal
excitation. Powerful analytic insight is available here, permitting straightforward design of
interesting circuits.

   In contrast, the analysis of transients is generally more difficult and less amenable to simple
closed-form analysis, especially when loads are reactive. This laboratory will explore the propagation
of transients on transmission lines with the aid of numerical experiments in SPICE.

2. Purely Resistive Termination:

   First, let's use SPICE to investigate the propagation of pulses on a transmission line terminated
by purely resistive loads.

2.1 A step function, matched load

   First, create a 50  transmission line with total length (time delay) of 25 ns, and excite it with a
Thevenin source 10u(t), with a source resistance Rg = 50  . With the load resistance RL = 50  ,
run the simulation.

                             Rg                  T1
                      Vg            Vsource                               Vload
                             50
                                                   TD = 25ns
                     Vg                            Z0 = 50                               RL
                                                                                         50
                                         0                            0



                     0                                                               0

   To create the voltage source, use the VPWL source. Using VPWL allows various times and the
voltages at those times to be specified using the T1, T2, T3, ... and V1, V2, V3, ... parameters. The
voltage source will be piece-wise linear, connecting each specified point. Using VPULSE allows
specification of the initial voltage, V1, the voltage of the pulse, V2, the delay time, TD, the rise time,
TR, the fall time, TF, the pulse width, PW, and the period, PER.

   The VPWL source is piece-wise linear and allows the user to specify voltages at specific times
using T1, T2, T3… and the corresponding V1, V2, V3 parameters. Please note that the source will
connect each specified point in the most direct way. Additionally, two voltages cannot be specified
for the same time, so that instantaneous changes must be approximated.

   For Example: to specify a VPWL source that produces a 10V square pulse starting at t=0 and
lasting for 10 ns, would have the following specified parameters: T1=0, V1=0, T2=0.001n, V2=10,
T3=10n, V3=10, T4=10.001n, V4=0. (Making V3=0 would form a sawtooth wave because of the
reasons stated above.)

Nguyễn Thị Bảo Trâm – 06DT1                                                                        Page 2
Báo cáo TN SIÊU CAO TẦN                                                                            Lab3


   Using VPULSE allows specification of an initial voltage, V1, the voltage of the pulse, V2, the delay
time, TD, the rise time, TR, the fall time, TF, the pulse width, PW, and the period, PER. Single
pulses can be formed with this source. More complex signals can be formed by combining multiple
sources.

Problem 1 Plot the voltage at the source and load ends of the transmission line for t = 0…50 ns.
Using your understanding of “bounce diagrams”, explain whether this plot makes sense and shows
what you would expect to see in the “exact” answer. Do the two agree? If not, why not? A full
credit answer will describe the bounce diagram until a reasonable (whatever you consider
reasonable) number of bounces, which can explain what exactly is happening in this situation.
Please do the same in any other bounce diagram questions that may follow.

Answer:

   -         The voltage at the source and load ends of the transmission line for t = 0…50 ns

  10V




   5V




   0V
        0s           5ns      10ns      15ns     20ns      25ns     30ns     35ns   40ns   45ns   50ns
             V(VG)    V(VSOURCE)   V(VLOAD)
                                                           Time



             The reflection coefficient at the source is:

                                                      𝑅 𝑔 − 𝑍0 50 − 50
                                               Γ𝑔 =           =        =0
                                                      𝑅 𝑔 + 𝑍0 50 + 50

             The reflection coefficient at the load is:

                                                      𝑅 𝐿 − 𝑍0 50 − 50
                                               Γ𝐿 =           =        =0
                                                      𝑅 𝐿 + 𝑍0 50 + 50

   ⇒ There is no reflection wave of voltage at the source and the load.
                                                         𝑉𝑔 𝑍 𝐿   10 .50
                                               𝑉𝐿 =             =        = 5(𝑉)
                                                      𝑅 𝑔 + 𝑍 𝐿 50 + 50

Nguyễn Thị Bảo Trâm – 06DT1                                                                              Page 3
Báo cáo TN SIÊU CAO TẦN                                                                                          Lab3


     VL = 5 (V) after 25ns (time delay of the transmission line.)
   ⇒ The theory and the plot are the same.

2.2 A step function, mismatched load

Now, change the load impedance in the previous case to 20  .

                                    Rg                      T1
                            Vg             Vsource                                  Vload
                                    50
                                                             TD = 25ns
                           Vg                                Z0 = 50                                   RL
                                                                                                       20
                                                 0                              0



                            0                                                                      0

Problem 2 Plot the voltage at the source and load ends of the transmission line for t = 0…100
ns. Using your understanding of “bounce diagrams”, compare this with what you would expect to
see in the “exact” answer. Do the two agree? If not, why not? How long does it take the answer to
settle to the final answer?

Answer:

   -         The voltage at the source and load ends of the transmission line for t = 0…100 ns

  10V




   5V




   0V
        0s           10ns      20ns      30ns        40ns        50ns    60ns   70ns        80ns        90ns   100ns
             V(VG)     V(VSOURCE)   V(VLOAD)
                                                                 Time



             The reflection coefficient at the source is:

                                                        𝑅 𝑔 − 𝑍0 50 − 50
                                                Γ𝑔 =            =        =0
                                                        𝑅 𝑔 + 𝑍0 50 − 50

Nguyễn Thị Bảo Trâm – 06DT1                                                                                            Page 4
Báo cáo TN SIÊU CAO TẦN                                                                     Lab3


       The reflection coefficient at the load is:

                                                 RL  Z 0 20  50    3
                                        L                      
                                                 RL  Z 0 20  50    7

                                                     Vg Z 0         10.50
                                            V1                           5(V )
                                                    Rg  Z 0       50  50
                                                                                       3
At t = T = 25ns, the wave reaches the load (receiving end) z = l, and because L        0 , the
                                                                                       7
mismatch generates a reflected wave with the amplitude:

                                                               15
                                           V1  L .V1        (V)
                                                                7
So the voltage on line (in this case, the load voltage) is the sum of two waves:

                       15 20
VL  V1  V1  5           2.86(V )
                        7   7
At t = 2T = 50ns, the wave reaches the sending end z = 0, and because g  0 , there is no
reflection wave in form of a wave with voltage amplitude V2+ = 0. Thus, the voltage on line (in this
case, the source voltage) is:

                       15 20
VS  V1  V1  5           2.86(V )
                        7   7
                                                                                        3
At t = 3T = 75ns, the wave reaches the load (receiving end) z = l, and because L        0 , the
                                                                                        7
mismatch generates a reflected wave with the amplitude: V2  L .V2  0 (V)
    VL = 2.86 (V)
Similarly, we also have: VS = 2.86 (V)
                            g                       L

                                                         z=l
                       z=0
                       t=0                 V1+

                                                          T
                       t=0
                               L V1+



                   2T
                                        L g V1+

                                                        3T


Thus, after 50ns, the voltage at two ends of the transmission line have the same final answers.

Nguyễn Thị Bảo Trâm – 06DT1                                                                    Page 5
Báo cáo TN SIÊU CAO TẦN                                                                              Lab3


2.3 A step function, mismatched load and source

Now, change the load impedance in the previous case to RL=20  , and change the source
impedance to Rg=200  .

                                  Rg                     T1
                            Vg            Vsource                             Vload
                                  200
                                                          TD = 25ns
                           Vg                             Z0 = 50                             RL
                                                                                              20
                                                     0                   0



                           0                                                              0

Problem 3 Plot the voltage at the source and load ends of the transmission line for t = 0…300
ns. Using your understanding of “bounce diagrams”, compare this to the “exact” answer. Do the two
agree? If not, why not? How long does it take the answer to settle down to the final answer?

Answer:

   -         The voltage at the source and load ends of the transmission line for t = 0…300 ns
  12V




   8V




   4V




   0V
        0s                50ns               100ns        150ns       200ns           250ns        300ns
             V(VG)   V(VSOURCE)   V(VLOAD)
                                                              Time



        Rg  Z 0         200  50
g                               0.6
        Rg  Z 0         200  50

        RL  Z 0 20  50    3
L                     
        RL  Z 0 20  50    7



Nguyễn Thị Bảo Trâm – 06DT1                                                                                Page 6
Báo cáo TN SIÊU CAO TẦN                                                                    Lab3


         Vg Z 0         10.50
V1                            2(V )
        Rg  Z 0       200  50

                                                                                       3
At t = T = 25ns, the wave reaches the load (receiving end) z = l, and because L        0 , the
                                                                                       7
mismatch generates a reflected wave with the amplitude:

                  3        6
V1  L .V1  ( ) .2    0.86 (V)
                  7        7
So the voltage on line (in this case, the load voltage) is the sum of two waves:

                          6 8
VL  V1  V1  2          1.14(V )
                          7 7

At t = 2T = 50ns, the wave reaches the sending end z = 0, and because g  0.6 , there is a
                                                                   
reflection wave in form of a wave with voltage amplitude V2+ = gV1 . Thus, the voltage on line (in
this case, the source voltage) is:

VS  V1  V1  V2  (1  L  L  g ).V1  0.63(V )

                                                                                        3
At t = 3T = 75ns, the wave reaches the load (receiving end) z = l, and because L        0 , the
                                                                                        7
mismatch generates a reflected wave with the amplitude: V2  L .V2 (V)

     VL = 0.85 (V)
                               g                             L

                        z=0                         V1+          z=l
                        t=0
                        t=0                                        T
                                         L V1
                                              +




                             2T
                                                  L g V1+

                                                                   3T
                                  L 
                                      2        +
                                           g V1



                        4T
                                                   L g V1+
                                                      2   2



                                                                   5T




Nguyễn Thị Bảo Trâm – 06DT1                                                                    Page 7
Báo cáo TN SIÊU CAO TẦN                                                                              Lab3


 Calculate like the process above, we have the table:


     Time                          V at sending end                                 V at receiving end


t = 0ns                          Vg Z 0         10.50                  VL  0(V )
                   VS = V1                            2(V )
                                Rg  Z 0       200  50


t = T =25ns                      Vg Z 0         10.50                                         6 8
                   VS = V1                            2(V )        VL  V1  V1  2       1.14(V )
                                Rg  Z 0       200  50                                       7 7


t = 2T = 50ns      VS  V1  V1  V2                                                       6 8
                                                                       VL  V1  V1  2       1.14(V )
                    (1  L  L  g ).V1  0.63(V )                                        7 7



t = 3T=75ns        VS  V1  V1  V2                                VL  (1  L  L  g L g ).V1  0.85(V )
                                                                                               2


                    (1  L  L  g ).V1  0.63(V )


t = 4T=100ns       VS  (1  L  L  g L g  L g ).V1  0.98(V ) L  (1  L  L  g L g ).V1  0.85(V )
                                           2       2 2
                                                                       V                        2




t = 5T =125ns      VS  (1  L  L  g L g
                                           2
                                                                       VL  (1  L  L  g L g  L g2
                                                                                               2       2


                    L g2 ).V1  0.98(V )
                      2
                                                                        L g2 ).V1  0.92(V )
                                                                          3




T = 6T =150ns      VS = 0.98 (V)                                       VL = 0.924(V)


T = 7T =175ns      VS = 0.89(V)                                        VL = 0.924(V)


T = 8T =200ns      VS = 0.89(V)                                        VL = 0.909(V)


T = 9T =225ns      VS = 0.913(V)                                       VL = 0.909(V)


    -     Thus, the plot and the “exact” answer agree.

 Nguyễn Thị Bảo Trâm – 06DT1                                                                              Page 8
Báo cáo TN SIÊU CAO TẦN                                                                                                  Lab3


                                                    Vg Z L         10.20
   -   The final voltage is: V                                           0.909(V )
                                                   Rg  Z 0       200  20
       ⇒ It takes 225ns to settle down to the final answer.

2.4 A short pulse

Now break the transmission line into two equal pieces, with total length 25 ns (you should now have
two different transmission lines, both with the same 50  characteristic impedance, but each with a
time delay of only 12.5 ns). This permits us to sample “inside” the transmission line. With the same
transmission line, and Rg=200  and RL=20  apply a pulse of duration 10 ns to the transmission
line, namely vg(t) = 10(u(t)- u(t-10ns)).

                    Rg                      T1                                        T2
          Vg                 Vsource                                   Vmiddle                                 Vload
                    200
        Vg                                          Z0 = 50                                 Z0 = 50
                                                  TD = 12.5ns                             TD = 12.5ns                        RL
                                                                                                                               20

                                 0                                      0      0                                0

        0                                                                                                                0

Problem 4 Plot the voltage at the source, middle, and load ends of the transmission lines for t =
0…100 ns. Sketch the bounce diagram; do you understand the voltage plots? How long before the
“ghost” pulse (the pulse you are seeing at the middle of the transmission line) arrives at the load
end? How large is the “ghost” pulse?

Answer:

   -   The voltage at the source, middle, and load ends of the transmission lines for t = 0…100ns

        2.0V




        1.0V




          0V




       -1.0V




       -2.0V
               0s         10ns          20ns        30ns      40ns      50ns       60ns      70ns       80ns    90ns   100ns
                    V(VSOURCE)       V(VMIDDLE)      V(VLOAD)
                                                                        Time


Nguyễn Thị Bảo Trâm – 06DT1                                                                                                     Page 9
Báo cáo TN SIÊU CAO TẦN                                                                                     Lab3


          Rg  Z 0       200  50
  g                             0.6
          Rg  Z 0       200  50

          RL  Z 0 20  50    3
  L                     
          RL  Z 0 20  50    7

            Vg Z 0        10.50
  V1                            2(V )
          Rg  Z 0       200  50

     -      The bounce diagram:

                                g                                      L
                                                    z l
                                                           2
                           z=0                             V1+              z=l

                           t=0                                              T
                                        L V1
                                             +




                             2T                            L g V1+

                                                                             3T
                                      L 
                                        2       +
                                            g V1




                             4T
                                                        L g V1+
                                                               2   2




                                                                             5T


     -      We have the table of values (by calculating):


     Time                         V at sending end                               V middle          V at receiving end


t = 0+ ns                               Vg Z 0                         Vm = 0 (V)             VL = 0 (V)
                         VS  V1                   2(V )
                                      Rg  Z 0


t = T/2                        Vg Z 0    0.50                          Vm = V1+ (t = 0ns) =   VL = 0 (V)
=12.5ns                  VS                   0                     2(V)
                              Rg  Z 0 200  50



  Nguyễn Thị Bảo Trâm – 06DT1                                                                                   Page 10
Báo cáo TN SIÊU CAO TẦN                                                                       Lab3



t = T = 25ns    VS = 0(V)                        Vm = VS (t = 12.5ns) =      VL  V1  V1
                                                 0(V)                               6 8
                                                                              2      1.14(V )
                                                                                    7 7


t = 3T/2 =      VS = 0(V)                        Vm  V1  LV1                      
                                                                             VL  Vm  Vm
37.5ns                                                                                        (Vm at t = 2T)
                                                    6                         0(V )
                                                    0.86(V )
                                                    7


t = 2T = 50ns   VS  V1  V2                   Vm  VL  0(V )            VL = 0 (V)

                  (L  L  g ).V1
                  1.37(V )


t = 5T/2 =               Vg Z 0                  Vm  V2  L gV1         VL = 0 (V)
62.5ns          VS 
                        Rg  Z 0                    3
                                                    0.6  2  0.51(V )
                       0.50                         7
                              0(V )
                     200  50


t = 3T=75ns     VS = 0(V)                        Vm = VS (t = 12.5ns) =      VL  V2  V2
                                                 0(V)
                                                                              (L  g L g ).V1  0.29(V )
                                                                                         2




t=              VS = 0(V)                        Vm  V2  L gV1
                                                              2
                                                                             VL = 0 (V)
7T/2=82.5ns
                                                  0.22(V )


t = 4T =100ns   VS  V2  V3                   Vm  VL  0(V )            VL = 0 (V)

                  (L g  L g2 ).V1
                     2       2


                  0.35(V )



        It takes 12.5ns for the “ghost” pulse to get the load end. The ghost pulse has width of
        12.5ns.



  Nguyễn Thị Bảo Trâm – 06DT1                                                                     Page 11
Báo cáo TN SIÊU CAO TẦN                                                                                                Lab3


2.5 A longer pulse

In the previous problem, the pulse was brief (10 ns) compared to the length of the transmission line
(25 ns). Now investigate a more complicated system.

Problem 5                Using the same transmission line and source impedance, define a new source for
which vg = +10 V for t = 0 … 20 ns, and vg   V for t = 20 … 40ns. Plot the voltage at the
source, center, and load end of the transmission line for t = 0…100 ns. Is the transition from “high”
to “low” perfectly clear at the load end?

Answer:

                        Rg                     T1                                T2
             Vg                 Vsource                               Vmiddle                           Vload
                        200
            Vg                                     Z0 = 50                           Z0 = 50
                                                 TD = 12.5ns                       TD = 12.5ns                             RL
                                                                                                                           20

                                    0                                  0   0                             0

             0                                                                                                         0

       -      The voltage at the source, center, and load end of the transmission line for t = 0…100ns

           2.0V




             0V




       -2.0V




       -4.0V
                  0s         10ns          20ns      30ns      40ns     50ns    60ns     70ns    80ns           90ns       100ns
                       V(VSOURCE)       V(VMIDDLE)    V(VLOAD)
                                                                        Time

   -       From the graph, we can see that the transition from high to low is perfectly clear at the load
           end.

2.6 An Impedance Bump

Transmission lines must be protected against damage, or their impedance properties could be
compromised. In this section we’ll “damage” the transmission line by putting a weak load in the

Nguyễn Thị Bảo Trâm – 06DT1                                                                                                Page 12
Báo cáo TN SIÊU CAO TẦN                                                                                              Lab3


middle. In particular, at the center of the transmission line, add a shunt resistance of 50  (a shunt
resistance connects the node at the middle to ground).

                    Rg                  T1                                                T2
            Vg                Vsource                             Vmiddle                                  Vload
                    200
        Vg                                    Z0 = 50                                        Z0 = 50
                                            TD = 12.5ns                   Rshunt           TD = 12.5ns                     RL

                                                                          50                                               20


                                   0                          0           0           0                    0
            0                                                                                                         0

Problem 6 With the shunt resistance in place, repeat the previous problem. How did the
presence of the “bump” (break in the transition line) affect the voltage plots? Did any new “ghosts”
show up? Looking only at the source and end voltages, could you determine where the “bump” is?
Can you explain what you see in terms of a bounce diagram?

Answer:

   2.0V




       0V




  -2.0V




  -4.0V
            0s         10ns       20ns       30ns      40ns        50ns        60ns        70ns     80ns   90ns    100ns
                 V(VSOURCE)    V(VMIDDLE)     V(VLOAD)
                                                                   Time



   -        The presence of the impedance “bump” (break in the transition line) reduced the magnitude
            of the middle voltage.

3. Reactive Termination

As mentioned in class, it is frequently the case that the loads at the end of a data bus are reactive
(and often capacitive).

3.1 A step into a capacitive load


Nguyễn Thị Bảo Trâm – 06DT1                                                                                            Page 13
Báo cáo TN SIÊU CAO TẦN                                                                                   Lab3


For this exercise, again form a circuit with a source vg(t) = 10u(t), a source impedance Rg=25  ,
and a transmission line with characteristic impedance 50  and length 25ns.

                                             Rg             T1
                                  Vg              Vsource                        Vload
                                             25
                                 Vg
                                                             TD = 25ns
                                                             Z0 = 50
                                                                                             CL
                                                       0                         0           1n


                                 0                                                       0

Problem 7 Terminate the transmission line with a 1nF capacitor. Plot the voltage at the source
and load ends of the transmission line for t = 0…400ns. If you see any “exponential” charging or
discharging, estimate the time constant, and solve for the R. You may use the following formulas.




    15V




    10V




     5V




     0V
          0s            50ns         100ns         150ns         200ns   250ns       300ns        350ns   400ns
               V(VSOURCE)    V(VLOAD)
                                                                 Time

                        Vinitial = 0V
                        VFinal = 12.133V
                        V(t) = 8.4292V
                        t        = (75 – 25) = 50ns



Nguyễn Thị Bảo Trâm – 06DT1                                                                                 Page 14
Báo cáo TN SIÊU CAO TẦN                                                                                                 Lab3


                                        −𝑡                           −50. 10−9
                         𝜏=                                 =                      = 4.214. 10−8
                                    𝑉(𝑡) − 𝑉𝑓𝑖𝑛𝑎𝑙                  8.4292 − 12.133
                              𝑙𝑛 𝑉                              𝑙𝑛
                                   𝐼𝑛𝑖𝑡𝑖𝑎𝑙 − 𝑉𝑓𝑖𝑛𝑎𝑙                   0 − 12.133

                                                  𝜏 4.214. 10−8
                                      𝜏 = 𝑅𝐶 ⇒      =   𝑅=        = 42.14(Ω)
                                                  𝐶      10−9
Problem 8            Repeat the previous problem, but with a load capacitance of 100pF.

                                           Rg                   T1
                                 Vg             Vsource                               Vload
                                           25
                                Vg
                                                                  TD = 25ns
                                                                  Z0 = 50
                                                                                                    CL
                                                        0                             0               100pF


                                 0                                                              0

  15V




  10V




   5V




   0V
        0s            50ns         100ns        150ns             200ns       250ns           300ns           350ns   400ns
             V(VSOURCE)    V(VLOAD)
                                                                     Time



                        Vinitial = 0V
                        VFinal = 13.33V
                        V(t) = 13.244V
                        t        = (50 – 25) = 25ns
                                          −𝑡                −25. 10−9
                          𝜏=                          =                   = 4.956. 10−9
                                      𝑉(𝑡) − 𝑉𝑓𝑖𝑛𝑎𝑙        13.244 − 13.33
                               𝑙𝑛 𝑉                     𝑙𝑛
                                     𝐼𝑛𝑖𝑡𝑖𝑎𝑙 − 𝑉𝑓𝑖𝑛𝑎𝑙         0 − 13.33

                                                                              −9
                                                                𝜏 4.956. 10
                                      𝜏 = 𝑅𝐶 ⇒        𝑅=          =           = 49.56(Ω)
                                                                𝐶   100.10−12



Nguyễn Thị Bảo Trâm – 06DT1                                                                                               Page 15
Báo cáo TN SIÊU CAO TẦN                                                                                           Lab3


Problem 9            Repeat the previous problem, but with a load capacitance of 10nF.

                                           Rg               T1
                                   Vg           Vsource                          Vload
                                           25
                                  Vg
                                                             TD = 25ns
                                                             Z0 = 50
                                                                                               CL
                                                        0                        0               10nF


                                  0                                                        0

  10V




   5V




   0V
        0s            50ns         100ns        150ns        200ns       250ns           300ns          350ns   400ns
             V(VSOURCE)    V(VLOAD)
                                                             Time



                            Vinitial = 0V
                            VFinal = 10V
                            V(t) = 8.056V
                            t        = (400 – 25)= 375ns
                                              −𝑡               −375. 10−9
                              𝜏=                          =                = 2.29. 10−7
                                          𝑉(𝑡) − 𝑉𝑓𝑖𝑛𝑎𝑙         8.056 − 10
                                   𝑙𝑛 𝑉                     𝑙𝑛
                                         𝐼𝑛𝑖𝑡𝑖𝑎𝑙 − 𝑉𝑓𝑖𝑛𝑎𝑙         0 − 10

                                                                         −7
                                                          𝜏 2.29. 10
                                        𝜏 = 𝑅𝐶 ⇒        𝑅= =         = 22.9(Ω)
                                                          𝐶  10.10−9


Problem 10 Repeat the previous problem, but with a load inductance of 2.5μH.




Nguyễn Thị Bảo Trâm – 06DT1                                                                                         Page 16
Báo cáo TN SIÊU CAO TẦN                                                                                              Lab3


                                             Rg                 T1
                                   Vg              Vsource                           Vload
                                             25                                                1
                                  Vg
                                                                 TD = 25ns
                                                                 Z0 = 50                           L

                                                                                                   2.5uH
                                                          0                           0
                                                                                               2

                                  0                                                             0

  15V




  10V




   5V




   0V
        0s            50ns         100ns          150ns         200ns        250ns           300ns         350ns   400ns
             V(VSOURCE)    V(VLOAD)
                                                                 Time



                            Vinitial = 13.202V
                            VFinal = 0V
                            V(t) = 4.8052V
                            t        = (75 – 25) = 50ns
                                             −𝑡               −50. 10−9
                             𝜏=                          =               = 4.947. 10−8
                                         𝑉(𝑡) − 𝑉𝑓𝑖𝑛𝑎𝑙        4.8052 − 0
                                  𝑙𝑛 𝑉                     𝑙𝑛 13.202 − 0
                                        𝐼𝑛𝑖𝑡𝑖𝑎𝑙 − 𝑉𝑓𝑖𝑛𝑎𝑙

                                                                         −6
                                             𝑅                𝐿   2.5. 10
                                        𝜏=     ⇒      𝑅=        =           = 50.53(Ω)
                                             𝐿                𝜏 4.947. 10−8


Problem 11 Repeat the previous problem, but with a load inductance of 0.25μH.




Nguyễn Thị Bảo Trâm – 06DT1                                                                                            Page 17
Báo cáo TN SIÊU CAO TẦN                                                                                           Lab3


                                           Rg               T1
                                   Vg           Vsource                           Vload
                                           25                                              1
                                  Vg
                                                             TD = 25ns
                                                             Z0 = 50                           L

                                                                                               0.25uH
                                                        0                          0
                                                                                           2

                                  0                                                         0

  15V




  10V




   5V




   0V




  -5V
        0s            50ns         100ns        150ns        200ns        250ns           300ns         350ns   400ns
             V(VSOURCE)    V(VLOAD)
                                                             Time



                              Vinitial = 13.3V
                              VFinal = 0V
                              V(t) = 1.51V
                              t        = (36 – 25)ns
                                               −𝑡             −11. 10−9
                              𝜏=                           =             = 5.056. 10−9
                                           𝑉(𝑡) − 𝑉𝑓𝑖𝑛𝑎𝑙        1.51 − 0
                                    𝑙𝑛 𝑉                     𝑙𝑛 13.3 − 0
                                          𝐼𝑛𝑖𝑡𝑖𝑎𝑙 − 𝑉𝑓𝑖𝑛𝑎𝑙

                                                                         −6
                                           𝑅          𝐿  0.25. 10
                                        𝜏=   ⇒      𝑅= =            = 49.44(Ω)
                                           𝐿          𝜏 5.056. 10−9


Problem 12 Repeat the previous problem, but with a load composed of a parallel combination of
RL=1000  , L = 1μH and C = 100pF.




Nguyễn Thị Bảo Trâm – 06DT1                                                                                         Page 18
Báo cáo TN SIÊU CAO TẦN                                                                                               Lab3


                                       Rg               T1
                                Vg           Vsource                          Vload
                                       25                                                     1
                               Vg
                                                          TD = 25ns                RL             L       C
                                                          Z0 = 50
                                                                                   1k             1uH     100pF
                                                  0                            0
                                                                                              2

                               0                                                              0


        10V




         5V




         0V




        -5V
              0s            50ns         100ns         150ns          200ns           250ns       300ns       350ns   400ns
                   V(VSOURCE)    V(VLOAD)
                                                                      Time



Problem 13 How important is the value of Rg in these exercises?

Answer:

    -         R is very important since it allows the system to reach steady state. The value of R helps us
               g                                                                                                      g
              to determine whether the circuit is matched or not at the input of transmission line.

4. Coupling

Many data buses are in parallel, in close proximity, such as the 32 bit and 64 bit buses found in
computers. These transmission lines will have “mutual impedance” which causes signals on one
transmission line to show up on another one.

In EE571 students analyze this coupling in great detail, but we can simulate a simplified model of a
two-wire data bus using SPICE1:




1
 Note that your SPICE library contains a model for coupled lines; you could use this, but it does the modeling with an
explicit form of the Telegrapher’s Equation, and is painfully slow. I tried to use it, but realized that it would take about
one day to run every simulation!
Nguyễn Thị Bảo Trâm – 06DT1                                                                                               Page 19
Báo cáo TN SIÊU CAO TẦN                                                                                          Lab3




Here T1 and T4 represent the “actual” transmission lines, while T2 and T3 represent the cross
coupling. The coupling is slightly faster (95 ns instead of 100 ns) and has a higher characteristic
impedance.

Connect a Thevenin signal pulse (10 V, 50  ) to A and 50  loads to B, C and D2.

                                                       Z0 = 50
                                                     TD = 100ns
                                                   T1
                         A                                                                       C



                            R1
                                                                                                         R3
                             50             0                              0
                      Vg                                Z0 = 200                                         50
                       Vg                               TD = 95ns
                                                   T2




                                                                                                     0
                        0
                                            0                              0
                                                        Z0 = 200
                                                        TD = 95ns
                                                   T3




                                            0                              0

                                                       Z0 = 50
                                                     TD = 100ns
                                                   T4
                         B                                                                   D


                                                                                                         R4
                            R2
                                                                                                         50
                             50             0                              0

                        0                                                                            0


2
  To make this model even closer to the real thing, the signal injected into T2 should have opposite sign of that injected
into T1. However, this lab will not require this.
Nguyễn Thị Bảo Trâm – 06DT1                                                                                         Page 20
Báo cáo TN SIÊU CAO TẦN                                                                         Lab3


4.1 A simple pulse

Inject a 10ns pulse with the Thevenin source at A. Use a rise and fall time of 1ns.

Problem 14 Simulate the problem for 250 ns, and plot the voltage at A, B, C, and D. Describe
what you observe. How big is the VC compared to VD when the pulse arrives?

Which arrives first?

Answer:

   -         Plot the voltage at A, B, C, and D

  10V




   5V




   0V




  -5V
        0s                   50ns                 100ns          150ns         200ns          250ns
             V(VG)   V(A)   V(B)    V(C)   V(D)
                                                          Time



   -         V is about 4 times compared to the magnitude of V when the pulse arrives.
              C                                                     D
   -         V arrives first.
              D


Problem 15 When does a signal arrive at B? If you change the values of the load resistances at C
and D, can you eliminate the reflection? If so what value should the load have?

Answer:

   -         A signal arrives at B at 195ns.
   -         We cannot eliminate the reflection by changing the values of the load resistances at C and
             D. We just can reduce VC and VD to zero.
   -         The plot when the load resistances at C and D are 0.001Ω:




Nguyễn Thị Bảo Trâm – 06DT1                                                                       Page 21
Báo cáo TN SIÊU CAO TẦN                                                                                  Lab3


    10V




       5V




       0V




    -5V
            0s                   50ns                  100ns                       150ns   200ns         250ns
                 V(VG)   V(A)   V(B)    V(C)   V(D)
                                                                    Time



5. Impedance Matching

5.1. Pre-lab Assignment

5.1. A. Design a quarter-wave transformer to match a 150 Ω load to a source resistance of 75 Ω.
State the length of your transmission line(s) in terms of the wavelength.

Answer:

                                                      𝑍 𝐿 = 150Ω

                                                      𝑍 𝑖𝑛 = 75Ω

The input impedance is:
                                                                   ZL + jZ0 tgβl
                                                       𝑍 𝑖𝑛 = Z0
                                                                   Z0 + jZL tgβl
                                                        𝜆               2𝜋 𝜆       𝜋
With                                              𝑙 = 4 ⇒ 𝛽𝑙 =             .
                                                                         𝜆 4
                                                                               =   2

                                                                                                   π
We can divide the numerator and the denominator by tgβl and take the limit as βl →                     to get:
                                                                                                   2

                                                                         𝑍0 2
                                                               𝑍 𝑖𝑛 =
                                                                          𝑍𝐿

The characteristic impedance of the matching section is:

                                         ⇒ 𝑍0 =        𝑍 𝐿. 𝑍 𝑖𝑛 = 150.75 = 106.066(Ω)




Nguyễn Thị Bảo Trâm – 06DT1                                                                                 Page 22
Báo cáo TN SIÊU CAO TẦN                                                                          Lab3


5.1. B. Using the Smith Chart, if the characteristic impedance is given as 75 Ω, design a stub-
matching network to match a 150 Ω load to a 75 Ω source. Do this for both a shorted and an open
circuited stub. State the length of your transmission line(s) in terms of wavelength.

Answer:

                                      𝑍0 = 75Ω

                                      𝑍 𝑖𝑛 = 75Ω

                                      𝑍 𝐿 = 150Ω
                                                   ZL       150
   -   The normalized load impedance is: 𝑧 𝐿 =          =         = 2Ω (point A on the Smith chart)
                                                   Z0       75
   -   Construct the appropriate SWR circle through point A. From the Smith chart, the normal load
       admittance: yL = 0.5 (at point B l  0  )
   -   The SWR circle intersects the 1+jb circle at two points, denoted as y1 , y2. Thus the distance
       d, from the load to the stub, is given by either of these two intersections. Reading the WTG
       scale, we obtain:
       d2 = (0.348– 0)  = 0.348 
       At the two intersection points, the normalized admittances are:
       y1 = 1 + j0.7
       y2 = 1 – j0.7
   -   Thus, the first tuning solution requires a stub with a susceptance of – j0.7. The length of an
       open-circuited stub that gives this susceptance can be found on Smith chart by starting at y
       = 0 (the open circuit) and moving along the outer edge of the chart (g=0) toward the
       generator to the – j0.7 point. The length is then:
       lo1= 0.402 
       Similarly, the required open-circuited stub length for the second solution is:
       lo2= 0.097 
   -   The length of an shorted-circuited stub that gives this susceptance can be found on Smith
       chart by starting at y = ∞ (the shorted circuit) and moving along the outer edge of the chart
       (g=0) toward the generator to the – j0.7 point. The length is then:
       ls1=(0.402 – 0.25)  = 0.152 
       Similarly, the required shorted-circuited stub length for the second solution is:
       ls2= (0.25 + 0.097)  = 0.347 

5.2. Lab Assignment

5.2.A. Find the actual length of the quarter-wave matching network you designed in part 5.1.A if up
= 2E+8 (m/s) and frequency = 1 GHz. Simulate the frequency response of the circuit by sweeping
the frequency from 1 MHz to 3 GHz using a 5Vpp sine wave source with a source resistance of 75 Ω.
Plot the input and load voltage over frequency. Plot the magnitude of the reflection coefficient of



Nguyễn Thị Bảo Trâm – 06DT1                                                                           Page 23
Báo cáo TN SIÊU CAO TẦN                                                                     Lab3


the matching network and find the bandwidth where |Γ| is less than 0.2.           What is the input
impedance of the matching network at 1 GHz?

Answer:
                m
up = 2.108        ;       f = 1GHz
                s

     2.108
     up
         0.2(m)
  f   10 9

            0.2
l               0.05 (m)
     4        4

          l    0.05 m
TD              8
                         2.5.10 10 ( s)  0.25ns
         u p 2.10 m / s




                                   Rs                T1
                                        Vinput                            Vload
                                   75
                              Vs
                 2.5Vac                                TD = 0.25ns                RL
                 0Vdc                                  Z0 = 106.066
                                                                                  150
                                                 0                    0

                              0                                                         0

     -    The input and load voltage over frequency:




Nguyễn Thị Bảo Trâm – 06DT1                                                                  Page 24
Báo cáo TN SIÊU CAO TẦN                                                                                     Lab3


       1.8V




       1.6V




       1.4V




       1.2V
         1.0MHz      3.0MHz        10MHz        30MHz           100MHz       300MHz     1.0GHz     3.0GHz     10GHz
              V(VINPUT)   V(VLOAD)
                                                           Frequency



   -      The magnitude of the reflection coefficient of the matching network:
         400m




         300m




         200m




         100m




               0
              1.0MHz      3.0MHz       10MHz       30MHz          100MHz       300MHz     1.0GHz     3.0GHz        10GHz
                   (V(VINPUT)/ I(Rs)-75)/(V(VINPUT)/I(Rs)+75)
                                                                 Frequency

    |Γ| is less than 0.2 from 608.1 MHz to 1.388 GHz and frequencies from 2.607 GHz to 3 GHz
   - The input impedance of the matching network at 1 GHz is 75Ω.




Nguyễn Thị Bảo Trâm – 06DT1                                                                                   Page 25
Báo cáo TN SIÊU CAO TẦN                                                                        Lab3

  150




  100




                                                                          (1.0000G,75.000)



   50
   1.0MHz      3.0MHz           10MHz   30MHz    100MHz      300MHz      1.0GHz      3.0GHz    10GHz
        V(VINPUT)/ I(Rs)
                                                Frequency



5.2.B. Using the assumptions of section 5.2.A, simulate your pre-lab design in part 5.1.B and find
the Γ bandwidth (the portion of the signal less than 0.2) of the matching network as well as the
input impedance at 1 GHz. Include the same plots as in section 5.2.A.

Answer:
                 m
up = 2.108         ;      f = 1GHz
                 s

     up        2.108
                   0.2(m)
       f        10 9

                                                d1 0.0304 m
d1 =0.152𝜆 = 0.152×0.2 = 0.0304 (m) ⇒ TD                       1.52.10 10 ( s)  0.152ns
                                                u p 2.108 m / s

                                                l o1 0.0804 m
lo1= 0.402𝜆 = 0.402×0.2 = 0.0804 (m) ⇒ TD                      4.02.10 10 ( s)  0.402ns
                                                u p 2.108 m / s
                                                l s1 0.0304 m
ls1=0.152𝜆 = 0.152×0.2 = 0.0304 (m) ⇒ TD                       1.52.10 10 ( s)  0.152ns
                                                u p 2.108 m / s
          Open-circuited stub:




Nguyễn Thị Bảo Trâm – 06DT1                                                                      Page 26
Báo cáo TN SIÊU CAO TẦN                                                                                  Lab3


                                   Rs                   T1
                                         Vinput                                  Vload
                                   75
                            Vs
                 2.5Vac                                   TD = 0.152ns                    RL
                 0Vdc                                     Z0 = 75
                                                                                          150
                                                    0                        0

                                                        T2
                            0                                                                    0

                                                          TD = 0.402ns                         R1
                                                          Z0 = 75
                                                                                                1000G

                                                    0                        0
                                                                                           0

   -      The input and load voltage over frequency:
  2.0V




  1.5V




  1.0V




  0.5V




       0V
       1.0MHz      3.0MHz        10MHz      30MHz        100MHz     300MHz       1.0GHz         3.0GHz   10GHz
            V(VINPUT)   V(VLOAD)
                                                        Frequency



   -      The magnitude of the reflection coefficient of the matching network:
          |Γ| is less than 0.2 from 924 MHz to 1.11 GHz.




Nguyễn Thị Bảo Trâm – 06DT1                                                                                Page 27
Báo cáo TN SIÊU CAO TẦN                                                                              Lab3


  1.0




  0.5




    0
   1.0MHz      3.0MHz        10MHz       30MHz       100MHz     300MHz         1.0GHz       3.0GHz   10GHz
        (V(VINPUT)/I(Rs)-75)/(V(VINPUT)/I(Rs)+75)
                                                    Frequency



   -    The input impedance of the matching network at 1 GHz is 75.029Ω.


  150




  100
                                                                         (1.0000G,75.029)




   50




    0
   1.0MHz      3.0MHz       10MHz       30MHz        100MHz     300MHz         1.0GHz       3.0GHz   10GHz
        V(VINPUT)/ I(Rs)
                                                    Frequency



       Shorted-circuited stub:




Nguyễn Thị Bảo Trâm – 06DT1                                                                            Page 28
Báo cáo TN SIÊU CAO TẦN                                                                                Lab3


                                     Rs                 T1
                                          Vinput                                 Vload
                                     75
                              Vs
                   2.5Vac                                  TD = 0.152ns                  RL
                   0Vdc                                    Z0 = 75
                                                                                         150
                                                   0                        0

                                                        T2
                              0                                                                 0

                                                           TD = 0.152ns
                                                           Z0 = 75
                                                                                     0
                                                   0                        0

   -      The input and load voltage over frequency:
  2.0V




  1.5V




  1.0V




  0.5V




       0V
       1.0MHz      3.0MHz        10MHz     30MHz        100MHz     300MHz       1.0GHz        3.0GHz   10GHz
            V(VINPUT)   V(VLOAD)
                                                       Frequency



   -      The magnitude of the reflection coefficient of the matching network:




Nguyễn Thị Bảo Trâm – 06DT1                                                                              Page 29
Báo cáo TN SIÊU CAO TẦN                                                                              Lab3


        |Γ| is less than 0.2 from 850 MHz to 1.21 GHz and from 2.07 GHz to 2.44 GHz

  1.0




  0.5




    0
   1.0MHz      3.0MHz        10MHz       30MHz       100MHz     300MHz       1.0GHz         3.0GHz   10GHz
        (V(VINPUT)/I(Rs)-75)/(V(VINPUT)/I(Rs)+75)
                                                    Frequency

   -     The input impedance of the matching network at 1 GHz is 75.029Ω.
  100
                                                                         (1.0000G,75.029)




   50




    0
   1.0MHz      3.0MHz       10MHz       30MHz        100MHz     300MHz       1.0GHz         3.0GHz   10GHz
        V(VINPUT)/ I(Rs)
                                                    Frequency



Problem 16 Compare the results for the matching networks that you designed in the lab (quarter
wave, open and short stub). Which one is a better choice. Why?

Answer:
   - Compare the results for the matching networks that we designed in the lab (quarter wave,
     open and short stub), the quarter wave is the best choice among of these. Because: it has
     the largest Γ bandwidth (the portion of the signal less than 0.2) about 1.102GHz while the
     open and short stub’s are quite less than 1.0GHz. Besides, it also has an input impedance of
     exactly 75 ohms.


Nguyễn Thị Bảo Trâm – 06DT1                                                                            Page 30
Báo cáo TN SIÊU CAO TẦN                                                              Lab3


Problem 17      For stub matching networks compare the performance of an open stub versus a
shorted stub.

Answer:
   - For stub matching networks compare the performance of an open stub versus a shorted
     stub: Γ bandwidth (the portion of the signal less than 0.2) about 0.186GHz and 0.73GHz
     respectively. So the shorted stub circuit is the better one.

Problem 18 Suppose you had a lossless line terminated by a complex load, but wanted to carry
out the match using a quarter-wave transformer. How could you accomplish this?

Answer:

   -   Suppose we had a lossless line terminated by a complex load, but wanted to carry out the
       match using a quarter-wave transformer. To accomplish this we could use a transmission
       line with a complex characteristic impedance.




Nguyễn Thị Bảo Trâm – 06DT1                                                            Page 31

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09 a lab3-nguyen thi bao tram

  • 1. TRƯỜNG ĐẠI HỌC BÁCH KHOA ĐÀ NẴNG KHOA ĐIỆN TỬ – VIỄN THÔNG  BÁO CÁO THÍ NGHIỆM KỸ THUẬT SIÊU CAO TẦN LAB 3: Transients on Transmission Lines Student : Nguyễn Thị Bảo Trâm Group : 09A Class : 06DT1 Đà Nẵng – 2010 dddDDDASARTETE
  • 2. Báo cáo TN SIÊU CAO TẦN Lab3 1. Introduction: We have thus far focused on techniques for understanding transmission lines under sinusoidal excitation. Powerful analytic insight is available here, permitting straightforward design of interesting circuits. In contrast, the analysis of transients is generally more difficult and less amenable to simple closed-form analysis, especially when loads are reactive. This laboratory will explore the propagation of transients on transmission lines with the aid of numerical experiments in SPICE. 2. Purely Resistive Termination: First, let's use SPICE to investigate the propagation of pulses on a transmission line terminated by purely resistive loads. 2.1 A step function, matched load First, create a 50  transmission line with total length (time delay) of 25 ns, and excite it with a Thevenin source 10u(t), with a source resistance Rg = 50  . With the load resistance RL = 50  , run the simulation. Rg T1 Vg Vsource Vload 50 TD = 25ns Vg Z0 = 50 RL 50 0 0 0 0 To create the voltage source, use the VPWL source. Using VPWL allows various times and the voltages at those times to be specified using the T1, T2, T3, ... and V1, V2, V3, ... parameters. The voltage source will be piece-wise linear, connecting each specified point. Using VPULSE allows specification of the initial voltage, V1, the voltage of the pulse, V2, the delay time, TD, the rise time, TR, the fall time, TF, the pulse width, PW, and the period, PER. The VPWL source is piece-wise linear and allows the user to specify voltages at specific times using T1, T2, T3… and the corresponding V1, V2, V3 parameters. Please note that the source will connect each specified point in the most direct way. Additionally, two voltages cannot be specified for the same time, so that instantaneous changes must be approximated. For Example: to specify a VPWL source that produces a 10V square pulse starting at t=0 and lasting for 10 ns, would have the following specified parameters: T1=0, V1=0, T2=0.001n, V2=10, T3=10n, V3=10, T4=10.001n, V4=0. (Making V3=0 would form a sawtooth wave because of the reasons stated above.) Nguyễn Thị Bảo Trâm – 06DT1 Page 2
  • 3. Báo cáo TN SIÊU CAO TẦN Lab3 Using VPULSE allows specification of an initial voltage, V1, the voltage of the pulse, V2, the delay time, TD, the rise time, TR, the fall time, TF, the pulse width, PW, and the period, PER. Single pulses can be formed with this source. More complex signals can be formed by combining multiple sources. Problem 1 Plot the voltage at the source and load ends of the transmission line for t = 0…50 ns. Using your understanding of “bounce diagrams”, explain whether this plot makes sense and shows what you would expect to see in the “exact” answer. Do the two agree? If not, why not? A full credit answer will describe the bounce diagram until a reasonable (whatever you consider reasonable) number of bounces, which can explain what exactly is happening in this situation. Please do the same in any other bounce diagram questions that may follow. Answer: - The voltage at the source and load ends of the transmission line for t = 0…50 ns 10V 5V 0V 0s 5ns 10ns 15ns 20ns 25ns 30ns 35ns 40ns 45ns 50ns V(VG) V(VSOURCE) V(VLOAD) Time The reflection coefficient at the source is: 𝑅 𝑔 − 𝑍0 50 − 50 Γ𝑔 = = =0 𝑅 𝑔 + 𝑍0 50 + 50 The reflection coefficient at the load is: 𝑅 𝐿 − 𝑍0 50 − 50 Γ𝐿 = = =0 𝑅 𝐿 + 𝑍0 50 + 50 ⇒ There is no reflection wave of voltage at the source and the load. 𝑉𝑔 𝑍 𝐿 10 .50 𝑉𝐿 = = = 5(𝑉) 𝑅 𝑔 + 𝑍 𝐿 50 + 50 Nguyễn Thị Bảo Trâm – 06DT1 Page 3
  • 4. Báo cáo TN SIÊU CAO TẦN Lab3 VL = 5 (V) after 25ns (time delay of the transmission line.) ⇒ The theory and the plot are the same. 2.2 A step function, mismatched load Now, change the load impedance in the previous case to 20  . Rg T1 Vg Vsource Vload 50 TD = 25ns Vg Z0 = 50 RL 20 0 0 0 0 Problem 2 Plot the voltage at the source and load ends of the transmission line for t = 0…100 ns. Using your understanding of “bounce diagrams”, compare this with what you would expect to see in the “exact” answer. Do the two agree? If not, why not? How long does it take the answer to settle to the final answer? Answer: - The voltage at the source and load ends of the transmission line for t = 0…100 ns 10V 5V 0V 0s 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns 100ns V(VG) V(VSOURCE) V(VLOAD) Time The reflection coefficient at the source is: 𝑅 𝑔 − 𝑍0 50 − 50 Γ𝑔 = = =0 𝑅 𝑔 + 𝑍0 50 − 50 Nguyễn Thị Bảo Trâm – 06DT1 Page 4
  • 5. Báo cáo TN SIÊU CAO TẦN Lab3 The reflection coefficient at the load is: RL  Z 0 20  50 3 L    RL  Z 0 20  50 7 Vg Z 0 10.50 V1    5(V ) Rg  Z 0 50  50 3 At t = T = 25ns, the wave reaches the load (receiving end) z = l, and because L    0 , the 7 mismatch generates a reflected wave with the amplitude: 15 V1  L .V1   (V) 7 So the voltage on line (in this case, the load voltage) is the sum of two waves: 15 20 VL  V1  V1  5    2.86(V ) 7 7 At t = 2T = 50ns, the wave reaches the sending end z = 0, and because g  0 , there is no reflection wave in form of a wave with voltage amplitude V2+ = 0. Thus, the voltage on line (in this case, the source voltage) is: 15 20 VS  V1  V1  5    2.86(V ) 7 7 3 At t = 3T = 75ns, the wave reaches the load (receiving end) z = l, and because L    0 , the 7 mismatch generates a reflected wave with the amplitude: V2  L .V2  0 (V)  VL = 2.86 (V) Similarly, we also have: VS = 2.86 (V)   g   L z=l z=0 t=0 V1+ T t=0 L V1+ 2T L g V1+ 3T Thus, after 50ns, the voltage at two ends of the transmission line have the same final answers. Nguyễn Thị Bảo Trâm – 06DT1 Page 5
  • 6. Báo cáo TN SIÊU CAO TẦN Lab3 2.3 A step function, mismatched load and source Now, change the load impedance in the previous case to RL=20  , and change the source impedance to Rg=200  . Rg T1 Vg Vsource Vload 200 TD = 25ns Vg Z0 = 50 RL 20 0 0 0 0 Problem 3 Plot the voltage at the source and load ends of the transmission line for t = 0…300 ns. Using your understanding of “bounce diagrams”, compare this to the “exact” answer. Do the two agree? If not, why not? How long does it take the answer to settle down to the final answer? Answer: - The voltage at the source and load ends of the transmission line for t = 0…300 ns 12V 8V 4V 0V 0s 50ns 100ns 150ns 200ns 250ns 300ns V(VG) V(VSOURCE) V(VLOAD) Time Rg  Z 0 200  50 g    0.6 Rg  Z 0 200  50 RL  Z 0 20  50 3 L    RL  Z 0 20  50 7 Nguyễn Thị Bảo Trâm – 06DT1 Page 6
  • 7. Báo cáo TN SIÊU CAO TẦN Lab3 Vg Z 0 10.50 V1    2(V ) Rg  Z 0 200  50 3 At t = T = 25ns, the wave reaches the load (receiving end) z = l, and because L    0 , the 7 mismatch generates a reflected wave with the amplitude: 3 6 V1  L .V1  ( ) .2    0.86 (V) 7 7 So the voltage on line (in this case, the load voltage) is the sum of two waves: 6 8 VL  V1  V1  2    1.14(V ) 7 7 At t = 2T = 50ns, the wave reaches the sending end z = 0, and because g  0.6 , there is a  reflection wave in form of a wave with voltage amplitude V2+ = gV1 . Thus, the voltage on line (in this case, the source voltage) is: VS  V1  V1  V2  (1  L  L  g ).V1  0.63(V ) 3 At t = 3T = 75ns, the wave reaches the load (receiving end) z = l, and because L    0 , the 7 mismatch generates a reflected wave with the amplitude: V2  L .V2 (V)  VL = 0.85 (V)   g   L z=0 V1+ z=l t=0 t=0 T  L V1 + 2T L g V1+ 3T L  2 + g V1 4T L g V1+ 2 2 5T Nguyễn Thị Bảo Trâm – 06DT1 Page 7
  • 8. Báo cáo TN SIÊU CAO TẦN Lab3 Calculate like the process above, we have the table: Time V at sending end V at receiving end t = 0ns Vg Z 0 10.50 VL  0(V ) VS = V1    2(V ) Rg  Z 0 200  50 t = T =25ns Vg Z 0 10.50 6 8 VS = V1    2(V ) VL  V1  V1  2    1.14(V ) Rg  Z 0 200  50 7 7 t = 2T = 50ns VS  V1  V1  V2 6 8 VL  V1  V1  2    1.14(V )  (1  L  L  g ).V1  0.63(V ) 7 7 t = 3T=75ns VS  V1  V1  V2 VL  (1  L  L  g L g ).V1  0.85(V ) 2  (1  L  L  g ).V1  0.63(V ) t = 4T=100ns VS  (1  L  L  g L g  L g ).V1  0.98(V ) L  (1  L  L  g L g ).V1  0.85(V ) 2 2 2 V 2 t = 5T =125ns VS  (1  L  L  g L g 2 VL  (1  L  L  g L g  L g2 2 2  L g2 ).V1  0.98(V ) 2  L g2 ).V1  0.92(V ) 3 T = 6T =150ns VS = 0.98 (V) VL = 0.924(V) T = 7T =175ns VS = 0.89(V) VL = 0.924(V) T = 8T =200ns VS = 0.89(V) VL = 0.909(V) T = 9T =225ns VS = 0.913(V) VL = 0.909(V) - Thus, the plot and the “exact” answer agree. Nguyễn Thị Bảo Trâm – 06DT1 Page 8
  • 9. Báo cáo TN SIÊU CAO TẦN Lab3 Vg Z L 10.20 - The final voltage is: V    0.909(V ) Rg  Z 0 200  20 ⇒ It takes 225ns to settle down to the final answer. 2.4 A short pulse Now break the transmission line into two equal pieces, with total length 25 ns (you should now have two different transmission lines, both with the same 50  characteristic impedance, but each with a time delay of only 12.5 ns). This permits us to sample “inside” the transmission line. With the same transmission line, and Rg=200  and RL=20  apply a pulse of duration 10 ns to the transmission line, namely vg(t) = 10(u(t)- u(t-10ns)). Rg T1 T2 Vg Vsource Vmiddle Vload 200 Vg Z0 = 50 Z0 = 50 TD = 12.5ns TD = 12.5ns RL 20 0 0 0 0 0 0 Problem 4 Plot the voltage at the source, middle, and load ends of the transmission lines for t = 0…100 ns. Sketch the bounce diagram; do you understand the voltage plots? How long before the “ghost” pulse (the pulse you are seeing at the middle of the transmission line) arrives at the load end? How large is the “ghost” pulse? Answer: - The voltage at the source, middle, and load ends of the transmission lines for t = 0…100ns 2.0V 1.0V 0V -1.0V -2.0V 0s 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns 100ns V(VSOURCE) V(VMIDDLE) V(VLOAD) Time Nguyễn Thị Bảo Trâm – 06DT1 Page 9
  • 10. Báo cáo TN SIÊU CAO TẦN Lab3 Rg  Z 0 200  50 g    0.6 Rg  Z 0 200  50 RL  Z 0 20  50 3 L    RL  Z 0 20  50 7 Vg Z 0 10.50 V1    2(V ) Rg  Z 0 200  50 - The bounce diagram:   g   L z l 2 z=0 V1+ z=l t=0 T L V1 + 2T L g V1+ 3T L  2 + g V1 4T L g V1+ 2 2 5T - We have the table of values (by calculating): Time V at sending end V middle V at receiving end t = 0+ ns Vg Z 0 Vm = 0 (V) VL = 0 (V) VS  V1   2(V ) Rg  Z 0 t = T/2 Vg Z 0 0.50 Vm = V1+ (t = 0ns) = VL = 0 (V) =12.5ns VS   0 2(V) Rg  Z 0 200  50 Nguyễn Thị Bảo Trâm – 06DT1 Page 10
  • 11. Báo cáo TN SIÊU CAO TẦN Lab3 t = T = 25ns VS = 0(V) Vm = VS (t = 12.5ns) = VL  V1  V1 0(V) 6 8  2   1.14(V ) 7 7 t = 3T/2 = VS = 0(V) Vm  V1  LV1   VL  Vm  Vm 37.5ns (Vm at t = 2T) 6  0(V )    0.86(V ) 7 t = 2T = 50ns VS  V1  V2 Vm  VL  0(V ) VL = 0 (V)  (L  L  g ).V1  1.37(V ) t = 5T/2 = Vg Z 0 Vm  V2  L gV1 VL = 0 (V) 62.5ns VS  Rg  Z 0 3    0.6  2  0.51(V ) 0.50 7   0(V ) 200  50 t = 3T=75ns VS = 0(V) Vm = VS (t = 12.5ns) = VL  V2  V2 0(V)  (L  g L g ).V1  0.29(V ) 2 t= VS = 0(V) Vm  V2  L gV1 2 VL = 0 (V) 7T/2=82.5ns  0.22(V ) t = 4T =100ns VS  V2  V3 Vm  VL  0(V ) VL = 0 (V)  (L g  L g2 ).V1 2 2  0.35(V ) It takes 12.5ns for the “ghost” pulse to get the load end. The ghost pulse has width of 12.5ns. Nguyễn Thị Bảo Trâm – 06DT1 Page 11
  • 12. Báo cáo TN SIÊU CAO TẦN Lab3 2.5 A longer pulse In the previous problem, the pulse was brief (10 ns) compared to the length of the transmission line (25 ns). Now investigate a more complicated system. Problem 5 Using the same transmission line and source impedance, define a new source for which vg = +10 V for t = 0 … 20 ns, and vg   V for t = 20 … 40ns. Plot the voltage at the source, center, and load end of the transmission line for t = 0…100 ns. Is the transition from “high” to “low” perfectly clear at the load end? Answer: Rg T1 T2 Vg Vsource Vmiddle Vload 200 Vg Z0 = 50 Z0 = 50 TD = 12.5ns TD = 12.5ns RL 20 0 0 0 0 0 0 - The voltage at the source, center, and load end of the transmission line for t = 0…100ns 2.0V 0V -2.0V -4.0V 0s 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns 100ns V(VSOURCE) V(VMIDDLE) V(VLOAD) Time - From the graph, we can see that the transition from high to low is perfectly clear at the load end. 2.6 An Impedance Bump Transmission lines must be protected against damage, or their impedance properties could be compromised. In this section we’ll “damage” the transmission line by putting a weak load in the Nguyễn Thị Bảo Trâm – 06DT1 Page 12
  • 13. Báo cáo TN SIÊU CAO TẦN Lab3 middle. In particular, at the center of the transmission line, add a shunt resistance of 50  (a shunt resistance connects the node at the middle to ground). Rg T1 T2 Vg Vsource Vmiddle Vload 200 Vg Z0 = 50 Z0 = 50 TD = 12.5ns Rshunt TD = 12.5ns RL 50 20 0 0 0 0 0 0 0 Problem 6 With the shunt resistance in place, repeat the previous problem. How did the presence of the “bump” (break in the transition line) affect the voltage plots? Did any new “ghosts” show up? Looking only at the source and end voltages, could you determine where the “bump” is? Can you explain what you see in terms of a bounce diagram? Answer: 2.0V 0V -2.0V -4.0V 0s 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns 100ns V(VSOURCE) V(VMIDDLE) V(VLOAD) Time - The presence of the impedance “bump” (break in the transition line) reduced the magnitude of the middle voltage. 3. Reactive Termination As mentioned in class, it is frequently the case that the loads at the end of a data bus are reactive (and often capacitive). 3.1 A step into a capacitive load Nguyễn Thị Bảo Trâm – 06DT1 Page 13
  • 14. Báo cáo TN SIÊU CAO TẦN Lab3 For this exercise, again form a circuit with a source vg(t) = 10u(t), a source impedance Rg=25  , and a transmission line with characteristic impedance 50  and length 25ns. Rg T1 Vg Vsource Vload 25 Vg TD = 25ns Z0 = 50 CL 0 0 1n 0 0 Problem 7 Terminate the transmission line with a 1nF capacitor. Plot the voltage at the source and load ends of the transmission line for t = 0…400ns. If you see any “exponential” charging or discharging, estimate the time constant, and solve for the R. You may use the following formulas. 15V 10V 5V 0V 0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns V(VSOURCE) V(VLOAD) Time Vinitial = 0V VFinal = 12.133V V(t) = 8.4292V t = (75 – 25) = 50ns Nguyễn Thị Bảo Trâm – 06DT1 Page 14
  • 15. Báo cáo TN SIÊU CAO TẦN Lab3 −𝑡 −50. 10−9 𝜏= = = 4.214. 10−8 𝑉(𝑡) − 𝑉𝑓𝑖𝑛𝑎𝑙 8.4292 − 12.133 𝑙𝑛 𝑉 𝑙𝑛 𝐼𝑛𝑖𝑡𝑖𝑎𝑙 − 𝑉𝑓𝑖𝑛𝑎𝑙 0 − 12.133 𝜏 4.214. 10−8 𝜏 = 𝑅𝐶 ⇒ = 𝑅= = 42.14(Ω) 𝐶 10−9 Problem 8 Repeat the previous problem, but with a load capacitance of 100pF. Rg T1 Vg Vsource Vload 25 Vg TD = 25ns Z0 = 50 CL 0 0 100pF 0 0 15V 10V 5V 0V 0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns V(VSOURCE) V(VLOAD) Time Vinitial = 0V VFinal = 13.33V V(t) = 13.244V t = (50 – 25) = 25ns −𝑡 −25. 10−9 𝜏= = = 4.956. 10−9 𝑉(𝑡) − 𝑉𝑓𝑖𝑛𝑎𝑙 13.244 − 13.33 𝑙𝑛 𝑉 𝑙𝑛 𝐼𝑛𝑖𝑡𝑖𝑎𝑙 − 𝑉𝑓𝑖𝑛𝑎𝑙 0 − 13.33 −9 𝜏 4.956. 10 𝜏 = 𝑅𝐶 ⇒ 𝑅= = = 49.56(Ω) 𝐶 100.10−12 Nguyễn Thị Bảo Trâm – 06DT1 Page 15
  • 16. Báo cáo TN SIÊU CAO TẦN Lab3 Problem 9 Repeat the previous problem, but with a load capacitance of 10nF. Rg T1 Vg Vsource Vload 25 Vg TD = 25ns Z0 = 50 CL 0 0 10nF 0 0 10V 5V 0V 0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns V(VSOURCE) V(VLOAD) Time Vinitial = 0V VFinal = 10V V(t) = 8.056V t = (400 – 25)= 375ns −𝑡 −375. 10−9 𝜏= = = 2.29. 10−7 𝑉(𝑡) − 𝑉𝑓𝑖𝑛𝑎𝑙 8.056 − 10 𝑙𝑛 𝑉 𝑙𝑛 𝐼𝑛𝑖𝑡𝑖𝑎𝑙 − 𝑉𝑓𝑖𝑛𝑎𝑙 0 − 10 −7 𝜏 2.29. 10 𝜏 = 𝑅𝐶 ⇒ 𝑅= = = 22.9(Ω) 𝐶 10.10−9 Problem 10 Repeat the previous problem, but with a load inductance of 2.5μH. Nguyễn Thị Bảo Trâm – 06DT1 Page 16
  • 17. Báo cáo TN SIÊU CAO TẦN Lab3 Rg T1 Vg Vsource Vload 25 1 Vg TD = 25ns Z0 = 50 L 2.5uH 0 0 2 0 0 15V 10V 5V 0V 0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns V(VSOURCE) V(VLOAD) Time Vinitial = 13.202V VFinal = 0V V(t) = 4.8052V t = (75 – 25) = 50ns −𝑡 −50. 10−9 𝜏= = = 4.947. 10−8 𝑉(𝑡) − 𝑉𝑓𝑖𝑛𝑎𝑙 4.8052 − 0 𝑙𝑛 𝑉 𝑙𝑛 13.202 − 0 𝐼𝑛𝑖𝑡𝑖𝑎𝑙 − 𝑉𝑓𝑖𝑛𝑎𝑙 −6 𝑅 𝐿 2.5. 10 𝜏= ⇒ 𝑅= = = 50.53(Ω) 𝐿 𝜏 4.947. 10−8 Problem 11 Repeat the previous problem, but with a load inductance of 0.25μH. Nguyễn Thị Bảo Trâm – 06DT1 Page 17
  • 18. Báo cáo TN SIÊU CAO TẦN Lab3 Rg T1 Vg Vsource Vload 25 1 Vg TD = 25ns Z0 = 50 L 0.25uH 0 0 2 0 0 15V 10V 5V 0V -5V 0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns V(VSOURCE) V(VLOAD) Time Vinitial = 13.3V VFinal = 0V V(t) = 1.51V t = (36 – 25)ns −𝑡 −11. 10−9 𝜏= = = 5.056. 10−9 𝑉(𝑡) − 𝑉𝑓𝑖𝑛𝑎𝑙 1.51 − 0 𝑙𝑛 𝑉 𝑙𝑛 13.3 − 0 𝐼𝑛𝑖𝑡𝑖𝑎𝑙 − 𝑉𝑓𝑖𝑛𝑎𝑙 −6 𝑅 𝐿 0.25. 10 𝜏= ⇒ 𝑅= = = 49.44(Ω) 𝐿 𝜏 5.056. 10−9 Problem 12 Repeat the previous problem, but with a load composed of a parallel combination of RL=1000  , L = 1μH and C = 100pF. Nguyễn Thị Bảo Trâm – 06DT1 Page 18
  • 19. Báo cáo TN SIÊU CAO TẦN Lab3 Rg T1 Vg Vsource Vload 25 1 Vg TD = 25ns RL L C Z0 = 50 1k 1uH 100pF 0 0 2 0 0 10V 5V 0V -5V 0s 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns V(VSOURCE) V(VLOAD) Time Problem 13 How important is the value of Rg in these exercises? Answer: - R is very important since it allows the system to reach steady state. The value of R helps us g g to determine whether the circuit is matched or not at the input of transmission line. 4. Coupling Many data buses are in parallel, in close proximity, such as the 32 bit and 64 bit buses found in computers. These transmission lines will have “mutual impedance” which causes signals on one transmission line to show up on another one. In EE571 students analyze this coupling in great detail, but we can simulate a simplified model of a two-wire data bus using SPICE1: 1 Note that your SPICE library contains a model for coupled lines; you could use this, but it does the modeling with an explicit form of the Telegrapher’s Equation, and is painfully slow. I tried to use it, but realized that it would take about one day to run every simulation! Nguyễn Thị Bảo Trâm – 06DT1 Page 19
  • 20. Báo cáo TN SIÊU CAO TẦN Lab3 Here T1 and T4 represent the “actual” transmission lines, while T2 and T3 represent the cross coupling. The coupling is slightly faster (95 ns instead of 100 ns) and has a higher characteristic impedance. Connect a Thevenin signal pulse (10 V, 50  ) to A and 50  loads to B, C and D2. Z0 = 50 TD = 100ns T1 A C R1 R3 50 0 0 Vg Z0 = 200 50 Vg TD = 95ns T2 0 0 0 0 Z0 = 200 TD = 95ns T3 0 0 Z0 = 50 TD = 100ns T4 B D R4 R2 50 50 0 0 0 0 2 To make this model even closer to the real thing, the signal injected into T2 should have opposite sign of that injected into T1. However, this lab will not require this. Nguyễn Thị Bảo Trâm – 06DT1 Page 20
  • 21. Báo cáo TN SIÊU CAO TẦN Lab3 4.1 A simple pulse Inject a 10ns pulse with the Thevenin source at A. Use a rise and fall time of 1ns. Problem 14 Simulate the problem for 250 ns, and plot the voltage at A, B, C, and D. Describe what you observe. How big is the VC compared to VD when the pulse arrives? Which arrives first? Answer: - Plot the voltage at A, B, C, and D 10V 5V 0V -5V 0s 50ns 100ns 150ns 200ns 250ns V(VG) V(A) V(B) V(C) V(D) Time - V is about 4 times compared to the magnitude of V when the pulse arrives. C D - V arrives first. D Problem 15 When does a signal arrive at B? If you change the values of the load resistances at C and D, can you eliminate the reflection? If so what value should the load have? Answer: - A signal arrives at B at 195ns. - We cannot eliminate the reflection by changing the values of the load resistances at C and D. We just can reduce VC and VD to zero. - The plot when the load resistances at C and D are 0.001Ω: Nguyễn Thị Bảo Trâm – 06DT1 Page 21
  • 22. Báo cáo TN SIÊU CAO TẦN Lab3 10V 5V 0V -5V 0s 50ns 100ns 150ns 200ns 250ns V(VG) V(A) V(B) V(C) V(D) Time 5. Impedance Matching 5.1. Pre-lab Assignment 5.1. A. Design a quarter-wave transformer to match a 150 Ω load to a source resistance of 75 Ω. State the length of your transmission line(s) in terms of the wavelength. Answer: 𝑍 𝐿 = 150Ω 𝑍 𝑖𝑛 = 75Ω The input impedance is: ZL + jZ0 tgβl 𝑍 𝑖𝑛 = Z0 Z0 + jZL tgβl 𝜆 2𝜋 𝜆 𝜋 With 𝑙 = 4 ⇒ 𝛽𝑙 = . 𝜆 4 = 2 π We can divide the numerator and the denominator by tgβl and take the limit as βl → to get: 2 𝑍0 2 𝑍 𝑖𝑛 = 𝑍𝐿 The characteristic impedance of the matching section is: ⇒ 𝑍0 = 𝑍 𝐿. 𝑍 𝑖𝑛 = 150.75 = 106.066(Ω) Nguyễn Thị Bảo Trâm – 06DT1 Page 22
  • 23. Báo cáo TN SIÊU CAO TẦN Lab3 5.1. B. Using the Smith Chart, if the characteristic impedance is given as 75 Ω, design a stub- matching network to match a 150 Ω load to a 75 Ω source. Do this for both a shorted and an open circuited stub. State the length of your transmission line(s) in terms of wavelength. Answer: 𝑍0 = 75Ω 𝑍 𝑖𝑛 = 75Ω 𝑍 𝐿 = 150Ω ZL 150 - The normalized load impedance is: 𝑧 𝐿 = = = 2Ω (point A on the Smith chart) Z0 75 - Construct the appropriate SWR circle through point A. From the Smith chart, the normal load admittance: yL = 0.5 (at point B l  0  ) - The SWR circle intersects the 1+jb circle at two points, denoted as y1 , y2. Thus the distance d, from the load to the stub, is given by either of these two intersections. Reading the WTG scale, we obtain: d2 = (0.348– 0)  = 0.348  At the two intersection points, the normalized admittances are: y1 = 1 + j0.7 y2 = 1 – j0.7 - Thus, the first tuning solution requires a stub with a susceptance of – j0.7. The length of an open-circuited stub that gives this susceptance can be found on Smith chart by starting at y = 0 (the open circuit) and moving along the outer edge of the chart (g=0) toward the generator to the – j0.7 point. The length is then: lo1= 0.402  Similarly, the required open-circuited stub length for the second solution is: lo2= 0.097  - The length of an shorted-circuited stub that gives this susceptance can be found on Smith chart by starting at y = ∞ (the shorted circuit) and moving along the outer edge of the chart (g=0) toward the generator to the – j0.7 point. The length is then: ls1=(0.402 – 0.25)  = 0.152  Similarly, the required shorted-circuited stub length for the second solution is: ls2= (0.25 + 0.097)  = 0.347  5.2. Lab Assignment 5.2.A. Find the actual length of the quarter-wave matching network you designed in part 5.1.A if up = 2E+8 (m/s) and frequency = 1 GHz. Simulate the frequency response of the circuit by sweeping the frequency from 1 MHz to 3 GHz using a 5Vpp sine wave source with a source resistance of 75 Ω. Plot the input and load voltage over frequency. Plot the magnitude of the reflection coefficient of Nguyễn Thị Bảo Trâm – 06DT1 Page 23
  • 24. Báo cáo TN SIÊU CAO TẦN Lab3 the matching network and find the bandwidth where |Γ| is less than 0.2. What is the input impedance of the matching network at 1 GHz? Answer: m up = 2.108 ; f = 1GHz s 2.108 up    0.2(m) f 10 9  0.2 l   0.05 (m) 4 4 l 0.05 m TD   8  2.5.10 10 ( s)  0.25ns u p 2.10 m / s Rs T1 Vinput Vload 75 Vs 2.5Vac TD = 0.25ns RL 0Vdc Z0 = 106.066 150 0 0 0 0 - The input and load voltage over frequency: Nguyễn Thị Bảo Trâm – 06DT1 Page 24
  • 25. Báo cáo TN SIÊU CAO TẦN Lab3 1.8V 1.6V 1.4V 1.2V 1.0MHz 3.0MHz 10MHz 30MHz 100MHz 300MHz 1.0GHz 3.0GHz 10GHz V(VINPUT) V(VLOAD) Frequency - The magnitude of the reflection coefficient of the matching network: 400m 300m 200m 100m 0 1.0MHz 3.0MHz 10MHz 30MHz 100MHz 300MHz 1.0GHz 3.0GHz 10GHz (V(VINPUT)/ I(Rs)-75)/(V(VINPUT)/I(Rs)+75) Frequency |Γ| is less than 0.2 from 608.1 MHz to 1.388 GHz and frequencies from 2.607 GHz to 3 GHz - The input impedance of the matching network at 1 GHz is 75Ω. Nguyễn Thị Bảo Trâm – 06DT1 Page 25
  • 26. Báo cáo TN SIÊU CAO TẦN Lab3 150 100 (1.0000G,75.000) 50 1.0MHz 3.0MHz 10MHz 30MHz 100MHz 300MHz 1.0GHz 3.0GHz 10GHz V(VINPUT)/ I(Rs) Frequency 5.2.B. Using the assumptions of section 5.2.A, simulate your pre-lab design in part 5.1.B and find the Γ bandwidth (the portion of the signal less than 0.2) of the matching network as well as the input impedance at 1 GHz. Include the same plots as in section 5.2.A. Answer: m up = 2.108 ; f = 1GHz s up 2.108    0.2(m) f 10 9 d1 0.0304 m d1 =0.152𝜆 = 0.152×0.2 = 0.0304 (m) ⇒ TD    1.52.10 10 ( s)  0.152ns u p 2.108 m / s l o1 0.0804 m lo1= 0.402𝜆 = 0.402×0.2 = 0.0804 (m) ⇒ TD    4.02.10 10 ( s)  0.402ns u p 2.108 m / s l s1 0.0304 m ls1=0.152𝜆 = 0.152×0.2 = 0.0304 (m) ⇒ TD    1.52.10 10 ( s)  0.152ns u p 2.108 m / s  Open-circuited stub: Nguyễn Thị Bảo Trâm – 06DT1 Page 26
  • 27. Báo cáo TN SIÊU CAO TẦN Lab3 Rs T1 Vinput Vload 75 Vs 2.5Vac TD = 0.152ns RL 0Vdc Z0 = 75 150 0 0 T2 0 0 TD = 0.402ns R1 Z0 = 75 1000G 0 0 0 - The input and load voltage over frequency: 2.0V 1.5V 1.0V 0.5V 0V 1.0MHz 3.0MHz 10MHz 30MHz 100MHz 300MHz 1.0GHz 3.0GHz 10GHz V(VINPUT) V(VLOAD) Frequency - The magnitude of the reflection coefficient of the matching network: |Γ| is less than 0.2 from 924 MHz to 1.11 GHz. Nguyễn Thị Bảo Trâm – 06DT1 Page 27
  • 28. Báo cáo TN SIÊU CAO TẦN Lab3 1.0 0.5 0 1.0MHz 3.0MHz 10MHz 30MHz 100MHz 300MHz 1.0GHz 3.0GHz 10GHz (V(VINPUT)/I(Rs)-75)/(V(VINPUT)/I(Rs)+75) Frequency - The input impedance of the matching network at 1 GHz is 75.029Ω. 150 100 (1.0000G,75.029) 50 0 1.0MHz 3.0MHz 10MHz 30MHz 100MHz 300MHz 1.0GHz 3.0GHz 10GHz V(VINPUT)/ I(Rs) Frequency  Shorted-circuited stub: Nguyễn Thị Bảo Trâm – 06DT1 Page 28
  • 29. Báo cáo TN SIÊU CAO TẦN Lab3 Rs T1 Vinput Vload 75 Vs 2.5Vac TD = 0.152ns RL 0Vdc Z0 = 75 150 0 0 T2 0 0 TD = 0.152ns Z0 = 75 0 0 0 - The input and load voltage over frequency: 2.0V 1.5V 1.0V 0.5V 0V 1.0MHz 3.0MHz 10MHz 30MHz 100MHz 300MHz 1.0GHz 3.0GHz 10GHz V(VINPUT) V(VLOAD) Frequency - The magnitude of the reflection coefficient of the matching network: Nguyễn Thị Bảo Trâm – 06DT1 Page 29
  • 30. Báo cáo TN SIÊU CAO TẦN Lab3 |Γ| is less than 0.2 from 850 MHz to 1.21 GHz and from 2.07 GHz to 2.44 GHz 1.0 0.5 0 1.0MHz 3.0MHz 10MHz 30MHz 100MHz 300MHz 1.0GHz 3.0GHz 10GHz (V(VINPUT)/I(Rs)-75)/(V(VINPUT)/I(Rs)+75) Frequency - The input impedance of the matching network at 1 GHz is 75.029Ω. 100 (1.0000G,75.029) 50 0 1.0MHz 3.0MHz 10MHz 30MHz 100MHz 300MHz 1.0GHz 3.0GHz 10GHz V(VINPUT)/ I(Rs) Frequency Problem 16 Compare the results for the matching networks that you designed in the lab (quarter wave, open and short stub). Which one is a better choice. Why? Answer: - Compare the results for the matching networks that we designed in the lab (quarter wave, open and short stub), the quarter wave is the best choice among of these. Because: it has the largest Γ bandwidth (the portion of the signal less than 0.2) about 1.102GHz while the open and short stub’s are quite less than 1.0GHz. Besides, it also has an input impedance of exactly 75 ohms. Nguyễn Thị Bảo Trâm – 06DT1 Page 30
  • 31. Báo cáo TN SIÊU CAO TẦN Lab3 Problem 17 For stub matching networks compare the performance of an open stub versus a shorted stub. Answer: - For stub matching networks compare the performance of an open stub versus a shorted stub: Γ bandwidth (the portion of the signal less than 0.2) about 0.186GHz and 0.73GHz respectively. So the shorted stub circuit is the better one. Problem 18 Suppose you had a lossless line terminated by a complex load, but wanted to carry out the match using a quarter-wave transformer. How could you accomplish this? Answer: - Suppose we had a lossless line terminated by a complex load, but wanted to carry out the match using a quarter-wave transformer. To accomplish this we could use a transmission line with a complex characteristic impedance. Nguyễn Thị Bảo Trâm – 06DT1 Page 31