Some architectures support the ‘memory indirect’ addressing mode. Below is an example. In this case, the register R3 contains a pointer to a pointer. Two memory accesses are required to load the data. ADD R1, @(R3) The MIPS CPU doesn’t support this addressing mode. Write a MIPS code that’s equivalent to the instruction above. The pointer-to-pointer is in register $t3. The other data is in register $t1. Solution LW &t2,o(&t1) ; t2=*t1; LW &t3,o($t2) ; t3=**t1; ADD $t3,$t4.

1. Some architectures support the ‘memory indirect’ addressing mode. Below is an example. In this
case, the register R3 contains a pointer to a pointer. Two memory accesses are required to load
the data. ADD R1, @(R3) The MIPS CPU doesn’t support this addressing mode. Write a MIPS
code that’s equivalent to the instruction above. The pointer-to-pointer is in register $t3. The other
data is in register $t1.
Solution
LW &t2,o(&t1) ; t2=*t1;
LW &t3,o($t2) ; t3=**t1;
ADD $t3,$t4