The i2C-MS core is a controller for the Inter-Integrated Circuit (I2C) bus. Lattice Semiconductor's general-purpose i2c slave IP provides device addressing, read/write operation and an acknowledgement mechanism. To know more visit us at https://www.digitalblocks.com/i2c-ip-core-reference-design/

1. I2C
Master IP

2. ABOUT US
Digital Blocks adheres to industry standard
processes as well as internally developed
processes that guide our IP Core market
definition, documentation, RTL micro-
architecture design, Verilog / VHDL RTL
design, and verification activities, which
include linting, clock domain crossing
analysis, and comprehensive simulation with
results checking.

3. i2C Master IP
The i2C-MS core is a controller for the
Inter-Integrated Circuit (I2C) bus. Lattice
Semiconductor's general-purpose i2c
slave IP provides device addressing,
read/write operation and an
acknowledgement mechanism. To know
more visit us at
https://www.digitalblocks.com/i2c-ip-
core-reference-design/

4. Contact us
201-251-1281
https://www.digitalblocks.com/
Digital Blocks, Inc. PO Box 192, 587 Rock Rd, Glen Rock, NJ 07452
USA
digitalblocksinc09@gmail.com