To completely off-load the I2C transfers from the CPU, the I2C slave Controller IP Cores have the Slave function from the Master/Slave releases, with parameterized FIFO, I2C Slave Control Unit, and Interrupt Controller. A reduced VLSI footprint is provided by the I2C Slave Controller IP. To know more visit us at https://www.digitalblocks.com/i2c-ip-core-reference-design/

1. I2CSlaveIP

2. AboutUs:-
Digital Blocks adheres to industry standard processes
as well as internally developed processes that guide our
IP Core market definition, documentation, RTL micro-
architecture design, Verilog / VHDL RTL design, and
verification activities, which include linting, clock
domain crossing analysis, and comprehensive simulation
with results checking.

3. I2CSlaveIP
To completely off-load the I2C
transfers from the CPU, the I2C slave
Controller IP Cores have the Slave
function from the Master/Slave
releases, with parameterized FIFO, I2C
Slave Control Unit, and Interrupt
Controller. A reduced VLSI footprint is
provided by the I2C Slave Controller IP.

4. Digital Blocks, Inc. PO Box 192, 587 Rock Rd
Glen Rock, NJ 07452 USA
201-251-1281
info@digitalblocks.com
https://www.digitalblocks.com/