The AXI DMA scatter gather controller has an interrupt controller, optional data parity generator and checker, per channel finite state control, single- or dual-clock FIFOs (parameterized in depth and width), and scatter-gather functionality. Get more details about us from https://www.digitalblocks.com/dma/

1. AXI DMA Scatter Gather

2. About Us:-
Digital Blocks adheres to industry standard processes as well
as internally developed processes that guide our IP Core
market definition, documentation, RTL micro-architecture
design, Verilog / VHDL RTL design, and verification activities,
which include linting, clock domain crossing analysis, and
comprehensive simulation with results checking.

3. The AXI DMA scatter gather controller has an interrupt controller,
optional data parity generator and checker, per channel finite state
control, single- or dual-clock FIFOs (parameterized in depth and
width), and scatter-gather functionality.
AXI DMA Scatter Gather

4. Digital Blocks, Inc. PO Box 192, 587 Rock Rd,
Glen Rock, NJ 07452 USA
201-251-1281
digitalblocksinc09@gmail.com
https://www.digitalblocks.com/