INTERNSHIP_PTTX_1066.pptx

INTERNSHIP PROGRAM
PRESENTATION
TRAINING ON-VLSI DESIGN AND VERIFICATION
Started on:-03-JUN-2022 to Ended on:-18-JUN-20212
Friday, June 30, 2023
1
Electronics & Communication Engineering
Name: GOLLA PAVAN SAI
Reg No: URK20EC1066
UNDER THE SUPERVISION OF
NEPOLEAN MANI
Project Leader
H

Contents
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 Objective
 Introduction
 Overview of Training
 Software Tools
 Project Details
 Result
 Skills Acquired (Software)
 Discussion & Conclusion
 References
Department of Electronics & Communication Engineering

Objective
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 XILINX VIVADO is a software suite produced by Xilinx for synthesis and analysis
of HDL designs, superseding Xilinx ISE with additional features for system on a
chip development and high-level synthesis.
 Vivado also introduces high-level synthesis, with a toolchain that converts C code into
programmable logic.
 In this laboratory session, we learned how to use some of the basic VERILOG functions and
how to display output in graphical form.
 The output came from analyzing codes as well as from examining the frequency response .
 In addition, it is used to program FPGAs.

Introduction
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 XILINX VIVADO is a software package for high-performance mathematical computation,
visualization, and programming environment. It provides an interactive environment with
hundreds of built-in functions for technical computing, graphics, and animations.
 Xilinx's new Vivado Design Suite addressed this issue, because the software was developed
for higher capacity FPGAs
 Xilinx Vivado is a programming language environment, and it has refined data structures,
included built-in editing and debugged tools, and supports object-oriented programming.

Overview of Training
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 VerilogHDL:
In the semiconductor and electronic design industry,
Verilog is a hardware description language(HDL)used to model electronic systems.
Verilog HDL, not to be confused with VHDL (a competing language), is most
commonly used in the design, verification, and implementation of digital logic chips at
the register- transfer level of abstraction.
It is also used in the verification of analog and mixed-signal circuits. A Verilog design
consists of a hierarchy of modules. Modules encapsulate design hierarchy, and
communicate with other modules through a set of declared input, output, and
bidirectional ports. Internally, a module can contain any combination of the following:
net/variable declarations (wire, reg,integer,etc.), concurrent and sequential statement
blocks, and instances of other modules (sub-hierarchies).

Overview of Training
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 Hardware description languages such as Verilog differ from software programming
languages because they includeways of describing the propagation of time and
signal dependencies (sensitivity).
 Two assignment operators,a blocking assignment(=),anda non-blocking (<=)
assignment. The non-blocking assignment allows designers to describe a state-
machine update without needing to declare and use temporary storage variables.
 Since these concepts are part of Verilog's language semantics, designers could
quickly write descriptions of large circuits in a relatively compact and concise
form. At the time of Verilog's introduction (1984), Verilog represented a
tremendous productivity improvement for circuit designers who were already using
graphical schematic capture software and specially written software programs to
document and simulate electronic circuits.

Software Tools
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 XILINX VIVADO

Project Details
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A clock in verilog with Alarm
We are generating a clock with 7 output signals including Alarm signal, Hour, Minute, and seconds. All
the signals are discussed in detail further. The clock generated is in a 24 - hour format. We can give an
initial time value to the system when reset signal=1 or by turning the signal LD_time=1.
You can further set the alarm time by turning LD_alarm=1. The alarm is enabled or disabled using the
input AL_ON. The alarm rings only if AL_ON is 1.
STOP_al signal is used to stop the alarm. The input clock given as input is 10Hz. We have generated a
clk with time period 1 second from this input clock and used it to increment seconds and further minutes
and hours.
Input Signals: reset : Active high reset pulse, to set the time to the input hour and minute (as defined by
the H_in1, H_in0, M_in1, and M_in0 inputs) and the second to 00.
 It should also set the alarm value to 0.00.00, and to set the Alarm (output) low.For normal operation, this
input pin should be 0

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Source code Retinopathy

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 CODE EXPLANATION :
clk : A 10Hz input clock. This should be used to generate each real-time second H_in1 : A
2-bit input used to set the most significant hour digit of the clock (if LD_time=1),or the most
significant hour digit of the alarm (if LD_alarm=1). Valid values are 0 to 2.
H_in0 : A 4-bit input used to set the least significant hour digit of the clock (if LD_time=1)
or the least significant hour digit of the alarm (if LD_alarm=1). Valid values are 0 to 9.
M_in1 : A 4-bit input used to set the most significant minute digit of the clock (if
LD_time=1),or the most significant minute digit of the alarm (if LD_alarm=1). Valid values
are 0 to 5.
M_in0 : A 4-bit input used to set the least significant minute digit of the clock (if
LD_time=1),or the least significant minute digit of the alarm (if LD_alarm=1). Valid values
are 0 to 9.
LD_time : If LD_time=1, the time should be set to the values on the inputs H_in1, H_in0,
M_in1, and M_in0. The second time should be set to 0.If LD_time=0, the clock should act
normally (i.e. second should be incremented every 10 clock cycles).

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LD_alarm : If LD_alarm=1, the alarm time should be set to the values on the inputs H_in1,
H_in0, M_in1, and M_in0.If LD_alarm=0, the clock should act normally.
STOP_al : If the Alarm (output) is high, then STOP_al=1 will bring the output back low.
AL_ON : If high, the alarm is ON (and Alarm will go high if the alarm time equals the real
time). If low the the alarm function is OFF.
Output Signals:
Alarm : This will go high if the alarm time equals the current time, and AL_ON is high.
This will remain high, until STOP_al goes high, which will bring Alarm back low.
H_out1 : The most significant digit of the hour. Valid values are 0 to 2.
H_out0 : The least significant digit of the hour. Valid values are 0 to 9.
M_out1 : The most significant digit of the minute. Valid values are 0 to 5.
M_out0 : The least significant digit of the minute. Valid values are 0 to 9.
S_out1 : The most significant digit of the minute. Valid values are 0 to 5.

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S_out0 : The least significant digit of the minute. Valid values are 0 to 9.
Internal Signals: clk_1s : 1-s
clock
17tmp_1s : count for creating 1-s clock
 tmp_hour, tmp_minute, tmp_second : counter for clock hour, minute and second c_hour1,a_hour1 :
The most significant hour digit of the temp clock and alarm.
c_hour0,a_hour0 : The least significant hour digit of the temp clock and alarm. c_min1,a_min1 :
The most significant minute digit of the temp clock and alarm. c_min0,a_min0 : The least
significant minute digit of the temp clock and alarm. c_sec1,a_sec1 : The most significant second
digit of the temp clock and alarm.
c_sec0,a_sec0 : The least significant minute digit of the temp clock and alarm.
);

Result
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Result
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Skills Acquired (Software)
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• Implement and test your algorithms easily.
• Develop the computational codes easily.
• Debug easily.

Discussion & Conclusion
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I acknowledge my gratitude and thank to all the well
knowledge persons for giving me opportunity to
avail all the best facilities available at this
technologic through which I have gained knowledge
thinking so as too just in the environment suitable for
harmonic adjustment. I am grateful to the following
persons for various help rendered by them during the
training period

References
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• IEEE Standard for System Verilog— Unified Hardware Design, Specification, and
Verification Language.
• Quick Reference for Verilog HDL by Rajeev Madhavan.
• Verilog HDL (A guide to digital design and synthesis) by Samir Palnitkar. • SV
Testbench Architecture: https://www.edaplayground.com/x/BvMQ
• Reference Websites: - testbench.in, verificationguide.com, chipverify.com

INTERNSHIP_PTTX_1066.pptx

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