Using altera signal tap embedded fpga logic ananlyzer

1. Using Altera Signal tap
Embedded Logic Analyzer
Rafe Husain
Thinkom

2. Introduction
This PPT will walk you through process of using Altera Signal Tap
embedded logic analyzer
1. Open/restore archived Quartus project
2. Add signal tap analyzer
3. Set up clocking
4. Set up signals to be monitored
5. Set up trigger
6. Update and build
7. Run, Rinse and Repeat

3. 1. Open/restore archived Quartus project
• Goto Project/Restore
Archive project

4. 1. Open/restore archived Quartus project
• Select src/destination
• This will unzip the sample project and create a new project

5. 2. Add signal tap analyzer
• Goto Tools/Signal Tap II Logic analyzer

6. 3. Set up clocking
• The Analyzer needs a high speed clock
• Search the netlist and select a high speed clock, 100mhz+
• Click on clock module … (triple dot)

7. 3. Set up clocking
• Search for clock
• Select filter as design entry
• Set * as Named
• Click on list

8. 3. Set up clocking
• The list will show top level signals
• The clock we want is in master_timing so click on master_timing
• Select clock_400 and click
it over to right side
• Click ok

9. 3. Set up clocking
• Back in main analyzer menu clk400 should be set

10. 4. Set up signals to be monitored
• Click on setup in main analyzer menu

11. 4. Set up signals to be monitored
• Double click on add nodes

12. 4. Set up signals to be monitored
• Set filter to Design entry
• Set Named to *
• Click on list button

13. 4. Set up signals to be monitored
• Select Signals to be monitored by highlighting
• Then click single arrow
in center to move the
signals left
4. Set up signals to be monitored

14. 4. Set up signals to be monitored
• Select all the signal on the left and then click on insert

15. 5. Set up trigger
• Right click on
trigger signal
(EMIF_CS for
example)
• On drop down
menu select 0
Low condition

16. 5. Set up trigger
• Trigger setup
shows Basic AND
with EMIF_CS as 0

17. 6. Update and build
• Once, clock signals and trig are finished
• Use File save to save fpga setup
• Then need final build to
update Logic analyzer
gates inside FPGA.
• Click on start button to
recompile. May take some
time.

18. 7. Run, Rinse and Repeat
• Make sure the Jtag Chain config says Jtag ready
• Hardware is correct
• And device matches
• If any issues go thru
setup and re-scan

19. 7. Run, Rinse and Repeat
• Program FPGA with new fpga code (click on Program button)

20. 7. Run, Rinse and Repeat
• Highlight instance
and click on run
analysis
• Or click on auto
run (round arrow)
to run
continuously

21. 7. Run, Rinse and Repeat
• Run sequence
to cause
trigger
• In this case an
EMIF_CS=0
read
Transaction

22. 7. Run, Rinse and Repeat
• Repeat adding different sequences
• If need to modify trigger
for example EMIF_WS
go to setup and set
EMIF_WS=0 (step 5)
• If need more pins go to
setup and add pins
(step 4)
• May need to recompile

23. 7. Run, Rinse and Repeat
• Results of Modified
trigger
• EMIF_WE=0

24. Summary
There are other options to change size of analyzer memory and have
more complex triggers. Options can be explored as needed.
References
1. VHDL: SignalTap II with VHDL Design
2. Youtube: 8 minute video https://www.youtube.com/watch?v=vhkzxCEXuaA
3. Online course: (about 2 Hrs.) https://www.altera.com/support/training/course.html?courseCode=ODSW1164
4. SignalTap handbook: Design Debugging Using the SignalTap II Logic Analyzer
5. Quartus help: Setting up the SignalTap II Logic Analyzer – Quartus Help