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Integrated Inductors Modeling for Library Development
                and Layout Generation
   J.R. Sendra, J. del Pino, A. Hernández, B. González, J. García, A. García-Alonso and A. Nuñez
                                                                                               	

                     Dep. Ingeniería Electrónica y Automática / Instituto Universitario de Microelectrónica Aplicada (IUMA), Universidad de Las Palmas de Gran Canaria, Spain.




                   Publicated in Analog Integrated Circuits and Signal Processing
                                         vol. 35, pp. 121-132
                                                 2003.

                                                                                      Abstract
In this work we propose a modification to the conventional lumped equivalent circuit model for integrated inductors. Also the
widely used parametric model is modified. The proposed models expand the frequency range where the integrated inductor
behavior is accurately predicted. They are useful in developing automatic tools to assist the designers in selecting and
automatically laying-out integrated inductors [1]. This work is based on measurements from integrated inductors fabricated in a
standard silicon process.
.

                         Inductor Modelling	

                                                                 Measurements & Simulations




                                                                                                 Fig. 2. Measured (circles) and computed (lines)     Fig. 5. Real (solid circles) and imaginary (open
                                                                                                 real (solid circles) and imaginary (open circles)   circles) parts of the main branch admittance vs.
                                                                                                 parts of the input-to-ground branch admittance      frequency and the result obtained with the
                                                                                                 against frequency.                                  modified model. Lines are modeled values.




       Fig. 1. Two ports conventional equivalent integrated inductor circuit model.




                                              0



                                                                                                    Fig. 3. Real (solid circles) and imaginary
                                                                                                                                                       Fig. 9. Normalized resistance (R S /R DC )
                                                                                                    (open circles) parts of the main branch
                                                                                                                                                       against frequency for an integrated
                                                                                                    admittance vs. frequency and the result
                                                                                                                                                       inductor with w/t = 6. Hollow circles
                                                                                                    obtained with the conventional model. Lines
                                                                                                                                                       represent simulation results; solid line
                                                                                                    are modeled values.
                                                                                                                                                       represents the proposed model. σ = 3.54 ·
                                                                                                                                                       107 S/m.


 Fig. 8. Integrated inductor layout showing the terminals and . Modified two ports integrated
 inductor model with more components (non-physically based).


                                                                                                                                       Conclusions
                                                                                                  In this paper we report our work in modeling spiral-integrated inductors
                                                                                                  based on measurements taken from integrated inductors on a standard
                                                                                                  silicon technology. These models extend the application of the
                                                                                                  conventional model being wide band models: inductor behavior is
                                                                                                  represented in a wide frequency range. Also a parametric model based
                                                                                                  on the existing literature is reported. The extracted models are valid up
                                                                                                  to 10 GHz with a maximum error in the quality factor estimation smaller
                                                                                                  than 10% in all studied cases, while the parametric model may
                                                                                                  introduce greater errors (we have measured up to a 15–20%). Different
                                                                                                  CAD tools to assist the designs in de- signing and automatically laying-
                                                                                                  out integrated inductors are also reported. The desired inductance and
                                                                                                  the operating frequency are given to the tool as inputs and the result is
                                                                                                  the integrated inductors fitting the requirements, the lumped equivalent
                                                                                                  model so as the layout. These programs reduce the design time
                                                                                                  needed to meet RF circuit constraints.
                              Fig. 11. Automatic layout generator.



                                                  INSTITUTO UNIVERSITARIO DE MICROELECTRÓNICA APLICADA (IUMA)
                                                       UNIVERSIDAD DE LAS PALMAS DE GRAN CANARIA (ULPGC)

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Integrated Inductors Modeling for Library Development and Layout Generation

  • 1. Integrated Inductors Modeling for Library Development and Layout Generation J.R. Sendra, J. del Pino, A. Hernández, B. González, J. García, A. García-Alonso and A. Nuñez Dep. Ingeniería Electrónica y Automática / Instituto Universitario de Microelectrónica Aplicada (IUMA), Universidad de Las Palmas de Gran Canaria, Spain. Publicated in Analog Integrated Circuits and Signal Processing vol. 35, pp. 121-132 2003. Abstract In this work we propose a modification to the conventional lumped equivalent circuit model for integrated inductors. Also the widely used parametric model is modified. The proposed models expand the frequency range where the integrated inductor behavior is accurately predicted. They are useful in developing automatic tools to assist the designers in selecting and automatically laying-out integrated inductors [1]. This work is based on measurements from integrated inductors fabricated in a standard silicon process. . Inductor Modelling Measurements & Simulations Fig. 2. Measured (circles) and computed (lines) Fig. 5. Real (solid circles) and imaginary (open real (solid circles) and imaginary (open circles) circles) parts of the main branch admittance vs. parts of the input-to-ground branch admittance frequency and the result obtained with the against frequency. modified model. Lines are modeled values. Fig. 1. Two ports conventional equivalent integrated inductor circuit model. 0 Fig. 3. Real (solid circles) and imaginary Fig. 9. Normalized resistance (R S /R DC ) (open circles) parts of the main branch against frequency for an integrated admittance vs. frequency and the result inductor with w/t = 6. Hollow circles obtained with the conventional model. Lines represent simulation results; solid line are modeled values. represents the proposed model. σ = 3.54 · 107 S/m. Fig. 8. Integrated inductor layout showing the terminals and . Modified two ports integrated inductor model with more components (non-physically based). Conclusions In this paper we report our work in modeling spiral-integrated inductors based on measurements taken from integrated inductors on a standard silicon technology. These models extend the application of the conventional model being wide band models: inductor behavior is represented in a wide frequency range. Also a parametric model based on the existing literature is reported. The extracted models are valid up to 10 GHz with a maximum error in the quality factor estimation smaller than 10% in all studied cases, while the parametric model may introduce greater errors (we have measured up to a 15–20%). Different CAD tools to assist the designs in de- signing and automatically laying- out integrated inductors are also reported. The desired inductance and the operating frequency are given to the tool as inputs and the result is the integrated inductors fitting the requirements, the lumped equivalent model so as the layout. These programs reduce the design time needed to meet RF circuit constraints. Fig. 11. Automatic layout generator. INSTITUTO UNIVERSITARIO DE MICROELECTRÓNICA APLICADA (IUMA) UNIVERSIDAD DE LAS PALMAS DE GRAN CANARIA (ULPGC)