We have included System-on-a-chip as a part of our course and we provide training from Silicon to Chips.

1. OBJECT AUTOMATION Software Solutions Pvt Ltd
No.1, Nehru Street, Second Floor,
Kooturavu Nagar, Adambakkam, Chennai – 600 088
Email id – hr@object-automation.comPhone:044 4335 6149
www.object-automation.com
Module 1: RTL Coding using Verilog HDL
 Introduction to HDLs
 Basic constructs
 Syntax
 Modeling styles
 Combinational circuit design
 Sequential circuit design
 Finite state machine design
 Digital system design
 Simulation & Synthesis issues
 Unwanted Latches
 Clock-gating
 Clock-domain crossing issues
 Low power techniques
 RTL Design strategies
Module 2 : Functional Verification using Verilog HDL
 Delay Concepts
 Tasks & Functions
 Stimulus generation
 Race conditions
 File IO Operations
 Miscellaneous constructs
 System tasks
 Compiler Directives
 Verification Process
 Test bench structures
 Bus function models
 Assertion based Verification
 Functional Verification Coverage
o Statement
o Branch
o Expression
o Path
o Toggle
Module 3 : Standard mini project – using Verilog
Module 4 : Interface Protocols
 UART
 I2C
 SPI
 APB
 AHB
 AXI
 Glimpse of USB
 Glimpse of PCIe

2. OBJECT AUTOMATION Software Solutions Pvt Ltd
No.1, Nehru Street, Second Floor,
Kooturavu Nagar, Adambakkam, Chennai – 600 088
Email id – hr@object-automation.comPhone:044 4335 6149
www.object-automation.com
Module 5 : Overview of SoC Architectures
 What is an SoC ?
 Advantages of SoCs over conventional ASICs?
 Typical components of an SoCs
 Sample SoC Architectures
Module 6 : Advanced FV using SystemVerilog
 Importance of Functional verification
 Evolution of SystemVerilog
 New Additions to SystemVerilog
 New features
 Data types
 Arrays
 Operators
 Subroutines
 Procedural statements
 Concurrency
 Interfaces
 Object Oriented Programming
 Encapsulation
 Randomization
 Inheritance & Polymorphism
 Virtual Interfaces
 Inter thread mechanism
 Callbacks
 Assertions
 Functional Coverage
 DPI
 Layered testbench architecture
 Driver
 Monitor
 Transactor
 Generator
 Scoreboard
 Reference models
 Bus function models
 Testplan creation