1. 鄭乃禎
Nai-Chen Cheng
13F., No.126, Longshan W. Rd.,
East Dist., Hsinchu City 300,
Taiwan (R.O.C.)
0918347686
obewan18@gmail.com
EDUCATION
• National Cheng Kung university, Bachelor of Electrical Engineering,
1999.09~2003.6
• National Cheng Kung university, Master of Electrical Engineering, major in VLSI /
CAD, 2003.09~2005.6
- Advisor: Prof. Soon-Jyh Chang
- Thesis : On-Chip Low Jitter Clock Generation
EXPERIENCE IN ITRI
Project leader of Prothesis Epiretinal Stimulation ASIC (under cooking) — 2015-
Present
Coordinated with different research team, assisted to define reasonable system spec.,
and developed project
Project leader and researcher of low power RF design group — 2010-Present
Initiated several projects, clarified challenges and problems, co-worked for solutions,
and scheduled milestones.
As the Main Designer
- Low in-band noise digital frequency synthesizer design (on-going):
Investigated for a new architecture of a low in-band noise digital PLL
- A quantization noise elimination method for fractional-N frequency
synthesizers (2014-2015 spring) :
Proposing a new multi-phase method for eliminating quantization noise of a
fractional-N frequency synthesizer
- Low-cost temperature-compensated on-chip crystal-less oscillator
(2013):
By using a digital calibration method to compensate frequency-drift of a free-
running LC-VCO due to temperature variation. The frequency instability is less than
0.5% due to temperature variation.

2. As the Project Leader
- 2.4GHz low power wake up receivers with high sensitivity: identified system spec,
supervised for test-chip performance, and assisted for patent application
- Human body communication of IEEE 802.15.6: identified system spec, built
demonstration platform, recommended for circuit design, and supervised for overall
TRX performance
- Low power 2.4GHz frequency synthesizer: supervised test-chip performance,
assisted for patent application and paper presentation
★Honour : Outstanding research award of ITRI, 2013
★Contribution: 2 international conferences, 1 IEEE journal, 3 US patents.
Engineer of analog BIST — 2006-2009
Focusing on BIST (Built-in Self Test) research for on-chip clock jitter measurement.
Responsible for system level spec. definition, co-work with test-chip design, and final
evaluation. Challenges: measuring high-speed clock by BIST with pico-second
accuracy.
★Contribution: 3 international conferences, 1 internal journal, 2 US patents.
PATENTS AND PAPERS
- Patents:
1. Chih-Hsiang Chang, Nai-Chen Cheng, Yu Lee, Ching-Yuan Yang, “Current reuse
frequency divider and method thereof and voltage control oscillator module and phase-
locked loop using the same, “ US 8829966, 2014, Sep.
2. Yu-Lin Tsou, Nai-Chen Cheng, “Radio frequency front-end circuit and operation
method thereof,” US 8774744 B2, 2014, July
3. Chih-Hsiang Chang, Nai-Chen Cheng, Yu Lee, “Ching-Yuan YangVoltage-controlled
oscillator module and method for generating oscillator signals,” US 8723609 B2, 2014,
May
4. Yu Lee, Nai-Chen Cheng, Ji-Jan Chen, Yuan-Hua Chu, Ching-Yuan Yang, “Apparatus
for clock skew compensation,” US 8384455 B2, 2013, Feb.
5. Yu Lee, Nai-Chen Cheng, Ji-Jan Chen,”Jitter measuring system and method,”US
8144756 B2, 2012, March
- Journal:
- Yu Lin Tsou; Gong, C.-S.A.; Nai -Chen Cheng; Yu Lee; Jou, C.F., “Integrated Biosensing
Platform Based on a 1.74-mW −90-dBm Sensitivity Dual- Mode-Operation Receiver for
IEEE 802.15.6 Human Body Communication Standard, ” Sensors Journal, IEEE,
2015,Volume: 15, Issue: 6
- Conferences:

3. 1. Chih-Hsiang Chang; Ching-Yuan Yang; Yu Lee; Jun-Hong Weng; Nai-Chen Cheng, “A
3.4mW 2.3-to-2.7GHz frequency synthesizer in 0.18-µm CMOS,” ESSCIRC, 2013
2. Yu Lin Tsou; Cheng, N.-C.D.; Jou, C.F.,“A 32.4 μW RF front end for 2.4 GHz wake-up
receiver,” ISCAS, 2013
3. Yu Lee; Ching-Yuan Yang; Cheng, N.-C.D.; Ji-Jan Chen, “An embedded wide-range
and high-resolution CLOCK jitter measurement circuit,” Design, Automation & Test in
Europe Conference & Exhibition (DATE), 2010
4. Cheng, N.-C.D.; Yu Lee; Ji-Jan Chen,“Experimental Results of Built-In Jitter
Measurement for Gigahertz Clock,” Asian Test Symposium, 2008
5. Cheng, N.-C.D.; Yu Lee; Ji-Jan Chen,“A 2-ps Resolution Wide Range BIST Circuit for
Jitter Measurement,” Asian Test Symposium, 2007.
SKILLS
- Familiar tools: Spectre RF, HSPICE, laker, virtuoso, MATLAB, cppsim
- Languages: Fluent in English and Chinese, both for professional proficiency.
Japanese in elementary proficiency.
INTERESTS
- Photography, classical music, and tennis.
PROFILE
Born in Changhua, grown in country side, I was lucky enough to live in a happy
middle class family. My growing experience has strong impact on my personalities- to
be enthusiasm and positive on surroundings, no matter for work or for life, and to be
thankful to my companions, because they are always your greatest tutors. I also enjoy
communicate with people, either for chatting, negotiation, or teamwork. The best
motto for me is “ To be or not to be, that is the question”.