TỔNG ÔN TẬP THI VÀO LỚP 10 MÔN TIẾNG ANH NĂM HỌC 2023 - 2024 CÓ ĐÁP ÁN (NGỮ Â...
Lab1 introduction
1. Revised by Juan F Proano
Verilog on Intel FPGAs
Lab 1: FPGA BOARD BASICS
SIMULATOR AND BLINK EXAMPLE
1
https://www.mojotronicsltd.co.uk/
2. Revised by Juan F Proano
Quartus Software Installation
2
Download link:
https://www.intel.com/content/www/us/en/programmable/downloads/download-center.html
Version: 13.0 Web edition (Free license)
Device support: Cyclone II, Cyclone IV, Cyclone V
Installer file size: Approximately 3GB
Hard Disk space required: 10GB
https://www.mojotronicsltd.co.uk/
3. Revised by Juan F Proano
Mojotronics Remote FPGA Access
3
1. Student Installs Teamviwer
Desktop remote access tool
and connects to Mojotronics
100 MB on user side hard drive
2. Remote connection stablished
3. Mojotronics PC runs Quartus and Simulation program controlling the FPGA
Mojotronics Server PC
4. User connected
using the FPGA
remotely
Student PC after connection
Student PC
https://www.mojotronicsltd.co.uk/
4. Revised by Juan F Proano
The Boards
4
Inputs Slide switches Inputs Push switches
Outputs
Simulator options
And link to support
material
https://www.mojotronicsltd.co.uk/
Physical board
Remote Interface board
5. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
5
B A X
Example AND GATE:
Switch A = 0
Switch B = 1
Switch A up = 1
Switch A down = 0
Switch B up = 1
Switch B down = 0
https://www.mojotronicsltd.co.uk/
6. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
6
https://www.mojotronicsltd.co.uk/
1 2 3
Click on New Project
Wizard
Click on Next Click on the 3 dots
7. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
7
https://www.mojotronicsltd.co.uk/
4
Select the documents folder
8. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
8
https://www.mojotronicsltd.co.uk/
5
Add FPGA/lab1 after the documents
location
9. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
9
https://www.mojotronicsltd.co.uk/
6
Confirm you want to create the folder
Click in Yes and then click Next
10. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
10
https://www.mojotronicsltd.co.uk/
7 8 9
Click in next Open the files explorer Double click on Desktop
11. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
11
https://www.mojotronicsltd.co.uk/
10
Open the spreadsheet
file called:
XXXX_pins
This name can change
depending on the board
Being used.
12. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
12
https://www.mojotronicsltd.co.uk/
11
Th file contains the FPGA family
And FPGA version
Family: Cyclone 2
FPGA: EP2C5T144C8
13. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
13
https://www.mojotronicsltd.co.uk/
12
Select the settings as found
in the spreadsheet and click next
(Example below please refer to
the spreadsheet document)
Family: Cyclone 2
FPGA: EP2C5T144C8
14. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
14
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13 14
Click on next Click on next
15. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
15
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15
Click on the icon for new file
Or go to File and select New
16. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
16
https://www.mojotronicsltd.co.uk/
16 17
Select Verilog HDL file
Type the following text. This is the basic structure of a
Verilog module. After click on Save.
Keyword: module
module name: lab1
Input and output Ports to be created: ();
Keyword to indicate the end of the module: endmodule
17. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
17
https://www.mojotronicsltd.co.uk/
18
Make sure that the name we created
in step 5 (in page 8) matches the
module name
And the file name. Then click on save
18. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
18
https://www.mojotronicsltd.co.uk/
19
Double check that the
Module name
matches the
Top level entity
And the file name
19. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
19
https://www.mojotronicsltd.co.uk/
20
Ports can now be declared for
our AND GATE refer to the
diagram in page 5
1 bit INPUT A
1 bit INPUT B
1 bit OUTPUT X
20. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
20
https://www.mojotronicsltd.co.uk/
21
We assign the operation
AND to our output.
Notice that we are using
The bitwise AND
operation.
21. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
21
https://www.mojotronicsltd.co.uk/
22
Compile by clicking on the play button or
by going to Porcessing/Start Compilation
then click on Yes save changes
22. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
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https://www.mojotronicsltd.co.uk/
23 24
After successful compilation click OK
Click on Assignments / Pin Planner
23. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
23
https://www.mojotronicsltd.co.uk/
25
Bring back the spreadsheet we opened in page 11 and have it side by side with pin planner
24. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
24
https://www.mojotronicsltd.co.uk/
26
Copy and paste the
Inputs from the spreadsheet
On te inputs on Pin Planner
25. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
25
https://www.mojotronicsltd.co.uk/
27
Copy the location for
the output X and
paste it in Pin planner
26. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
26
https://www.mojotronicsltd.co.uk/
28
After setting up the locations
We can close Pin Planner
27. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
27
https://www.mojotronicsltd.co.uk/
29
Back in Quartus click on Compile
28. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
28
https://www.mojotronicsltd.co.uk/
30
After successful compilation
Click OK
29. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
29
https://www.mojotronicsltd.co.uk/
31 32
To program the FPGA click on Tools / Programmer Click on Hardware Setup so it can detect the FPGA hardware
30. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
30
https://www.mojotronicsltd.co.uk/
33,34 35
Select the USB blaster 0 on both locations and them close If your programming file is not shown under File like in the
Picture click Add file
31. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
31
https://www.mojotronicsltd.co.uk/
36 37
Make sure you are in the project location lab 1
Then select the output_files folder
Select the lab1.sof file and click Open
32. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
32
https://www.mojotronicsltd.co.uk/
38
lab1.sof programming file should appear under the File tab as well as the device click on Start
33. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
33
https://www.mojotronicsltd.co.uk/
39 40
Upload to the FPGA board is successful close the programmer Click no on the message shown after closing the programmer
34. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
34
https://www.mojotronicsltd.co.uk/
41 42
Minimize Quartus Minimize Pin Planner and the pins spreasheet
35. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
35
https://www.mojotronicsltd.co.uk/
43 44
Open Mojotronics FPGA Interface program Enter the provided password and click OK
36. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
36
https://www.mojotronicsltd.co.uk/
45 46
Open Mojotronics FPGA Interface program Select the Highest port available
37. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
37
https://www.mojotronicsltd.co.uk/
47 48
With highest port selected click OK Open the Spreadsheet and put it side by side with Mojotronics program
38. Revised by Juan F Proano
Lab1: Blink program (AND GATE)
38
https://www.mojotronicsltd.co.uk/
49
Input 0 and input 1 in the spreadsheet correspond to the first two slide switches o the right. The rest of the slide switches
although we are not using them correspond to the other pins in the same order.
39. Revised by Juan F Proano
Lab1: Blink program (AND GATE TEST)
39
https://www.mojotronicsltd.co.uk/
By clicking on the slide switches you can slide them up and down
BA
00
BA
01
BA
10
BA
11
Output X =1
Led ON
40. Revised by Juan F Proano
Lab1: Challenge
40
https://www.mojotronicsltd.co.uk/
I hope you enjoyed lab1 and try the following challenge
Implement all the gates in the diagram in one program.
Use different inputs for each gate. In total you should have
7 inputs and 4 outputs.