1. MADHURIMA DAS
Mobile: +91-9836639259
E-Mail: madhurima_das_24@yahoo.co.in
Seeking challenging assignments in Software Design & Development with an organization of high repute
preferably in IT, EDA, Product and Service industry
Location Preference: No problem in relocation
PROFILE SUMMARY
 A technocrat with nearly 7 years of experience in Software Design & Development
 Experienced in handling complete SDLC including requirement gathering & analysis,
designing, testing, maintenance and support
 Abilities in mapping the requirements, custom designing solutions & troubleshooting for
complex software & application problems
 Adroit in providing effective resolution to customer queries related to production
support and improving relationships with the customer by anticipating customer
future requirements, thereby ensuring a positive customer experience
 Expertise in using tools for Verilog and VHDL with in-depth knowledge &
understanding of object oriented programming with C++
 Proficiency in managing complex system architecture (hardware & software) in EDA
tool definition & EDA Parser tool development forming the basis of technical
solutions provided to resolve customers’ designing needs
 A team player with strong communication, analytical, logical and problem-solving skills
 Leading and monitoring modules
CORE COMPETENCIES
 Gathering technical requirements and documenting the same to attain smooth development process
 Providing guidance to application developers tasked with implementation of applications based on prototype results
 Managing data analysis & involved in change management
 Handling development of software projects from designing, implementation, configuration management, etc.
 Ensuring requirement gathering, system analysis and finalisation of technical / functional specifications
 Offering post-implementation, application maintenance & support to the client with regard to the product / software application
ORGANISATIONAL EXPERIENCE
Since Oct’14 Interra Systems Private Limited, Noida (www.interradesign.com)
as Principal Engineer
Clients Handled: Synopsys, Fishtail etc.
Feb’09 – Sep’14 Electra Design Automation Private Limited, Kolkata (Contractor of Verific
Design Automation, USA (www.verific.com)) as Senior Software Engineer
Clients Handled: Aldec, Altera, Apache, Atrenta, Ausdia, Blue Pearl, Calypto, DeFacTo,

2. Excellicon, Forte, IBM, Intel, Jasper, LatticeSemi, NEC, Nvidia, Oasys, Real Intent, Rocketick, Synopsys,
Tabula, Tektronix, Yogitech, Xilinx etc
Role:
 Understanding the technical & functional specifications as provided by the client
 Accountable for designing, developing, testing, troubleshooting and debugging of the applications
 Implementing and testing the application
 Handling post-implementation, enhancement & maintenance support to client for application
 Preparing & testing Unit Test Case and conducting regression testing
EDUCATION
 Master of Computer Applications from Birla Institute of Technology, Mesra
with CGPA 8.43 in 2009
 B.Sc. (Hons.) in Chemistry from University of Calcutta (Bethune College),
Kolkata in 2005
 12th
from W.B.C.H.S.E, West Bengal with 80% in 2002
 10th
from W.B.B.S.E, West Bengal with 84.88% in 2000
Others:
 5 years Diploma in Painting & Dancing
IT SKILLS
Operating Systems: Linux, Windows98/XP/Windows 7
Technologies: EDA (Electronic Design Automation)
Languages: C++, Verilog, VHDL
Key Skills: Data Structures, Algorithm
Editors: VI, VIM, GVIM
Debug Tool: GDB, CGDB, EMACS, DDD
Memory Management Tool: VALGRIND
Software Tools and Packages: LEX & YACC, Profiling Tools, CVS, VCS, ModelSim, NC-VERILOG, NC-VHDL, DC (Design
Compiler), Geometry Extractor, and Swig
ACADEMIC ACCOLADES
 Holds the credit of being among top 2 in the MCA batch and top 5 in school
 Received various certificates & awards for painting & dancing
PERSONAL DETAILS
Date of Birth: 24th
September, 1983
Address: B-45, Sector-15, Noida, UP-201301
Languages Known: Bengali, English and Hindi
(Please refer annexure)

3. ANNEXURE:
Major Assignments:
Interra Systems Assignments:
Title: Mixed SystemVerilog VHDL2008 Elaboration Support: Elaboration Project
Description: Project involved support of VHDL2008 features in mixed Verilog-VHDL designs
Process:
Part-1: Generic type/ subprogram/ package propagation from VHDL to Verilog in mixed domain
Part-2: Parameter type propagation from Verilog to VHDL in mixed domain
Part-3: Port type matching in mixed Verilog-VHDL
Title: Type Conversion in Mixed SystemVerilog VHDL: Elaboration Project
Description: Project involved conversion of Verilog types to VHDL types and vice versa
Process:
Part-1: Convert Verilog types to corresponding VHDL types and VHDL types to corresponding Verilog types
Title: Mixed SystemVerilog VHDL2008: Monitoring Beacon Project
Description: Project involved monitoring module in designing test suit for support of Verilog VHDL2008 features
Process:
Part-1: VHDL2008 features in mixed Verilog VHDL domain
Others: Fixed a number of JIRA (id for our product bugs)
Team size: Individual
Role: Developer
Technologies Used: C++, Shell Script, Debug Tools (DDD), Memory Management Tool (VALGRIND)
Skills Used: Data Structures, Algorithm
Environment: Linux
Role:
 Involved in understanding requirements and analysing the requirements from technical aspects
 Accountable for development / maintenance of MVV (Elaboration), Cheetah (Verilog/ System Verilog Analyzer),
Jaguar (VHDL Analyzer)
 Accountable for monitoring team of Beacon (Test Suit)
 Carried out unit & system testing
 Implemented workflow/unit cases as per client requirements and handled defect fixing
Verific Assignments:
Title: State Machine Conversion: Analysis Project
Description: Project involved conversion of non-synthesizable Verilog/VHDL design to synthesizable one.
Process:
Part-1: Implicit to explicit state machine conversion with clocking event for Verilog
Part-2: Implicit to explicit state machine conversion with clocking event for VHDL
Part-3: Implicit to explicit state machine conversion with event triggering for Verilog
Title: Graph Optimization: Static Elaboration Project
Description: Project dealt with optimisation of full static elaborated parse tree (graph) depending upon the
presence of hierarchical references.
Title: Package Conversion: Mixed Language Project (Mixed VHDL-Verilog)
Description: Project involved conversion of Verilog package to corresponding VHDL package while importing
Verilog package in VHDL design and VHDL package to corresponding Verilog package while importing
VHDL package in Verilog design.
Process:
Part-1: Conversion of Verilog package to VHDL package
Part-2: Conversion of VHDL package to Verilog package

4. Title: Netlist Optimization Project
Process:
Part-1: Optimisation of Netlist Operators: driven by constant adder/multiplier for Shifter, Mux and Decoder
Part-2: Optimised adders if an upstream adder is solely connected to a downstream adder
Part-3: Constant propagation on Netlist Operators (with constant inputs) such as Adder, Subtractor,
Multiplier, Divider, Mux, Decoder, Encoder, Selector, etc.
Part-4: Created Netlist for Verilog Power Operator: Matlab Algorithm
Title: Netlist Writer Customization Project
Process:
Part-1: Destructed Netlist operators
Part-2: Scripted Netlist in different fashion for Verilog-95 and SystemVerilog mode
Title: Convert Recursive Algorithms to Iterative Algorithms
Description: Project involved implementation some recursive algorithms (both in Verific’s VHDL and Verilog
branches) to get rid of recursion stack overflow
Title: Handing Keywords in Different Verilog Mode: LEX-YACC Manipulation Project
Description: Project deal with handling keywords of Verilog Versions (95, 2001, 2005, SystemVerilog) by switching
flex mode.
Title: Application Writing: User Interface to control Verific’s Parser Tool
Process:
Part-1: Module Inlining: Flattening of multilevel modules
Part-2: Traverse hierarchy: Traverse hierarchy crossing the language boundary (VERILOG-VHDL Mixed
Language Application)
Others: Fixed a number of VIPERs (id for our product bugs)
Team size: Individual
Role: Developer
Technologies Used: C++, TCL Script, Debug Tools (GDB, CGDB, EMACS), Memory Management Tool (VALGRIND)
Skills Used: Data Structures, Algorithm
Environment: Linux
Role:
 Involved in understanding requirements and analysing the requirements from technical aspects
 Accountable for development / maintenance of Verific’s tool
 Carried out unit & system testing
 Implemented workflow/unit cases as per client requirements and handled defect fixing