1. RESUME
M.MADH SUDHAN
E-Mail : madhumachireddypally@gmail.com
Phone : 9000089545
Career Objective:
Seeking a challenging position, where I can utilize my technical and personal skills for personal
as well as organization’s growth. Work in an competitive and healthy environment where all my
skill’s and talent can be used for the growth of organization.
Self-motivated and hardworking fresher seeking for an opportunity to work in a challenging
environment to prove my skills and utilize my knowledge & intelligence in the growth of
organization.
Educational Qualification:
Course Discipline
College /
School
University/
Board
Year of
Passing
U.G B.TECH
(ECE)
TRR COLLEGE
OF
ENGINEERING
JNTUH
University
2014
Intermediate MPC
SHAANKARY
JR. COLLEGE
B.I.E.A.P 2009
S.S.C -
GEETHANJALI
HIGH SCHOOL
AP SSC 2007
Technical Skills:
 OS: Widows XP ,Windows 7.Windows 8.
 SAP BW/BI,BEX,REPORTING TOOLS DASHBOARDS,CRYSTAL,WEBI
 MS-Office
 Basic Hardware & Internet Knowledge

2. Mini project
Title : Serializer and De-serializer using Verilog
Description : Serializer/Deserializers (Ser-Des) commonly used in
telecommunication networks are now becoming widespread in computer and
embedded systems to meet higher data bandwidth demand and support higher
peripheral device performance requirements. These input/output (IOs) peripherals
are design to provide reliable high speed data transfer capabilities to computers and
embedded devices.
The basic Ser Des function is made up of two functional blocks: the Parallel In
Serial Out (PISO) block (aka Parallel-to-Serial converter) and the Serial In Parallel
Out (SIPO) block (aka Serial-to-Parallel converter). There are 4 different Ser-Des
architectures: (1) Parallel clock Ser-Des, (2) Embedded clock Ser-Des, (3) 8b/10b
Ser-Des, (4) Bit interleaved Ser-Des.
The PISO (Parallel Input, Serial Output) block typically has a parallel clock input,
a set of data input lines, and input data latches. It may use an internal or
external phase-locked loop (PLL) to multiply the incoming parallel clock up to the
serial frequency. The simplest form of the PISO has a single shift register that
receives the parallel data once per parallel clock, and shifts it out at the higher
serial clock rate. Implementations may also make use of a double-buffered register
to avoid metastability when transferring data between clock domains.
The SIPO (Serial Input, Parallel Output) block typically has a receive clock output,
a set of data output lines and output data latches. The receive clock may have been
recovered from the data by the serial clock recovery technique. However, Ser-Des
which do not transmit a clock use reference clock to lock the PLL to the correct Tx
frequency, avoiding low harmonic frequencies present in the data stream. The
SIPO block then divides the incoming clock down to the parallel rate.
Implementations typically have two registers connected as a double buffer. One
register is used to clock in the serial stream, and the other is used to hold the data
for the slower, parallel side.
Some types of Ser-Des include encoding/decoding blocks. The purpose of this
encoding/decoding is typically to place at least statistical bounds on the rate of
signal transitions to allow for easier clock recovery in the receiver, to
provide framing, and to provide DC balance.

3. Main project
Title : CMOS full-adders for energy efficient arithmetic
applications.
Description : We present two high-speed and low-power full-adder
cells designed with an alternative internal logic structure and pass-transistor logic
styles that lead to have a reduced power-delay product (PDP). We carried out a
comparison against other full-adders reported as having a low PDP, in terms of
speed, power consumption and area.
1. There is no requirement of internal signal for controlling the select line of
multiplexers. Instead, the Carry input signal, which has full voltage swing and
without delay, is used to drive the select line of multiplexers, which reduces the
overall propagation delay of full adder.
2. It reduces the capacitive load for the carry input, because it is connected only to
some transistor gates and not to some drain or source terminals, where the
diffusion capacitance is becoming very large. Hence, the overall delay for larger
modules where the carry signal falls on the critical path can be reduced.
3. The propagation delay can be tuned up individually by adjusting the
XOR/XNOR and the AND/OR gates for the So and Co outputs; this criteria is
advantageous for applications where the skew between arriving signals is critical
for a proper operation (e.g., wave pipelining). 4. By interchanging the XOR/XNOR
signals, and the AND/OR gates to NAND/NOR gates at the input of the
multiplexers, the placement of buffers at the full-adder outputs can be implemented
which can improve the performance for load sensitive applications.
Interpersonal Skills:
.Quick Learning & Dedication.
.Self confidence.
.good Communication Skill.
.Sincere and honest.
.Work proficiency.

4. Personal Information:
Name : M.MADHU SUDHAN
Father’s name : MOHAN.M
Date of birth : 13-07-1992
Languages known : English, Hindi, Telugu.
Nationality : Indian
Residency : HNO: 11-345,
SHANTHI NAGAR COLONY,
PATANCHERU,HYDERABAD.
Permanent address : M.MADHU SUDHAN
S/O:M.MOHAN
HNO:1-1
VILL:PICHARAGADI,
MDL:KOHIR
DIST:MEDAK-TELANGANA
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Declaration:
I here by declare that all the information furnished above is true to the best of my knowledge and
belief.
Place : Hyderabad
Date :
M.MADHU SUDHAN