15. Certess approach to Mutation Analysis Fault Model Analysis Fault Activation Analysis Qualify the Verif. Env. Static analysis of the design Analysis of the verification environment behavior Measure the ability of the verification environment to detect mutations Iterate if needed Report Report Report
16.
17.
18.
19.
20. Design Bugs Caught by SLEC System Bugs Found Application High- Level Synthesis bug in “wait_until()” interpretation DCT Function High-Level Synthesis bug in array’s access range Wireless baseband Design bug in logic on asynchronous reset line Video processing Design bug in normalization of operands Custom DSP Block Design bug at proof depth = 1. Image Resizer High-Level Synthesis bug in sign extension Video processing
21.
22. High-level Synthesis Bugs found by SLEC Bugs Found Application Shift by an integer in the C-code could be a shift by a negative number which is undefined in C Multi-media processor Dead end states created Multi-media Processor Combinational loops created FFT Shift left or right by N bits, when the value being shifted is less than N bits Ultra wideband Filter Divide by zero defined in RTL, but undefined in C code Quantize
When the initial block of design does not meet timing engineers must transform the RTL into a faster implementation . A common technique is re-timing. By moving logic around, long paths can be reduced . However, by moving logic around the value/meaning of state elements is completely changed . Combinatorial formal techniques do not support these changes. SLEC handles this type of design easily Outside of changes, two designs should have identical functionality No requirement for internal statepoints to map/match
When the initial block of design does not meet timing engineers must transform the RTL into a faster implementation . A common technique is re-timing. By moving logic around, long paths can be reduced . However, by moving logic around the value/meaning of state elements is completely changed . Combinatorial formal techniques do not support these changes. SLEC handles this type of design easily Outside of changes, two designs should have identical functionality No requirement for internal statepoints to map/match
When the initial block of design does not meet timing engineers must transform the RTL into a faster implementation . A common technique is re-timing. By moving logic around, long paths can be reduced . However, by moving logic around the value/meaning of state elements is completely changed . Combinatorial formal techniques do not support these changes. SLEC handles this type of design easily Outside of changes, two designs should have identical functionality No requirement for internal statepoints to map/match
![An excursion out of the ivory tower ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)