• Share
  • Email
  • Embed
  • Like
  • Save
  • Private Content
Mpmc
 

Mpmc

on

  • 3,852 views

about microcontroller and microprocessor

about microcontroller and microprocessor

Statistics

Views

Total Views
3,852
Views on SlideShare
3,852
Embed Views
0

Actions

Likes
0
Downloads
151
Comments
0

0 Embeds 0

No embeds

Accessibility

Categories

Upload Details

Uploaded via as Adobe PDF

Usage Rights

© All Rights Reserved

Report content

Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
  • Full Name Full Name Comment goes here.
    Are you sure you want to
    Your message goes here
    Processing…
Post Comment
Edit your comment

    Mpmc Mpmc Document Transcript

    • ELECTRONICS & COMMUNICATION ENGINEERING 1. Introduction to MASMIntroduction:The aim of this experiment is to introduce the student to assembly languageprogramming and the use of the tools that he will need throughout the labexperiments. This first experiment let the student use the Dos Debugger and theMicrosoft Macro Assembler (MASM). Editing, Assembling, Linking, Execute up canbe done using MASM softwareObjectives: 1. Introduction to Microsoft Macro Assembler (MASM) 2. General structure of an assembly language program 3. Use of the Dos Debugger programOverview:In general, programming of microprocessor usually takes several iterations beforethe right sequence of machine code instruction is written. The process, however isfacilitated using a special program called an “Assembler”. The Assembler allows theuser to write alphanumeric instructions. The Assembler, in turn, generates thedesired machine instructions from the assembly language instructions.Assembly language programming consists of following steps: STEP PRODUCES 1 Editing Source file 2 Assembling Object file 3 Linking Executable file 4 Executing Results Table1.1: Assembly Language Programming PhasesMICROPROCESSORS LAB 1
    • ELECTRONICS & COMMUNICATION ENGINEERINGAssembling the program:The assembler is used to convert the assembly language instructions to machinecode. It is used immediately after writing the Assembly language program. Theassembler starts by checking the syntax or validity of the structure of each instructionin the source file .if any errors are found, the assemblers displays a report on theseerrors along with brief explanation of their nature. HoweverIf the program does contain any errors ,the assembler produces an object file thathas the same name as the original file but with the “obj” extensionLinking the program:The Linker is used convert the object file to an executable file. The executable file isthe final set of machine code instructions that can directly be executed by themicroprocessor. It is the different than the object file in the sense that it is self-contained and re-locatable. An object file may represent one segment of a longprogram. This segment can not operate by itself, and must be integrated with otherobject files representing the rest of the program ,in order to produce the final self-contained executable fileIn addition to the executable file, the linker can also generate a special file called the“map”file.this file contains information about the start, end, length of the stack, code,and data segments. it also lists the entry point of the programExecuting the programThe executable contains the machine language code .it can be loaded in the RAMand executed by the microprocessor simply by typing ,from the DOS prompt ,thename of the file followed by the carriage Return Key (Enter Key). If the programproduces an output on the screen or sequence of control signals to control a piece ofhard ware, the effect should be noticed almost immediately.However,if the programmanipulates data in memory, nothing would seem to have happened as a result ofexecuting the program.MICROPROCESSORS LAB 2
    • ELECTRONICS & COMMUNICATION ENGINEERINGDebugging the programThe debugger can also be used to find logical errors in the program. Even if aprogram does not contain syntax errors it may not produce the desired results afterexecution. Logical errors may be found by tracing the action of the program. oncefound, the source file should be rewrite to fix the problem, then the re-assembled andre-linked. A special program called the debugger is designed for that purpose.The debugger allows the user to trace the action of the program, by single steppingthrough the program or executing the program up to a desired point, called breakpoint. It also allows the user to inspect or change the contents of the microprocessorinternal registers or the contents of any memory location.The DOS –Debugger:The DOS “Debug” program is an example of simple debugger that comes with MS-DOS.Hence, it is available on any PC .it was initially designed to give the user thecapability to trace logical errors in executable file. It allows the user to take anexisting executable file and unassembled it,i.e convert it to assemblylanguage.Also,it allows the user to write assembly language instructions directly,and then convert them to machine language. The program is simple and easy touse. But offers limited capabilities, which make it unsuitable for serious assemblylanguage programming.Below, are summarized the basic DOS – Debugger commands COMMAND SYNTAX Assemble A [address] Compare C range address Dump D [range] Enter E address[list] Fill F range list Go G [=address] [addresses]MICROPROCESSORS LAB 3
    • ELECTRONICS & COMMUNICATION ENGINEERING Hex H value1 value2 Input I port Load L[address] [drive][first sector][number] Move M range address Name N[pathname][argument list] Output O port byte Proceed P[=address][number] Quit Q Register R[register] Search S range list Trace T[=address][value] Unassembler u[range] Write W[address}[drive][first sector][number]MS-MASM:Microsoft’s Macro Assembler (MASM) is an integrated software package written byMicrosoft Corporation for professional software developers. it consists of an editor,an assembler, a linker and a debugger(Code View). The programmer’s workbenchcombines these four parts into a user-friendly programming environment with built inon line help.The following are the steps used if you are to run MASM from DOS COMMAND FILE NAME 1 Edit, any editor will do Name.asm 2 Masm Filename Name.obj 3 Filename Table1.3: Assembly language programming phasesMICROPROCESSORS LAB 4
    • ELECTRONICS & COMMUNICATION ENGINEERINGProcedure to enter a program using MASM software Start ↓ Run ↓ Type CMD ↓ Ok Display shows ↓ C :> D: (Change to D drive because MASM is in D drive) ↓ Press ENTER ↓ D :> CD MASM ↓ Press ENTER ↓ D: MASM> DEBUG ↓ Press ENTER ↓ __? [Help] ↓ Press ENTER ↓ Then the display shows the main menu. ↓ Press ‘A’ and starting address of your program Ex: A 1000 ↓ Press ENTERMICROPROCESSORS LAB 5
    • ELECTRONICS & COMMUNICATION ENGINEERING ↓ Then the display shows 0B19: 1000__ ↓ Type your instructions Ex: Mov al, 20 ↓ Press ENTER then the display next address i.e. 0B19:1002__ ↓ Then type next instruction Ex: Mov bl, 30 ↓ After typing of every instruction press ENTER ↓ After typing of last instruction i.e. HLT then press ENTER and again press ENTER ↓ Display shows (__) blinking cursor______________________________________________________________________Procedure to enter the data into memory location. Sample program Mov al, [2000] Mov bl, [3000] Add al, bl Mov [4000], al HLTFor the above sample program we have to enter the data into memory locations. For that the procedure is given belowStep1: Type the sample program by using the above procedure.Step2: Then type ‘e’ 2000 (← address of the memory location)Step3: Then press ENTERMICROPROCESSORS LAB 6
    • ELECTRONICS & COMMUNICATION ENGINEERINGStep4: Display shows 0b19:2000 20 ← ( previous data in 2000 memory location)Step5: Type new data in that particular memory location. If you want to continue that memory location (i.e.2001, 2002------) then presses SPACE BAR KEY.Step6: If you want to exit from that memory location after typing the data then press ENTER.Step7: Then the display shows __Step8: Uses the same procedure for enter the data into 3000 memory location.Procedure to execute the program & to see the results a) register b) memory locations.Step1: After entered the data into memory locations by using the above procedure __ then the display shows __ ( blinking cursor)Step2: Type G=Starting address Ending address (Ex:G =1000 1020 ,starting address:1000 & ending address :1020)Step3: Then press ENTER.Step4: Then the display shows the REGISTERS with RESULTS.Step5: To see the results in memory locations press D 4000 (4000 is the address of the memory location where the result is stored. D is the command for displaying the data in memory locations)Step6: Then press ENTER.Step7: Then the display shows the data in 4000 location.MICROPROCESSORS LAB 7
    • ELECTRONICS & COMMUNICATION ENGINEERINGProcedure to edit the program.Step1: Press A 1007 ( 1007 is the address where you want to change the instruction)Step2: Then press ENTER.Step3: Then the display shows 0B19:1007 __Step4: Type the instruction which you want to change.Step5: Then press ENTER.Procedure to un assemble the program .Step1: Press U starting address ending address (U is the command to unassemble the program with Opcodes)Step2: Then press ENTER.Step3: Then the display shows the program with opcodes. 0B19: 1000 A00010 Mov al, [2000] ↓ ↓ ↓ ↓ (Starting address) (Opcode) (Mnemonic) (Operand)MICROPROCESSORS LAB 8
    • ELECTRONICS & COMMUNICATION ENGINEERING 2. Arithmetic Operation: Additiona) Aim: Write an ALP to add ‘n’ 8-bit numbers and store the result in any of the memory location.b) Appartus/Software: 1.8086 microprocessor kit/MASM-- 1 2.RPS(+5V). --1c) Algorithm:Step1: load CL with 03Step2 : Initialize the source IndexStep3: Initialize the AL with ‘00’Step4: Add the contents of the AL with the contents of the SI and the result is stored in ALStep5: Increment SIStep6: Decrement the content in CLStep7: If CL is not equal to zero, go to step4Step8: Store the contents of the Al into any memory location.Step9: Stopd) Assembly Language Program before execution:Label Mnemonic operand Comments MOV CL,03 Load CLl with 03; count initialized MOV SI,2000 initialize source index at 2000;memory pointer MOV AL,00 load AL with 00UP ADD AL,[SI] add content of SI with AL INC SI increment SI next memory location. DEC CL decrement count JNZ UP if it is non zero jump up MOV [3000],AL move the content of AL to 3000memory location HALT End of the programMICROPROCESSORS LAB 9
    • ELECTRONICS & COMMUNICATION ENGINEERINGe) Expected results:Input: 10h Output: 60H 20h 30hf)Assembly Language Program after execution: Address Opcode Mnemonic Operand 1000 B1,03 MOV CL,03 1002 BE,00,20 MOV SI,2000 1005 B0,00 MOV AL,00 1007 02,04 ADD AL,[SI] 1009 46 INC SI 100A FE,C9 DEC CL 100C 75,F9 JNZ UP 100E A2,00,30 MOV [3000],AL 1011 F4 HLTg) Results:Input : output:Address data Address data2000: 10h 3000: 60H2001: 20h2002: 30h CL : 03h AL: 00hh) Viva–Voce: i) Write instructions which perform addition operation in direct addressing, indirect addressing? A: Direct addressing mode : ADD AL,[2000], Indirect Addressing mode : ADD AL,[BX] ii) What are the flags effected after executing ADD instruction? A: All Flags effected (S,Z,A,P,C flags)MICROPROCESSORS LAB 10
    • ELECTRONICS & COMMUNICATION ENGINEERING 2. Arithmetic Operation: Multibyte additiona) Aim: Write an ALP to add two 32 bit operands which are in memory and store the data & result in the memory including carry. Use base + index addressing mode to read and store data in memory.b) Apparatus/Software:1. 8086 microprocessor kit/MASM ---1 2.RPS+5V). -- 1c) Algorithm:Step1: Load BX with 1230Step2: Load SI with Specific offset valueStep3: Add the contents of BX with SI load the content of memory location whoseaddress is Specified by sum of BX and SI and displacement into DXStep4: Add the contents of BX, SI with Displacement and load the content in DXStep5: Repeat Step4Step6: Add the contents of BX, SI with Displacement and load the content in DX Also carryStep7: Initialize CX registerStep8: Add with carryStep9: Load BX with 1440Step10: the contents of Ax loaded with memory location whose address is specifiedby sum of BX and SIStep11: the contents of DX loaded with memory location whose address is specifiedby sum of BX and SI with Displacement and load the content in DXStep12: Add the contents of BX, SI with Displacement and load the content in DXStep13: StopMICROPROCESSORS LAB 11
    • ELECTRONICS & COMMUNICATION ENGINEERINGd) Assembly language program before execution: Mnemonic Operand Comments MOV BX,1230 Load BX with 1230 MOV SI,0002 Load SI with Offset value MOV AX,[BX+SI] Add the contents of BX with SI load the content of memory location whose address is specified by sum of BX and SI and displacement into DX MOV DX,[BX+SI+02] Load the content of memory location whose address is specified by BX and SI and displacement into DX ADD AX,[BX+SI+04] add the contents of BX ,SI with Displacement and load the content in DX ADC DX,[BX+SI+06] add the contents of BX ,SI with Displacement and load the content in DX Also carry MOV CX,0000 Initialize CX register ADC CH,CL Add with carry MOV BX,1440 Load BX with 1440 MOV [BX+SI],AX Add the contents of BX with SI load the content in AX MOV [BX+SI+02],DX add the contents of BX ,SI with Displacement and load the content in DX MOV [BX+SI+04],CH add the contents of BX ,SI with Displacement and load the content in DX HLT End of the programe) Expected results:Input: 12 32 12 32: 1st number 23 21 23 21: 2nd numberOutput : 35 53 35 53 hMICROPROCESSORS LAB 12
    • ELECTRONICS & COMMUNICATION ENGINEERINGf) Assembly language program after execution: Address Opcode mnemonic operands 1000 BB,30,12 MOV BX,1230 1003 BE,02,00 MOV SI,0002 1006 8B,00 MOV AX,[BX+SI] 1008 8B,50,02 MOV DX,[BX+SI+02] 100B 34,004 ADD AX,[BX+SI+04] 100E 13,50,06 ADC DX,[BX+SI+06] 1011 B9,00,00 MOV CX,0000 1014 10,CD ADC CH,CL 1016 BB,40,14 MOV BX,1440 1019 89,00 MOV [BX+SI],AX 101B 89,50,02 MOV [BX+SI+02],DX 101E 88,68,04 MOV [BX+SI+04],CH 1021 F4 HLTg) Results:Input: OutputAddress Data Address Data1232: 32 1442: 531233 12 1443: 351234: 34 1444: 531235: 12 1445: 351236: 21 1446: 001237: 231238: 211239: 23h) Viva–Voice: i)What is the difference between ADD&ADC instruction? A: ADD instruction adds two opernds,ADC instruction adds two operads and the carry iii) What are the flags effected after executing MOV BX, 1230 instruction? A : No flags are effectedMICROPROCESSORS LAB 13
    • ELECTRONICS & COMMUNICATION ENGINEERING 2. Arithmetic Operation: Subtractiona) Aim: Write an ALP in 8086 to perform the subtraction of two numbers.b) Apparatus/Software:1. 8086 microprocessor kit/MASM,--1 2. RPS (+5V). --2c) Algorithm:Step1: Initialize AL with the contents of the memory location say 2000.Step2: Initialize the BL with the contents of the memory location say 2001.Step3: Subtract the contents of the AL with the contents of the BL And the result is stored in AL.Step4: Result is stored in one more location say 3000.Step6: Stop.d) Assembly language program before execution: Mnemonic Operand comments Load AL with the contents of given memory MOV AL,[2000] location Load BL with the contents of given memory MOV BL,[2000] location Subtract the contents of AL with the contents SUB AL,BL of BL MOV [3000],AL Copy the AL contents to the 3000 location HLT End of the programe) Expected result:Input: 30 _ 20 _______________ 10 _______________MICROPROCESSORS LAB 14
    • ELECTRONICS & COMMUNICATION ENGINEERINGf) Assembly language program after execution: Address Opcode Mnemonic Operand 1000 A0,00,20 MOV AL,[2000] 1003 8A,1E,01,20 MOV BL,[2000] 1007 28,D8 SUB AL,BL 1009 S2,00,30 MOV [3000],AL 100C F4 HLTg) Results:Input: Output:Address Data Address Data2000: 302001: 20 3000: 10h) Viva -Voice: i ) What is the difference between SUB,SBB instruction? A: SUB instruction subtracts two operands,SBB instruction subtracts two operands along with the borrow/carry ii) What are the flags effected after execution of HLT instruction ? A: No flags are effectedMICROPROCESSORS LAB 15
    • ELECTRONICS & COMMUNICATION ENGINEERING 2. Arithmetic Operation: Multiplicationa) Aim: Write an assembly language program in 8086 to perform multiplication of given two numbers by using ADD and SHIFT method.b) Appartus/Software:1. 8086 microprocessor kit/MASM---1 2. RPS (+5V). ---1.c) Algorithm: Step1: Clear AX, DX Register. Step2: Initialise DL and BL register with some data. Step3: Load count register with 08, because number of bit’s in Multiplicand is equal to number of shifts. Step4: Rotate BL register by one time to right . Step5: If there is no carry skip addition and shift DL register by one time . To left and go to step4. Step6: If there is a carry then add AX register with DX and shift DL Register by one time left and repeat loop until count becomes zero Step7: Load result in AL. Step8: End of the program.MICROPROCESSORS LAB 16
    • ELECTRONICS & COMMUNICATION ENGINEERINGd) Assembly language program before execution: Label Mnemonics Comments XOR AX,AX Reset AX Register. XOR DX,DX Reset DX Register. MOV Load Dl register with data whose address DL,[1050] 1050 MOV load BL register with data available at BL,[1051] memory location MOV CL,08 load CL register with 08h UP: ROR BL,01 rotate BL register data by one time if there is no carry skip addition and jump JNB DOWN down ADD AX,DX add ax with DX store data in AX DOWN: SHL DL,01 shift dl register to left by one time to the right DEC CL Decrement CL register JNZ UP If CL is not zero ,repeat loop MOV store result from Accumulator to memory [1052],AX location HLT end programe) Expected resultsNumbers are : 65h & 2A hOutput/Result: 2B20MICROPROCESSORS LAB 17
    • ELECTRONICS & COMMUNICATION ENGINEERINGf) Assembly language program after execution: Address Opcode Mnemonic Operand 1000 31,C0 XOR AX,AX 1002 31,D2 XOR DX,DX 1004 8A,16,50,10 MOV DL,[1050] 1008 8A,1E,51,10 MOV BL,[1051] 100C B1,08 MOV CL,08 100E B0,CB ROR BL,1 1010 73,02 JNB 1014 1012 01,D0 ADD AX,DX 1014 D1,E2 SHL DL,1 1016 FE,C9 DEC CL 1018 75,F4 JNZ 100E 101A A3,52,10 MOV [1052],AX 101D F4 HLTg) Results: Input OutputAddress data address data1050: 2A h 1052: 20h1051: 65h 1053: 2Bhh) Viva –Voce:i) what are the flags effected after execute up ADD AX,DX instruction (Assume:AX=FFFFh,DX=0001h)?A:Z=1,P=1,AC=1,CY =1,S=0, other flags are not effectedii)what is the difference between MOV DX,[1050],MOV DX,1050?A: MOV DX,[1050]; the contents of memory location whose address 1050 moved toDL register,1,1051 contents moved to DH register MOV DX,[1050];50h moved to DL register 10h moved to DH registerMICROPROCESSORS LAB 18
    • ELECTRONICS & COMMUNICATION ENGINEERING2. ArithmeticOperation:Multiplication(signed numbers)a) Aim: Write an Assembly Language Program to multiply two signed numbers and store the result in memory.b) Appartus/Software:1. 8086 microprocessor kit/MASM---1 2. RPS (+5V). ---1c) Algorithm:Step-1: Initialize the source address.Step-2: Load AL with the contents of the source index register.Step-3: Increment the pointer.Step-4: Load BL with the content of the source index register.Step-5: Signed multiplication is takes place.Step-6: Move the result from the accumulator to the memory location.Step-7: End. of the programd) Assembly language program before execution: Mnemonic Operand Comments Initialize SI at 2000 MOV SI,2000 memory location load CL register with data available at memory MOV AL,[SI] location SI Increment memory pointer INC SI SI load BL register with data available at memory MOV BL,[SI] location SI Perform signed IMUL BL multiplication copy the data from AX to MOV [3000],AX 3000 location HLT End programMICROPROCESSORS LAB 19
    • ELECTRONICS & COMMUNICATION ENGINEERINGe) Expected results:Input OutputData DataE4 h (Decimal no is-28) 03C6h (Decimal no is -1652)3Bh (Decimal no is +59)f) Assembly language program after execution: Address Opcode Mnemonics Operand 10000 BE,00,20 MOV SI,2000 1003 8A,04 MOV AL,[SI] 1005 46 INC SI 1006 8A,1C MOV BL,[SI] 1008 F6,EB IMUL BL 100A A3,00,30 MOV [3000],AX 100D F4 HLTg) Results:Input OutputAddress Data Address Data2000: E4 h (Decimal no is-28) 3000: C6h (Decimal no is - 1652)2001: 3Bh (Decimal no is +59) 3001: 03hh) Viva- Voce: 1. After multiplying the AL with BL the result is stored in : AX Register 2. After multiplying AX with BX the result is stored in : DX.AX RegistersMICROPROCESSORS LAB 20
    • ELECTRONICS & COMMUNICATION ENGINEERING 2. Arithmetic Operation: Division (signed numbers)a) Aim: write an Assembly Language Program to perform Division of the two signed numbers and store the result in memory location.b) Appartus/Software:1. 8086 microprocessor kit/MASM---1 2. RPS (+5V). ---1c) Algorithm: Step1: Initialize the DX with 0000 Step2: Initialize the source index. Step3: Load AX with the contents of the source Index register. Step4: Increment the pointer SI. Step5: Increment the pointer SI. Step6: Load BL with the contents of SI. Step7: Signed division is takes place. Step8: Move the resent from the AX and DX to the memory locations. Step9: End of the programd) Assembly language program before execution: Mnemonic Operands Comments MOV DX, 0000 Load DL with 00 MOV SI, 2000 Initialize SI at 2000 memory location load AX register with data available at MOV AX, [SI] memory location SI INC SI Increment SI INC SI Increment SI load BL register with data available at MOV BL, [SI] memory location SI IDIV BL Perform signed division operation MOV [3000], AX Copy data from AX to 3000 location Copy data from DX to 3002 MOV [3002], DX Location HLT End programMICROPROCESSORS LAB 21
    • ELECTRONICS & COMMUNICATION ENGINEERINGe) Expected results:Input Output:Data Data:00E4/02 00F2f) Assembly language program after execution: Adders Opcode Mnemonic Operand DX, 1000 BA,00,00 MOV 0000 1003 BE,00,20 MOV SI, 2000 1006 SB,04 MOV AX, [SI} 1008 46 INC SI 1009 46 INC SI 100A 8A,1C MOV BL, [SI] 100C F6Fb IDIV BL [3000], 100E A30030 MOV AX [3002], 1011 89160230 MOV DX 1015 F4 HLTg) Results:Input OutputAddress Data Address Data2000: E4 3000: F22001: 00 3001: 002002: 02h)Viva- Voce: 1. What is the result of DIV BX? A: Quotient stored at AX , Remainder stored at DX register 2. What is range of signed numbers for 8 bit microprocessor? A. + 127 to -127MICROPROCESSORS LAB 22
    • ELECTRONICS & COMMUNICATION ENGINEERING 2. Arithmetic Operation: ASCII additiona) Aim: Write an Assembly Language Program to perform the ASCII addition.b) Appartus/Software:1. 8086 microprocessor kit/MASM---1 2. RPS (+5V). ---1c) Algorithm:Step-1: Initialize the AH with 00Step-2: Initialize the source IndexStep-3: Load the contents of the AL with contents of the SIStep-4: Increment the SIStep-5: Load the contents of the SI ti the BLStep-6Add AL and BLStep-7: Move the result from the accumulator to the memory locationStep-8: End of the programd) Assembly language program before execution: Mnemonic Operand Comments MOV AH,00 Clear the AH register Load the SI with specified MOV SI,2000 address MOV AL,[SI] Copy to AL from SI INC SI Increment SI address MOV BL,[SI] Copy to BL from SI ADD AL,BL Add AL with BL Adjust accumulator after AAA addition Copy the contents AX to MOV [3000],AX given address HLT End of the programMICROPROCESSORS LAB 23
    • ELECTRONICS & COMMUNICATION ENGINEERINGe) Expected resultsInput OutputAddress Data Address Data2000: 05 3000: 042001: 09 3001: 01f) Assembly language program after execution: Address Opcode Mnemonic Operand 1000 B4,00 MOV AH,00 1002 BE,00,20 MOV SI,2000 1005 8A,04 MOV AL,[SI] 1007 46 INC SI 1008 8A,3B MOV BL,[SI] 100A F6,E6 ADD AL,BL 100B D4,01 AAA 100D A3,00,50 MOV [3000],AX 1010 F4 HLTg) Results:Input OutputAddress Data Address Data2000: 05 3000: 042001: 09 3001: 01h) Viva- Voice: 1. Difference between CMPS&SCAS instruction 2. Difference between AAA&DAA instructionMICROPROCESSORS LAB 24
    • ELECTRONICS & COMMUNICATION ENGINEERING 2. Arithmetic Operation: ASCII Multiplicationa) Aim: Write an Assembly Language Program to perform the ASCII multiplication.b) Appartus/Software:1. 8086 microprocessor kit/MASM---1 2. RPS (+5V). ---1c) Algorithm:Step-1: Initialize the AH with 00Step-2: Initialize the source IndexStep-3: Load the contents of the AL with contents of the SIStep-4: Increment the SIStep-5: Load the contents of the SI to the BHStep-6: Multiply the contents of the BH with AL and result is stored in AXStep-7OR the contents of AX with 3030Step-8: Move the result from the accumulator to the memory locationStep-9: End of the programd) Assembly language program before execution: Mnemonic Operand Comments MOV AH,00 Initialize AH Load Index Register with Starting MOV SI,2000 address of array MOV AL,[SI] Load AL With First Byte of data INC SI Increment SI by one MOV BH,[SI] Load BH with second byte MUL BH Multiply BH with AL Perform ASCII adjust after AAM multiplication operation OR AX,3030 Add AX with 3030 MOV [5000],AX Move the result into memory HLT End of the programMICROPROCESSORS LAB 25
    • ELECTRONICS & COMMUNICATION ENGINEERINGe) Expected results:Input Output09*05 3435f) Assembly language program after execution: Address Opcode Mnemonic Operand 1000 B4,00 MOV AH,00 1002 BE,00,20 MOV SI,2000 1005 8A,04 MOV AL,[SI] 1007 46 INC SI 1008 8A,3C MOV BH,[SI] 110A F6,E7 MUL BH 100C D4,0A AAM 100E 0D,30,30 OR AX,3030 1011 A3,00,50 MOV [5000],AX 1014 F4 HLTg) Results:Input OutputAddress Data Address Data2000: 09 5000: 352001: 05 5001: 34MICROPROCESSORS LAB 26
    • ELECTRONICS & COMMUNICATION ENGINEERING 3. Logical Operation: shift right operationa) Aim: Write an Assembly Language Program to shift the given 8 bit data to the right and store the result in the memory.b) Appartus/Software:1. 8086 microprocessor kit/MASM---1 2. RPS (+5V). ---1c) Algorithm:Step-1: Initialize the AH with 00Step-2: Initialize the source IndexStep-3: Load the contents of the AL with contents of the SIStep-4: Shift the contents of the accumulator to the to the right by 1Step-5:If there is barrow increment AHStep-6: Otherwise load the contents of the AL to the memory locationStep-7: End of the programd) Assembly language program before execution: Label Mnemonics Operand Comments MOV AH,00 Load AH with 00 Initialize SI at 3050 memory MOV SI,3050 location Copy data from SI memory MOV AL,[SI] location to AL SAR AL,01 Shift AL content to right by 1 time JNB DOWN If there is no carry jump down INC AH Increment AH Copy the data from AL to 4000 DOWN MOV [4000],AL location HLT End programMICROPROCESSORS LAB 27
    • ELECTRONICS & COMMUNICATION ENGINEERINGe) Expected results:Input OutputData Data27 93f) Assembly language program after execution: 3000 B4,00 MOV AH,00 3002 BE,50,30 MOV SI,3050 3005 8A,04 MOV AL,[SI] 3007 D0,F8 SAR AL,01 3009 73,02 JNB 300D 300B FE,C4 INC AH 300D A2,00,40 MOV [4000],AL 3010 F4 HLTg) Results:Input OutputAddress Data Address Data3050: 71 4000: 93h) Viva –Voce: 1. What are the flags updated after execution of INC AH instruction? A. All flags(Zero,Parity,AC,Sign) except carry flag.MICROPROCESSORS LAB 28
    • ELECTRONICS & COMMUNICATION ENGINEERING 3. Logical Operation: shift left operationa) Aim: Write an Assembly Language Program to perform Shift the given 16 bit no to The left and the result is stored in any one of the memory locations.b)Appartus/Software:1. 8086 microprocessor kit/MASM---1 2. RPS (+5V). ---1c)Algorithm: Step 1: Initialize the same index Step 2: Load the BX with the contents of the SI. Step 3: Shift the contents of the BX to the left by one. Step 4: Load the contents of the BX to the memory location. Step 5: Endd) Assembly language program before execution: Mnemonic Operand Comments Initialize SI at 2000 MOV SI, 2000 memory location Copy the data from SI MOV BX, [SI] location to BX Shift BX content to left SHL BX, 01 by 1 time Copy data from BX to MOV [5000], BX specified location HLT End programMICROPROCESSORS LAB 29
    • ELECTRONICS & COMMUNICATION ENGINEERINGe) Expected results:Input OutputAddress Data Address Data2000: C3 5000: 862001: E5 5001: CBf) Assembly language program after execution: Address Opcode Mnemonic Operand 1000 BE0020 MOV SI, 20000 1003 8A04 MOV BX, [SI] 1005 00F8 SHL BX, 01 1007 A30050 MOV [5000], BX 100B F4 HLTg) Results:Input OutputAddress Data Address Data2000: C3 5000: 862001: E5 5001: CBh) Viva- Voce: 1. When microprocessor is restarted it goes to which address? A. FFF0 2. Why do we need 16 bit address to be converted in to 20 bit address? A. Physical address of the memory is 20bitMICROPROCESSORS LAB 30
    • ELECTRONICS & COMMUNICATION ENGINEERING 3. Logical Operation: Packed BCD to Unpacked BCDa) Aim:-Write an Assembly Language Program in 8086 to convert packed BCD to unpacked BCD.b) Appartus/Software:1. 8086 microprocessor kit/MASM---1 2. RPS (+5V). ---1c) Algorithm: Step1:Load accumulator with data. Step2:Copy the value into AH register. Step3:To get the first unpacked number mask the lower byte by F0 using AND operation and load result in AH. Step4: Shift the contents of AH register right by 4 times load result in AH. Step5:Again to get the second unpacked number, mask higher byte by 0Fand store result in AL. Step6: End of the program.MICROPROCESSORS LAB 31
    • ELECTRONICS & COMMUNICATION ENGINEERINGd) Assembly language program before execution: Mnemonic Operand Comments MOV AL,[2000] Contents of memory move to AL MOV AH,AL Copy of AL register move to AH register AND AH,F0 Mask the lower nibble of AH register SHR AH,1 Shift right AH by 1 bit position SHR AH,1 Shift right AH by 1 bit position SHR AH,1 Shift right AH by 1 bit position SHR AH,1 Shift right AH by 1 bit position AND AL,0F Mask the Higher order nibble of AL register MOV [3000],AX Unpacked BCD numbers storing at 3000 & 3001 locations HLT End of the programMICROPROCESSORS LAB 32
    • ELECTRONICS & COMMUNICATION ENGINEERINGe) Expected results:Input OutputData Data78 08 07f) Assembly language program after execution: Address Opcode Mnemonic Operand 1000 A0,00,10 MOV AL,[2000] 1003 88,C4 MOV AH,AL 1005 80,E4,F0 AND AH,F0 1008 D0,EC SHR AH,1 100A D0,EC SHR AH,1 100C D0,EC SHR AH,1 100E D0,EC SHR AH,1 1010 24,0F AND AL,0F 1012 A3,00,20 MOV [3000],AX 1015 F4 HLTg) Results: Input OutputAddress Data Address Data2000: 87 3000: 07 3001: 08h) Viva-Voce: i) What are the contents of AH Register, after executing AND AH, F0, Assume that AH contains 98h ? A: 98h ANDed with F0 ,Low order nibble of 98h is masked ,Result is 90h stored at AH Register ii)What is the addressing mode of MOV [3000],AX instruction ? A: Direct addressing modeMICROPROCESSORS LAB 33
    • ELECTRONICS & COMMUNICATION ENGINEERING 3. Operation: Packed BCD to ASCIIa) Aim: - Write an Assembly Language Program in 8086 to convert packed BCDto ASCII.b) Appartus/Software:1. 8086 microprocessor kit/MASM---1 2. RPS (+5V). ---1c) Algorithm: Step1:Load CH register with count value04. Step2:Initialize SI with 2000. Step3:Move value of CH to CL.. Step4:Load the contents of 3000 & 3001 into AX Step5:Load BX with the value in AX. Step6:Anded AX value with 000F. Step7:Ored AL value with 30. Step8:Load AL value to SI location. Step9:Rotate Right the contents of BX by CL number of times. Step10:Load AX with BX contents. Step11:Increment SI Step12:Decrement the CH Step13:Jump if not zero go to step6 Step 14: stop the programMICROPROCESSORS LAB 34
    • ELECTRONICS & COMMUNICATION ENGINEERINGd) Assembly language program before execution:LABLE Mnemonic Operand Comments MOV CH,04 Load CH register with count value04 MOV SI,2000 Initialize SI with 2000. MOV CL,CH Move value of CH to CL. MOV AX,[3000] Load the contents of 3000 & 3001 into AX MOV BX,AX Load BX with the value in AX.UP AND AX,000F Anded AX value with 000F OR AL,30 Ored AL value with 30. MOV [SI],AL Load AL value to SI location. ROR BX,CL Rotate Right the contents of BX by CL number of times. MOV AX,BX Load AX with BX contents. INC SI Increment SI DEC CH Decrement the CH JNZ UP Jump if not zero go to step6 HLT stop the programe) Expected results:Input OutputData Data78 38 37MICROPROCESSORS LAB 35
    • ELECTRONICS & COMMUNICATION ENGINEERINGf) Assembly language program after execution: Address Opcode Mnemonic Operand 1000 B5,04 MOV CH,04 1002 BE,00,20 MOV SI,2000 1005 B1,04 MOV CL,CH 1007 A1,00,30 MOV AX,[3000] 89,C3 MOV BX,AX 100A 25,0F,00 AND AX,000F 100C 100F 0C,30 OR AL,30 1011 88,04 MOV [SI],AL 1013 D3,C8 ROR BX,CL 1015 89,D8 MOV AX,BX 1017 46 INC SI 1018 FE,CD DEC CH 75,F0 JNZ 100C 101A HLT 101Cg) Results: Input OutputAddress Data Address Data2000: 87 3000: 37 3001: 38MICROPROCESSORS LAB 36
    • ELECTRONICS & COMMUNICATION ENGINEERING 4. String Operation: Length of the stringa) Aim:- Write an Assembly Language Program in 8086 to find the length of givenstring, and string ended with 00h.b) Appartus/Software: 1. 8086 microprocessor kit/MASM---1 2. RPS (+5V). ---1c) Algorithm: Step1: Load CL, DL registers with 00H. Step2: Initialise memory pointer SI. Step3: Load Accumulator with data Step4: Compare AL with DL, if it is zero, move CL value to 3000 memory location Step5: if it is not zero, increment count register and memory Pointer To get the total length of the string Step6: Repeat loop until count becomes zero Step7: End of the programd) Assembly language program before execution: Lable Mnemonic Operand Comments MOV DL,00 Load DL with zero MOV CL,00 Load CL with zero MOV SI,1050 Load SI with 1050 UP MOV AL,[SI] AL,[SI] CMP AL,DL Compare AL with DL JZ DOWN If it is zero go to down INC CL increment CL by 1 INC SI increment SI by1 JMP UP Jump to up lable copy the contents of the CL in DOWN MOV [1075],CL to1075 HLT End of the programMICROPROCESSORS LAB 37
    • ELECTRONICS & COMMUNICATION ENGINEERINGe) Expected results: Input Output 58 07 59 61 62 63 64 65 00 All the data in Hexadecimal systemf) Assembly Language Program after execution: Address Opcode Mnemonic Operand 1000 B2,00 MOV DL,00 1002 81,00 MOV CL,00 1004 BE,50,10 MOV SI,1050 1007 8A,04 MOV AL,[SI] 1009 38,D0 CMP AL,DL 100B 74,05 JZ DOWN 100D FE,CL INC CL 100F 46 INC SI 1010 EB,F5 JMP UP 1012 88.0E,75,10 MOV [1075],CL 1016 F4 HLTMICROPROCESSORS LAB 38
    • ELECTRONICS & COMMUNICATION ENGINEERINGg) Results: Input OutputAddress data Address data1050: 76 1075: 071051: 591052: 691053: 621054: 641055: 651056: 331057: 00H) Viva-Voce: i).What is the purpose of SI register in above program? A: SI register used as Memory pointer ii) What is the addressing mode of MOV AL,[SI] instruction? A: Indirect addressing mode: addressMICROPROCESSORS LAB 39
    • ELECTRONICS & COMMUNICATION ENGINEERING 4. String Operation: Reverse ordera) Aim: Write an assembly language program in 8086 to arrange the given array in reverse order.b) Appartus/Software: 1. 8086 microprocessor kit/MASM ---1 2. RPS (+5V). ---1c) Algorithm : Step 1: Load the count register with no of array elements. Step 2: Add the count with source starting address and move it to source register. So the source register now contains address of last array element. Step 3: Load the destination address into destination index. Step 4: Load first byte from source into a register, and load it into a destination Memory location. Step 5: Increment destination address to load next byte of data, and decrement source address for next byte of data. Step 6: Repeat the steps 4 and 5 until the count is zero. Step 7: end the program.MICROPROCESSORS LAB 40
    • ELECTRONICS & COMMUNICATION ENGINEERINGd) Assembly language program before execution: Lable Mnemonic Operand Comments Initialize the memory pointer MOV SI,2050 for data MOV AH,00 Initialize the AH with 00H MOV CL,[2070] Load count into CH register Copy the contents in to CH MOV CH,CL register The data from memory to al UP1 MOV AL,[SI] Register PUSH AX Save AX in to stack INC SI Go to next data DEC CL Decrement the count If count is not equal to zero JNZ UP then go to up1 MOV SI,2050 SI is loaded with 2050 UP1 POP AX Pop the valve from AX Move the Al valve to SI MOV [SI],AL Register INC SI Increment the valve in SI Decrement the cont valve CL DEC CH,CL from CH register If the valve is not equal to zero then jump to UP1,otherwise JNZ UP1 halt HLT End of the programMICROPROCESSORS LAB 41
    • ELECTRONICS & COMMUNICATION ENGINEERINGe) Expected results: Input Output Address Data Address Data2070: 042050: 09 2050: 062051: 08 2051: 072052 07 2052: 082053: 06 2053: 09f) Assembly language program after execution: 2000 BE,50,20 MOV SI,2050 2003 B4,00 MOV AH,00 2005 8A,0E,70,20 MOV CL,[2070] 2009 88,C0 MOV CH,CL 200B 8A,04 MOV AL,[SI] 200D 50 PUSH AX 200E 46 INC SI 200F FE,C9 DEC CL 2011 75,F8 JNZ UP 2013 BE,50,20 MOV SI,2050 2016 58 POP AX 2017 88,04 MOV [SI],AL 2019 46 INC SI 201A FE,CD DEC CH,CL 201C 75,F8 JNZ UP1 201E F4 HLTMICROPROCESSORS LAB 42
    • ELECTRONICS & COMMUNICATION ENGINEERINGg) Results:Input OutputAddress Data Address Data2070: 042050: 09 2050: 062051: 08 2051: 072052 07 2052: 082053: 06 2053: 09H) Viva -Voice:i)what is the addressing mode of MOV DI,2002 instruction?a) Immediate addressing mode.ii)what is the difference between CMP AX,DX and SUB AX,DX instructions? a) In CMP AX, DX instruction, perform AX-DX, but AX is not modified. b) SUB AX, DX instruction performs AX-DX.,result is stored at AX registerMICROPROCESSORS LAB 43
    • ELECTRONICS & COMMUNICATION ENGINEERING 4. String Operation: Deletea) Aim: Write an ALP to delete an element from a String using normal instructions.b) Apparatus/Software: 1.8086 microprocessor kit/MASM-- 1 2.RPS(+5V). -- 1c) Algorithm: Step1.Initialize memory pointer at 2000 location. Step2.Load counter register value. Step3.Initialize memory pointer DI at 3000 memory location. Step4.Copy data from 3000 location to DL . Step5.Subtract count value with DL. Step6.Add data register value to memory location.. Step7.Increment memory location and copy that value to AL. Step8.Again move AL value to SI. Step9.To delete element from string ,repeat this procedure until count becomes zero.d) Assembly Language Program before execution: Lable Mnemonic Operand Comments MOV SI,2000 Load the SI with specified address MOV CL,[SI] Copy data to CL from SI MOV DI,3000 Load the DI with specified address MOV DX,0000 Clear DX register MOV DL,[DI] Copy data to DL from DI SUB CL,DL Subtract content of CL from content of DL ADD SI,DX Add SI with DX UP MOV AL,[SI+1] Increment SI and copy that data to AL MOV [SI],AL Move accumulator content to SI location DEC CL Decrement CL INC SI Increment memory pointer SI JNZ UP If CL is not zero ,repeat loop HLT End of the ProgramMICROPROCESSORS LAB 44
    • ELECTRONICS & COMMUNICATION ENGINEERINGe) Expected result: Input Output 10h 10h 20h 30h 30h 40h 40h 01hf) Assembly language program after execution: Address Opcode Mnemonic Operand 1000 BE,00,20 MOV SI,2000 1003 8A,0C MOV CL,[SI] 1005 BF,00,30 MOV DI,3000 1008 BA,00,00 MOV DX,0000 100B 8A,15 MOV DL,[DI] 100D 28,D1 SUB CL,DL 100F 01,06 ADD SI,DX 1011 8A,44,01 MOV AL,[SI+1] 1014 88,04 MOV [SI],AL 1016 FE,C9 DEC CL 1018 46 INC SI 1019 75,F6 JNZ 1011 101B F4 HLTMICROPROCESSORS LAB 45
    • ELECTRONICS & COMMUNICATION ENGINEERINGg) Results: Input OutputAddress Data Address Data2000: 10H 2000: 10H2001: 20H 2001: 30H2002: 30H 2002: 40H2003: 40H3000: 01Hh) Viva –Voice: i) What are the flags effected after executing ADD SI,DX instruction? A: C,Z,AF,S,P flagsMICROPROCESSORS LAB 46
    • ELECTRONICS & COMMUNICATION ENGINEERING 4. String Operation: Inserta) Aim: Write an ALP to insert an element into a String using normal instructions.b)Appartus/Software: 1.8086 microprocessor kit/MASM-- 1 2.RPS(+5V). --1c)Algorithm: Step1.Initialize memory pointer at 2000 location. Step2.Load counter register value. Step3.Initialize memory pointer DI at 3000 memory location. Step4.Copy data from 3000 location to DL . Step5.Subtract count value with DL. Step6.ADD data register value to memory location.. Step7.Increment memory location and copy that value to AH. Step8.Increment memory pointer DI . Step9.Copy the data from SI memory location AL and AL to DI memory location. Step10.Again increment memory pointer SI Step11.Copy the data from SI memory location to Al. Step13.Copy the data from Ah to SI memory location . Step14.Copy the data from AL to AH. Step15.To insert an element into a string ,repeat this procedure until count becomes zeroMICROPROCESSORS LAB 47
    • ELECTRONICS & COMMUNICATION ENGINEERINGd) Assembly Language Program before execution: Lable Mnemonic Operand Comments MOV SI,2000 Intilise the memory pointer at SI MOV CL,[SI] Load the count into CL register MOV DI,3000 Intilise the memory pointer MOV DX,0000 Intilise DX register with 0000h MOV DL,[DI] Move contents of memory location whose address at Di to DL register SUB CL,DL Substract DL from CL register INC CL CL is incremented by 1 ADD SI,DX Move DX contents to SI register MOV AH,[SI] Move memory data to AH register INC DI Increment DI by 1 MOV AL,[DI] Move Memry data whose address DI to AL register MOV [SI],AL Move AL to memory whose address at SI UP INC SI Increment SI MOV AL,[SI] Move memory data to AL MOV [SI],AH Move AH data to memory MOV AH,AL Move AL data to AH DEC CL CL is decremented by 1 JNZ UP Whether all numbers completed or not. HLT End of the [programMICROPROCESSORS LAB 48
    • ELECTRONICS & COMMUNICATION ENGINEERINGe) Expected result: Input Output 10h 10h 20h 20h 30h 30h 50h 40h 02h 50h 30hf) Assembly language program after execution: Address Opcode Mnemonic Operand 1000 BE,00,20 MOV SI,2000 1003 8A,0C MOV CL,[SI] 1005 BF,00,30 MOV DI,3000 1008 BA,00,00 MOV DX,0000 100B 8A,75 MOV DL,[DI] 100D 28,75 SUB CL,DL 100F FE,C1 INC CL 1011 01,D6 ADD SI,DX 1013 8A,24 MOV AH,[SI] 1015 47 INC DI 1016 8A,05 MOV AL,[DI] 1018 88,04 MOV [SI],AL 101A 46 INC SI 101B 8A,04 MOV AL,[SI] 101D 88,24 MOV [SI],AH 101F 88,C4 MOV AH,AL 1021 FE,C9 DEC CL 1023 75,F5 JNZ UP 1025 F4 HLTMICROPROCESSORS LAB 49
    • ELECTRONICS & COMMUNICATION ENGINEERINGg) Results: Input Output:Address Data Address Data2000: 10h 2000: 10h2001: 20h 2001: 20h2002: 30h 2002: 30h2003: 50h 2003: 40h3000: 02h 2004: 50h3001: 30hH) Viva –Voice: i) What is the difference between MOV AX,SI and MOV AX,[SI] ? A: MOV AX,SI : Moves SI register data to AX register MOV AX,[SI] : Moves contents of memory location whose addresses at SI ,SI+1 to AX registerMICROPROCESSORS LAB 50
    • ELECTRONICS & COMMUNICATION ENGINEERING 4. Operation: sortinga) Aim: Write an Assembly Language Program to find maximum of given ‘n’ 16 bit numbers.b) Appartus /Software: 1. 8086 microprocessor kit/MASM---1 2. RPS (+5V). ---1c) Algorithm:Step1: Load the count into count register.Step2: Load the starting address of array into a register.Step3: Move the first word of data into AX register and second word into another Register DX.Step4: Compare these two words. If the first one, AX is greater than DX, then go toStep5: Get the next word into DX, and repeat the steps 3 and 4 until the countregister is zero.Step6: Load the final maximum 16 bit number which is at AX into memory location.MICROPROCESSORS LAB 51
    • ELECTRONICS & COMMUNICATION ENGINEERINGd) Assembly language program before execution: Lable mnemonic Operand Comments Move the valve in address of MOV CX,[2000] 2000 to register CX MOV DI,0002 Initialize the register ,DI up MOV BX,2002 Initialize the register ,BX Assign BX valve to AX register. MOV AX,[BX] again MOV DX,[BX+DI] Compare the values in CMP AX,DX registers, AX & DX. JNB up Jump if AX is greater DX Move DX register valve to MOV AX,DX AX. ADD DI,+02 Increment DI valve with 02 Decrement CX register valve DEC CX by valve in 2000 JNZ again Jump if CX register MOV [BX+DI],AX HLTe) Expected results:Input OutputData Data3003,3032,9030,0083 9030MICROPROCESSORS LAB 52
    • ELECTRONICS & COMMUNICATION ENGINEERINGf) Assembly language program after execution: Address Opcode Mnemonics Operand 1000 8B0E020 MOV CX,[2000] 1004 BF0200 MOV DI,0002 1007 BB0220 MOV BX,2002 100A 8B07 MOV AX,[BX] 100C 8B11 MOV DX,[BX+DI] 100E 3900 CMP AX,DX 1010 7302 JNB 1014 1012 89D0 MOV AX,DX 1014 83C702 ADD DI,+02 1017 49 DEC CX 1018 75F2 JNZ 100C 101A 8901F4 MOV [BX+DI],AX 101C HLTg) Results:Input OutputAddress Data Address Data1000: 031001: 301002: 321003: 301004: 901005: 831006: 00H) Viva –Voice:1.What is the addressing mode of MOV [BX+DI], AXA.Base plus Index addressing modeMICROPROCESSORS LAB 53
    • ELECTRONICS & COMMUNICATION ENGINEERING 4. String Operation: Move blocka) Aim: Write an Assembly Language Program to transfer string from one location into another location which is in memory.b) Appartus/Software: 1. 8086 microprocessor kit/MASM---1 2. RPS (+5V). ---1c) Algorithm:Step1: Load source register with source address.Step2: Load destination register with destination address.Step3: Choose the direction of transfer by using appropriate instruction.Step4: Move the data until the byte is equal to 99.Step5: when the byte is equal to 99, transfer this 99 to last location.Step6: End the program.d) Assembly language program before execution: Mnemonic Operand comments MOV SI,2000 Load SI with source address MOV DI,2050 Load DI with destination address load CL register with data available at MOV CL,[SI] memory location SI INC SI Increment memory pointer SI Move all bytes form one location to MOVSB another location REPZ Repeat loop until count becomes zero HLT End of the programMICROPROCESSORS LAB 54
    • ELECTRONICS & COMMUNICATION ENGINEERINGe) Expected results:Input OutputAddress Data Address Data2000: 05 2050: 012001: 01 2051: 022002: 02 2052: 032003: 03 2053: 042004: 04 2054: 052005: 05f) Assembly language program after execution: Address Opcode Mnemonic Operand 1000 BE,80,30 MOV SI,2000 1003 BF,50,30 MOV DI,2050 1006 8A,0C MOV CL,[SI] 1008 46 INC SI 1009 F3 REPZ 100A A4 MOVSB 100B F4 HLTg) Results:Input OutputAddress Data Address Data2000: 05 2050: 012001: 01 2051: 022002: 02 2052: 032003: 03 2053: 042004: 04 2054: 052005: 05H) Viva- Voice: 1. What is the purpose of REP instruction? A. Repeat the set of instructions until CX becomes zeroMICROPROCESSORS LAB 55
    • ELECTRONICS & COMMUNICATION ENGINEERING 5.Dos / Bios Programminga) Aim: write an Assembly language program Reading Key board with ECHOb)Appartus/Software:1. 8086 microprocessor kit/MASM---1 2. RPS (+5V). ---1c) Algorithm: Step1. Read keyboard with echo Step2. Extended Key Step3. No, plain ASCII in AL Step4. Read key board again to get extended Key code Step5. Extended Key code is returned in AL alsod) Assembly language program before execution:i) Reading Keyboard with ECHO Label Mnemonic Operand Comments key MOV AL,01 Read keyboard with echo MOV AH,01 INT 21 Extended key JNZ key no, plain ASCII in AL MOV AH,01 extended key code extended key code is returned in INT 21H AL alsoMICROPROCESSORS LAB 56
    • ELECTRONICS & COMMUNICATION ENGINEERINGf) Assembly language program after execution: Address Opcode Mnemonic Operand 1000 B0,01 MOV AL,01 1002 B4,01 MOV AH,01 1004 CD,21 INT 21 1006 75,F8 JNZ 1000 1008 B4,01 MOV AH,01 100A CD,21 INT 21Hii) Reading Keyboard without ECHO Mnemonic Operand Comments Read keyboard MOV AH,08 echo INT 21iii) Video Display Output Mnemonic Operand Comments MOV DL,0D MOV AH,02 INT 21g) Results:Input OutputKey pressed asdfg;lkjhh) viva-voce: i) What is the use of BIOS calls? A: The BIOS interacts with the system hardware, MS DOS kernel accepts requests from the application programs and passes these on to BIOS and sytem hardwareMICROPROCESSORS LAB 57
    • ELECTRONICS & COMMUNICATION ENGINEERING II. Interfacing: 1. Intel 8259 : Interrupt Generationa) Aim: Write an ALP in 8086 to generate an interrupt using Intel 8259.b) Apparatus: 8086 kit ---1 8259 module ---1 Power supply(+Vcc=5)c) Assembly language program before execution:LABEL MNEMONIC OPERAND PUSH CS POP ES CALL FAR CLRDSP MOV AX,0000H MOV DS,AX MOV BX, MOV CX,08H MOV WORD PTR [BX],00H ADD BX,4 LOOP FILL_ CS MOV BX,0200H LEA AX,CS:SERV1 MOV [BX],AX ADD BX,4 LEA AX,CS:SERV2 MOV [BX],AX ADD BX,4 LEA AX,CS:SERV3 MOV [BX],AX ADD BX,4MICROPROCESSORS LAB 58
    • ELECTRONICS & COMMUNICATION ENGINEERING LEA AX,CS:SERV4 MOV [BX],AX ADD BX,4 LEA AX,CS:SERV5 MOV [BX],AXLABEL MNEMONIC OPERAND ADD BX,4 LEA AX,CS:SERV6 MOV [BX],AX ADD BX,4 LEA AX,CS:SERV7 MOV [BX],AX ADD BX,4 LEA AX,CS:SERV8 MOV [BX],AX ADD BX,4 MOV DX,0FF30H MOV AL,13H OUT DX,AL MOV DX,0FF32H MOV AL,60 OUT DX,AL MOV AL,0FH OUT DX,AL MOV AL,00H OUT DX,AL MOV DI,80H MOV SI,OFFSET MSG CALL FAR OP STIBCK: JMP BCKSERV1: MOV DI,080H MOV SI,OFFSET MSG1 CALL FAR OPMICROPROCESSORS LAB 59
    • ELECTRONICS & COMMUNICATION ENGINEERING STI IRETSERV2: MOV DI,080H MOV SI,OFFSET MSG2 CALL FAR OPLABEL MNEMONIC OPERAND STI IRETSERV3: MOV DI,080H MOV SI,OFFSET MSG3 CALL FAR OP STI IRETSERV4: MOV DI,080H MOV SI,OFFSET MSG4 CALL FAR OP STI IRESERV5: MOV DI,080H MOV SI,OFFSET MSG5 CALL FAR OP STI IRETSERV6: MOV DI,080H MOV SI,OFFSET MSG6 CALL FAR OP STI IRETORG 0:6030HSERV7: MOV DI,080H MOV SI,OFFSET MSG7 CALL FAR OP STI IRETSERV8: MOV DI,080HMICROPROCESSORS LAB 60
    • ELECTRONICS & COMMUNICATION ENGINEERING MOV SI,OFFSET MSG8 CALL FAR OP STICSEG ENDSENDSd) Assembly language program after execution:ADDRESS OPCODE MNEMONIC OPERAND 0000:52B0 0E PUSH CS 0000:52B1 07 POP ES 0000:52B2 9A B1 4B 00 F8 CALL 4BB1,F800 0000:52B7 B8 00 00 MOV AX,0000H 0000:52BA 8E D8 MOV DS,AX 0000:52BC BB 02 02 MOV BX,0202H 0000:52BF B9 08 00 MOV CX,08H 0000:52C2 LOOP FILL_CS: 0000:52C2 C7 07 00 00 MOV WORDPTR[BX],00H;0F000H 0000:52C6 83 C3 04 ADD BX,4 0000:52C9 E2 F7 LOOP FILL_CS 0000:52CB BB 00 02 MOV BX,0200H 0000:52CE 2E 8D 06 00 60 LEA AX,CS:SERV1 0000:52D3 89 07 MOV [BX],AX 0000:52D5 83 C3 04 ADD BX,4 0000:52D8 2E 8D 06 08 60 LEA AX,CS:SERV2 0000:52DD 89 07 MOV [BX],AX 0000:52DF 83 C3 04 ADD BX,4 0000:52E2 2E 8D 06 10 60 LEA AX,CS:SERV3 0000:52E7 89 07 MOV [BX],AX 0000:52E9 83 C3 04 ADD BX,4 0000:52EC 2E 8D 06 18 60 LEA AX,CS:SERV4 0000:52F1 89 07 MOV [BX],AX 0000:52F3 83 C3 04 ADD BX,4 0000:52F6 2E 8D 06 20 60 LEA AX,CS:SERV5 0000:52FB 89 07 MOV [BX],AXMICROPROCESSORS LAB 61
    • ELECTRONICS & COMMUNICATION ENGINEERING 0000:52FD 83 C3 04 ADD BX,4 0000:5300 2E 8D 06 28 60 LEA AX,CS:SERV6 0000:5305 89 07 MOV [BX],AX 0000:5307 83 C3 04 ADD BX,4 0000:530A 2E 8D 06 30 60 LEA AX,CS:SERV7 0000:530F 89 07 MOV [BX],AX 0000:5311 83 C3 04 ADD BX,4 0000:5314 2E 8D 06 38 60 LEA AX,CS:SERV8 0000:5319 89 07 MOV [BX],AX 0000:531B 83 C3 04 ADD BX,4 0000:531E BA 30 FF MOV DX,0FF30H 0000:5321 B0 13 MOV AL,13H 0000:5323 EE OUT DX,AL 0000:5324 BA 32 FF MOV DX,0FF32H 0000:5327 B0 60 MOV AL,60H 0000:5329 EE OUT DX,AL 0000:532A B0 0F MOV AL,0FH 0000:532C EE OUT DX,AL 0000:532D B0 00 MOV AL,00H 0000:532F EE OUT DX,AL 0000:5330 BF 80 00 MOV DI,80H 0000:5333 BE 00 52 MOV SI, 5200 0000:5336 9A C0 4F 00 F8 CALL FAR OP 0000:533B FB STI 0000:533C E9 FD FF BCK: JMP BCK 0000:6000 ORG 0:6000H 0000:6000 BF 80 00 SERV1 MOV DI,080H 0000:6003 BE 11 52 MOV SI,OFFSET MSG1 0000:6006 9A C0 4F 00 F8 CALL FAR OP 0000:600B FB STI 0000:600C CF IRET 0000:6008 ORG 0:6008H 0000:6008 BF 80 00 SERV2: MOV DI,8000 0000:600E 9A C0 4F 00 F8 CALL FAR OP FB STIMICROPROCESSORS LAB 62
    • ELECTRONICS & COMMUNICATION ENGINEERING 0000:6013 0000:6014 CF IRET 0000:6010 ORG 0:6010H 0000:6010 BF 80 00 SERV3: MOV DI,080H 0000:6013 BE 33 52 MOV SI,OFFSET MSG3 0000:6016 9A C0 4F 00 F8 CALL FAR OP;F000:1000H 0000:601B FB STI 0000:601C CF IRET 0000:6018 ORG 0:6018H 0000:6018 BF 80 00 SERV4: MOV DI,080H 0000:601B BE 44 52 MOV SI,OFFSET MSG4 0000:601E 9A C0 4F 00 F8 CALL FAR OP;F000:1000H 0000:6023 FB STI 0000:6024 CF IRET 0000:6020 ORG 0:6020H 0000:6020 BF 80 00 SERV5: MOV DI,080H 0000:6023 BE 55 52 MOV SI,OFFSET MSG5 0000:6026 9A C0 4F 00 F8 CALL FAR OP;F000:1000H 0000:602B FB STI 0000:602C CF IRET 0000:6028 ORG 0:602 0000:6028 BF 80 00 SERV6: MOV DI,080H 0000:602B BE 66 52 MOV SI,OFFSET MSG6 0000:602E 9A C0 4F 00 F8 CALL FAR OP;F000:1000H 0000:6033 FB STI 0000:6034 CF IRE 0000:6030 ORG 0:6030H 0000:6030 BF 80 00 SERV7: MOV DI,080H 0000:6033 BE 77 52 MOV SI,OFFSET MSG7 0000:6036 9A C0 4F 00 F8 CALL FAR OP 0000:603B FB STI 0000:603C CF ORG IRETMICROPROCESSORS LAB 63
    • ELECTRONICS & COMMUNICATION ENGINEERING 0:6038H 0000:6038 SERV8: 0000:6038 BF 80 00 MOV DI,080H 0000:603B BE 88 52 MOV SI,OFFSET MSG8 0000:603E 9A C0 4F 00 F8 CALL FAR OP 0000:6043 FB STI 0000:6044 CF IRET CSEG ENDS ENDSe) Observations:After executing the above programThe message 8259 displayed on the address on the address field of the kitOnce the interrupt acknowledge is received displays FE on the data field of the kitFor interrupt no ’0’.MICROPROCESSORS LAB 64
    • ELECTRONICS & COMMUNICATION ENGINEERING 2 .8279 Key board displaya) Aim: Write an ALP in 8086 to display string of characters from left to right (leftentry mode) in output mode.b) Apparatus: 8086 microprocessor kit i. Intel 8279 interfacing module ii. +5v D C supply iii. Serial port communication cablec) Specifications: Keyboard and display interface module must be connectedto 8086 microprocessor kit through a 50 pin connecter.d) Description of module: Intel 8279 is a general purpose programmablekeyboard and display interface I/O device .A keyboard portion can provide scannedinterface to a 64 contact key matrix. Key board entries are debounced and strobed inan 8-character FIFO.The display portion provides a scanned display interface for LED .It has 16*8 displayRam which can be organized into a dual 16*4.Both right entry and left entry displayformats are possible.Circuit DiagramFig: Inter facing Key boardmodule to 8086 MicroprocessorMICROPROCESSORS LAB 65
    • ELECTRONICS & COMMUNICATION ENGINEERINGe) Algorithm: Step1: Load left entry 8 bit character Display Step 2:Load clock dividing factor Step3:Send command word to clear the display Step4:Introduce the wait instruction until the display is cleared Step5:Now send control word for left entry mode. Step6:Load count 8 into the count register for number of character to be. Step7:Initalize the memory pointer to store the character to be displayed. Step8Write a control word for writing to display, auto increment mode. Step9Displays 0 to 7 when both ctrl and sht is not pressed.f) Program requirements:Intel 8279 control wordsControl word for left entry 8bit character display D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 0 0 1 =:09HClock dividing factor D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 0 0 0 1 =31HTo clear the display D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 0 0 0 0 =D0MICROPROCESSORS LAB 66
    • ELECTRONICS & COMMUNICATION ENGINEERINGControl word for 8 characters left entry mode D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 0 0 0 0 =90Hg) Assembly Language Program before execution: Lable Mnemonic Operand Comments Left entry 8 bit character MOV AL.09H display MOV DX,CTRL OUT DX,AL MOV AL,31H clock dividing factor OUT DX,AL MOV AL,D0H clear display OUT DX,AL MOV CX,0FFFFH wait till display is cleared LI: LOOP L1 MOV AL,00H Control word for 8 characters OUT DX,AL Left entry mode and 8 no of MOV AH,08 Characters will be displayed Memory pointer to store 8 no DX,OFFSET of MOV ADDRESS Characters to be displayed MOV AL,90H OUT DX,AL MOV AL,[BX] DX,Address of the MOV data word register OUT DX,AL MOV CX,0FFFFH L2: LOOP L2 INC BX DEC AH JNZ UP MOV CX,0FFFFH L3: LOOP L3 INT 3MICROPROCESSORS LAB 67
    • ELECTRONICS & COMMUNICATION ENGINEERINGh) Expected results:The following are displayed from left to right at stretch of characters at a time.i) Assembly Language Program after execution: Address Opcode Mnemonic Operand 4000 B0 09 MOV AL.09H 4002 BA,02,30 MOV DX,CTRL 4005 EE, OUT DX,AL 4006 B0,31 MOV AL,31H 4008 EE, OUT DX,AL 4009 B0,D0 MOV AL,D0H 400B EE, OUT DX,AL 400C B9,FF,FF MOV CX,0FFFFH 400F E2,FE LOOP L1 4011 B0,00 MOV AL,00H 4013 EE, OUT DX,AL 4014 B4,08 MOV AH,08 DX,OFFSET 4016 BB,00,30 MOV ADDRESS 4019 B0,90 MOV AL,90H 401B EE, OUT DX,AL 401C 8A,07 MOV AL,[BX] 401E BA,00,30 MOV DX, 4021 EE, OUT DX,AL 4022 B9,FF,FF MOV CX,0FFFFH 4025 E2,FE LOOP L2 4027 43 INC BX 4028 FE,CC DEC AH 402A 75,F0 JNZ UP 402C B9,FF,FF MOV CX,0FFFFH 402F E2,FE LOOP L3 4031 CC INT 3MICROPROCESSORS LAB 68
    • ELECTRONICS & COMMUNICATION ENGINEERINGj) Results: after executing the program 8 characters are displayed on 7 segmentdisplay at a stretch of four characters from left to right.K) Viva- Voce: i) . Write an ALP in 8086 to display the string of characters from right to left in Decode mode?A: Lable Mnemonic Operand MOV AL,09 MOV DX,CTRL OUT DX,AL MOV AL,31 OUT DX,AL MOV CX,0FFFFH L1 LOOP1 L1 MOV AL,11H OUT DX,AL MOV AH,08 BX,OFFSET MOV TBL MOV AL,90H OUT DX,AL RPT MOV AL,[BX] MOV DX,DAT OUT DX,AL MOV CX,OFFFFH L2 LOOP2 L2 INC BX DEC AH JNZ RPT MOV CX,0FFFFH L3 LOOP3 L3 INT 3MICROPROCESSORS LAB 69
    • ELECTRONICS & COMMUNICATION ENGINEERINGii).Write a format for Key board/ Display mode set for Intel 8279?MSB LSB 0 0 0 D D K K KHere DD is the display mode and KKK is Keyboard mode D D 0 0 8 8 BIT CHARACTER DISPLAY Left entry 0 1 16 8 BIT CHARACTER DISPLAY Left entry 1 0 8 8 DISPLAY BIT CHARACTER Right entry 1 1 16 8 BIT CHARACTER DISPLAY Right entry K K K 0 0 1 ENCODED SCAN KEBOARD -2KEY LOCKOUT 0 0 0 DECODED SCAN KEBOARD -2KEY LOCKOUT 0 1 0 ENCODED SCAN KEBOARD –NKEY ROLLOVER 0 1 1 DECODED SCAN KEBOARD -2KEY LOCKOUT 1 0 0 ENCODED SCAN KEBOARD -2KEY LOCKOUT 1 0 1 1 1 0 ENCODED SCAN KEBOARD -2KEY LOCKOUT 1 1 1MICROPROCESSORS LAB 70
    • ELECTRONICS & COMMUNICATION ENGINEERING 3. A. Intel 8255: Digital Input Digital Output Module Interfacea) Aim: Write an ALP in 8086 to implement the following by interfacing DIDO(Digital Input and Digital Output) module with 8086 microprocessor using 8255 i) f(A,B,C)=∑(0,1,2,3,4,5,6) ii) 4:1 MULTIPLEXER iii) 3 to8 decoder iv) 2’s complementb) Apparatus:- 1. 8086Microprocessor kit 2. DIDO module 3. 5V DC power supply 4. key boardc) Specifications: - Interfacing kit specifications Vcc +5v IC7404 Vcc +5v Current max 12mAd) Circuit diagramMICROPROCESSORS LAB 71
    • ELECTRONICS & COMMUNICATION ENGINEERINGFig: Interfacing DIDO module to 8086 microprocessorFig: Internal diagram of DIDO (Digital input Digital output module)Circuit Description:The system consists of 8 input SPDT switches which give logic 0 or1 signal to input linesOf port B (bit0-7) the output port A (bit 0-7) is buffered by open collector inverter, the7406.The output LED’s are connected to output bufferMICROPROCESSORS LAB 72
    • ELECTRONICS & COMMUNICATION ENGINEERINGe) Algorithm: i Step 1.Send control word (to make Port B as input port and Port A as output port) to CWR of 8255. Step 2.Read data byte from port B. Step 3.To get the desired output Mask the corresponding bits in data byte except required one by using AND operation. Step 4.Store the result in accumulator. Step 5.Compare accumulator with 03H and 07H. Step 6.To get the desired output for each input go to step 3.f) Program requirements:Port declaration: Intel 8255: Input port : Port B Out put port: Port A:Control word register: D7 D6 D5 D4 D3 D2 D1 1 0 0 0 0 1 0 = 82Hg) Assembly Language Program before execution: LABEL MNEMONIC OPERAND Comments MOV DX,0013 Load the address of control word register (CWR) in to DX MOV AL,82H Initialization of control word OUT DX,AL Load the control word in to CWR UP: MOV DX,0011 Load address of Port B into DX IN AL,DX Read data from Port B AND AL,07 Mask the bits in data byte by using AND operation CMP AL,03 Compare result with 03h JE DOWN If it is equal jump down CMP AL,07 Again compare result with 07h JE DOWN If it equal jump to down MOV AL,01 If it is not equal load AL with o1 MOV DX,0010 Load address of port A in to DX register OUT DX,AL Send 01H to Port A JMP UP For each input condition repeat this procedure DOWN MOV AL,00 Load accumulator with 00 MOV DX,0010 Load address of Port A in to DX register OUT DX,AL Write data into Port A JMP UP For each condition repeat this procedure go up againMICROPROCESSORS LAB 73
    • ELECTRONICS & COMMUNICATION ENGINEERINGh): Expected results: Inputs Output A B C Y 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0i) Assembly Language Program after execution:ADRESS OPCODE LABEL MNEMONICS OPERANDS 2000 BA,13,00 MOV DX,0013 2003 B0,80 MOV AL,82H 2005 EE OUT DX,AL 2006 BA,11,00 UP MOV DX,0011 2009 EC IN AL,DX 200A 24,07 AND AL,07 200C 3C,03 CMP AL,03 200E 74,0D JE 201D 2010 3C,07 CMP AL,07 2012 74,09 JE 201D 2014 B0,01 MOV AL,01 2016 BA,10,00 MOV DX,0010 2019 EE OUT DX,AL 201A E9,E9,FF JMP 2006 201D B0,00 DOWN MOV AL,00 201F BA,10,00 MOV DX,0010 2022 EE OUT DX,AL 2023 E9,E0,FF JMP 2006MICROPROCESSORS LAB 74
    • ELECTRONICS & COMMUNICATION ENGINEERINGj) Results:Input out put(Switch position) LED ON100 1 ” ”101 1 ” ”110 1 ” ”0 00 1 ” ”001 1 ” ”010 1 ” ”1= switch ON for all other combinations the out put is zero0= switch OFF Hence the function is simulatedk) Instructions: 1. Check the polarities of D.C Chord (+5V) before switch ON the power supply to the module as well as to the 8086 microprocessor kit 2. Reset the Microprocessor Kit while connecting the bus between microprocessor and Interfacing Kit 3. Be sure about the direction of the cable 4. Verify all the connections and then execute the program 5. Change the switch positions of I0 to I7 on the interface card and observechange on the output LEDs 0o -07L) Viva –Voice: i) Explain the operation of Digital input and Digital out put? A: Inputs applied by using switches, fed to port B.7404 is an inverter, Inverted the I/P,same I/P,again send through another 7404 inverter Get the value in Port B according to the switch ON and OFF At the out put side anodes of diode connected to the portA if value “0” LED is ON if value “1” LED is OFFMICROPROCESSORS LAB 75
    • ELECTRONICS & COMMUNICATION ENGINEERING ii) What are the address lines are used to select the ports of Intel 8255? A: A1&A0 address linnes are used to select the Ports of Intel 8255 iii) Write the control word for all ports portA,portB,portC as input ports Of the Intel 8255? A: 10011011=9Bh Fig: 4:1 MultiplexerMICROPROCESSORS LAB 76
    • ELECTRONICS & COMMUNICATION ENGINEERING(ii)Algorithm: ii Step 1:- Send control word (to make portB as input port and portA asoutput port)to CWR of Intel 8255 Step 2:- Initialize count as 04 Step 3:-Read the input by using . I5&I4. Step 4:- Input data ANDed with 30H, then get I5&I4 values Step 5:- By manipulating the data get the multiplexer output Step 6:- Now send the value to the portA as output Step 7:-In this way,Repeat the steps 2to5,get the Mux output for any input combination .f) Program requirements:Intel 8255: Port declaration: Input port: Port B Out Put Port: Port A:Control word register: D7 D6 D5 D4 D3 D2 D1 1 0 0 0 0 1 0 = 82HMICROPROCESSORS LAB 77
    • ELECTRONICS & COMMUNICATION ENGINEERINGg) Assembly language program before execution: lableMnemonic Operand Comments MOV DX,0013 Load address of CWR(Control word register) Into DX register MOV AL,82 Send control word to AL OUT DX,AL Control word to CWR of 8255 Back MOV CL,04 Initialize the count MOV DX,0011 Load address of port B into DX IN AL,DX Read data from port A MOV BL,AL Input data load into BL AND AL,30 Input data ANDed with 30h to get desired select lines ROR AL,CL Rotate input data to the right by count MOV CL,AL After rotation the value stored at CL MOV AL,BL Present input data load into CL ROR AL,CL AL rotated right by CL times AND AL,01 AL value ANDed with 01h MOV DX,0010 Load address of port A into DX OUT DX,AL Send AL data to portA JMP BACK If required for another input conditions go to backh) Expected results:Select lines inputs outputS1 S0 I3 I2 I1 I0 (X)0 0 I00 1 I11 0 I21 1 I3MICROPROCESSORS LAB 78
    • ELECTRONICS & COMMUNICATION ENGINEERINGi) Assembly language program after execution: Address Opcode Mnemonic Operand 1000 BA1300 MOV DX,0013 1003 B082 MOV AL,82 1005 EE OUT DX,AL 1006 B104 MOV CL,04 1008 BA1100 MOV DX,0011 EC IN AL,DX 100B 88C3 MOV BL,AL 100C 2430 AND AL,30 100F 1010 D2C8 ROR AL,CL 1012 88C1 MOV CL,AL 1014 88D8 MOV AL,BL 1016 D2C8 ROR AL,CL 1018 2401 AND AL,01 BA1000 MOV DX,0010 101A EE OUT DX,AL 101D E9E5 JMP 1006 101Ej) Results:Select lines inputs outputS1 S0 I3 I2 I1 I0 O00 0 X X X 1 10 0 X X X 0 00 1 X X 1 X 10 1 X X 0 X 01 0 X 1 X X 11 0 X 0 X X 01 1 1 X X X 11 1 0 X X X 0 Note: outputs in the form of LEDs : ‘1’ means LED -ON ‘0’ means LED-OFFMICROPROCESSORS LAB 79
    • ELECTRONICS & COMMUNICATION ENGINEERINGI) Viva –Voice: i). Write the control word format of Intel 8255? A: ii).List the input output instruction in IO mapped IO technique as well as in Memory mapped IO technique? A: Input Instruction IN AL,DX O/P Instruction Out DX,AL iii).What is the purpose of DX register in your program A: DX register used to hold the address of I/O devicesFig: Block diagram of 3 to8 decoderMICROPROCESSORS LAB 80
    • ELECTRONICS & COMMUNICATION ENGINEERINGe) Algorithm: iiiStep 1. Send control word (to make portB as input port and portA asoutput port)toCWR of Intel 8255Step 2.Initialize port A as output portStep 3 .Read data byte from port BStep 4.to get the desired output masking remaining all bit except required one byusing AND operationStep 5.Load accumulator with 01hStep 6. Rotate accumulator by CL timesStep 7.To get the desired output for each input repeat the above procedureStep 8.Stopf) Assembly language program before execution: LABEL Mnemonic operand Comments MOV AL,82 Load ALwith 82 MOV DX,0013 Load address of CWR in to DX register OUT DX,AL Send control word to CWR(control word register of 8255) UP MOV DX,0011 Load address of port into DX IN AL,DX read data from port B AND AL,07 to get desired output,mask remaining bits MOV CL,AL load CL regiester with accumilator value MOV AL,01 load accumilator with 01 ROL AL,CL rotate accumilator with cl times MOV DX,0010 initalise port a as out put port OUT DX,AL write data into port A JMP UP for every desired output do the stepg) Expected results: INPUT OUTPUT A B C D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0MICROPROCESSORS LAB 81
    • ELECTRONICS & COMMUNICATION ENGINEERINGh) Assembly language program after execution: ADRESS OPCODE LABEL MNEMONIC OPERAND 1000 B0,B2 MOV AL,82 1002 BA,13,00 MOV DX,0013 1005 EE OUT DX,AL 1006 BA,11,00 UP MOV DX,0011 1009 EC IN AL,DX 100A 24,07 AND AL,07 100C 88,C1 MOV CL,AL 100E B0,01 MOV AL,01 1010 D2,C8 ROL AL,CL 1012 BA,10,00 MOV DX,0010 1015 EE OUT DX,AL 1016 E9,E0,FF JMP UPi) Results:Input OutputI2 I1 I0 O7 O6 O5 O4 O3 O2 O1O0(Switch status) (LED statuas)0 0 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 1 0 0 0 0 0 0 1 0 00 1 1 0 0 0 0 1 0 0 01 0 0 0 0 0 1 0 0 0 01 0 1 0 0 1 0 0 0 0 01 1 0 0 1 0 0 0 0 0 01 1 1 1 0 0 0 0 0 0 0Note : I7 to I3 are masked • Hence truth table of 3 to 8 decoder verifiedMICROPROCESSORS LAB 82
    • ELECTRONICS & COMMUNICATION ENGINEERINGJ) Viva-Voce: I).In the above program, why AND instruction is taken? A:AND instruction is used to mask the unwanted i/ps ii).what is the function of decoder? A: With the help of 3 select lines / input lines may select one of the the inputs at any timee) Algorithm: iv Step 1:- Load DX register with CWR address 0013h Step 2:- Load the accumulator with control word 82h(specifies portA:o/p port B :i/p) Step 3:- Load the control word into CWR (control word register) Step 4:- Load the DX register with 0011(address of port B) Step 5:- Read input data from port B Step 6:- Perform NOT operation on AL Step 7:- Add the content of AL with 01,get the 2’s complement of the number Step 8: - Repeat the procedure for different input from step 5 to step7f) Assembly language program before execution: Lable Mnemonic Operand Comments MOV DX,0013 Load the address of CWR in DX MOV AL,82 Load control word into AL OUT DX,AL Send control word to CWR START MOV DX,0011 Load the address of Port B into DX IN AL,DX Read input data NOT AL NOT with i/p data ADD AL,01 Add 01h to the contents AL MOV DX,0010 Copy address of port A into DX OUT DX,AL Send the results to Port A Again start the program for new JMP START datag) Expected Results: Input Output 0001 1111 0010 1110 0011 1101MICROPROCESSORS LAB 83
    • ELECTRONICS & COMMUNICATION ENGINEERINGh) Assembly language program after execution: Address Opcode Mnemonic Operand 1000 BA,13,00 MOV DX,0013 1003 B0,82 MOV AL,82 1005 EE OUT DX,AL 1006 BA,11,00 MOV DX,0011 1009 EC IN AL,DX 100A F6,D0 NOT AL 100C 04,01 ADD AL,01 100E BA,10,00 MOV DX,0010 1011 EE OUT DX,AL 1012 E9,F1,FF JMP 1006i) Results:Input Output(switch status) (LED status) I I O O O O O O O O I7 I6 I5 4 3 I2 I1 I0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 0 0 1 0 1 1 1 1 0 1MICROPROCESSORS LAB 84
    • ELECTRONICS & COMMUNICATION ENGINEERING3. b. Intel 8255:Digital to Analog converter Interfacea) Aim:- Write an ALP in 8086 to generate the following wave forms by interfacing DAC(Digital to Analog converter module) to 8086 microprocessor through Intel 8255. i) Square wave form ii) Triangular wave formb)Apparatus: 1. 8086 microprocessor kit 2. DAC interfacing module 3. Power supply +5v dc 4. Key boardc) Specifications:1. Voltage specifications: +12v,-12v&GND from PS-III2. Port A& port B are connected to chanel1`&chanel 23. Reference voltage =8vMICROPROCESSORS LAB 85
    • ELECTRONICS & COMMUNICATION ENGINEERINGd) Circuit diagram:Fig: Interfacing DAC module to 8086 microprocessorCircuit Description:Port A and Port B are connected to channel 1 and channel 2 respectively. Areference voltage of 8V is generated using IC 723 and is given to Vref points of theDAC 0800.The standard output voltage will be 7.98 when ff outputted and will be 0V when 00 isoutputted. The output of DAC0800 is fed to the operational amplifier to get the finaloutput as out and Y outMICROPROCESSORS LAB 86
    • ELECTRONICS & COMMUNICATION ENGINEERING Fig: Internal diagram of DAC modulee(i) Algorithm: To generate rectangular wave form with 50% duty cycleStep1: write control word in the control register(to make all ports O/P ports)Step2: Initialize the AL register with 00h equivalent digital dataStep3: send digital data to the DAC as inputStep4: call the delay sub program (ON time)Step5: initialize AL register with ff h value, send the digital data to the DAC as inputStep6: call the delay subprogram three times(off time)Step7: repeat the step2 to step6 to get continuous wave formf(i) Program requirements:-Intel 8255: Port declaration:Port A, Port B, Port C: O/P PortsControl word format: D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 0 0 =80HMICROPROCESSORS LAB 87
    • ELECTRONICS & COMMUNICATION ENGINEERINGg(i) Assembly Language Program before execution: Lable Mnemonic Operand Comments MOV AL,80 Load AL with 80 Send AL data to CWR of OUT 0013,AL 8255 UP MOV AL,00 Load AL with 00 OUT 0010,AL Send AL data to port A CALL 1025 call the delay program MOV AL,FF Load AL with FFh Send AL data to given OUT 0010,AL port JMP UP Jump to upDelay program Load CX with given MOV CX,0400 value Decrement CX value by UP DEC CX 1 JNZ UP Jump to up if no zero RET(i) Expected results: Fig : square waveMICROPROCESSORS LAB 88
    • ELECTRONICS & COMMUNICATION ENGINEERING t1 = off time =11ms t2= ON time=11 ms% duty cycle ON time = ________ ON time+ OFF time 11ms _______________ =1/2 (11+11)msF=1/t= 1/22ms=45 Hzi (i)Assembly language program after execution: Address Opcode Mnemonic Operand 1000 B080 MOV AL,80 1002 E613 OUT 13,AL 1004 BOFF MOV AL,00 1006 E610 OUT 10,AL 1008 E81A00 CALL 1025 100B B000 MOV AL,FF 100D E610 OUT 10,AL 100F E81300 CALL 1025 1018 EBEA JMP 1004Delay program 1025 B90004 MOV CX,0400 1028 49 DEC CX 1029 75FD JNZ 1028 102B C3 RETMICROPROCESSORS LAB 89
    • ELECTRONICS & COMMUNICATION ENGINEERINGj) (i) : Results : 250 Hz Wave form generatede) (ii).Algorithm : To generate triangular wave formStep1: Initialize the control register with control wordStep2: Place the 00 in the AL registerStep3: Send the register (AL) data to input of DAC moduleStep4: Increment the register data by oneStep5: Compare the increment data with the FF if it is not matches go to the step2Step6: Send FF digital data to the DAC ip via port AStep7: Decrement digital data by one send to portAStep8: Repeat the step7 until data reaches to 00hStep9: if equal then repeat the steps 2 to 8 to getf (ii) Program requirements:Port declaration:Port A, Port B, Port C: O/P PortsControl word format: D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 0 0 =80HMICROPROCESSORS LAB 90
    • ELECTRONICS & COMMUNICATION ENGINEERINGg(ii) Assembly Language Program before execution: Lable Mnemonic Operand Comments Load AL with 80(control word MOV AL,80 specifies all ports out put ports) send AL data to the CWR of OUT 13,AL 8255 Back MOV AL,00 Clear AL register up OUT 10,AL send AL data to given Port A INC AL Increment AL by 1 CMP AL,FF Compare AL data with FF JNZ up Jump if no zero OUT 10,AL send AL data to given port up1 DEC AL Clear AL register OUT 10,AL send AL data to given port CMP AL,00 Compare AL data with 00 JNZ up1 Jump if no zero JMP Back jumph(ii) : Expected Results: t1 =t3 t=t1 +t2 t2=t4 Fig: Triangular Wave FormMICROPROCESSORS LAB 91
    • ELECTRONICS & COMMUNICATION ENGINEERINGi(ii) Assembly Language Program after execution: Address Opcode Mnemonic Operand 1000 B080 MOV AL,80 1002 E613 OUT 13,AL 1004 B000 MOV AL,00 1006 E610 OUT 10,AL 1008 FEC0 INC AL 100A 3CFF CMP AL,FF 100C 75F8 JNZ 1006 100E E610 OUT 10,AL 1010 FEC8 DEC AL 1012 E610 OUT 0010,AL 1014 3C00 CMP AL,00 1016 75F8 JNZ 1010 1018 EBEA JMP 1004j) (ii) Results: t1=5.5ms t2=5.5ms t =t1+t2=11ms f = 1/11ms =90HZ Fig: Triangular Wave FormK). Viva-Voce: i). what is time resolution of DAC 0800 IC? A: 8bits ii).Explain mode 2 operation of 8255? A: In mode ‘0’ all Ports are simple I/0 portsMICROPROCESSORS LAB 92
    • ELECTRONICS & COMMUNICATION ENGINEERING3c.Intel 8255:Analog to Digital converter Interfacea) Aim: Write an ALP in 8086 to convert Analog information into digital by interfacing ADC (Analog to digital converter) module to 8086 microprocessor through Intel 8255.b) apparatus: 1. 8086microprocessor kit 2. ADC interfacing module 3. Power supply.+5V 4. Key boardc) Specifications: 1. Voltage specifications: +5V, GND 2. ADC 0809 IC specifications a).Resolution 8 bit b).Single supplu +5v DC c).Output power 15mW d).Conversion time 100 s e).Total unadjusted error ±½ LSB and ±1 LSB f).Input channels-8 g). Interface type: Paralleld) Circuit diagram:Fig: Interfacing ADC module to 8086 microprocessor through Intel 8255MICROPROCESSORS LAB 93
    • ELECTRONICS & COMMUNICATION ENGINEERING Fig: Internal diagram of ADC modulee) Algorithm: Step 1:Load the control word in to CWR of 8255 to make the PortA , PortC as input Port B as an output port Step 2:Send the dummy word to clear the A/D output Step 3: Send a soft ware pulse to start of conversion(SOC) &ALE Step 4:Read EOC signal if EOC =1,conversion is over, other wise read EOC until get EOC=1 Step 5:Enable the output buffers. Step 6: Read digital data from port A Step 7: End of the program MICROPROCESSORS LAB 94
    • ELECTRONICS & COMMUNICATION ENGINEERINGf) Program requirements: Port declaration: Input ports : Port A, Port C Outputport :portB Control word format: D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 0 0 0 1 =91H Pulse: PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 OE START ALE X X C B A Dummy Word: PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 0 1 1 0 0 1 1 1 =67 1 1 1 0 0 1 1 1 =E7 pulse to ALE&SOC 1 0 0 0 0 1 1 1 =87 1 1 1 0 0 1 1 1 =E7 Circuit description: IN0-IN7 are the Analog inputs to the ADC . These inputs are fed through the 16-way Relimate connector on the bourd. Pin1&pin10 on the ground points & 2-9 are the input channel MICROPROCESSORS LAB 95
    • ELECTRONICS & COMMUNICATION ENGINEERINGg) Assembly language program before execution: Label Mnemonics Operand Comments MOV DX,0013 Load DX with 0013(CWR address MOV AL,91 Load control word OUT DX,AL Sends AL to DX MOV DX,0011 Load port B address into DX MOV AL,67 OUT DX,AL MOV AL,E7 OUT DX,AL MOV AL,87 OUT DX,AL MOV AL,E7 OUT DX,AL Send a pulse for SOC&ALE Back MOV DX,0012 Load port C address into DX IN AL, DX Read EOC through PC0 ANDed with 01 & AL:working for Pc0 AND AL,01 bit CMP AL,01 Compare AL with 01 If conversion is not completed go back JNZ BACK Other wise proceeds MOV DX,0011 Load Port B address into DX MOV AL,67 Send a word to enable the output OUT DX,AL buffer MOV DX,0010 Load Port A address into DX IN AL,DX Read digital data from Port A MOV [2000],AL Load digital data into 2000H locations INT 3 End of the programh) Expected Results: Input Output (Analog) Address data 0V 2000: 00h 1V 2000: 33h 2V 2000: 66 3V 2000: 99h 4V 2000: BBh 5V 2000: FFhMICROPROCESSORS LAB 96
    • ELECTRONICS & COMMUNICATION ENGINEERINGi) Assembly language program after execution: Address Opcode Mnemonics Operand 1000 BA1300 MOV DX,0013 1003 13091 MOV AL,91 1005 EE OUT DX,AL 1006 BA1100 MOV DX,0011 1009 B060 MOV AL,60 100B EE OUT DX,AL 100C B0E0 MOV AL,E0 100E EE OUT DX,AL 100F B080 MOV AL,80 1011 EE OUT DX,AL 1012 BAE0 MOV AL,EO 1014 EE OUT DX,AL 1015 BA1200 MOV DX,0012 1018 EC IN AL,DX 1019 2401 AND AL,01 101B 3C01 CMP AL,O1 101D 75F6 JNE 1015 101F BA1100 MOV DX,0011 1022 B660 MOV AL,60 1024 EE OUT DX,AL 1025 BA1000 MOV DX,0010 1028 EC IN AL,DX 1029 88060020 MOV [2000],AL] 102D CC INT 3j) Results:1) i/p = 0v o/p = 00h2) i/p = 4v o/p = cch3 i/p = 5V o/p =FcHence the interfacing of ADC byusing 8255 PPI is implemented and o/p is verified.K) Viva-Voce: i) What is the importance of 0E,SOC, &EOC of ADC 0809? A: OE: Output enable pin is used to enable the output buffers to get the digital output SOC:Start of conversion signal: is used to start the conversion process ALE: Address latch enable is used to latch the address of the channel ii) How many channels available in ADC 08089,How to access their channels? A: A,B,C lines are used to select one of the 8 channelsMICROPROCESSORS LAB 97
    • ELECTRONICS & COMMUNICATION ENGINEERING 3d. Matrix Keyboard Interfacea) Aim: Write an ALP in 8086 to implement the keyboard (by reading the switch position and the then store the position value.)b) Apparatus: 1. 8086 microprocessor kit 2. Key board interfacing module 3. power supply+5V dc 4. key boardc) Specifications: +5v (Through 8255)d) i) Circuit diagram: Fig: Interfacing KEY BOARD module to 8086 microprocessorMICROPROCESSORS LAB 98
    • ELECTRONICS & COMMUNICATION ENGINEERING(ii). Key board module Fig: Internal diagram of keyboard interfacing moduleCircuit Description:Key board of 20 keys connected in a matrix of 8x3 through 8255 this key boardinterface is nonencode type i.e hardware recognizes the key closure and encode itand encode it.The row of matrix is connected through Port C (bit0,1,2)and columnare returned to port A (bit 0-7) all the 8 bits of input Port A are pulled down by 10Kresistances ,to avoid Any interference. Rows are enabled by sending ‘1’ to thepc2,pc1,pc0 respectively.If any of key connected topc2 ,pc1 , 0V pc 0 through port A ispressed ,the corresponding column bit will be also made to high and will be detectedby program.MICROPROCESSORS LAB 99
    • ELECTRONICS & COMMUNICATION ENGINEERINGe) Algorithm:Main programStep-1: Load DX with address of CWR (control word register).Step-2: load control word into the CWR.Step-3: Enable the first row of the key boardStep-4: BL is initialized 00 for first rowStep-5: Call the key check procedureStep-6:No key is pressed ,enable the second row.Step-7: BL is initialized 08 for second row .Step-8: Call the key check procedure.Step-9: No key is pressed in second row, enable the third row.Step-10: BL is loaded with 10h values for third rowStep-11: Repeat procedure go step3Key check procedure:Step-1: Read data from port AStep-2: Examine if any key is pressed or not with the help of OR operation (00 is ORed with port A contents )Step-3: no key is pressed go to stepStep-4: if key is pressed,CL is initialized to “00”, then rotate the contents of AL examine Carry and increment the CL value, this process continues until no carry comesStep-5: Add the CL value to BLStep-6: Store key position in to the memory locationStep-7: End of the procedureMICROPROCESSORS LAB 100
    • ELECTRONICS & COMMUNICATION ENGINEERINGf) Program requirements:Intel 8255 Port declaration: Input port : Port B Out Put Port: Port C:g) Assembly Language Program before execution: Label Mnemonics Operands Comments Main MOV DX, 0013 Copies 0013 to DX. MOV AL, 90 Copies 90 to AL. OUT DX, AL Sends AL to DX. MOV DX, 0012 Copies 0012 to DX MOV AL, 01 Copies 01 to AL OUT DX, AL Sends AL to DX. MOV BL, 00 Copies 00 to BL CALL sub program Call the sub program MOV DX, 0012 Copies 0012 to DX MOV AL, 02 Copies 02 to AL OUT DX, AL Sends AL to DX. MOV BL, 08 Copies 08 to BL CALL sub program Call the sub program MOV DX, 0012 Copies 0012 to DX MOV AL, 04 Copies 04 to AL OUT DX, AL Sends AL to DX. MOV BL, 10 Copies 10 to BL CALL sub program Call the sub program JMP Main Jump to Mainh) Expected results:key pressed key value stored00 0001 010A 0A10 10 ---- etcMICROPROCESSORS LAB 101
    • ELECTRONICS & COMMUNICATION ENGINEERINGKey checking program: MOV DX, 0010 Copies 0010 to DX INC AL, DX Sends 00 to AL OR AL, 00 OR with AL, 00 JE down If carry =1 go to down MOV CL, 00 Copies 00 to CL Up ROR AL, 01 Rotates right AL once If borrows occurs go to JC loop1 loop1 INC CL Increment CL JMP UP loop1 ADD CL, BL Adds CL with BL: Down MOV [2000], CL Copies CfL to 2000 Returns to the called RET programi) Assembly Language Program after execution: Address Opcode Mnemonics Operands 1000 BA 13 00 MOV DX, 0013 1003 B0 90 MOV AL, 90 1005 EE OUT DX, AL 1006 3A 12 00 MOV DX, 0012 1009 B0 01 MOV AL, 01 100B EE OUT DX, AL 100C B3 00 MOV BL, 00 100E E8 19 00 CALL 102A 1011 BA 12 00 MOV DX, 0012 1014 B0 02 MOV AL, 02 1016 EE OUT DX, AL 1017 B3 08 MOV BL, 08 1019 B8 0E 00 CALL 102A 1010 BA 12 00 MOV DX, 0012 101F B0 04 MOV AL, 04 1021 EE OUT DX, AL 1022 B3 10 MOV BL, 10 1024 B8 03 00 CALL 102A 1027 E9 D6 FF JMP 1000MICROPROCESSORS LAB 102
    • ELECTRONICS & COMMUNICATION ENGINEERINGKey check program: Address Opcode Mnemonics Operands 102A BA 10 00 MOV DX, 0010 102D EC IN AL, DX 102E 0C 00 OR AL, 00 1030 74 11 JE 1043 1032 B1 00 MOV CL, 00 1034 00 C8 ROR AL, 01 1036 72 05 JC 103D 1038 FE C1 INC CL 103A E9 F7 FF JMP 1034 1030 00 90 ADD CL, BL 103F 88 0E 00 20 MOV [2000], CL 1040 C3 RETj) Results: key pressed key value stored memory address value 00 2000: 00 01 2000: 01 02 2000: 02 03 2000: 03 04 2000: 04 05 2000: 05 06 2000: 06 07 2000: 07 08 2000: 08 09 2000: 09 0A 2000: 10 0B 2000: 11 0C 2000: 12 0D 2000: 13 0E 2000: 14 0F 2000: 15k) Instructions: 1. Check the polarities of D.C Chord (+5V) before switch ON the power supply 2. The BUS should be handled carefully i.e. it should be connected in a proper direction other wise pins may gets damaged 3. The current rating of microprocessor power supply should not exceed 1.5Ampsl) Viva-Voce: i).why the power supply is not required for key board module? A.KEYs in KEY board powered by data bitsMICROPROCESSORS LAB 103
    • ELECTRONICS & COMMUNICATION ENGINEERING 4. Intel 8251 Interfacea) Aim: Write an assembly language program in 8086 to test 8251 in the transmitting part.b) Appartus/Software: 1.8086 microprocessor kit/MASM -- 1 2.RPS(+5V). --1 3. 8251 inter facing module ---1c) Assembly Language Program before execution:LABEL MNEMONIC OPERAND MOV AX,00H ;initialisation of stack pointer MOV SS,AX MOV SP,2000H MOV AX,00H MOV DS,AX CLI CLI MOV BX,0202H ;initalisation of interrupt vector PUSH CS POP AX MOV [BX],AX MOV BX,0200H LEA AX,CS:SRVC1 MOV [BX],AX MOV DX,FFD8H ;ICW1 MOV AL,13H OUT DX,AL MOV DX,FFDAH ;ICW2(interrupt vector address) MOV AL,80H OUT DX,AL LABEL MNEMONIC OPERANDMICROPROCESSORS LAB 104
    • ELECTRONICS & COMMUNICATION ENGINEERING MOV AL,0FH OUT DX,AL ;ICW4 MOV AL,0FEH OUT DX,AL ;OCW1(IR0 mask reset) MOV BX,OFFSET MSG ;BX points to message MOV SI,EXT_RAM_LC ;SI points to RAM location; where the characters written to 8251 are stored MOV DX,CTL_8253 ;initialise timer1 in mode2 MOV AL,76H OUT DX,AL MOV DX,TMR1_8253 MOV AL,CNT_BAUD_9600_MODE16 ;load the LSB count in OUT DX,AL ;timer1 count reg MOV AL,CNT_BAUD_9600_MODE16 ;load the MSB count in OUT DX,AL ;timer1 count reg STI ;enable interrupt MOV DX,CTL_8251 ;8251 control port address.Send MOV AL,00H ;0s to guarantee,device is in OUT DX,AL ;the command instruction format. ;Repeat the same four times NOP NOP NOP NOP OUT DX,AL NOP NOPMICROPROCESSORS LAB 105
    • ELECTRONICS & COMMUNICATION ENGINEERING NOP NOP OUT DX,AL MOV DX,CTL_8251 ;send internal resetcommand MOV AL,40H ;to return device to idle state LABEL MNEMONIC OPERAND OUT DX,AL NOP NOP NOP NOP MOV DX,CTL_8251 ;load the mode control word MOV AL,MODE_WORD16 OUT DX,AL NOP NOP MOV DX,CTL_8251 ;load the command word MOV AL,33H ;when CTS* input of 8251 is OUT DX,AL ;asserted low and the 8251 buffer NOP ;is ready for a character,the TxRDY NOP ;pin will go high.Since TxRDY pin ;is connected to the interrupt pin, as soon as TxRDY is set INTR ; enabled and the process jumps to service routine. BACK: NOP JMP BACK SRVC1:MICROPROCESSORS LAB 106
    • ELECTRONICS & COMMUNICATION ENGINEERING MOV AX,0000H MOV DS,AX MOV AL,[BX] ;message address stored in regBX ADD BX,01H ;read the message byte by byte CMP AL,1BH ;check if the byte is a last byte JNZ AHEAD MOV BX,OFFSET MSG ;if yes reinitialise the pointer MOV SI,EXT_RAM_LC ;to message and RAM location JMP SRVC1 AHEAD: MOV DX,DATA_8251 ;if not send the char to data port OUT DX,AL ;of 8251 & also save in ram location MOV CL,AL LABEL MNEMONIC OPERAND MOV AX,00H MOV DS,AX MOV AL,CL MOV [SI],AL ADD SI,01H STI IRETd) Assembly Language Program before execution:ADDRESS OPCODE MNEMONIC OPERAND 0000:4000 B8 00 00 MOV AX,00H ;initialisation of stack pointer 0000:4003 8E D0 MOV SS,AX 0000:4005 BC 00 20 MOV SP,2000H 0000:4008 B8 00 00 MOV AX,00H 0000:400B 8E D8 MOV DS,AX 0000:400D FA CLI 0000:400E FC CLDMICROPROCESSORS LAB 107
    • ELECTRONICS & COMMUNICATION ENGINEERING 0000:400F 0000:400F BB 02 02 MOV BX,0202H ;initalisation of interrupt vector 0000:4012 0E PUSH CS 0000:4013 58 POP AX 0000:4014 89 07 MOV [BX],AX 0000:4016 BB 00 02 MOV BX,0200H 0000:4019 2E 8D 06 76 40 LEA AX,CS:SRVC1 0000:401E 89 07 MOV [BX],AX 0000:4020 BA F0 FF MOV DX,FFF0H ;ICW1 0000:4023 B0 13 MOV AL,13H 0000:4025 EE OUT DX,AL ADDRESS OPCODE MNEMONIC OPERAND 0000:4026 BA F2 FF MOV DX,FFF2H ;ICW2 (interrupt vectoraddress) 0000:4029 B0 80 MOV AL,80H 0000:402B EE OUT DX,AL 0000:402C B0 0F MOV AL,0FH 0000:402E EE OUT DX,AL ;ICW4 0000:402F B0 FE MOV AL,0FEH 0000:4031 EE OUT DX,AL ;OCW1(IR0 mask reset) 0000:4032 BB 00 30 MOV BX,OFFSET MSG ;BX points to message 0000:4035 BE 00 FF MOV SI,0000;FF00H;SI points to RAM locations ;where the characters written to 8251 are stored 0000:4038 BA 06 30 MOV DX,3002H ;initialise timer1 in mode2 0000:403B B0 76 MOV AL,76H 0000:403D EE OUT DX,AL 0000:403E BA 02 30 MOV DX,3002HMICROPROCESSORS LAB 108
    • ELECTRONICS & COMMUNICATION ENGINEERING 0000:4041 B0 0A MOV AL,000AH ;load the LSB count in 0000:4043 EE OUT DX,AL ;timer1 count reg 0000:4044 B0 00 MOV AL,000AH ;load the MSB count in 0000:4046 EE OUT DX,AL ;timer1 count reg 0000:4047 FB STI ;enable interrupt 0000:4048 BA 02 34 MOV Dx,3402H ;8251 control port address.Send 0000:404B B0 00 MOV AL,00H ;0s to guarantee,device 0000:404D EE OUT DX,AL ;the command instruction. format ;Repeat the same four times 0000:404E 90 NOP 0000:404F 90 NOP 0000:4050 90 NOP 0000:4051 90 NOP 0000:4052 EE OUT DX,AL 0000:4053 90 NOP 0000:4054 90 NOP 0000:4055 90 NOP 0000:4056 90 NOP 0000:4057 EE OUT DX,AL 0000:4058 BA 02 34 MOV DX,3402H ;send internal reset command 0000:405B B0 40 MOV AL,40H ;to return device to idle state 0000:405D EE OUT DX,AL 0000:405E 90 NOP 0000:405F 90 NOP 0000:4060 90 NOP 0000:4061 90 NOP 0000:4062 0000:4062 BA 02 34 MOV DX,3402H ;load the mode control word 0000:4065 B0 CE MOV AL,ceH 0000:4067 EE OUT DX,ALMICROPROCESSORS LAB 109
    • ELECTRONICS & COMMUNICATION ENGINEERING 0000:4068 90 NOP 0000:4069 90 NOP0000:406A BA 02 34 MOV DX,3402H ;load the command word0000:406D B0 33 MOV AL,33H ;when CTS* input of 8251 is0000:406F EE OUT DX,AL ;asserted low and the 8251buffer0000:4070 90 NOP ;is ready for a character,theTxRDY0000:4071 90 NOP ;pin will go high.Since TxRDY pin ;is connected to the interrupt pin,as soon as TxRDY is set INTR ;is enabled and the process jumps to service routine.0000:40720000:4072 90 BACK: NOP0000:4073 E9 FC FF JMP BACK0000:4076 SRVC1:0000:4076 B8 00 00 MOV AX,0000H0000:4079 8E D8 MOV DS,AX0000:407B 8A 07 MOV AL,[BX] ;message address stored in reg BX0000:407D 83 C3 01 ADD BX,01H ;read the message byte by byte0000:4080 3C 1B CMP AL,1BH ;check if the byte is a last byte0000:4082 75 09 JNZ AHEAD0000:40840000:40840000:4084 BB 00 30 MOV BX,OFFSET MSG ;if yes reinitialisethepointerMICROPROCESSORS LAB 110
    • ELECTRONICS & COMMUNICATION ENGINEERING0000:4087 BE 00 FF MOV SI,0000:FF00H ;to message and RAM location0000:408A E9 E9 FF JMP SRVC10000:408D BA 00 34 AHEAD: MOV DX,3400H ;if not send the char to data port0000:4090 EE OUT DX,AL ;of 8251 & also save in ram location0000:4091 8A C8 MOV CL,AL0000:4093 B8 00 00 MOV AX,00H0000:4096 8E D8 MOV DS,AX0000:4098 8A C1 MOV AL,CL0000:409A 88 04 MOV [SI],AL0000:409C 83 C6 01 ADD SI,01H0000:409F FB STIe) observations: When the data character is written to 8251 data port .the 8251 resets the Tx RDY out put. the process returns from interrupt routine after write-up data to 8251and waits until 8251 buffer is ready in the main loop.MICROPROCESSORS LAB 111
    • ELECTRONICS & COMMUNICATION ENGINEERING III. Microcontroller 8051 1.Intel 8051 : Reading Parallel Porta) Aim: Write an Assembly Language Program in 8051microcontroller to read the data on parallel port.b) Appartus/Software: 1. 8051 microcontroller kit---1 2. RPS (+5V). ---1c) Algorithm: Step1: Initialize the Port ‘0’ Step2: Load the accumulator with contents of the port ‘0’ Step3: Move the contents of the accumulator into the memory location Step4: Stop the program d) Assembly language program: Mnemonic Operand Comments MOV P0,#FF Initialize the Port ‘0’ MOV A,P0 Load the accumulator with contents of the port ‘0’ MOV 50,A Move the contents of the accumulator into the memory location LCALL 003 Stop the programe) Results:InputD7 D6 D5 D4 D3 D2 D1 D01 1 1 1 0 0 0 0OutputAddress Data50: F0MICROPROCESSORS LAB 112
    • ELECTRONICS & COMMUNICATION ENGINEERING 1. Intel 8051: Reading and writing Parallel Porta) Aim: Write an Assembly Language Program in 8051microcontroller to read and write the data on parallel port.b) Appartus/Software: 1. 8051 microcontroller kit---1 2. RPS (+5V). ---1c) Algorithm: Step1: Initialize the Port ‘0’ Step2: Load the accumulator with contents of the port ‘0’ Step3: Move the contents of the accumulator into the Port1 Step4: Stop the program d) Assembly language program: Mnemonic Operand Comments MOV P0, FF Initialize the Port ‘0’ MOV A,P0 Load the accumulator with contents of the port ‘0’ MOV P1,A Move the contents of the accumulator into the Port1 LCALL 003 Stop the programe) Results:InputAddress Data50: F0OutputD7 D6 D5 D4 D3 D2 D1 D01 1 1 1 0 0 0 0MICROPROCESSORS LAB 113
    • ELECTRONICS & COMMUNICATION ENGINEERING 2. Intel 8051: Timersa) Aim: Write assembly language program in 8051 micro controller to generate a square wave of 50% duty cycle.b) Apparatus: 1. 8051 micro controller kit -1 2. RS 232 Interface card-1 3. Fixed power supply 5v-1 4. CPU-1c) Algorithm:Step1:load the TMOD register indicating timer0,is to be used and mode 0selected.Step2: load registers TL and TH with initial count value.Step3: start the timer.Step 4: keep monitoring the timer flag(TF)with the jump instruction to see if it israised, get out of the loop when TF becomes high.Step5:stop the timer.Step6: clear the TF flag for the next round.Step7: go back to step2 to load TH and TL again.d) Assembly language program Label Mnemonic Operand Comments MOV TMOD,#01 timer0,mode1 selected HERE MOV TLO,#F2 initialize TLD value MOV THO,#FF initialize THD value complement the port1 CPL P1.5 value ACALL DELAY call the sub program SJMP HERE short jump of programMICROPROCESSORS LAB 114
    • ELECTRONICS & COMMUNICATION ENGINEERINGDelay program: . DELAY SETB TRO set the timer flag AGAIN JNB TFO,AGAIN jump if is not set CLR TRO clear TRO flag CLR TFO clear timer flag return to main RET programe) Model graph:f) RESULT: Using the 8051 micro controller program50%duty cycle square waveform generated and observed.g) Viva-Voce:1. Who provides the clock pulses to 8051 timer if CLT=0?2. What is the equivalent of the following instruction?”SETB TCON.6”.MICROPROCESSORS LAB 115
    • ELECTRONICS & COMMUNICATION ENGINEERING 3. Intel 8051: serial communicationa) Aim: Write an ALP using 8051 microcontroller to transfer the message “YES” serially At 9600 baud, 8-bit data, 1 stop bit, do this continuously.b) Apparatus: 1. 8051 micro control kit-1 2. RS 232c interface card-1 3. Fixed power supply-5v-1c) Algorithm:Step1. The TMOD register is loaded with the value 20H, indicating the use of timer1 in mode2 to set the baud rate.Step2. The TH1 is loaded with one of the value set the baud rate foe serial data transfer.Step3. The SCON register is loaded with the value of 50H, indicating serial mode1 where an 8bit data is framed with start and stop bits.Step4. TR1 is set to 1 to start timer 1.Step5. TI is cleared by the “CLRTI” instruction.Step6. The character byte to be transferred serially is written in to the SBUF register.Step7. The TI flag bit is monitored with the use of the instruction to see if the character has been transferred completely.Step8. To transfer the next character goes to step5.MICROPROCESSORS LAB 116
    • ELECTRONICS & COMMUNICATION ENGINEERINGd) Assembly language program: Label Mnemonic operand Comments Initialize the TMOD MOV TMOD,#20H register MOV TH1,#--3 set the band rate to 9600 Initialize the SCON MOV SCON,#50 register SETB TR1 set the TR flag AGAIN MOV A,#"Y" load they ASCII value ACALL TRANS call the sub-program MOV A,#"E" load e ASCII value ACALL TRANS call the sub program MOV A,#"S" load the s ASCII value ACALL TRANS call the subprogram SJMP AGAIN repeat the same process TRANS MOV SBUF,A Initialize the buffer register HERE JNB TI,HERE check the TI flag CLR TI clear TI RET return to maine) Results: using the 8051 micro controller program transfers the message “YES”serially at 9600 band rate.f) Viva-Voce:1. Which timer of the 8051 is used for band rate programming?2. Which mode of the timer is used for band rate programming?3. Is SMOD bit high or low when the 8051 is powered up?MICROPROCESSORS LAB 117
    • ELECTRONICS & COMMUNICATION ENGINEERING 4. Intel 8051: Understanding of memory access of 00 to FFa) Aim: Write an ALP in 8051 micro controller to transfer a block of data from one memory location to another memory location.b) Apparatus: 8051 micro controller kit -1 RS 232 Interface card -1 Monitor -1 Keyboard -1c) Before execution of the program: LABEL MNEMONIC COMMENTS MOV R0,#10 ; Initialize the source address MOV R1,#31 ; Initialize destination address MOV B,@R0 ; Transfer the count into B register GO INC R0 ; Increment source pointer MOV A,@R0 ; Transfer the first number into ACC MOV @R1,A ; Transfer ACC data to destination INC R1 ; Increment destination pointer DJNZ B,GO ; Decrement counter and repeat same process LCALL 0003 ; Stop the programd) Expected results:Before execution of program After execution of programInput: 10 : 44 10 : 04 11 : AA 11 : AA 12 : C2 12 : BB 13 : 12 13 : CC 14 : 13 14 : DDMICROPROCESSORS LAB 118
    • ELECTRONICS & COMMUNICATION ENGINEERINGOutput: 31 : 66 ` 31 : AA 32 : 00 32 : BB 33 : 03 33 : CC 34 : 12 34 : DDe) Viva –Voce:1. What is the size of flag register in the 8051?A. The size of the flag register in the 8051 is 8 bits.2. Which bits of the PSW register are user-definable?A. The PSW.5 and PSW.1 bits are general purpose status flag bits and can be usedby the programmer for any purpose. In other words, they are user definable.MICROPROCESSORS LAB 119
    • ELECTRONICS & COMMUNICATION ENGINEERING 5. Intel 8051: Using External Interrupta) Aim: write an ALP in 8051 to allow the external interrupt INT 1b) Apparatus: 1. 8051 kit- 1 2. RPSs-5v – 1c) Assembly language program:-LABEL Mnemonic Operand Task Org 0000h LJMP again ; by pass interrupt vector task; -- ISR for hardware interrupt INT1 to turn on the led ; INT1 ISR; Turn on LED Org 0013h SETB P1.3 MOV R3, #255;BACK: DJNZ R3,BACK ; keep LED on for a whole CLR P1.3 ; turn off the LED;-- Main program for initialization ORG 30hMAIN: MOV IE, #10000100B ; enable external INT1HERE: SJMP HERE ; stay here until get interrupted ENDD) Result: 1. when key is pressed, LED is ON 2. When key is opened, Led is OFFe) viva-voce:1. List the external hardware interrupts in the 8051?Ans: INT0 & INT12. What are the pins allocated for INT0&INT1?Ans: pin 12 & pin 13 of Intel 8051MICROPROCESSORS LAB 120
    • ELECTRONICS & COMMUNICATION ENGINEERING 6. Intel 8051: Using Instructions Rotatea) Aim: write an ALP in 8051 micro controller to rotate a given byte 3 times and 1’s complement the MSB bit of the same byte after rotation.b) Apparatus: 8051 micro controller kit -1 RS 232 Interface card -1 CPU -1 Monitor -1 Keyboard -1c) Assembly Language Program: MNEMONIC OPERANDS TASK MOV R0,#10 ; Initialize the source address MOV A,@R0 ; Transfer the first number into accumulator RL A ; Rotate accumulator one time RL A ; Rotate accumulator one time RL A ; Rotate accumulator one time RL A ; Rotate accumulator one time CPL E7 ; Complement the MSB bit MOV @R0, A ; Transfer ACC data to destination LACALL 0003 ; Stop the programd) Expected results:Before execution of program After execution of programInput: 10 : 00 10 : 32Output: 10 : 12 ` 10 : 11MICROPROCESSORS LAB 121
    • ELECTRONICS & COMMUNICATION ENGINEERINGe) Viva-Voce:1. What is the advantage in using the EQU directive in detecting a constant value?A. Assume that there is a constant used in many different places in the program, andthe programmer wants to change its value throughout. By the use of EQU one canchange it once and the assembler will change all of its occurrences, rather thansearch the entire program trying to find every occurrence.2. Which program produces the “obj” file?A. Assembler program.MICROPROCESSORS LAB 122
    • ELECTRONICS & COMMUNICATION ENGINEERINGAdditional Experiments1. Intel 8255: Stepper motor Module Interfacea) Aim: Write an ALP in 8086 to rotate the stepper motor for two rotations in clockwise directions and one rotations in anti-clockwise direction repeatively (or) continuously.By interfacing stepper motor control module to 8086 microprocessor through Intel8255 .b) Apparatus: 1. 8086 Microprocessor kit -1 2. Keyboard -1 3. Fixed power supply (D.C) 5V,1.5A -1 4. Fixed power supply (D.C) 12V,1.5A -1 5. Stepper motor module -1 6. Stepper motor 12V -1c) Specifications:1) Permanent magnet D.C. stepping motors two phase bifillar wound.2) Step angle :1.80 ± 5% non cumulative .3) step/revolution :200 .d) Circuit Diagram:Fig: Interfacing stepper motor module to8086 microprocessorMICROPROCESSORS LAB 123
    • ELECTRONICS & COMMUNICATION ENGINEERING Fig: Internal diagram of stepper motor control modulee) Program requirements:Intel 8255 Port declaration: Port C :output Control word :80H Command words: To activate the windings Clock wise direction Anti clock wise direction 77 h EE h BB h DD h DD h BB h EE h 77 hf) Algorithm:Step 1:write the control word in the control register.Step 2:locate the forward revolution count value in the count register.Step 3:activate the armature 1 of the stepper motor.Step 4:call the delay sub program.Step 5:activate the armature2 of the stepper motor.Step 6:call the delay sub program.Step 7:activate the armature 3 of a stepper motorStep 8:call the delay sub program.Step 9:activate the armature 4 of a stepper motorStep 10: call the delay sub program.Step 11:repeat the step 3 to step 10 until count value equal to zero.Step 12:activate the armature 4 of the stepper motor.Step 13: call the delay sub program.Step 14: activate the armature 3 of a stepper motor.Step 15: call the delay sub program.Step 16:activate the armature2 of the stepper motor.Step 17: call the delay sub program.Step 18:activate the armature 1 of the stepper motor.Step 19: call the delay sub program.Step 20:repeat the step 3 to step 10 until count value equal to zero.Step 21:repeat the step 1 to step 20.Note: count may vary in clockwise and anticlockwise directionMICROPROCESSORS LAB 124
    • ELECTRONICS & COMMUNICATION ENGINEERINGg) Assembly Language Program before execution: label operand comment mnemonic MOV DX,0013 :select the CW address MOV AL,80 ;initialize with control word ;locate control word in CW OUT DX,AL register back : MOV CL,64 ;initializing with count value go MOV DX,0012 ;choose the port c address MOV AL,77 ;initialize AL with 77H OUT DX,AL ;send AL data to port C CALL delay ;call the delay subprogram MOV AL,BB ;initialize AL with BBH OUT DX,AL ;send AL data to port C CALL delay ;call the delay subprogram MOV AL,DD ;initialize AL with DDH OUT DX,AL ;send AL data to port C CALL delay ;call the delay subprogram MOV AL,EE ;initialize AL with EEH OUT DX,AL ;send AL data to port C CALL delay ;call the delay subprogram DEC CL ;decrement the counter JNE go ;if not equal go to go label MOV CH,32 :initialize the counter value. xyz MOV DX,0.012 ;choose the port c MOV AL,EE ;initialize AL with EEH OUT DX,AL ;send AL data to port C CALL delay ;call the delay subprogram MOV AL,DD ;initialize AL with 77H OUT DX,AL ;send AL data to port C CALL delay ;call the delay subprogram MOV AL,BB ;initialize AL with 77H OUT DX,AL ;send AL data to port C CALL delay ;call the delay subprogram MOV AL,77 ;initialize AL with 77H OUT DX,AL ;send AL data to port C CALL delay ;call the delay subprogram DEC CH ;decrement the counter JNE xyz ;if not equal goto xyz label JMP back ;jump to back labelDelay program Labl e Mnemonics Operand Comments MOV BX,FFFF ;initialize the count value. abc: DEC BX ;decrement the register ;if it is not equal to zero goto JNE abc abc label RET ;return to the main programMICROPROCESSORS LAB 125
    • ELECTRONICS & COMMUNICATION ENGINEERINGh) Expected Results:When windings are excited in proper manner, stepper motor may rotate two times inclock wise and one time in anti clock wise direction this process repeat.i) Assembly Language Program after execution: Address Opcode Mnemonic Operand 1000 BA,13,00 MOV DX,0013 1003 B0,80 MOV AL,80 1005 EE OUT DX,AL 1006 B1,64 MOV CL,64 1008 BA,12,00 MOV DX,0012 100B B0,77 MOV AL,77 100D EE OUT DX,AL 100E EB,EF,0F CALL 104B 1011 B0,B8 MOV AL,BB 1013 EE OUT DX,AL 1014 EB,E9,0F CALL delay 1017 B0,DD MOV AL,DD 1019 EE OUT DX,AL 101A E8,E3,0F CALL 104B 101D B0,DD MOV AL,EE 101F EE OUT DX,AL 1020 EE,DD,0F CALL 104B 1023 FE,C9 DEC CL 1025 75,E1 JNE 1008 1027 85,32 MOV CH,32 1029 BA,12,00 MOV DX,0.012 102C B0,EE MOV AL,EE 102E EE OUT DX,AL 102F E8,CE,0F CALL 104B 1032 B0,DD MOV AL,DD 1034 EE OUT DX,AL 1035 E8,C8,0F CALL 104B 1038 B0,BB MOV AL,BB 103A EE OUT DX,AL 103B E8,C2,0F CALL 104B 103E B0,77 MOV AL,77 1040 EE OUT DX,AL 1041 E8,BC,0F CALL 104B 1044 FE,CD DEC CH 1046 75,E1 JNE 1029 1048 E9,BB,FE JMP 1006MICROPROCESSORS LAB 126
    • ELECTRONICS & COMMUNICATION ENGINEERINGDelay program: Address Opcode Mnemonic Operand 104B BB,10,4B MOV BX,FFFF 104E 4B DEC BX 104F 75,F0 JNE 104E 1051 C3 RETj) Results: After executing the program, first stepper motor is rotated two times inclock wise direction and then one times in anti clock wise direction and repeats thesame until microprocessor kit is resetted.k) Viva-Voce:i) What is the step angle of 4 winding stepper motor?A:1.8 degreesii) Write the control word for 8255 to make all the ports are output portsA: 80hMICROPROCESSORS LAB 127
    • ELECTRONICS & COMMUNICATION ENGINEERING 2. Intel 8255: Traffic Light control Module Interfacea) Aim: Write an assembly language program to implement a simple traffic byinterfacing traffic control module to 8086 through Intel 8255. Assume it is simpletraffic and allows east to west and west to east and not allow north to south andsouth to north after delay allow the traffic from north to south or viceversa,then notallow the traffic from East to West or vice versab) Apparatus: 1.8086 microprocessor kit --1 2. Key board --1 3. RPS +5v --1 4. Traffic light interfacing module --1c) Specifications: traffic light kit Vcc +5v Current max 1.5Amps IC 74LS 244 (Tri- State buffer) Vcc +5v Current max.25mAd) Circuit diagram: Fig: Inter facing traffic control module to 8086 MicroprocessorMICROPROCESSORS LAB 128
    • ELECTRONICS & COMMUNICATION ENGINEERING Fig: Traffic light control modulee) Program requirement:Port declarationPortA, portB, portc: output portsControl word register: D7 D6 D5 D4 D3 D2 D1 1 0 0 0 0 0 0 = 80HCommand words: To enable the Yellow, Red, Green, LEDs BF h: EE h: FB h: FF h: FC h:f) Algorithm:Step 1: write the control word in the control register.Step 2.Intialise port A,portB,portc as output ports.Step3. Allow the traffic from east to west and west to east.Step4.before allowing the traffic from north to south south to north Enable all yellow lights.Step5.then allow the traffic from north to south, not allow the traffic from east to west or vice versa.Step6.for each time repeat above procedure means go to step3.MICROPROCESSORS LAB 129
    • ELECTRONICS & COMMUNICATION ENGINEERINGg) Assembly Language Program before execution: Lable Mnemonics Operand Comments MOV DX,0013 Initialize control word register MOV AL,80 OUT DX,AL UP MOV DX,0010 initialize port A as output port MOV AL,BF Load AL with BFH OUT DX,AL write AL in to port A MOV DX,0011 initialize portB as output port MOV AL,BF Load AL with BFH OUT DX,AL write AL in to port B MOV DX,0012 initialize portC as output port MOV AL,FF Load AL with FFH OUT DX,AL wrte AL in to port C CALL DELAY1 Wait for some time MOV DX0010 initialize port A as output port MOV AL,EE Load AL with EEH MOV DX,0011 Initialize port B as output port MOV AL,EE Load AL with EEH OUT DX,AL write AL in to port B MOV DX,0012 initialize portC as output port MOV AL,FC Load AL with FCH OUT DX,AL write AL in to port C CALL DELAY2 Wait for some time MOV DX,0010 initialize port A as output port MOV AL,FB Load AL with FBH OUT DX,AL write AL in to port A MOV DX,0011 initialize portB as output port MOV AL,FB Load AL with FBH OUT DX,AL write AL in to port B MOV DX,0012 initialize portC as output port MOV AL,F0 Load AL with F0H OUT DX,AL write AL in to port C CALL DELAY1 Wait for some time MOV DX,0010 initialize port A as output port MOV AL,EE Load AL with EEH OUT DX,AL write AL in to port B MOV DX,0011 initialize portB as output port MOV AL,EE Load AL with EEH OUT DX,AL write AL in to port B MOV DX,0012 initialize portC as output port MOV AL,FC Load AL with FCH OUT DX,AL write AL in to port C CALL DELAY2 Wait for some time JMP UP jump to up labelMICROPROCESSORS LAB 130
    • ELECTRONICS & COMMUNICATION ENGINEERINGh) Expected results:Allow traffic from east to west vice versa, not allow from north to south vice versaafter some time allowing the traffic from south to north vice versa, not allow the trafficfrom east to west vice versa. i) Assembly Language Program After execution: 2000 BA,13,00 MOV DX,0013 2003 B0,80 MOV AL,80 2005 EE OUT DX,AL 2006 BA,00,00 MOV DX,0010 2009 B0,BF MOV AL,BF 200B EE OUT DX,AL 200C BA,11,00 MOV DX,0011 200F B0,BF MOV AL,BF 2011 EE OUT DX,AL 2012 BA,12,00 MOV DX,0012 2015 B0,FF MOV AL,FF 2017 EE OUT DX,AL 2018 E8,E5,0F CALL 3000 201B BA,10,00 MOV DX0010 201E BE,EE MOV AL,EE 2020 BA,11,00 MOV DX,0011 2023 B0,EE MOV AL,EE 2025 EE OUT DX,AL 2026 BA,12,00 MOV DX,0012 2029 B0,FC MOV AL,FC 202B EE OUT DX,AL 202C E8,D1,0F CALL 4000 202F BA,10,00 MOV DX,0010 2032 B0,FB MOV AL,FB 2034 EE OUT DX,AL 2035 BA,11,00 MOV DX,0011 2038 B0,FB MOV AL,FB 203A EE OUT DX,AL 203B BA,12,00 MOV DX,0012 203E B0,F0 MOV AL,F0 2040 EE OUT DX,AL 2041 E8,BC,0F CALL 3000 2044 BA,10,00 MOV DX,0010 2047 B0,EE MOV AL,EE 2049 EE OUT DX,AL 204A BA,11,00 MOV DX,0011 204B B0,EE MOV AL,EE 204F EE OUT DX,AL 2050 BA,12,00 MOV DX,0012 2053 BO,FC MOV AL,FC 2055 EE OUT DX,AL 2056 E8,A7,0F CALL 4000 2059 E9,AA,FF JMP UPMICROPROCESSORS LAB 131
    • ELECTRONICS & COMMUNICATION ENGINEERINGDelay program before execution:Delay1 Lable mnemonics Operand Comments MOV CX,F000 Load CX with F000 UP1 DEC CX decrement count by 1 JNZ UP1 if it is not zero go to up1 lable RET Return to main programDelay2 Lable mnemonics Operand Comments MOV CX,5000h Load CX with 5000h UP1 DEC CX decrement count by 1 JNZ UP1 if it is not zero go to up1 lable RET Return to main programDelay program after execution:Delay 1 3000 B9,F0,00 MOV CX,F000 3003 49 DEC CX 3004 75,FB JNZ 3003 3006 C3 RETDelay 2 4000 B9,50,00 MOV CX,5000 4003 49 DEC CX 4004 75,FB JNZ 4003 4006 C3 RETj) Results: After executing the program East, West : green lights ON: allow the traffic South, north: red ON : not allow the traffic After some time all sides: yellow ON Then East, West: red ON South, north: green ON Then yellow ON all sides, this process is repeated successfully traffic control is implementedk) Viva-Voce:i) What are the instructions are used for accessing I/O devices?A:IN, OUT instructions.ii) What is difference between direct port addressing and indirect port Addressing technique?A: Direct port addressing IN AL, 90h 90h: address of I/O device Indirect port addressing MOV DX, 9000h,IN AL, DX, 9000h is the address of the I/O.MICROPROCESSORS LAB 132
    • ELECTRONICS & COMMUNICATION ENGINEERING Appendices1.8086 Microprocessor ArchitectureIntel 8086 MicroprocessorIt has 16-bit Arithmetic Logic Unit, 16-bit data bus (8088 has 8-bit data bus),20-bitaddress bus ,It can access 1,048,576 = 1 meg memory locations. The addressrefers to a byte in memory.Bytes at even addresses come in on the low half of thedata bus (bits 0-7) and bytes at odd addresses come in on the upper half of the databus (bits 8-15).The 8086 can read a 16-bit word at an even address in one operationand at an odd address in two operations. The 8088 needs two operations in eithercase.The least significant byte of a word on an 8086 family microprocessor is at thelower address.Intel 8086 Microprocessor Signals and Pin Diagram:MICROPROCESSORS LAB 133
    • ELECTRONICS & COMMUNICATION ENGINEERING8086 Architecture:The 8086 has two parts, the Bus Interface Unit (BIU) and the Execution Unit (EU).,•The BIU fetches instructions, reads and writes data, and computes the ,20-bitaddress,• The EU decodes and executes the instructions using the 16-bit ALU.The BIU contains the following registers: IP - the Instruction Pointer,CS - the CodeSegment Register,DS - the Data Segment Register,SS - the Stack SegmentRegister,ES - the Extra Segment Register,The BIU fetches instructions using the CSand IP, written CS:IP, to contractthe 20-bit address. Data is fetched using a segment register (usually the DS)and an effective address (EA) computed by the EU depending on the addressingmode.The EU contains the following registers:AX - accumulator register,BX – baseregister,CX – counter register,DX – data register,SP – stack pointer,BP – basepointer,SI-source index register,DI-destination index registerMICROPROCESSORS LAB 134
    • ELECTRONICS & COMMUNICATION ENGINEERING8086 programming Model: 8086 Programmer’s Model ES Extra Segment BIU registers (20 bit adder) CS Code Segment SS Stack Segment DS Data Segment IP Instruction Pointer EU registers AX AH AL Accumulator BX BH BL Base Register CX CH CL Count Register DX DH DL Data Register SP Stack Pointer BP Base Pointer SI Source Index Register DI Destination Index Register FLAGS Registers:Registers are in the CPU and are referred to by specific names 1.Data registers:Hold data for an operation to be performed , There are 4 data registers (AX, BX, CX, DX) 2.Address registers:Hold the address of an instruction or data element, Segment registers (CS, DS, ES, SS),Pointer registers (SP, BP, IP),Index registers (SI, DI) 3.Status register:Keeps the current status of the processor ,On an IBM PC the Status register is called the FLAGS register. In total there are fourteen 16-bit registers in an 8086 1. Data Registers:Instructions execute faster if the data is in a register, Low and High bytes of the data registers can be accessed separately AH, BH, CH, DH are the high bytes,AL, BL, CL, and DL are the low bytes .Data Registers are general purpose registers but they also perform special functionsAX :Accumulator Register :Preferred register to use in arithmetic, logic and data transfer instructions because it generates the shortest Machine Language Code,Must be used in multiplication and division operations,Must also be used in I/O operations, Must be used in multiplication and division operations,Must also be used in I/O operationsMICROPROCESSORS LAB 135
    • ELECTRONICS & COMMUNICATION ENGINEERINGBX :Base Register:Also serves as an address register,Used in array operations,Usedin Table Lookup operations (XLAT)CX :Count register:Used as a loop counter,Used in shift and rotate operations.DX :Data register :Used in multiplication and division,Also used in I/Ooperations,Contain theoffset addresses of memory locations,Can also be used in arithmetic and otheroperations,2.Address registers:SP: Stack pointer :Used with SS to access the stack segmentBP: Base Pointer :Primarily used to access data on the stack,Can be used to accessdata in other segmentsSI: Source Index register :is required for some string operations,When stringoperations are performed, the SI register points to memory locations in the datasegment which is addressed by the DS register. Thus, SI is associated with the DSin string operations.DI: Destination Index register :is also required for some string operations.When stringoperations are performed, the DI register points to memory locations in the datasegment which is addressed by the ES register. Thus, DI is associated with the ESin string operations.The SI and the DI registers may also be used to access data stored in arrays,AreAddress registersStore the memory addresses of instructions and data.3.Status Register:Conditional flags:They are set according to some results of arithmetic operation. Youdo not need to alter the value yourself.Control flags: Used to control some operations of the MPU. These flags are to be setby you in order to achieve some specific purposes.Flag O D I T S Z A P CBit no. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0CF (carry) Contains carry from leftmost bit following arithmetic, also contains last bitfrom a shift or rotate operation • OF (overflow) Indicates overflow of the leftmost bit during arithmetic. • DF (direction) Indicates left or right for moving or comparing string data. • IF (interrupt) Indicates whether external interrupts are being processed or ignored. • TF (trap) Permits operation of the processor in single step mode. • SF (sign) Contains the resulting sign of an arithmetic operation (1=negative) • ZF (zero) Indicates when the result of arithmetic or a comparison is zero. (1=yes) • AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized arithmetic. • PF (parity) indicates the number of 1 bits that result from an operation.MICROPROCESSORS LAB 136
    • ELECTRONICS & COMMUNICATION ENGINEERINGMemory Organization:Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1 meg ofaddressable memory,Addresses are expressed as 5 hex digits from 00000 – FFFFF.Problem: But 20 bit addresses are TOO BIG to fit in 16 bit registers!Solution: Memory Segment:Block of 64K (65,536) consecutive memory bytes,Asegment number is a 16 bit number,Segment numbers range from 0000 toFFFF,Within a segment, a particular memory location is specified with an offset,Anoffset also ranges from 0000 to FFFF.Segment:Offset AddressLogical Address is specified as segment:offset,Physical address is obtained byshifting the segment address 4 bits to the left and adding the offset address,Thus thephysical address of the logical address A4FB:4872 is A4FB0+ 4872A9822A computer’s instructions are made up of two parts. The first is the OP Code oroperation code. This defines the action the instruction is to perform. The OP code isa verb, a word that indicates that something is being done. Examples are move,compare, add, jump. All instructions have at least an OP code if nothing else.The second part of the instruction is optional, depending upon the OP code. Forinstance, for the instruction HALT, there are no arguments in the second part of theinstruction because no more information is needed to do the HALT function. SomeOP codes have one secondary argument, some two. These can be a GeneralPurpose Register (GPR), a location in memory, an I/O device, an interrupt number,or other things that make sense to the OP code.There are four ways in system design: • Register to Register – Both the source data and the target location for the destination data are in registers, and memory isn’t involved. Example: MOV AX, BX. The 8086 provides this type of addressing. • Register to Memory – The source data is located in a GPR, and the destination is a memory location. Example: MOV [BX], AX. The 8086 provides this type of addressing. • Memory to Register – The source data is in located in memory, and ends up in a GPR. Example: MOV AX,[BX]. The 8086 supports this type of addressing. • Memory to Memory – Both the source data and destination data are in memory. The 8086 does not support this method.Memory locations are involved in instructions under two conditions. One is that thememory location contains a data item needed by the instruction (source), or alocation where an item will be placed as a result of the instruction (destination). Theother involves a location to which a control instruction will direct the system whenlooking for instructions out of sequence. This involves jumps, calls, returns, andinterrupts.MICROPROCESSORS LAB 137
    • ELECTRONICS & COMMUNICATION ENGINEERING 8086 has a segmented memory architecture. The entire physical memory is logicallydivided into 64K-byte segments. Segments can be between 16 bytes and 64K bytesin size. A location in memory is determined by adding two values together. The first isthe contents of the segment register involved. The second is an offset valuedetermined by the contents of the GPR’s or other values provided in the instructionsyntax. The two are added together in an offset method, where the 16-bit offset valueis added to the 16-bit segment value which has been set four bit positions to the left.This generates a 20-bit physical address that the processor provides on its pins forthe memory addressing circuitry.There are four segment types in the system: • Code Segment – This segment contains the instructions to be executed. • Data Segment – This segment contains data items required by the program. • Extra Segment – This is essentially a second Data Segment and contains data required by the program. • Stack Segment – This segment contains the scratchpad known as the stack.For each segment, certain of the GPR’s default to working with them: • Code Segment – The only offset allowed here is the contents of the Instruction Pointer, IP. This generates the familiar CS:IP format shown in Debug. • Data Segment – The data segment works with the BX register and the Source Index (SI) registers by default. It can be forced to work with others if needed. When BX works with the data segment, it is referred to as a Base Register. • Extra Segment - The extra segment works with the Destination Index (DI) register by default. It can be forced to work with others if needed. • Stack Segment – The stack segment can work with the Stack Pointer (SP) and the Base Pointer (BP) registers. BP can be forced to work with other segments if needed, but SP cannot.If brackets are used with a register name, we assume that the register contains theaddress of the data in memory, not the data itself. The "address of the data"becomes the offset value that is added to the segment register contents to form thephysical address of the data. Example: MOV AX, [BX] – in this instruction, the data’soffset is in BX, not the data itself.Addressing modes are formed by various combinations of offsets. Here is the syntaxfor some examples. • MOV AX,BX – Register Direct Mode – the contents of BX is the data. It is moved into the AX register. The data in BX remains unchanged. • MOV AX,[BX] – Base Mode – the contents of the memory location in the current Data Segment (default here) whose offset is in BX is fetched from memory, and is moved to the AX register. • MOV AX, [SI] – Indexed Mode – the contents of the memory location in the current Data Segment (default) pointed to by the contents of SI is fetched and moved to AX.MICROPROCESSORS LAB 138
    • ELECTRONICS & COMMUNICATION ENGINEERING • MOV AX, [BX + SI] or MOV AX, [BX]+[SI] – Base-Index Mode – The sum of the BX and SI registers is added to the DS register to form the address of the data.It is possible, of course, to have the destination refer to memory instead of thesource. Examples include MOV [BX], AX and MOV [SI], AX.Default SegmentsAddressing modes have default segments with which they expect to operate. Insome cases, this default is determined by the OP code. The defaults are: • BX and SI default to the Data Segment • DI defaults to the Extra Segment • SP and BP default to the Stack Segment • IP defaults to the Code SegmentDS: or ES: to the instruction part that identifies the memory access. Examples: MOV AX, DS:[DI] forces the offset in DI to apply to the Data Segmentrather than to its regular Extra Segment. MOV AX, ES:[SI] forces the offset in SI toapply to the Extra Segment rather than to its regular Data Segment. MOV AX,DS:[BP] allows us to use the BP register in the Data Segment rather than in itsdefault Stack Segment.String InstructionsThe 8086’s string instructions provide a degree of flexibility when moving orworking with strings of data bytes or words in memory. Depending upon the OPcode, they make use of the DS:SI and/or the ES:DI register pairs in particular ways.Here’s how they work.Move String – This instruction moves a string of bytes or words from one area inmemory to another. To use it, set up DS:SI to point to the source data of the string.(Note that use the data segment and the Source Index register here). Then, set upthe ES:DI to aim at the location into which the data will be moved. (Note the extrasegment and destination index register.) One execution of the instruction under theseconditions will move one byte or word from the address formed of DS:SI to theaddress formed of ES:DI. Then, SI and DI will be incremented by 1 if the data beingmoved are bytes, or by 2 if the data are words. That’s assuming that the direction flagis set. If the direction flag is cleared, SI and DI are decremented.Scan String – This instruction compares a byte or word in AL or AX with a byte orword located in ES:DI. Must move the byte or word into AL or AX, then set up ES:DIaccordingly to point to the string to be scanned. The result of the comparison isregistered with the flags bits. The contents of DI is incremented if DF is set, ordecremented if DF is clear, by 1 for bytes or 2 for words. This can be useful to scan aMICROPROCESSORS LAB 139
    • ELECTRONICS & COMMUNICATION ENGINEERINGstring looking for the first occurrence of some particular byte (used in arrayprocessing).Compare String – This instruction compares two strings. The first is located byDS:SI and the second is located with ES:DI. Each execution of the instructioncompares one byte or word, sets the flags accordingly, and then increments ordecrements SI and DI by 1 or 2. This is useful for looking for that point at which thetwo strings no longer match, such as in a spelling checker.Load String – This instruction loads a byte or word pointed to by DS:SI into AL orAX and increments (decrements) SI by 1 or 2 (byte or word). In itself, it doesn’t domuch for you.Store String – This instruction saves a byte or word already located in AL or AXinto the address pointed to by ES:DI. DI is then incremented or decremented by 1 or2 as needed. To use the instruction you must first load AL or AX with the data to bestored. This can be useful for filling a range of memory with some constant, such asin the F command in Debug.The Load String and Store String instructions allow us to build our own special stringprocessing. We can load data with a LODS, subject it to some inspection orprocessing, then store it with a STOS. You can build quite a complicated processingsequence this way.Each execution of the string OP codes processes one byte or word. To process anentire string all at once, use the Repeat Prefix, REP. To do this, you must first loadsome value into the CX registers that represents the number of times you want theprocess repeated. For instance, to move a string of 128 bytes between to locations,set up DS:SI to point to the source string, ES:DI to point to the destination area,move 128 into CX, and then execute REP MOVSB, that is, repeat execute a move-string-byte. The system will move the first byte from DS:SI to ES:DI, increment SIand DI by 1 (for a byte), decrement CX by 1, and go around again if the contents ofCX is not yet 0. There are also variations of the REP prefix for SCANS and CMPScalled REPNZ (repeat as long as the Zero Flag is off) and REPZ (repeat as long asthe Zero Flag remains set). In these cases, the value in CX is a backup. You arescanning, for example, for a point in a string where the contents of the fetched byteand the contents of AL are equal. But what happens if there are no bytes in the stringthat are equal to AL? The value of CX eventually going to 0 will stop the process inthis case.Shorts, Nears, and FarsRedirection instructions include jumps, calls, and returns. Normally, the execution ofa program is linear, with the instruction to be executed next immediately above thecurrently executing instruction in memory. In the case of redirection, the executionline is stopped and the machine goes to some non-sequential location for the nextMICROPROCESSORS LAB 140
    • ELECTRONICS & COMMUNICATION ENGINEERINGinstruction to be executed. There are three locations to which a change in direction ofexecution of instructions can go:Near – In a near redirection, the next instruction to be executed is in the same codesegment as the redirection instruction.Far – In a far redirection, the next instruction to be executed is in a different codesegment from the one in which the redirection instruction is located.Short – In a short instruction, the next instruction to be executed is within 128 bytesof the redirection instruction in the same code segment.When encounter a near instruction, the instruction needs to have only an offsetprovided for the target instruction, since they are both in the same segment. The 16-bit offset is attached to the OP code byte of the instruction.When encounter a far instruction, the instruction must provide both a CS and an IPoffset since we need to go to a different segment altogether. Both the 16-bit segmentand the 16-bit offset of the next instruction must be attached to the OP code(generating a 5-byte-long instruction).In the case of a short instruction, attach a single byte to the OP code. This byteconsists of a signed value to be added to the offset of the address of the instructionfollowing the redirection instruction. It is a signed byte (7 bits of significant value, withbit position 7, the 8th bit, indicating + or -) because we want to be able to go as far as128 bytes above our current location (to a higher address) or as far as 128 bytesbelow our current location (to a lower address). By adding this value to the location ofthe instruction following the redirection instruction, we make the target addressrelative to the location of the redirection instruction itself. This is called RelativeAddressing. This type of redirection is the only placed relative addressing is used inthe 8086.MICROPROCESSORS LAB 141
    • ELECTRONICS & COMMUNICATION ENGINEERING 2.8086 Microprocessor addressing modesThe 8086 Addressing Modes Most 8086 instructions can operate on the 8086s general purpose register set. Byspecifying the name of the register as an operand to the instruction, you may accessthe contents of that register. Consider the 8086 mov (move) instruction: mov destination, sourceThis instruction copies the data from the source operand to the destination operand.The eight and 16 bit registers are certainly valid operands for this instruction. Theonly restriction is that both operands must be the same size. Now lets look at someactual 8086 mov instructions: mov ax, bx ;Copies the value from BX into AX mov dl, al ;Copies the value from AL into DL mov si, dx ;Copies the value from DX into SI mov sp, bp ;Copies the value from BP into SP mov dh, cl ;Copies the value from CL into DH mov ax, ax ;Yes, this is legal!The registers are the best place to keep often used variables. Instructions using theregisters are shorter and faster than those that access memory. Throughout thischapter youll see the abbreviated operands reg and r/m (register/memory) usedwherever you may use one of the 8086s general purpose registers.In addition to the general purpose registers, many 8086 instructions (including themov instruction) allow you to specify one of the segment registers as an operand.There are two restrictions on the use of the segment registers with the movinstruction. First of all, you may not specify cs as the destination operand, second,only one of the operands can be a segment register. You cannot move data from onesegment register to another with a single mov instruction. To copy the value of cs tods, youd have to use some sequence like: mov ax, cs mov ds, axYou should never use the segment registers as data registers to hold arbitraryvalues. They should only contain segment addresses. But more on that, later.Throughout this text youll see the abbreviated operand sreg used wherever segmentregister operands are allowed (or required).The addressing modes provided by the 8086 family include displacement-only, base,displacement plus base, base plus indexed, and displacement plus base plusindexed. Variations on these five forms provide the 17 different addressing modes onthe 8086. See, from 17 down to five. Its not so bad after all!The Direct Addressing ModeIn this addressing mode address of the data specified in the instruction it self, thataddress indicates offset address of the memoryExample: MOV AX,[5000]MICROPROCESSORS LAB 142
    • ELECTRONICS & COMMUNICATION ENGINEERINGThe Register Indirect Addressing ModesThe 80x86 CPUs access memory indirectly through a register using the registerindirect addressing modes. There are four forms of this addressing mode on the8086, best demonstrated by the following instructions: mov al, [bx] mov al, [bp] mov al, [si] mov al, [di]As with the x86 [bx] addressing mode, these four addressing modes reference thebyte at the offset found in the bx, bp, si, or di register, respectively. The [bx], [si], and[di] modes use the ds segment by default. The [bp] addressing mode uses the stacksegment (ss) by default.[bx] and [bp] as base addressing modes and bx and bp as base registers (in fact, bpstands for base pointer) and [si] and [di] addressing modes as indexed addressingmodes (si stands for source index, di stands for destination index).Note: the [si] and [di] addressing modes work exactly the same way, just substitute siand di for bx above.Indexed Addressing ModesThe indexed addressing modes use the following syntax: mov al, disp[bx] mov al, disp[bp] mov al, disp[si] mov al, disp[di]If bx contains 1000h, then the instruction mov cl,20h[bx] will load cl from memorylocation ds:1020h. Likewise, if bp contains 2020h, mov dh,1000h[bp] will load dhfrom location ss:3020.The offsets generated by these addressing modes are the sum of the constant andthe specified register. The addressing modes involving bx, si, and di all use the datasegment, the disp[bp] addressing mode uses the stack segment by default. As withMICROPROCESSORS LAB 143
    • ELECTRONICS & COMMUNICATION ENGINEERINGthe register indirect addressing modes, you can use the segment override prefixes tospecify a different segment: mov al, ss:disp[bx] mov al, es:disp[bp] mov al, cs:disp[si] mov al, ss:disp[di]may substitute si or di in the figure above to obtain the [si+disp] and [di+disp]addressing modes.Based Indexed Addressing ModesThe based indexed addressing modes are simply combinations of the registerindirect addressing modes. These addressing modes form the offset by addingtogether a base register (bx or bp) and an index register (si or di). The allowableforms for these addressing modes are mov al, [bx][si] mov al, [bx][di] mov al, [bp][si] mov al, [bp][di]Suppose that bx contains 1000h and si contains 880h. Then the instruction mov al,[bx][si]would load al from location DS:1880h. Likewise, if bp contains 1598h and di contains1004, mov ax,[bp+di] will load the 16 bits in ax from locations SS:259C and SS:259D.The addressing modes that do not involve bp use the data segment by default.Those that have bp as an operand use the stack segment by default.substitute di in the figure above to obtain the [bx+di] addressing mode.MICROPROCESSORS LAB 144
    • ELECTRONICS & COMMUNICATION ENGINEERINGsubstitute di in the figure above for the [bp+di] addressing mode.Based Indexed Plus Displacement Addressing ModeThese addressing modes are a slight modification of the base/indexed addressingmodes with the addition of an eight bit or sixteen bit constant.The following are some examples of these addressing modes: mov al, disp[bx][si] mov al, disp[bx+di] mov al, [bp+si+disp] mov al, [bp][di][disp]may substitute di in the figure above to produce the [bx+di+disp] addressing mode.may substitute di in the figure above to produce the [bp+di+disp] addressing mode.Suppose bp contains 1000h, bx contains 2000h, si contains 120h, and di contains 5.Then mov al,10h[bx+si] loads al from address DS:2130; mov ch,125h[bp+di] loads chfrom location SS:112A; and mov bx,cs:2[bx][di] loads bx from location CS:2007.Immediate Data Addressing Mode Immediate data is real data, not the address of data. It is contained in the source ofan instruction and causes the instruction to use the value as live data with its OPcode.For example, MOV AX, 1234 would move the real value 1234 into the AX register.ADD BX,2345 would add the value 2345 to the value already located in BX, with theanswer remaining in BX.MICROPROCESSORS LAB 145
    • ELECTRONICS & COMMUNICATION ENGINEERINGMASM Syntax for 8086 Memory Addressing ModesMicrosofts assembler uses several different variations to denote indexed,based/indexed, and displacement plus based/indexed addressing modes Thefollowing list some of the possible combinations that are legal for the various 80x86addressing modes:disp[bx], [bx][disp], [bx+disp], [disp][bx], and [disp+bx][bx][si], [bx+si], [si][bx], and [si+bx]disp[bx][si], disp[bx+si], [disp+bx+si], [disp+bx][si], disp[si][bx], [disp+si][bx],[disp+si+bx], [si+disp+bx], [bx+disp+si], etc.MASM treats the "[ ]" symbols just like the "+" operator. This operator is commutative,just like the "+" operator. Of course, this discussion applies to all the 8086 addressingmodes, not just those involving BX and SI. You may substitute any legal registers inthe addressing modes above.An Easy Way to Remember the 8086 Memory AddressingModesThere are a total of 17 different legal memory addressing modes on the 8086: disp,[bx], [bp], [si], [di], disp[bx], disp[bp], disp[si], disp[di], [bx][si], [bx][di], [bp][si], [bp][di],disp[bx][si], disp [bx][di], disp[bp][si], and disp[bp][di]. You could memorize all theseforms so that you know which are valid (and, by omission, which forms are invalid).However, there is an easier way besides memorizing these 17 forms. Consider thechart:Choose zero or one items from each of the columns and wind up with at least oneitem, got a valid 8086 memory addressing mode. Some examples: • Choose disp from column one, nothing from column two, [di] from column 3, you get disp[di]. • • Choose disp, [bx], and [di]. You get disp[bx][di]. • • Skip column one & two, choose [si]. You get [si] • • Skip column one, choose [bx], then choose [di]. You get [bx][di]Likewise, an addressing mode that you cannot construct from this table, then it is notlegal. For example, disp[dx][si] is illegal because you cannot obtain [dx] from any ofthe columns above.MICROPROCESSORS LAB 146
    • ELECTRONICS & COMMUNICATION ENGINEERING 3.8086 Microprocessor instruction set INSTRUCTION SET OF 8086 MICROPROCESSOR ARITHMETIC INSTRUCTIONS ADD dst,src add two operands, result remains in dst Format: dst <- (src + dst) Flags: OSZAPC ADC dst,src add two operands with carry from previous add Format: dst <- (src + dst + CF) Flags: O S Z A PC INC dst add 1 to dst Format: dst <- (dst+1) Flags: OSZAP SUB dst,src subtract src from dst, leaving result in dst Format: dst <- (dst - src) Flags: OSZAPC SBB dst,src subtract src and the C bit from dst Format: dst <- ((dst - src) - CF) Flags: OSZAPC DEC dst decrement dst by 1 Format: dst <- (dst - 1) Flags: OSZAPC CMP dst,src compare by subtracting src from dst Format: dst - src Flags: OSZAPC Peforms a non-destructive subtraction of src from dst but without storing a result. The flags are Notes: adjusted to indicate the result of the subtraction.MICROPROCESSORS LAB 147
    • ELECTRONICS & COMMUNICATION ENGINEERING NEG dst changes the sign of an operand (Negate) Format: dst <- (0 - dst) Flags: OSZAPC Notes: Performs a 2s complement of dst. AAA ASCII adjust for addition Format: AL <-(AL adjusted for ASCII addition) Flags: A C; the O, S, Z, and P flags are left in an indeterminate state. Notes: This instruction follows an addition of "unpacked" ASCII data. AAS ASCII adjust for subtraction Format: AL <-(AL adjusted for ASCII subtraction) Flags: A C; the O, S, Z, and P flags are left in an indeterminate state. Notes: This instruction follows a subtraction of "unpacked" ASCII data. AAM ASCII adjust for multiplication Format: AH:AL <- (AH:AL adjusted for ASCII multiplication) Flags: S Z P; the O, A, and C flags are left in an indeterminate condition. AAD ASCII adjust for division Format: AH:AL <- (AH:AL prepared for division of ASCII codes) Flags: S Z P; the O, A, and P flags are left in an indeterminate condition. Notes: This instruction is executed before the division instruction to prepare the data for the function. DAA Decimal adjust for addition Format: AL <- (AL adjusted for BCD addition) Flags: S Z A P C; the O flag is left in an indeterminate condtition. DAS Decimal adjust for subtraction Format: AL <- (AL adjusted for BCD subtraction) Flags: S Z A P C; the O flag is left in an indeterminate condition. MUL src multiply 8 or 16 bit src by 8-bit (AL) or 16-bit (AX) value (unsigned) AX <- (AL * src8) Format: DX:AX <-(AX * src16) Flags: O C; the S, Z, A, and P flags are left in an indeterminate condition. This is an unsigned multiplication. An 8-bit src is multiplied by the contents of AL to generate a Notes: 16-bit result in AX. A 16-bit src is multiplied by the contents of AX to generate a 32-bit result stored with the higher 16 bits in DX and the lowre 16 bits in AX.MICROPROCESSORS LAB 148
    • ELECTRONICS & COMMUNICATION ENGINEERING IMUL src multiply 8 or 16 bit src by 8-bit (AL) or 16-bit (AX) value (signed) AX <- (AL * src8) Format: DX:AX <- (AX * src16) Flags: O C; the S, Z A and P flags are left in an indeterminate condition. This is a signed multiplication. An 8-bit src is multiplied by the contents of AL to generate a 16- Notes: bit result in AX. A 16-bit src is multiplied by the contents of AX to generate a 32-bit result stored with the higher 16 bits in DX and the lowre 16 bits in AX. DIV src divide of 16-bit or 32-bit number by 8- or 16-bit number (unsigned) AL <- (AX ÷ src8) AH <- Remainder Format: AX <- (DX:AX ÷ src16) DX <- Remainder Flags: The O, S, Z, A, P, and C flags are left in an inderterminate condition. This is an unsigned divide. A 16 bit value in AX is divided by an 8-bit src with the quotient Notes: remaining in AL and the remainder in AH. A 32-bit number in DX:AX is divided by a 16-bit src with the quotient remaining in AX and the remainder in DX. A 0 divisor results in an INT 0 error. divide of unsigned divide of 16-bit or 32-bit number by 8- or 16-bit number IDIV src (unsigned) AL <- (AX ÷ src8) AH <- Remainder Format: AX <- (DX:AX ÷ src16) DX <- Remainder Flags: The O, S, Z, A, P, and C flags are left in an inderterminate condition. This is a signed divide. A 16 bit value in AX is divided by an 8-bit src with the quotient remaining Notes: in AL and the remainder in AH. A 32-bit number in DX:AX is divided by a 16-bit src with the quotient remaining in AX and the remainder in DX. A 0 divisor results in an INT 0 error. CBW convert from byte to word (8-bit -> 16-bit) Format: AH <- (filled with bit-7 of AL) Flags: None Notes: Converts an 8-bit byte in AL to a 16-bit word in AX by sign extension of bit 7 of AL through AH. CWD convert from word to double word Format: DX <- (filled with bit-15 of AX) Flags: None Converts a 16-bit word in AX to a 32 bit word in DX:AX by sign extension of bit 15 of AX Notes: through DX. AND dst,src logical AND Format: dst <- (dst AND src) Flags: S Z P; O, C -> 0; A is set to an indeterminate condition Notes: Performs a bitwise logical AND of src and dst with result remaining in dst.MICROPROCESSORS LAB 149
    • ELECTRONICS & COMMUNICATION ENGINEERING TEST dst,src non-destructive logical AND Format: flags <- (dst AND src) Flags: S Z P; O, C -> 0; A is set to an indeterminate condition Performs a non-destructive bit-wise logical AND of src and dst, setting flags and leaving dst Notes: unchanged. OR dst,src inclusive logical OR Format: dst <-(dst OR src) Flags: S Z P; O, C -> 0; A is set to an indeterminate condition Notes: Performs a bit-wise logical inclusive OR of src and dst with result remaining in dst. XOR dst,src exclusive logical OR Format: dst <-(dst XOR src) Flags: S Z P; O, C -> 0; A is set to an indeterminate condition Notes: Performs a bit-wise logical exclusive OR of src and dst with result remaining in dst. NOT dst 1s complement of dst Format: dst <- (~dst) Flags: None Notes: Converts 1s to 0s and 0s to 1s in dst. CLC clear the carry flag Format: (CF <- 0) Flags: C CMC complement the carry flag Format: CF <- ~CF Flags: C STC set the carry flag Format: CF <- 1 Flags: C CLD clear direction flag Format: DF <- 0 Flags: D Notes: Clear direction flag to 0 which sets direction to UP.MICROPROCESSORS LAB 150
    • ELECTRONICS & COMMUNICATION ENGINEERING STD set direction flag Format: DF <- 1 Flags: D Notes: Sets direction flag to 1 which sets directio to DOWN CLI clear interrupt flag Format: IF <- 0 Flags: I Notes: Clears the interrupt enable flag which disables interrupts. STI set interrupt flag Format: IF <- 1 Flags: I Notes: Sets the interrupt enable flag which enables interrupts. HLT halt Format: None Flags: None Notes: Hangs the processor in a series of self-inflicted NOPs until an interrupt occurs. WAIT/FWAIT wait Format: None Flags: None Notes: Causes the processor to wait for completion signal from coprocessor. LOCK lock bus (prefix byte to instruction OP code) Format: None Flags: None Notes: Locks the bus attached to LOCK pin of device while a multi-cycle instruction completes. SEG segreg change default segment (prefix byte to instruction OP Code) Format: None Flags: None Notes: Overrides the default segment of a memory operand to a different segment. Data Transfer Instructions MOV dst,src copy data from src to dst Format: dest <- src Flags: NoneMICROPROCESSORS LAB 151
    • ELECTRONICS & COMMUNICATION ENGINEERING Notes: Moves or makes a copy of src in dst. Original contents of dst is lost. XCHG dst,src exchange data between src and dst Format: dst <-> src Flags: None IN port8 or DX input data from i/o device byte: AL <- port Format: word: AL <-[port]; AH <- [port+1] or AX <- (DX) Flags: None Brings a byte or word into AL or AX from an 8-bit port or the 16-bit address contained in DX. Notes: The 8-bit port supports the I/O technique of earlier processors. OUT port8 or DX output data to i/o device byte: [port] <- AL Format: word: [port] <- AL [port+1]*AH or (DX <- AX) Flags: None Notes: Sends a byte or word to an 8-bit port address or the 16-bit port address contained in DX. XLAT translate byte in AL by table lookup Format: AL <- ES:[BX+(AL)] Flags: None Translates the byte in AL by adding it to a base value in BX which has been set to point to the bottom of a lookup table; the byte located is returned in AL. Notes: LEA reg16,addr load effective address Format: reg16 <- effective address (offset) of addr Flags: None Notes: Loads the effective address or offset of memory variable into reg16. LDS reg16,mem load data segment Format: reg16 <- [mem16]; DS <- [mem16+2] Flags: None Notes: Loads the DS register and reg16 with the segment and offset values for the variable in mem. LES reg16,mem load extra segment Format: reg16 <- [mem16]; ES <- [mem16+2 Flags: None Notes: Loads the ES register and reg16 with the segment and offset values for the variable in mem. LAHF Loads the lower flags byte into AH Format: AH <- flagsMICROPROCESSORS LAB 152
    • ELECTRONICS & COMMUNICATION ENGINEERING Flags: OACZP Notes: Loads the low byte of the flags word into the AH register. Provides support for 8080 legacy. SAHF Saves AH into lower flags byte Format: flags <- AH Flags: None Notes: Saves the AH register bit pattern into the low byte of the flags register. PUSH src push src onto stack Format: SP = SP-2; SS:[SP] <- src Flags: None Notes: SP is decremented by 2, then src is pushed onto stack at this new offset. PUSH immed push immediate data onto stack Format: SP = SP-2; SS:[SP] <- immed16 |286| only. Flags: None SP is decremented by 2, then immed is pushed onto stack at this new offset. Works in 286 or Notes: later processors only, not available on the 8086. PUSHA push all registers onto stack SP = SP-10H; AX,BX,CX,DX,SI,DI, Format: BP,SP saved on stack Flags: None Notes: Saves all registers onto stack at once. PUSHF push flags word onto stack Format: SP = SP-2; SS:[SP] <- flags Flags: None Notes: Saves flag word onto stack. POP dst pop word at top of stack to dst Format: dst <- SS:[SP]; SP = SP+2 Flags: None Notes: Copies the word at top of stack to dst, then increments SP by 2. POPA pop all registers from stack to regs Format: SP = SP+10H; AX,BX,CX,DX,SI,DI,BP restored from stack Flags: None POPF pop word at top of stack to flags register Format: flags <- SS:[SP]; SP = SP+2MICROPROCESSORS LAB 153
    • ELECTRONICS & COMMUNICATION ENGINEERING Flags: All Notes: FLOW CONTROL INSTRUCTIONS JMP target unconditional jump to target short: IP <- (IP+(target displacement sign-extended)) near: IP <- (IP+(target displacement)) Format: I ndirect: IP <- (reg or value in mem) f ar: CS <- targ_seg; IP <- targ_offset Flags: None Short jumps are within += 128 bytes of jmp instruction - only IP is affected. Near jumps are within same segment - only IP is affected. Notes: Indirect jumps are within same segment - only IP is affected. Far jumps are to a different segment - both CS and IP are affected. JCXZ target(short) jump short if CX register is 0 Format: None Flags: None LOOP target(short) loop to short target Format: CX <- (CX-1); jump if CX != 0 Flags: C The CX register is decremented by 1. If CX now is not equal to 0, loop back to target. Notes: Otherwise, continue. LOOPE/Z target(short) loop to short target if Z bit set Format: CX <- (CX-1); jump if CX!=0 && ZF==ZR==1 Flags: C The CX register is decremented by 1. If CX is not equal to 0 or if the Z bit is set, loop back to Notes: short target. LOOPNE/NZ loop to short target if Z bit is clear Format: CX <- (CX-1); jump if CX!=0 && ZF==NZ==0 Flags: C Jcond jump on condition Format: IP <- (IP+(8-bit displacement sign-extended to 16 bits)) Flags: None Jump on condition to short target. The conditions are: Notes: JO O=1 Jump on overflow set JNO O=0 Jump on overflow clear JB / JNAE C=1 Jump if below / Jump if not above or equal JAE / JNB C=0 Jump if above or equal / Jump if not below JE / JNZ Z=1 Jump if equal / Jump if not zeroMICROPROCESSORS LAB 154
    • ELECTRONICS & COMMUNICATION ENGINEERING JNE / JNZ Z=0 Jump if not equal / Jump if not zero JBE / JNA C=1or Z=1 Jump if below or equal / Jump if not above JA / JNBE C=0 and Z=0 Jump if above / Jump if not below or equal JS S=1 Jump on sign set JNS S=0 Jump on sign clear JP / JPE P=1 Jump on parity bit set (parity even) JNP / JPO P=0 Jump on partiy bit clear (parity odd) JL / JNGE S=1 or O=1 Jump if less / Jump if not greater than or equal to JGE / JNL S=O Jump if greater than or equal to / Jump if not less Z=1 or S and JLE / JNG Jump if less than or equal to / Jump if not greater than O=1 JG / JNLE Z=0 or S=O Jump if greater than / Jump if not less than or equal to CALL target call a procedure Near call: PUSH IP, JMP to target Format: Fall call: PUSH CS, PUSH IP, JMP to target Flags: None The syntax for a near call (same segment) is CALL target. Notes: The syntax for a far call (different segment) is CALL FAR target. RET return from procedure RET n return from procedure and add n to SP Near return: POP IP Format: Far return: POP IP, POP CS Flags: None The syntax for a near return is RET. The syntax for a far return is RET FAR. Notes: The RET n form adds n to the SP to compensate for stack growth when arguments are pushed onto the stack prior to a procedure call. INT n interrupt (software) PUSHF; IF <- 0; TF <- 0; PUSH CS; PUSH IP Format: IP <- 0000:[type * 4]; CS <- 0000:[(type * 4) + 2] Flags: IT INTO interrupt on overflow Format: if OF=1, then perform INT through vector 4 Flags: None Interrupts the system if the overflow bit is set following a mathematical instruction. This Notes: indicates a carry from a signed value. IRET return from interrupt service routine Format: POP IP; POP CS; POPF Flags: All Notes: This instruction appears at the bottom of all interrupt service routines.MICROPROCESSORS LAB 155
    • ELECTRONICS & COMMUNICATION ENGINEERING STRING INSTRUCTIONS CLD clear direction flag Format: DF <- UP=0 Flags: D Notes: Sets the default direction of string operations to UP. STD set direction flag Format: DF <-DN=1) Flags: D Notes: Sets the default direction of string operations to DOWN. REP / REPE / REPZ repeat string instruction (prefix) Format: CX <- (CX-1); until CX=0 Flags: Z This is a prefix byte that forces a string operation to be repeated as long as CX is not equal to Notes: 0. CX is decremented once for each repetition. REPNE / REPNZ repeat string instruction while not zero (prefix) Format: ZF <- 0; CX <- (CX-1); StrOp repeats while (CX!=0 and ZF!=0) Flags: Z Notes: This is a prefix byte that keeps a string operation repeating while CX is not zero and Z!=0. MOVSB move string byte Format: ES:[DI] <- DS:[SI]; DI=DI±1; SI=SI±1 Flags: None Moves a string a byte at a time from DS:SI to ES:DI. SI and DI are incremented or Notes: decremented by 1, depending on Direction FLag MOVSW move string word Format: ES:[DI] <- DS:[SI]; DI=DI±2; SI=SI±2 Flags: None Moves a string a word at a time from DS:SI to ES:DI. SI and DI are incremented or decremented by 2, depending on Direction Flag Notes: LODSB load string byte Format: AL <- DS:[SI]; SI=SI±1 Flags: None Moves a string one byte at a time from DS:SI to AL; SI is then incremented or decremented by Notes: 1, depending on Direction Flag.MICROPROCESSORS LAB 156
    • ELECTRONICS & COMMUNICATION ENGINEERING LODSW load string word Format: AX <- DS:[SI]; SI=SI±2 Flags: None Moves a string one word at a time from DS:SI to AX; SI is then incremented or decremented by Notes: 2, depending on Direction Flag. STOSB store string byte Format: ES:[DI] <- AL; DI=DI±1 Flags: None Moves a string one byte at a time from AL to ES:DI; DI is then incremented or decremented by Notes: 1, depending on Direction Flag. STOSW store string word Format: ES:[DI] <- AX; DI=DI±2 Flags: None Moves a string one word at a time from AX to ES:DI; DI is then incremented or decremented Notes: by 2, depending on Direction Flag. CMPSB compare string byte Format: flags <-(result of CMP DS:[SI],ES:[DI]); DI=DI±1; SI=SI±1 Flags: See the CMP instruction The byte at DS:SI is compared with the byte at ES:DI and the flags are set accordingly. SI and DI are both incremented or decremented by 1, depending on the Direction Flag. Combined with Notes: an REP prefix, this allows us to compare a two strings to determine at what point they no longer are equal. CMPSW compare string word Format: flags <- (result of CMP DS:[SI],ES:[DI])DI=DI±2; SI=SI±2 Flags: See the CMP instruction The word at DS:SI is compared with the word at ES:DI and the flags are set accordingly. SI and DI are both incremented or decremented by 2, depending on the Direction Flag. Combined with Notes: a REP prefix, this allows us to compare a two strings to determine at what point they no longer are equal. SCASB scan string byte Format: f lags <- (result of CMP ES:[DI],AL); DI=DI±1 Flags: See the CMP instruction The byte at ES:DI is compared to the contents of AL setting flags. DI is incremented or Notes: decremented by 1 depending upon the Direction Flag. Combined with a REP prefix, this allows us to scan a string looking for the first occurance of a particular byte.MICROPROCESSORS LAB 157
    • ELECTRONICS & COMMUNICATION ENGINEERING SCASW scan string word Format: flags <- (result of CMP ES:[DI],AX); DI=DI±2 Flags: See the CMP instruction The word at ES:DI is compared to the contents of AX setting flags. DI is incremented or Notes: decremented by 2 depending upon the Direction Flag. Combined with a REP prefix, this allows us to scan a string looking for the first occurance of a particular word. INSB input string byte |286 and later| Format: ES:[DI] <- (byte at port DX); DI=DI±1 Flags: None Brings a byte from the port in DX to ES:DI; increments or decrements DI by 1 depending on Notes: Direction Flag. Combined with a REP prefix, this allows us to read a stream of bytes from an input device to memory at high speed. INSW input string word |286 and later| Format: ES:[DI] <- (word at port DX); DI=DI±2 Flags: None Brings a word from the port in DX to ES:DI; increments or decrements DI by 2 depending on Notes: Direction Flag. Combined with a REP prefix, this allows us to read a stream of words from an input device to memory at high speed. OUTSB input string word |286 and later| Format: [port DX] <- DS:[SI]; SI=SI±1 Flags: None Sends a byte from DS:SI to the port in DX; increments or decrements DI by 1 depending on Notes: Direction Flag. Combined with a REP prefix, this allows us to send a stream of bytes to an output device from memory at high speed. OUTSW output string word |286 and later| Format: [port DX] <- DS:[SI]; SI=SI±2 Flags: None Sends a word from DS:SI to the port in DX; increments or decrements DI by 2 depending on Notes: Direction Flag. Combined with a REP prefix, this allows us to send a stream of words to an output device from memory at high speed. STRING INSTRUCTIONS CLD clear direction flag Format: DF <- UP=0 Flags: D Notes: Sets the default direction of string operations to UP. STD set direction flag Format: DF <-DN=1)MICROPROCESSORS LAB 158
    • ELECTRONICS & COMMUNICATION ENGINEERING Flags: D Notes: Sets the default direction of string operations to DOWN. REP / REPE / REPZ repeat string instruction (prefix) Format: CX <- (CX-1); until CX=0 Flags: Z This is a prefix byte that forces a string operation to be repeated as long as CX is not equal to Notes: 0. CX is decremented once for each repetition. REPNE / REPNZ repeat string instruction while not zero (prefix) Format: ZF <- 0; CX <- (CX-1); StrOp repeats while (CX!=0 and ZF!=0) Flags: Z Notes: This is a prefix byte that keeps a string operation repeating while CX is not zero and Z!=0. MOVSB move string byte Format: ES:[DI] <- DS:[SI]; DI=DI±1; SI=SI±1 Flags: None Moves a string a byte at a time from DS:SI to ES:DI. SI and DI are incremented or Notes: decremented by 1, depending on Direction FLag MOVSW move string word Format: ES:[DI] <- DS:[SI]; DI=DI±2; SI=SI±2 Flags: None Moves a string a word at a time from DS:SI to ES:DI. SI and DI are incremented or Notes: decremented by 2, depending on Direction FLag LODSB load string byte Format: AL <- DS:[SI]; SI=SI±1 Flags: None Moves a string one byte at a time from DS:SI to AL; SI is then incremented or decremented Notes: by 1, depending on Direction Flag. LODSW load string word Format: AX <- DS:[SI]; SI=SI±2 Flags: None Moves a string one word at a time from DS:SI to AX; SI is then incremented or decremented Notes: by 2, depending on Direction Flag. STOSB store string byte Format: ES:[DI] <- AL; DI=DI±1 Flags: NoneMICROPROCESSORS LAB 159
    • ELECTRONICS & COMMUNICATION ENGINEERING Moves a string one byte at a time from AL to ES:DI; DI is then incremented or decremented Notes: by 1, depending on Direction Flag. STOSW store string word Format: ES:[DI] <- AX; DI=DI±2 Flags: None Moves a string one word at a time from AX to ES:DI; DI is then incremented or decremented Notes: by 2, depending on Direction Flag. CMPSB compare string byte Format: flags <-(result of CMP DS:[SI],ES:[DI]); DI=DI±1; SI=SI±1 Flags: See the CMP instruction The byte at DS:SI is compared with the byte at ES:DI and the flags are set accordingly. SI and DI are both incremented or decremented by 1, depending on the Direction Flag. Combined with Notes: an REP prefix, this allows us to compare a two strings to determine at what point they no longer are equal. CMPSW compare string word Format: flags <- (result of CMP DS:[SI],ES:[DI])DI=DI±2; SI=SI±2 Flags: See the CMP instruction The word at DS:SI is compared with the word at ES:DI and the flags are set accordingly. SI and DI are both incremented or decremented by 2, depending on the Direction Flag. Combined Notes: with a REP prefix, this allows us to compare a two strings to determine at what point they no longer are equal. SCASB scan string byte Format: flags <- (result of CMP ES:[DI],AL); DI=DI±1 Flags: See the CMP instruction The byte at ES:DI is compared to the contents of AL setting flags. DI is incremented or Notes: decremented by 1 depending upon the Direction Flag. Combined with a REP prefix, this allows us to scan a string looking for the first occurance of a particular byte. SCASW scan string word Format: flags <- (result of CMP ES:[DI],AX); DI=DI±2 Flags: See the CMP instruction The word at ES:DI is compared to the contents of AX setting flags. DI is incremented or Notes: decremented by 2 depending upon the Direction Flag. Combined with a REP prefix, this allows us to scan a string looking for the first occurance of a particular word. INSB input string byte |286 and later| Format: ES:[DI] <- (byte at port DX); DI=DI±1 Flags: None Brings a byte from the port in DX to ES:DI; increments or decrements DI by 1 depending on Notes: Direction Flag. Combined with a REP prefix, this allows us to read a stream of bytes from an input device to memory at high speed.MICROPROCESSORS LAB 160
    • ELECTRONICS & COMMUNICATION ENGINEERING INSW input string word |286 and later| Format: ES:[DI] <- (word at port DX); DI=DI±2 Flags: None Brings a word from the port in DX to ES:DI; increments or decrements DI by 2 depending on Notes: Direction Flag. Combined with a REP prefix, this allows us to read a stream of words from an input device to memory at high speed. OUTSB input string word |286 and later| Format: [port DX] <- DS:[SI]; SI=SI±1 Flags: None Sends a byte from DS:SI to the port in DX; increments or decrements DI by 1 depending on Notes: Direction Flag. Combined with a REP prefix, this allows us to send a stream of bytes to an output device from memory at high speed. OUTSW output string word |286 and later| Format: [port DX] <- DS:[SI]; SI=SI±2 Flags: None Sends a word from DS:SI to the port in DX; increments or decrements DI by 2 depending on Notes: Direction Flag. Combined with a REP prefix, this allows us to send a stream of words to an output device from memory at high speed.MICROPROCESSORS LAB 161
    • ELECTRONICS & COMMUNICATION ENGINEERING 4. Intel 8259 overview Intel 8259A PROGRAMMABLE INTERRUPT CONTROLLER (8259A/8259A-2)• 8086, 8088 Compatible• MCS-80, MCS-85 Compatible• Eight-Level Priority Controller• Expandable to 64 Levels• Programmable Interrupt Modes• Individual Request Mask Capability• Single + 5V Supply (No Clocks)• Available in 28-Pin DIP and 28-Lead PLCC Package (See Packaging Spec., Order #231369)• Available in EXPRESS — Standard Temperature Range — Extended Temperature RangeThe Intel 8259A Programmable Interrupt Controller handles up to eight vectoredpriority interrupts for the CPU. It is cascadable for up to 64 vectored priority interruptswithout additional circuitry. It is packaged in a 28-pin DIP, uses NMOS technologyand requires a single +5V supply. Circuitry is static, requiring no clock input.The 8259A is designed to minimize the software and real time overhead in handlingmulti-level priority interrupts. It has several modes, permitting optimization for avariety of system requirements.The 8259A is fully upward compatible with the Intel 8259. Software originally writtenfor the 8259 will operate the 8259A in all 8259 equivalent modes (MCS-80/85, Non-Buffered, Edge Triggered).MICROPROCESSORS LAB 162
    • ELECTRONICS & COMMUNICATION ENGINEERING Table 1: Pin DescriptionSymbol Pin No. Type Name and FunctionVcc 28 I SUPPLY: + 5V Supply.GND 14 I GROUNDCS 1 I CHIP SELECT: A low on this pin enables RD and WR communication between the CPU and the 8259A. INTA functions are independent of CS.WR 2 I WRITE: A low on this pin when CS is low enables the 8259A to accept command words from the CPU.RD 3 I READ: A low on this pin when CS is low enables the 8259A to release status onto the data bus for the CPU.D7-D0 4-11 I/O BIDIRECTIONAL DATA BUS: Control, status and interrupt- vector information is transferred via this bus.CAS0-CAS2 12, 13, 15 I/O CASCADE LINES: The CAS lines form a private 8259A bus to control a multiple 8259A structure. These pins are outputs for a master 8259A and inputs for a slave 8259A.SP/EN 16 I/O SLAVE PROGRAM/ENABLE BUFFER: This is a dual function pin. When in the Buffered Mode it can be used as an output to control buffer transceivers (EN). When not in the buffered mode it is used as an input to designate a master (SP = 1) or slave (SP = 0). MICROPROCESSORS LAB 163
    • ELECTRONICS & COMMUNICATION ENGINEERINGSymbol Pin No. Type Name and FunctionINT 17 0 INTERRUPT: This pin goes high whenever a valid interrupt request is asserted. It is used to interrupt the CPU, thus it is connected to the CPUs interrupt pin.IR0-IR7 18-25 I INTERRUPT REQUESTS: Asynchronous inputs. An interrupt request is executed by raising an IR input (low to high), and holding it high until it is acknowledged (Edge Triggered Mode), or just by a high level on an IR input (Level Triggered Mode).TNTA 26 I INTERRUPT ACKNOWLEDGE: This pin is used to enable 8259A interrupt-vector data onto the data bus by a sequence of interrupt acknowledge pulses issued by the CPU.AO 27 I AO ADDRESS LINE: This pin acts in conjunction with the CS, WR, and RD pins. It is used by the 8259A to decipher various Command Words the CPU writes and status the CPU wishes to read. It is typically connected to the CPU AO address line (A1 for 8086, 8088). FUNCTIONAL DESCRIPTION Interrupts in Microcomputer Systems Microcomputer system design requires that I.O devices such as keyboards, displays, sensors and other components receive servicing in a an efficient manner so that large amounts of the total system tasks can be assumed by the microcomputer with little or no effect on throughput. The most common method of servicing such devices is the Polled approach. This is where the processor must test each device in sequence and in effect "ask" each one if it needs servicing. It is easy to see that a large portion of the main program is looping through this continuous polling cycle and that such a method would have a serious detrimental effect on system throughput, thus limiting the tasks that could be assumed by the microcomputer and reducing the cost effectiveness of using such devices. A more desirable method would be one that would allow the microprocessor to be executing its main program and only stop to service peripheral devices when it is told to do so by the device itself. In effect, the method would provide an external asynchronous input that would inform the processor that it should complete whatever instruction that is currently being executed and fetch a new routine that will service the requesting device. Once this servicing is complete, however, the processor would resume exactly where it left off. This method is called Interrupt. It is easy to see that system throughput would drastically increase, and thus more tasks could be assumed by the microcomputer to further enhance its cost effectiveness. The Programmable Interrupt Controller (PIC) functions as an overall manager in an Interrupt-Driven system environment. It accepts requests from the peripheral equipment, determines which of the incoming requests is of the highest importance (priority), ascertains whether the incoming request has a higher priority value than MICROPROCESSORS LAB 164
    • ELECTRONICS & COMMUNICATION ENGINEERINGthe level currently being serviced, and issues an interrupt to the CPU based on thisdetermination.Each peripheral device or structure usually has a special program or "routine" that isassociated with its specific functional or operational requirements; this is referred toas a "service routine". The PIC, after issuing an Interrupt to the CPU, must somehowinput information into the CPU that can "point" the Program Counter to the serviceroutine associated with the requesting device. This "pointer" is an address in avectoring table and will often be referred to, in this document, as vectoring data. Figure 3a: Polled MethodMICROPROCESSORS LAB 165
    • ELECTRONICS & COMMUNICATION ENGINEERING Figure 3b: Interrupt MethodMICROPROCESSORS LAB 166
    • ELECTRONICS & COMMUNICATION ENGINEERINGThe 8259A is a device specifically designed for use in real time, interrupt drivenmicrocomputer systems. It manages eight levels or requests and has built-in featuresfor expandability to other 8259As (up to 64 levels). It is programmed by the systemssoftware as an I/O peripheral. A selection of priority modes is available to theprogrammer so that the manner in which the requests are processed by the 8259Acan be configured to match his system requirements. The priority modes can bechanged or reconfigured dynamically at any time during the main program. Thismeans that the complete interrupt structure can be defined as required, based on thetotal system environment.INTA (INTERRUPT ACKNOWLEDGE)INTA pulses will cause the 8259A to release vectoring information onto the data bus.The format of this data depends on the system mode (fj-PM) of the 8259A.DATA BUS BUFFERThis 3-state, bidirectional 8-bit buffer is used to interface the 8259A to the systemData Bus. Control words and status information are transferred through the Data BusBuffer.INTERRUPT REQUEST REGISTER (IRR) AND IN-SERVICE REGISTER (ISR)The interrupts at the IR input lines are handled by two registers in cascade, theInterrupt Request Register (IRR) and the In-Service (ISR). The IRR is used to storeall the interrupt levels which are requesting service; and the ISR is used to store allthe interrupt levels which are being serviced.PRIORITY RESOLVERThis logic block determines the priorites of the bits set in the IRR. The highest priorityis selected and strobed into the corresponding bit of the ISR during INTA pulse.INTERRUPT MASK REGISTER (IMR)The IMR stores the bits which mask the interrupt lines to be masked. The IMRoperates on the IRR. Masking of a higher priority input will not affect the interruptrequest lines of lower quality.INT (INTERRUPT)This output goes directly to the CPU interrupt input. The VQH level on this line isdesigned to be fully compatible with the 8080A, 8085A and 8086 input levels.READ/WRITE CONTROL LOGICThe function of this block is to accept OUTput commands from the CPU. It containsthe Initialization Command Word (ICW) registers and Operation Command Word(OCW) registers which store the various control formats for device operation. Thisfunction block also allows the status of the 8259A to be transferred onto the DataBus.CS (CHIP SELECT)A LOW on this input enables the 8259A. No reading or writing of the chip will occurunless the device is selected.WR (WRITE)A LOW on this input enables the CPU to write control words (ICWs and OCWs) tothe 8259A.MICROPROCESSORS LAB 167
    • ELECTRONICS & COMMUNICATION ENGINEERINGRD (READ)A LOW on this input enables the 8259A to send the status of the Interrupt RequestRegister (IRR), In Service Register (ISR), the Interrupt Mask Register (IMR), or theInterrupt level onto the Data Bus.AOThis input signal is used in conjunction with WR and RD signals to write commandsinto the various command registers, as well as reading the various status registers ofthe chip. This line can be tied directly to one of the address lines.MICROPROCESSORS LAB 168
    • ELECTRONICS & COMMUNICATION ENGINEERINGTHE CASCADE BUFFER/COMPARATORThis function block stores and compares the IDs of all 8259As used in the system.The associated three I/O pins (CASO-2) are outputs when the 8259A is used as amaster and are inputs when the 8259A is used as a slave. As a master, the 8259Asends the ID of the interrupting slave device onto the CASO-2 lines. The slave thusselected will send its preprogrammed subroutine address onto the Data Bus duringthe next one or two consecutive INTA pulses. (See section "Cascading the 8259A".)INTERRUPT SEQUENCEThe powerful features of the 8259A in a microcomputer system are itsprogrammability and the interrupt routine addressing capability. The latter allowsdirect or indirect jumping to the specific interrupt routine requested without anypolling of the interrupting devices. The normal sequence of events during an interruptdepends on the type of CPU being used.The events occur as follows in an MCS-80/85 system:1. One or more of the INTERRUPT REQUEST lines (IR7-0) are raised high, setting the corresponding IRR bit(s).2. The 8259A evaluates these requests, and sends an INT to the CPU, if appropriate.MICROPROCESSORS LAB 169
    • ELECTRONICS & COMMUNICATION ENGINEERING3. The CPU acknowledges the INT and responds with an INTA pulse.4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set, and the corresponding IRR bit is reset. The 8259A will also release a CALL instruction code (11001101) onto the 8-bit Data Bus through its D7-0 pins.5. This CALL instruction will initiate two more INTA pulses to be sent to the 8259A from the CPU group.6. These two INTA pulses allow the 8259A to release its preprogrammed subroutine address onto the Data Bus. The lower 8-bit address is re-leased at the first INTA pulse and the higher 8-bit address is released at the second INTA pulse.7. This completes the 3-byte CALL instruction released by the 8259A. In the AEOI mode the ISR bit is reset at the end of the third INTA pulse. Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt sequence.The events occuring in an 8086 system are the same until step 4.4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set and the corresponding IRR bit is reset. The 8259A does not drive the Data Bus during this cycle.5. The 8086 will initiate a second INTA pulse. During this pulse, the 8259A releases an 8-bit pointer onto the Data Bus where it is read by the CPU.6. This completes the interrupt cycle. In the AEOI mode the ISR bit is reset at the end of the second INTA pulse. Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt subroutine.If no interrupt request is present at step 4 of either sequence (i.e., the request wastoo short in duration) the 8259A will issue an interrupt level 7. Both the vectoringbytes and the CAS lines will look like an interrupt level 7 was requested.When the 8259A PIC receives an interrupt, INT becomes active and an interruptacknowledge cycle is started. If a higher priority interrupt occurs between the twoINTA pulses, the INT line goes inactive immediately after the second INTA pulse.After an unspecified amount of time the INT line is activated again to signify thehigher priority interrupt waiting for service. This inactive time is not specified and canvary between parts. The designer should be aware of this consideration whendesigning a system which uses the 8259A. It is recommended that properasynchronous design techniques be followed.MICROPROCESSORS LAB 170
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 171
    • ELECTRONICS & COMMUNICATION ENGINEERINGDuring the third INTA pulse the higher address of the appropriate service routine,which was programmed as byte 2 of the initialization sequence (As-A-is), is enabledonto the bus. When Interval e 4 bits A5±A7 are programmed, while A0±A4 areautomatically inserted by the 8259A. When Interval e 8 only A6 and A7 areprogrammed, while A0±A5 are automatically inserted.MICROPROCESSORS LAB 172
    • ELECTRONICS & COMMUNICATION ENGINEERING8086, 80888086 mode is similar to MCS-80 mode except that only two Interrupt Acknowledgecycles are issued by the processor and no CALL opcode is sent to the processor.The first interrupt acknowledge cycle is similar to that of MCS-80, 85 systems in thatthe 8259A uses it to internally freeze the state of the interrupts for priority resolutionand as a master it issues the interrupt code on the cascade lines at the end of theINTA pulse. On this first cycle it does not issue any data to the processor and leavesits data bus buffers disabled. On the second interrupt acknowledge cycle in 8086mode the master (or slave if so programmed) will send a byte of data to theprocessor with the acknowledged interrupt code composed as follows (note the stateof the ADI mode control is ignored and As-A-i 1 are unused in 8086 mode):Content of Interrupt Vector Byte for 8086 System ModePROGRAMMING THE 8259AThe 8259A accepts two types of command words generated by the CPU:1. Initialization Command Words (ICWs): Before normal operation can begin, each 8259A in the system must be brought to a starting_p_oint—by a sequence of 2 to 4 bytes timed by WR pulses.2. Operation Command Words (OCWs): These are the command words which command the 8259A to operate in various interrupt modes. These modes are: a. Fully nested mode b. Rotating priority mode c. Special mask mode d. Polled mode The OCWs can be written into the 8259A anytime after initialization.IMICROPROCESSORS LAB 173
    • ELECTRONICS & COMMUNICATION ENGINEERINGNITIALIZATION COMMAND WORDS (ICWS)GeneralWhenever a command is issued with AO = 0 and D4 = 1, this is interpreted asInitialization Command Word 1 (ICW1). ICW1 starts the initialization sequence duringwhich the following automatically occur.a. The edge sense circuit is reset, which means that following initialization, an interrupt request (IR) input must make a low-to-high transistion to generate an interrupt.b. The Interrupt Mask Register is cleared.c. IR7 input is assigned priority 7.d. The slave mode address is set to 7.e. Special Mask Mode is cleared and Status Read is set to IRR.f. If IC4 = 0, then all functions selected in ICW4 are set to zero. (Non-Buffered mode*, no Auto-EOI, MCS-80, 85 system).*NOTE:Master/Slave in ICW4 is only used in the buffered mode.Initialization Command Words 1 and 2 (ICW1.ICW2)As-Ais: Page starting address of service routines. In an MCS 80/85 system, the 8request levels will generate CALLs to 8 locations equally spaced in memory. Thesecan be programmed to be spaced at intervals of 4 or 8 memory locations, thus the 8routines will occupy a page of 32 or 64 bytes, respectively.The address format is 2 bytes long (Ao-A-is). When the routine interval is 4, Ao-A4are automatically inserted by the 8259A, while As-A-is are programmed externally.When the routine interval is 8, AQ-AS are automatically inserted by the 8259A, whileAe-A-is are programmed externally.The 8-byte interval will maintain compatibility with current software, while the 4-byteinterval is best for a compact jump table.In an 8086 system A-is-A-n are inserted in the five most significant bits of thevectoring byte and the 8259A sets the three least significant bits according to theinterrupt level. A-IQ-AS are ignored and ADI (Address interval) has no effect.LTIM: If LTIM = 1, then the 8259A will operate in the level interrupt mode. Edgedetect logic on the interrupt inputs will be disabled.ADI: CALL address interval. ADI = 1 then interval = 4; ADI = 0 then interval = 8.SNGL: Single. Means that this is the only 8259A in the system. If SNGL = 1 no ICW3will be issued.IC4: If this bit is set—ICW4 has to be read. If ICW4 is not needed, set IC4 = 0.Initialization Command Word 3 (ICW3)This word is read only when there is more than one 8259A in the system andcascading is used, in which case SNGL = 0. It will load the 8-bit slave register. Thefunctions of this register are:MICROPROCESSORS LAB 174
    • ELECTRONICS & COMMUNICATION ENGINEERINGa. In the master mode (either when SP = 1, or in buffered mode when M/S = 1 in ICW4) a "1" is set for each slave in the system. The master then will release byte 1 of the call sequence (for MCS-80/85 system) and will enable the corresponding slave to release bytes 2 and 3 (for 8086 only byte 2) through the cascade lines.b. In the slave mode (either when SP = 0, or if BUF = 1 and M/S = 0 in ICW4) bits 2-0 identify the slave. The slave compares its cascade input with these bits and, if they are equal, bytes 2 and 3 of the call sequence (or just byte 2 for 8086) are released by it on the Data Bus.MICROPROCESSORS LAB 175
    • ELECTRONICS & COMMUNICATION ENGINEERINGFigure 6: Initialization SequenceInitialization Command Word 4 (ICW4)SFNM: If SFNM = 1 the special fully nested mode is programmed.BUF: If BUF = 1 the buffered mode Js_ programmed. In buffered mode SP/EN be-comes an enable output and the master/ slave determination is by M/S.M/S: If buffered mode is selected: M/S = 1 means the 8259A is programmed to be amaster, M/S = 0 means the 8259A is programmed to be a slave. If BUF = 0, M/S hasno function.AEOI: If AEOI = 1 the automatic end of interrupt mode is programmed. fj-PM:Microprocessor mode: fj-PM = 0 sets the 8259A for MCS-80, 85 system operation, fj-PM = 1 sets the 8259A for 8086 system operation.IRQ2/IRQ9 RedirectionThe redirection of IRQ2 causes quite some confusion, and thus is discussed here. Inthe original XTs there were only one PIC, thus only eight IRQs. However users soonout grew these resources, thus an additional 7 IRQs were added to the PC. Thisinvolved attaching another PIC to the existing one already in the XT. Compatibilityalways causes problems as the new configuration still had to be compatible with oldhardware and software. The "new" configuration is shown below.MICROPROCESSORS LAB 176
    • ELECTRONICS & COMMUNICATION ENGINEERINGThe CPU only has one interrupt line, thus the second controller had to be connectedto the first controller, in a master/slave configuration. IRQ2 was selected for this. Byusing IRQ2 for the second controller, no other devices could use IRQ2, so whathappened to all these devices using IRQ2? Nothing, the interrupt request line foundon the bus, was simply diverted into the IRQ 9 input. As no devices yet used thesecond PIC or IRQ9, this could be done.The next problem was that a hardware device using IRQ2 would install its ISR at INT0x0A. Therefore an ISR routine was used at INT 71h, which sent a EOI to PIC2 andthen called the ISR at INT 0x0A. If you dis-assemble the ISR for IRQ9, it will go alittle like, MOV AL,20 OUT A0,AL ; Send EOI to PIC2 INT 0A ; Call ISR for IRQ2 IRET The routine only has to send a EOI to PIC2, as it is expected that a ISR routine written for IRQ2 will send a EOI to PIC1. This example destroys the contents of Register AL, thus this must be placed on the stack first (Not shown in example). As PIC2 is initialized with a Slave on IRQ2, any request using PIC2 will not call the ISR routine for IRQ2. The 8 bit pointer will come from PIC2.MICROPROCESSORS LAB 177
    • ELECTRONICS & COMMUNICATION ENGINEERINGFigure 7: Initialization Command Word FormatMICROPROCESSORS LAB 178
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 179
    • ELECTRONICS & COMMUNICATION ENGINEERINGOPERATION COMMAND WORDS (OCWS)After the Initialization Command Words (ICWs) are programmed into the 8259A, thechip is ready to accept interrupt requests at its input lines. However, during the8259A operation, a selection of algorithms can command the 8259A to operate invarious modes through the Operation Command Words (OCWs).Figure 8: Operation Command Word FormatMICROPROCESSORS LAB 180
    • ELECTRONICS & COMMUNICATION ENGINEERINGOperation Control Word 1 (OCW1)OCW1 sets and clears the mask bits in the interrupt Mask Register (IMP). My-Morepresent the eight mask bits. M = 1 indicates the channel is masked (inhibited), M =0 indicates the channel is enabled.Operation Control Word 2 (OCW2)R, SL, EOI—These three bits control the Rotate and End of Interrupt modes andcombinations of the two. A chart of these combinations can be found on theOperation Command Word Format.L2, L1, LQ These bits determine the interrupt level acted upon when the SL bit is active.Figure 8: Operation Command Word Format (Continued)Operation Control Word 3 (OCW3)ESMM—Enable Special Mask Mode. When this bit is set to 1 it enables the SMM bitto set or reset the Special Mask Mode. When ESMM = 0 the SMM bit becomes a"dont care".SMM—Special Mask Mode. If ESMM = 1 and SMM = 1 the 8259A will enter SpecialMask Mode. If ESMM = 1 and SMM = 0 the 8259A will revert to normal mask mode.When ESMM = 0, SMM has no effect.MICROPROCESSORS LAB 181
    • ELECTRONICS & COMMUNICATION ENGINEERINGWhen a mode is used which may disturb the fully nested structure, the 8259A mayno longer be able to determine the last level acknowledged. In this case a SpecificEnd of Interrupt must be issued which includes as part of the command the IS levelto be reset. A specific EOI can be issued with OCW2 (EOI = 1, SL = 1, R = 0, andLO-L2 is the binary level of the IS bit to be reset).It should be noted that an IS bit that is masked by an IMP bit will not be cleared by anon-specific EOI if the 8259A is in the Special Mask Mode.Fully Nested ModeThis mode is entered after initialization unless another mode is programmed. Theinterrupt requests are ordered in priority from 0 through 7 (0 highest). When aninterrupt is acknowledged the highest priority request is determined and its vectorplaced on the bus. Additionally, a bit of the Interrupt Service register (ISO-7) is set.This bit remains set until the microprocessor issues an End of Interrupt (EOI)command immediately before returning from the service routine, or if AEOI(Automatic End of Interrupt) bit is set, until the trailing edge of the last INTA. Whilethe IS bit is set, all further interrupts of the same or lower priority are inhibited, whilehigher levels will generate an interrupt (which will be acknowledged only if themicroprocessor internal Interupt enable flip-flop has been re-enabled throughsoftware).After the initialization sequence, IRQ has the highest prioirity and IR7 the lowest.Priorities can be changed, as will be explained, in the rotating priority mode.End of Interrupt (EOI)The In Service (IS) bit can be reset either automatically following the trailing edge ofthe last in sequence INTA pulse (when AEOI bit in ICW1 is set) or by a commandword that must be issued to the 8259A before returning from a service routine (EOIcommand). An EOI command must be issued twice if in the Cascade mode, once forthe master and once for the corresponding slave.There are two forms of EOI command: Specific and Non-Specific. When the 8259A isoperated in modes which perserve the fully nested structure, it can determine whichIS bit to reset on EOI. When a Non-Specific EOI command is issued the 8259A willautomatically reset the highest IS bit of those that are set, since in the fully nestedmode the highest IS level was necessarily the last level acknowledged and serviced.A non-specific EOI can be issued with OCW2 (EOI = 1, SL = 0, R = 0).Automatic End of Interrupt (AEOI) ModeIf AEOI = 1 in ICW4, then the 8259A will operate in AEOI mode continuously untilreprogrammed by ICW4. in this mode the 8259A will automatically perform a non-specific EOI operation at the trailing edge of the last interrupt acknowledge pulse(third pulse in MCS-80/85, second in 8086). Note that from a system standpoint, thismode should be used only when a nested multilevel interrupt structure is not requiredwithin a single 8259A.The AEOI mode can only be used in a master 8259A and not a slave. 8259As with acopyright date of 1985 or later will operate in the AEOI mode as a master or a slave.Automatic Rotation (Equal Priority Devices)In some applications there are a number of interrupting devices of equal priority. Inthis mode a device, after being serviced, receives the lowest priority, so a devicerequesting an interrupt will have to wait,MICROPROCESSORS LAB 182
    • ELECTRONICS & COMMUNICATION ENGINEERINGin the worst case until each of 7 other devices are serviced at most once. Forexample, if the priority and "in service" status is:Before Rotate (IR4 the highest prioirity requiring service)After Rotate (IR4 was serviced, all other priorities rotated correspondingly)There are two ways to accomplish Automatic Rotation using OCW2, the Rotation onNon-Specific EO Command (R = 1, SL = 0, EOI = 1) and the Rotate in AutomaticEOI Mode which is set by (R = 1, SL = 0, EOI = 0) and cleared by (R = 0, SL = 0, EOI= 0).Specific Rotation (Specific Priority)The programmer can change priorities by programming the bottom priority and thusfixing all other priorities; i.e., if IRS is programmed as the bottom priority device, thenIR6 will have the highest one.The Set Priority command is issued in OCW2 where: R = 1, SL = 1, LO-L2 is thebinary priority level code of the bottom priority device.Observe that in this mode internal status is updated by software control duringOCW2. However, it is independent of the End of Interrupt (EOI) command (alsoexecuted by OCW2). Priority changes can be executed during an EOI command byusing the Rotate on Specific EOI command in OCW2 (R = 1, SL = 1, EOI = 1 andLO-L2 = IR level to receive bottom priority).Interrupt MasksEach Interrupt Request input can bem masked individually by the Interrupt MaskRegister (IMR) programmed through OCW1.MICROPROCESSORS LAB 183
    • ELECTRONICS & COMMUNICATION ENGINEERINGEach bit in the IMR masks one interrupt channel if it is set (1). Bit 0 masks IRQ, Bit 1masks IR1 and so forth. Masking an IR channel does not affect the other channelsoperation.Special Mask ModeSome applications may require an interrupt service routine to dynamically alter thesystem priority structure during its execution under software control. For example, theroutine may wish to inhibit lower priority requests for a portion of its execution butenable some of them for another portion.The difficulty here is that if an Interrupt Request is acknowledged and an End ofInterrupt command did not reset its IS bit (i.e., while executing a service routine), the8259A would have inhibited all lower priority requests with no easy way for theroutine to enable them.That is where the Special Mask Mode comes in. In the special Mask Mode, when amask bit is set in OCW1, it inhibits further interrupts at that level and enablesinterrupts from a/1 other levels (lower as well as higher) that are not masked.Thus, any interrupts may be selectively enabled by loading the mask register.The special Mask Mode is set by OWC3 where: SSMM = 1,SMM = 1, and clearedwhere SSMM = 1, SMM = 0.Poll CommandIn Poll mode the INT output functions as it normally does. The microprocessor shouldignore this output. This can be accomplished either by not connecting the INT outputor by masking interrupts within the microprocessor, thereby disabling its interruptinput. Service to devices is achieved by software using a Poll command.The Poll command is issued by setting P = T in OCW3. The 82_59A treats the nextRD pulse to the 8259A (i.e., RD = 0, CS = 0) as an interrupt acknowledge, sets theappropriate IS bit if there is a request, and reads the priority level. Interrupt is frozenfrom WR to RD.This mode is useful if there is a routine command common to several levels so thatthe INTA sequence is not needed (saves ROM space). Another application is to usethe poll mode to expand the number of priority levels to more than 64.MICROPROCESSORS LAB 184
    • ELECTRONICS & COMMUNICATION ENGINEERINGReading the 8259A StatusThe input status of several internal registers can be read to update the userinformation on the system.Figure 9: Priority Cell—Simplified Logic DiagramThe following registers can be read via OCW3 (IRR and ISR or OCW1 [IMP]).Interrupt Request Register (IRR): 8-bit register which contains the levels requestingan interrupt to be acknowledged. The highest request level is reset from the IRRwhen an interrupt is acknowledged. (Not affected by IMR.)In-Service Register (ISR): 8-bit register which contains the priority levels that arebeing serviced. The ISR is updated when an End of Interrupt Command is issued.Interrupt Mask Register: 8-bit register which contains the interrupt request lines whichare masked.The IRR can be read when, prior to the RD pulse, a Read Register Command isissued with OCW3 (RR = 1, RIS = 0.)The ISR can be read, when, prior to the RD pulse, a Read Register Command isissued with OCW3 (RR = 1, RIS = 1).There is no need to write an OCW3 before every status read operation, as long asthe status read corresponds with the previous one; i.e., the 8259A "remembers"whether the IRR or ISR has been previously selected by the OCW3. This is not truewhen poll is used.MICROPROCESSORS LAB 185
    • ELECTRONICS & COMMUNICATION ENGINEERINGAfter initialization the 8259A is set to IRR.For reading the IMR, no OCW3 is needed. The out-put data bus will contain the IMRwhenever RD is active and AO = 1 (OCW1).Polling overrides status read when P = 1, RR = 1 in OCW3.Edge and Level Triggered ModesThis mode is programmed using bit 3 in ICW1.If LTIM = 0, an interrupt request will be recognized by a low to high transition on anIR input. The IR input can remain high without generating another interrupt.Figure 10: IR Triggering Timing RequirementsIf LTIM = T, an interrupt request will be recognized by a high level on IR Input, andthere is no need for an edge detection. The interrupt request must be removedbefore the EOI command is issued or the CPU interrupts is enabled to prevent asecond interrupt from occurring.The priority cell diagram shows a conceptual circuit of the level sensitive and edgesensitive input circuitry of the 8259A. Be sure to note that the request latch is atransparent D type latch.In both the edge and level triggered modes the IR inputs must remain high until afterthe falling edge of the first INTA. If the IR input goes low before this time a DEFAULTIR7 will occur when the CPU acknowledges the interrupt. This can be a usefulsafeguard for detecting interrupts caused by spurious noise glitches on the IR inputs.To implement this feature the IR7 routine is used for "clean up" simply executing areturn instruction, thus ignoring the interrupt. If IR7 is needed for other purposes adefault IR7 can still be detected by reading the ISR. A normal IR7 interrupt will setthe corresponding ISR bit, a default IR7 wont. If a default IR7 routine occurs during anormal IR7 routine, however, the ISR will remain set. In this case it is necessary tokeep track of whether or not the IR7 routine was previously entered. If another IR7occurs it is a default.MICROPROCESSORS LAB 186
    • ELECTRONICS & COMMUNICATION ENGINEERINGThe Special Fully Nest ModeThis mode will be used in the case of a big system where cascading is used, and thepriority has to be conserved within each slave. In this case the fully nested mode willbe programmed to the master (using ICW4). This mode is similar to the normalnested mode with the following exceptions:a. When an interrupt request from a certain slave is in service this slave is not locked out from the masters priority logic and further interrupt requests from higher priority IRs within the slave will be recognized by the master and will initiate interrupts to the processor. (In the normal nested mode a slave is masked out when its request is in service and no higher requests from the same slave can be serviced.)b. When exiting the Interrupt Service routine the software has to check whether the interrupt serviced was the only one from that slave. This is done by sending a non-specific End of Interrupt (EOI) command to the slave and then reading its In-Service register and checking for zero. If it is empty, a non-specific EOI can be sent to the master too. If not, no EOI should be sent.Buffered ModeWhen the 8259A is used in a large system where bus driving buffers are required onthe data bus and the cascading mode is used, there exists the problem of enablingbuffers.The buffered mode will structure the 8259A to send an enable signal on SP/EN toenable the buffers. In this mode, wheneyerjhe 8259As data bus outputs are enabled,the SP/EN output becomes active.This modification forces the use of software programming to determine whether the8259A is a master or a slave. Bit 3 in ICW4 programs the buffered mode, and bit 2 inICW4 determines whether it is a master or a slave.CASCADE MODEThe 8259A can be easily interconnected in a system of one master with up to eightslaves to handle up to 64 priority levels.The master controls the slaves through the 3 line cascade bus. The cascade busacts like chip selects to the slaves during the INTA sequence.In a cascade configuration, the slave interrupt outputs are connected to the masterinterrupt request inputs. When a slave request line is activated and afterwardsacknowledged, the master will enable the corresponding slave to release the deviceroutine address during bytes 2 and 3 of INTA. (Byte 2 only for 8086/8088).The cascade bus lines are normally low and will contain the slave address code fromthe trailing edge of the first INTA pulse to the trailing edge of the third pulse. Each8259A in the system must follow a separate initialization sequence and can be pro-grammed to work in a different mode. An EOI command must be issued twice: oncefor the master and once for the corresponding slave. An address decoder is requiredto activate the Chip Select (CS) input of each 8259A.The cascade lines of the Master 8259A are activated only for slave inputs, non-slaveinputs leave the cascade line inactive (low).MICROPROCESSORS LAB 187
    • ELECTRONICS & COMMUNICATION ENGINEERING Figure 11: Cascading the 8259A ABSOLUTE MAXIMUM RATINGS* Ambient Temperature Under Bias......0° to 70° C C Storage Temperature ..........-65° to +150° C C Voltage on Any Pin with Respect to Ground..........-0.5V to +7V Power Dissipation...........................1W NOTICE: This is a production data sheet. The specifications are subject to change without notice. "WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. D.C. CHARACTERISTICS TA = 0°Cto70° VCc = 5V + 10% C,Symbol Parameter Min Max Units Test ConditionsVIL Input Low Voltage -0.5 0.8 VVIH Input High Voltage 2.0* Vcc + 0.5V VVOL Output Low Voltage 0.45 V IQL = 2.2 mAVOH Output High Voltage 2.4 V IQH = -400fj,AVOH(INT) Interrupt Output High 3.5 V IOH =-100ju,A Voltage 2.4 V IQH = -400fj,AILI Input Load Current -10 + 10 £A 0V < VIN < VccILOL Output Leakage Current -10 + 10 ^A 0.45V < VQUT ^ Vcc MICROPROCESSORS LAB 188
    • ELECTRONICS & COMMUNICATION ENGINEERINGSymbol Parameter Min Max Units Test ConditionsICG VCG Supply Current 85 mAILIR IR Input Load Current -300 ^A V|N = 0 10 fj-A VIN = Vcc NOTE: For Extended Temperature EXPRESS V|H = 2.3V. CAPACITANCE TA = 25° VCc = 0V C;Symbol Parameter Min Typ Max Unit Test ConditionsCIN Input Capacitance 10 PF fc = 1 MHzC|/O I/O Capacitance 20 PF Unmeasured Pins Returned to Vss A.C. CHARACTERISTICS TA = 0°Cto70° VCc = 5V +10% C, TIMING REQUIREMENTS 8259A 8259A-2 TestSymbol Parameter Units Min Max Min Max ConditionsTAHRL AO/CS Setup to RD/INTA i 0 0 nsTRHAX AO/CS Hold after RD/INTA T 0 0 nsTRLRH RD Pulse Width 235 160 nsTAHWL AO/CS Setup to WR i 0 0 nsTWHAX AO/CS Hold after WRf 0 0 nsTWLWH WR Pulse Width 290 190 nsTDVWH Data Setup to WR t 240 160 nsTWHDX Data Hold after WRf 0 0 nsTJLJH Interrupt Request Width (Low) 100 100 ns See Note 1TCVIAL Cascade Setup to Second or 55 40 ns Third INTA i (Slave Only)TRHRL End of RD to Next RD 160 100 ns End of INTA to Next INTA within an INTA Sequence OnlyTWHWL End of WR to Next WR 190 100 nsTCHCL End of Command to Next 500 150 ns Command (Not Same 500 300 Command Type) End of INTA Sequence to Next INTA Sequence. MICROPROCESSORS LAB 189
    • ELECTRONICS & COMMUNICATION ENGINEERING•Worst case timing for TCHCL in an actual microprocessor system is typically muchgreater than 500 ns (i.e. 8085A = 1.6 fis, 8085A-2 = 1 fis, 8086 = 1 fiS, 8086-2 = 625ns)NOTE:This is the low time required to clear the input latch in the edge triggered mode.TIMING RESPONSESMICROPROCESSORS LAB 190
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 191
    • ELECTRONICS & COMMUNICATION ENGINEERINGData Sheet Revision ReviewThe following changes have been made since revision 2 of the 8259A data sheet.1. The first paragraph of the Poll Command section was rewritten to clarify the status of the INT pin.2. A paragraph was added to the Interrupt Sequence section to indicate the status of the INT pin during multiple interrupts.3. A reference to PLCC packaging was added.4. All references to the 8259A-8 have been deleted.MICROPROCESSORS LAB 192
    • ELECTRONICS & COMMUNICATION ENGINEERING 5.Intel 8279 overviewMICROPROCESSORS LAB 193
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 194
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 195
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 196
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 197
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 198
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 199
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 200
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 201
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 202
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 203
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 204
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 205
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 206
    • ELECTRONICS & COMMUNICATION ENGINEERING 6. Intel 8255 overviewIntel 8255 :The Intel 8255A is a general purpose programmable I/O device which is designed foruse with all Intel and most other microprocessors. It provides 24 I/O pins which maybe individually programmed in 2 groups of 12 and used in 3 major modes ofoperation.In MODE 0, each group of 12 I/O pins may be programmed in sets of 4 and 8 to beinputs or outputs. In MODE 1, each group may be programmed to have 8 lines ofinput or output. 3 of the remaining 4 pins are used for handshaking and interruptcontrol signals. MODE 2 is a strobed bi-directional bus configuration.The 8255 is a 40 pin integrated circuit (IC), designed to perform a variety of interfacefunctions in a computer environment. The 8255 wasnt originally designed to beconnected to the Z80. It was manufactured by Intel for the 8080 microprocessor. Fig: PIN Diagram of Intel 8255 PIN configuration D0 - D7 These are the data input/output lines for the device. Allinformation read from and written to the 8255 occurs via these 8 data lines.CS (ChipSelect Input). If this line is a logical 0, the microprocessor can read and write to the8255.MICROPROCESSORS LAB 207
    • ELECTRONICS & COMMUNICATION ENGINEERINGRD (Read Input) Whenever this input line is a logical 0 and the RD input is a logical0, the 8255 data outputs are enabled onto the system data bus.WR (Write Input) Whenever this input line is a logical 0 and the CS input is a logical0, data is written to the 8255 from the system data busA0 - A1 (Address Inputs) The logical combination of these two input lines determineswhich internal register of the 8255 data is written to or read from.RESET The 8255 is placed into its reset state if this input line is a logical 1. Allperipheral ports are set to the input mode.PA0 - PA7, PB0 - PB7, PC0 - PC7 These signal lines are used as 8-bit I/O ports.They can be connected to peripheral devices. The 8255 has three 8 bit I/O ports andeach one can be connected to the physical lines of an external device. These linesare labeled PA0-PA7, PB0-PB7, and PC0-PC7. The groups of the signals are dividedinto three different I/O ports labeled port A (PA), port B (PB), and port C (PC). Fig : Block diagram of Intel 8255Block diagram of the 8255 :Two control groups, labeled group A control and group B control define how the threeI/O ports operate. There are several different operating modes for the 8255 andthese modes must be defined by the CPU writing programming or control words tothe device 8255.The line group of port C consists of two 4 bit ports. One of the 4 bit group isassociated with group A control and the other 4 bit group with group B control deviceMICROPROCESSORS LAB 208
    • ELECTRONICS & COMMUNICATION ENGINEERINGsignals. The upper 4 bits of port C are associated with group A control while thelower 4 bits are associated with group B control.The final logic blocks are read/write control logic and data bus buffer. These blocksprovide the electrical interface between the Z80 and the 8255.The data bus buffer buffers the data I/O lines to/from the Z80 data bus. Theread/write control logic routes the data to and from the correct internal registers withthe right timing. The internal path being enabled depends on the type of operationperformed by the Z80. The type of operation can be I/O read or I/O write.Control Word RegisterBefore going to discuss the detailed description about the usage of the 8255 in theMZ-700, you should see the bit definitions of the 8255 control word register (port$E003 of the MZ-700).If bit 7 of the control word is a logical 1 then the 8255 will be configured. See thepicture of the practicable configurations:Mode definition of the 8255 control registerto configure the 8255If bit 7 of the control word is a logical 0 then each bit of the port C can be set or reset.See the picture of the practicable possibilities:Bit definitions of the 8255 control register to modify single bits of port CMICROPROCESSORS LAB 209
    • ELECTRONICS & COMMUNICATION ENGINEERINGExamples:If you want to set/reset bit 0 of port C then set D3 to D1 to 000.Bit 1 of port C will be set/reset if you code 001 to D3 to D1.Bit 6 of port C is set/reset if D3 to D1 is 110.MICROPROCESSORS LAB 210
    • ELECTRONICS & COMMUNICATION ENGINEERING 7. Intel 8251 overview Intel® 8251A PROGRAMMABLE COMMUNICATION INTERFACE• Synchronous and Asynchronous Operation• Synchronous 5-8 Bit Characters; Internal or External Character Synchronization; Automatic Sync Insertion• Asynchronous 5-8 Bit Characters; Clock Rate – 1, 16 or 64 Times Baud Rate; Break Character Generation; 1, 11/2, or 2 Stop Bits; False Start Bit Detection; Automatic Break Detect and Handling• Synchronous Baud Rate – DC to 64K Baud• Asynchronous Baud Rate – DC to 19.2K Baud• Full-Duplex, Double-Buffered Transmitter and Receiver• Error Detection – Parity, Overrun and Framing• Compatible with an Extended Range of Intel Microprocessors• 28-Pin DIP Package• All Inputs and Outputs are TTL compatible• Available in EXPRESS and Military VersionsThe Intel® 8251A is the industry standard Universal Synchronous/AsynchronousReceiver/Transmitter (USART), designed for data communications with Intelsmicroprocessor families such as MCS-48,80, 85, and iAPX-86, 88. The 8251A isused as a peripheral device and is programmed by the CPU to operate using virtuallyany serial data transmission technique presently in use (including IBM “bi-sync”). TheUSART accepts data characters from the CPU in parallel format and then convertsthem into a continuous serial data stream for transmission. Simultaneously, it canreceive serial data streams and convert them into parallel data characters for theCPU. The USART will signal the CPU whenever it can accept a new character fortransmission or whenever it has received a character for the CPU. The CPU can readthe complete status of the USART at any time. These include data transmissionerrors and control signals such as SYNDET, TxEMPTY. The chip is fabricated usingIntels high performance HMOS technology.MICROPROCESSORS LAB 211
    • ELECTRONICS & COMMUNICATION ENGINEERINGFigure 1: Block DiagramFEATURES AND ENHANCEMENTSThe 8251A is an advanced design of the industry standard USART, the Intel® 8251.The 8251A operates with an extended range of Intel microprocessors and maintainscompatibility with the 8251. Familiarization time is minimal because of compatibilityand involves only knowing the additional features and enhancements, and reviewingthe AC and DC specifications of the 8251 A.The 8251A incorporates all the key features of the 8251 and has the followingadditional features and enhancements:• 8251A has double-buffered data paths with separate I/O registers for control, status, Data In, and Data Out, which considerably simplifies control programming and minimizes CPU overhead.• In asynchronous operations, the Receiver detects and handles “break” automatically, relieving the CPU of this task.• A refined Rx initialization prevents the Receiver-from starting when in “break” state, preventing unwanted interrupts from a disconnected USART.• At the conclusion of a transmission, TxD line will always return to the marking state unless SBRK is programmed.• Tx Enable logic enhancement prevents a Tx Disable command from halting transmission until all data previously written has been transmitted. The logic also prevents the transmitter from turning off in the middle of a word.• When External Sync Detect is programmed, Internal Sync Detect is disabled, and an External Sync Detect status is provided via a flip-flop which clears itself upon a status read.• Possibility of false sync detect is minimized by ensuring that if double character sync is programmed, the characters be contiguously detected and also by clearing the Rx register to all ones whenever Enter Hunt command is issued in Sync mode.MICROPROCESSORS LAB 212
    • ELECTRONICS & COMMUNICATION ENGINEERING• As long as the 8251A is not selected, the RD and WR do not affect the internal operation of the device.• The 8251A Status can be read at any time but the status update will be inhibited during status read.• The 8251A is free from extraneous glitches and has enhanced AC and DC characteristics, providing higher speed and better operating margins.• Synchronous Baud rate from DC to 64K.FUNCTIONAL DESCRIPTIONGeneralThe 8251A is a Universal Synchronous/Asynchronous Receiver/Transmitterdesigned for a wide range of Intel microcomputers such as 8048, 8080, 8085, 8086and 8088. Like other I/O devices in a microcomputer system, its functionalconfiguration is programmed by the systems software for maximum flexibility. The8251A can support most serial data techniques in use, including IBM “bi-sync”.In a communication environment an interface device must convert parallel formatsystem data into serial format for transmission and convert incoming serial formatdata into parallel system data for reception. The interface device must also delete orinsert bits or characters that are functionally unique to the communication technique.In essence, the interface should appear “transparent” to the CPU, a simple input oroutput of byte-oriented system data.Data Bus BufferThis 3-state bidirectional, 8-bit buffer is used to interface the 8251A to the systemData Bus. Data is transmitted or received by the buffer upon execution of INput orOUTput instructions of the CPU. Control words, Command words and Statusinformation are also transferred through the Data Bus Buffer. The Command Status,Data-in and Data-Out registers are separate, 8-bit registers communicating with thesystem bus through the Data Bus Buffer.This functional block accepts inputs from the system Control bus and generatescontrol signals for overall device operation. It contains the Control Word Register andCommand Word Register that store the various control formats for the devicefunctional definition.RESET (Reset)A “high” on this input forces the 8251A into an “Idle” mode. The device will remain at“Idle” until a new set of control words is written into the 8251A to program itsfunctional definition. Minimum RESET pulse width is 6 ICY (clock must be running).A command reset operation also puts the device into the “Idle” state.MICROPROCESSORS LAB 213
    • ELECTRONICS & COMMUNICATION ENGINEERINGFigure 3: 8251A Block Diagram Showing Data Bus Buffer and Read/Write LogicFunctionsCLK (Clock)The CLK input is used to generate internal device timing and is normally connectedto the Phase 2 (TTL) output of the Clock Generator. No external inputs or outputs arereferenced to CLK but the frequency of CLK must be greater than 30 times theReceiver or Transmitter data bit rates.WR (Write)A “low” on this input informs the 8251A that the CPU is writing data or control wordsto the 8251 A.RD (Read)A “low” on this input informs the 8251A that the CPU is reading data or statusinformation from the 8251A.C/D (Control/Data)This input, in conjunction with the WR and RD inputs, informs the 8251A that theword on the Data Bus is either a data character, control word or status information.1 = CONTROL/STATUS; 0 = DATA.MICROPROCESSORS LAB 214
    • ELECTRONICS & COMMUNICATION ENGINEERINGCS (Chip Select)A “low” on this input selects the 8251 A. No reading or writing will occur unless thedevice is selected. When CS is high, the Data Bus is in the float state and RD andWR have no effect on the chip.Modem ControlThe 8251A has a set of control inputs and outputs that can be used to simplify theinterface to almost any modem. The modem control signals are general purpose innature and can be used for functions other than modem control, if necessary.DSR (Data Set Ready)The DSR input signal is a general-purpose, 1-bit inverting input port. Its condition canbe tested by the CPU using a Status Read operation. The DSR input is normallyused to test modem conditions such as Data Set Ready.DTR (Data Terminal Ready)The DTR output signal is a general-purpose, 1-bit inverting output port. It can be set“low” by programming the appropriate bit in the Command Instruction word. The DTRoutput signal is normally used for modem control such as Data Terminal Ready.RTS (Request to Send)The RTS output signal is a general-purpose, 1-bit inverting output port. It can be set“low” by programming the appropriate bit in the Command Instruction word. The RTSoutput signal is normally used for modem control such as Request to Send.CTS (Clear to Send)A “low” on this input enables the 8251A to transmit serial data if the Tx Enable bit inthe Command byte is set to a “one”. If either a Tx Enable off or CTS off condition”occurs while the Tx is in operation, the Tx will transmit all the data in the USART,written prior to Tx Disable command before shutting down.Transmitter BufferThe Transmitter Buffer accepts parallel data from the Data Bus Buffer, converts it toa serial bit stream, inserts the appropriate characters or bits (based on thecommunication technique) and outputs a composite serial stream of data on the TxDoutput pin on the falling edge of TxC. The transmitter will begin transmission uponbeing enabled if CTS = 0. The TxD line will be held in the marking state immediatelyupon a master Reset or when Tx Enable or CTS is off or the transmitter is empty.Transmitter ControlThe Transmitter Control manages all activities associated with the transmission ofserial data. It accepts and issues signals both externally and internally to accomplishthis function.TxRDY (Transmitter Ready)This output signals the CPU that the transmitter is ready to accept a data character.The TxRDY output pin can be used as an interrupt to the system, since it is maskedby TxEnable; or, for Polled operation, the CPU can check TxRDY using a StatusRead operation. TxRDY is automatically reset by the leading edge of WR when adata character is loaded from the CPU.MICROPROCESSORS LAB 215
    • ELECTRONICS & COMMUNICATION ENGINEERINGNote that when using the Polled operation, the TxRDY status bit is not masked byTxEnable, but will only indicate the Empty/Full Status of the Tx Data Input Register.TxE (Transmitter Empty)When the 8251A has no characters to send, the TxEMPTY output will go “high”. Itresets upon receiving a character from CPU if the transmitter is enabled. TxEMPTYremains high when the transmitter is disabled. TxEMPTY can be used to indicate theend of a transmission mode, so that the CPU “knows” when to “turn the line around”in the half-duplex operational mode.In the Synchronous mode, a “high” on this output indicates that a character has notbeen loaded and the SYNC character or characters are about to be or are beingtransmitted automatically as “filters”. Tx EMPTY does not go low when the SYNCcharacters are being shifted out.Figure 4.8251A Block Diagram Showing Modem and Transmitter Buffer andControl FunctionsTxC (Transmitter Clock)The Transmitter Clock controls the rate at which the character is to be transmitted. Inthe Synchronous transmission mode, the Baud Rate (1x) is equal to the TxCfrequency. In Asynchronous transmission mode, the baud rate is a fraction of theactual TxC frequency. A portion of the mode instruction selects this factor; it can be1, 1/16 or %4 the TxC.For Example:If Baud Rate equals 110 Baud, TxC equals 110 Hz in the 1x mode. TxC equals 1.72kHz in the 16x mode. TxC equals 7.04 kHz in the 64x mode.The falling edge of TxC shifts the serial data out of the 8251 A.MICROPROCESSORS LAB 216
    • ELECTRONICS & COMMUNICATION ENGINEERINGReceiver BufferThe Receiver accepts serial data, converts this serial input to parallel format, checksfor bits or characters that are unique to the communication technique and sends an“assembled” character to the CPU. Serial data is input to RxD pin, and is clocked inon the rising edge of RxC.Receiver ControlThis functional block manages all receiver-related activities which consists of thefollowing features.The RxD initialization circuit prevents the 8251A from mistaking an unused input linefor an active low data line in the “break condition”. Before starting to receive serialcharacters on the RxD line, a valid “1” must first be detected after a chip masterReset. Once this has been determined, a search for a valid low (Start bit) is enabled.This feature is only active in the asynchronous mode, and is only done once for eachmaster Reset.The False Start bit detection circuit prevents false starts due to a transient noisespike by first detecting the falling edge and then strobing the normal center of theStart bit (RxD = low).Parity error detection sets the corresponding status bit.The Framing Error status bit is set if the Stop bit is absent at the end of the data byte(asynchronous mode).RxRDY (Receiver Ready)This output indicates that the 8251A contains a character that is ready to be input tothe CPU. RxRDY can be connected to the interrupt structure of the CPU or, for polledoperation, the CPU can check the condition of RxRDY using a Status Readoperation.RxEnabie, when off, holds RxRDY in the Reset Condition. For Asynchronous mode,to set RxRDY, the Receiver must be enabled to sense a Start Bit and a completecharacter must be assembled and transferred to the Data Output Register. ForSynchronous mode, to set RxRDY, the Receiver must be enabled and a charactermust finish assembly and be transferred to the Data Output Register.Failure to read the received character from the Rx Data Output Register prior to theassembly of the next Rx Data character will set overrun condition error and theprevious character will be written over and lost. If the Rx Data is being read by theCPU when the internal transfer is occurring, overrun error will be set and the oldcharacter will be lost.RxC (Receiver Clock)The Receiver Clock controls the rate at which the character is to be received. InSynchronous Mode, the_Baud Rate (1x) is equal to theactual frequency of RxC. InAsynchronous Mode, the Baud Rate is a fraction of the actual RxC frequency. Aportion of the mode instruction selects this factor: 1, n/16 or Vw the RxC.For Example:Baud Rate equals 300 Baud, if RxC equals 300 Hz in the 1x mode; RxC equals 4800Hz in the 16x mode; RxC equals 19.2 kHz in the 64x mode.MICROPROCESSORS LAB 217
    • ELECTRONICS & COMMUNICATION ENGINEERINGBaud Rate equals 2400 Baud, if RxC equals 2400 Hz in the 1 x mode; RxC equals38.4 kHz in the 16 mode; RxC equals 153.6 kHz in the 64 mode.Figure 5.8251A Block Diagram Showing Receiver Buffer and Control FunctionsData is sampled into the 8251A on the rising edge of RxC.NOTE:In most communication systems, the 8251A will be handling both the transmissionand reception operations of a single link. Consequently, the Receive and TransmitBaud Rates will be the same. Both TxC and RxC will require identical frequencies forthis operation and can be tied together and connected to a single frequency source(Baud Rate Generator) to simplify the interface.SYNDET (SYNC Detect / BRKDET Break Detect)This pin is used in Synchronous Mode for SYNDET and may be used as either inputor output, programmable through the Control Word. It is reset to output mode lowupon RESET. When used as an output (internal Sync mode), the SYNDET pin will go"high" to indicate that the 8251A has located the SYNC character in the Receivemode, if the 8251A is programmed to use double Sync characters (bi-sync), thenSYNDET will go "high" in the middle of the last bit of the second Sync character.SYNDET is automatically reset upon a Status Read operation.When used as an input (external SYNC detect mode), a positive going signal willcause the 8251A to start assembling data characters on the rising edge of the nextRxC. Once in SYNC, the "high" input signal can be removed. When External SYNCDetect is programmed, Internal SYNC Detect is disabled.MICROPROCESSORS LAB 218
    • ELECTRONICS & COMMUNICATION ENGINEERINGBREAK (Async Mode Only)This output will go high whenever the receiver remains low through two consecutivestop bit sequences (including the start bits, data bits, and parity bits). Break Detectmay also be read as a Status bit. It is reset only upon a master chip Reset or Rx Datareturning to a "one" state.DETAILED OPERATION DESCRIPTION Programming the 8251AGeneralThe complete functional definition of the 8251A is programmed by the systemssoftware. A set of control words must be sent out by the CPU to initialize the 8251Ato support the desired communications format. These control words will program the:BAUD RATE, CHARACTER LENGTH, NUMBER OF STOP BITS, SYNCHRONOUSor ASYNCHRONOUS OPERATION, EVEN/ODD/OFF PARITY, etc. in the SynchronousMode, options are also provided to select either internal or external charactersynchronization.Once programmed, the 8251A is ready to perform its communication functions. TheTxRDY output is raised “high” to signal the CPU that the 8251A is ready to receive adata character from the CPU. This output (TxRDY) is reset automatically when theCPU writes a character into the 8251 A. On the other hand, the 8251A receives serialdata from the MODEM or I/O device. Upon receiving an entire character, the RxRDYoutput is raised “high” to signal the CPU that the 8251A has a complete characterready for the CPU to fetch. RxRDY is reset automatically upon the CPU data readoperation.The 8251A cannot begin transmission until the Tx Enable (Transmitter Enable) bit isset in the Command Instruction and it has received a Clear To Send (CTS) input. TheTxD output will be held in the marking state upon Reset.MICROPROCESSORS LAB 219
    • ELECTRONICS & COMMUNICATION ENGINEERING Figure 7: Typical Data BlockProgramming the 8251APrior to starting data transmission or reception, the 8251A must be loaded with a setof control words generated by the CPU. These control signals define the completefunctional definition of the 8251A and must immediately follow a Reset operation(internal or external).The control words are split into two formats:1. Mode Instruction2. Command InstructionMode InstructionThis instruction defines the general operational characteristics of the 8251 A. It mustfollow a Reset operation (internal or external). Once the Mode Instruction has beenwritten into the 8251A by the CPU, SYNC characters or Command Instructions maybe written.Command InstructionThis instruction defines a word that is used to control the actual operation of the 8251A.Both the Mode and Command Instructions must conform to a specified sequence forproper device operation (see Figure 7). The Mode Instruction must be writtenimmediately following a Reset operation, prior to using the 8251A for datacommunication.All control words written into the 8251A after the Mode Instruction will load theCommand Instruction. Command Instructions can be written into the 8251A at anytime in the data block during the operation of the 8251 A. To return to the ModeInstruction format, the master Reset bit in the Command Instruction word can be setto initiate an internal Reset operation which automatically places the 8251A back intothe Mode Instruction format. Command Instructions must follow the Mode Instructionor Sync characters.MICROPROCESSORS LAB 220
    • ELECTRONICS & COMMUNICATION ENGINEERINGMode Instruction DefinitionThe 8251A can be used for either Asynchronous or Synchronous datacommunication. To understand how the Mode Instruction defines the functionaloperation of the 8251 A, the designer can best view the device as two separatecomponents, one Asynchronous and the other Synchronous, sharing the samepackage. The format definition can be changed only after a master chip Reset. Forexplanation purposes the two formats will be isolated.NOTE:When parity is enabled it is not considered as one of the data bits for the purpose ofprogramming word length. The actual parity bit received on the Rx Data line cannotbe read on the Data Bus. In the case of a programmed character length of less than8 bits, the least significant Data Bus bits will hold the data; unused bits are “dontcare” when writing data to the 8251 A, and will be “zeros” when reading the data fromthe 8251 A.Asynchronous Mode (Transmission)Whenever a data character is sent by the CPU the 8251A automatically adds a Startbit (low level) followed by the data bits (least significant bit first), and the programmednumber of Stop bits to each character. Also, an even or odd Parity bit is inserted priorto the Stop bit(s), as defined by the Mode Instruction. The character is thentransmitted as a serial data stream on the TxD output. The serial data is shifted outon the falling edge of TxC at a rate equal to 1, 1/16, or 1/64 that of the TxC, as definedby the Mode Instruction. BREAK characters can be continuously sent to the TxD ifcommanded to do so.When no data characters have been loaded into the 8251A the TxD output remains“high” (marking) unless a Break (continuously low) has been programmed.Asynchronous Mode (Receive)The RxD line is normally high. A falling edge on this line triggers the beginning of aSTART bit. The validity of this START bit is checked by again strobing this bit at itsnominal center (16X or 64X mode only). If a low is detected again, it is a valid STARTbit, and the bit counter will start counting. The bit counter thus locates the center ofthe data bits, the parity bit (if it exists) and the stop bits. If parity error occurs, theparity error flag is set. Data and parity bits are sampled on the RxD pin with the risingedge of the RxC. If a low level is detected as the STOP bit the Framing Error flag willbe set. The STOP bit signals the end of a character. Note that the receiver requiresonly one stop bit, regardless of the number of stop bits programmed. This characteris then loaded into the parallel I/O buffer of the 8251 A. The RxRDY pin is raised tosignal the CPU that a character is ready to be fetched. If a previous character has notbeen fetched by the CPU, the present character replaces it in the I/O buffer, and theOVERRUN Error flag is raised (thus the previous character is lost). All of the errorflags can be reset by an Error Reset Instruction. The occurrence of any of theseerrors will not affect the operation of the 8251 A.MICROPROCESSORS LAB 221
    • ELECTRONICS & COMMUNICATION ENGINEERING Figure 8: Mode Instruction Format, Asynchronous ModeSynchronous Mode (Transmission)The TxD output is continuously high until the CPU sends its first character to the8251A which usually is a SYNC character. When the CTS line goes low, the firstcharacter is serially transmitted out. All characters are shifted out on the falling edgeof TxC. Data is shifted out at the same rate as the TxC.Once transmission has started, the data stream at the TxD output must continue at theTxC rate. If the CPU does not provide the 8251A with a data character before the8251A Transmitter Buffers become empty, the SYNC characters (or character if insingle SYNC character mode) will be automatically inserted in the TxD data stream. Inthis case, the TxEMPTY pin is raised high to signal that the 8251A is empty and SYNCcharacters are being sent out. TxEMPTY does not go low when the SYNC is beingshifted out (see figure below). The TxEMPTY pin is internally reset by a data characterbeing written into the 8251 A.MICROPROCESSORS LAB 222
    • ELECTRONICS & COMMUNICATION ENGINEERING Figure 9: Asynchronous Mode8251ASynchronous Mode (Receive)In this mode, character synchronization can be internally or externally achieved. If theSYNC mode has been programmed, ENTER HUNT command should be included inthe first command instruction word written. Data on the RxD pin is then sampled onthe rising edge of RxC. The content of the Rx buffer is compared at every bitboundary with the first SYNC character until a match occurs. If the 8251A has beenprogrammed for two SYNC characters, the subsequent received character is alsocompared; when both SYNC characters have been detected, the USART ends theHUNT mode and is in character synchronization. The SYNDET pin is then set high,and is reset automatically by a STATUS READ. If parity is programmed, SYNDETwill not be set until the middle of the parity bit instead of the middle of the last databit.In the external SYNC mode, synchronization is achieved by applying a high levelMICROPROCESSORS LAB 223
    • ELECTRONICS & COMMUNICATION ENGINEERINGon the SYNDET pin, thus forcing the 8251A out of the HUNT mode. The high levelcan be removed after one RxC cycle. An ENTER HUNT command has no effect inthe asynchronous mode of operation. Figure 10: Mode Instruction Format, Synchronous ModeParity error and overrun error are both checked in the same way as in theAsynchronous Rx mode. Parity is checked when not in Hunt, regardless of whetherthe Receiver is enabled or not.The CPU can command the receiver to enter the HUNT mode if synchronization islost. This will also set all the used character bits in the buffer to a “one,” thuspreventing a possible false SYNDET caused by data that happens to be in the RxBuffer at ENTER HUNT time. Note that the SYNDET F/F is reset at each StatusRead, regardless of whether internal or external SYNC has been programmed. Thisdoes not cause the 8251A to return to the HUNT mode. When in SYNC mode, butnot in HUNT, Sync Detection is still functional, but only occurs at the “known” wordboundaries. Thus, if one Status Read indicates SYNDET and a second Status Readalso indicates SYNDET, then the programmed SYNDET characters have beenreceived since the previous Status Read. (If double character sync has beenprogrammed, then both sync characters have been contiguously received to gate aSYNDET indication). When external SYNDET mode is selected, internal Sync Detectis disabled, and the SYNDET F/F may be set at any bit boundary.MICROPROCESSORS LAB 224
    • ELECTRONICS & COMMUNICATION ENGINEERINGCOMMAND INSTRUCTION DEFINITIONOnce the functional definition of the 8251A has been programmed by the ModeInstruction and the Sync characters are loaded (if in Sync Mode) then the device isready to be used for data communication. The Command Instruction controls theactual operation of the selected format. Functions such as: Enable Transmit/Receive,Error Reset and Modem Controls are provided by the Command instruction.Once the Mode Instruction has been written into the 8251A and Sync charactersinserted, of necessary, then all further “control writes” (C/D = 1) will load a CommandInstruction. A Reset Operation (internal or external) will return the 8251A to the ModeInstruction format.NOTE:Internal Reset on Power-up:When power is first applied, the 8251A may come up in the Mode, Sync character orCommand format. To guarantee that the device is in the Command Instruction formatbefore the Reset command is issued, it is safest to execute the worst-caseinitialization sequence (sync mode with two sync characters). Loading three 00Hsconsecutively into the device with C/D = 1 configures sync operation and writes twodummy OOH sync characters. An Internal Reset command (40H) may then beissued to return the device to the “idle” state. Figure 11: Data Format, Synchronous ModeMICROPROCESSORS LAB 225
    • ELECTRONICS & COMMUNICATION ENGINEERING Figure 12: Command Instruction FormatSTATUS READ DEFINITIONIn data communication systems it is often necessary to examine the “status” of theactive device to ascertain if errors have occurred or other conditions that require theprocessors attention. The 8251A has facilities that allow the programmer to “read”the status of the device at any time during the functional operation. (Status update isinhibited during status read.)A normal “read” command is issued by the CPU with C/D = 1 to accomplish thisfunction.Some of the bits in the Status Read Format have identical meanings to externaloutput pins so that the 8251A can be used in a completely polled or interrupt-drivenenvironment. TxRDY is an exception.Note that status update can have a maximum delay of 28 clock periods from theactual event affecting the status.MICROPROCESSORS LAB 226
    • ELECTRONICS & COMMUNICATION ENGINEERING Figure 13: Status Read FormatAPPLICATIONS OF THE 8251A Figure 14: Asynchronous Serial Interface to CRT Terminal, DC – 9600 BaudMICROPROCESSORS LAB 227
    • ELECTRONICS & COMMUNICATION ENGINEERING Figure 15: Synchronous Interface to Terminal or Peripheral Device8251AAPPLICATIONS OF THE 8251A (Continued) Figure 16: Asynchronous Interface to Telephone Lines Figure 17: Synchronous Interface to Telephone LinesMICROPROCESSORS LAB 228
    • ELECTRONICS & COMMUNICATION ENGINEERING NOTES: 1. AC timings measured VQH - 2.0 VOL = 0-8. and with load circuit of Figure 18. 2. Chip Select (CS) and Command/Data (C/D) are considered as Addresses. 3. Assumes that Address is valid before RD 4- • 4. This recovery time is for Mode Initialization onty. Write Data is allowed only when TxRDY = 1, Recovery Time between Writes for Asynchronous Mode is 8 tcv and for Synchronous Mode is 16 ICY- 5. The TxC and RxC frequencies have the following limitations with respect to CLK: For 1x Baud Rate, fr* or fpx <. 1 /(30 ICY): For 16x and 64x Baud Rate, frx or fRX <• 1 /(4.5 tcy)- This applies to Baud Rates less than or equal to 64K Baud. 6. Reset Pulse Width = 6 ICY minimum; System clock must be running during Reset. 7. Status update can have a maximum delay of 28 clock periods from the event affecting the status. 8. In external sync mode the tes spec, requires the ratio of the system clock (clock) to receive or transmit bit ratios to be greater than 34. 9. A float is defined as the point where the data bus falls below a logic 1 (2.0V @ 1OH limit) or rises above a Logic 0 (0.8V @ IOL limit). ABSOLUTE MAXIMUM RATINGS* Ambient Temperature Under Bias...... 0”C to 70°C Storage Temperature.......... – 65”C to + 150°C Voltage on Any Pin with Respect to Ground.......... – 0.5V to + 7V Power Dissipation........................... 1WNOTICE: This is a production data sheet. The specifications are subject to change withoutnotice. * WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. D.C. CHARACTERISTICS TA = o° to 70° vcc = sov ±.10%, GND = OV* c C,Symbol Parameter Min Max Unit Test ConditionsVIL Input Low Voltage -0.5 0.8 VVIH Input High Voltage 2.0 Vcc VVOL Output Low Voltage 0.45 V IQL * 2.2 mAVOH Output High Voltage 2.4 V IOH = -400 JJ.AOFL Output Float Leakage ±10 HA V0UT = VCC to 0.45VIIL Input Leakage ±10 ^A VIN = Vcc to 0.45Vice Power Supply Current 100 ma All Outputs = High MICROPROCESSORS LAB 229
    • ELECTRONICS & COMMUNICATION ENGINEERING CAPACITANCE TA = 25° vcc = GND = ov c, Symbol Parameter Min Max Unit Test ConditionsGIN Input Capacitance 10 PF fc = 1 MHzGI/O I/O Capacitance 20 PF Unmeasured pins returned to GND A.C. CHARACTERISTICS TA = o° to 70° vcc = 5.0V ±10%, GND = ov C c, Bus Parameters (Note 1) READ CYCLESymbol Parameter Min Max Unit Test Conditions tAR Address Stable Before READ (CS, C/D) 0 ns (Note 2) tRA Address Hold Time for READ (CS, C/D) 0 ns (Note 2) tRR REAl) Pulse Width 250 ns tRD Data Delay from READ 200 ns 3,CL= 150 pF tDF READ to Data Floating 10 100 ns (Note 1,9) WRITE CYCLE Symbol Parameter Min Max Unit Test ConditionsUw Address Stable Before WRITE 0 nstwA Address Hold Time for WRITE 0 nstww WRITE Pulse Width 250 nstow Data Set-Up Time for WRITE 150 nstwo Data Hold Time for WRITE 20 nstRV Recovery Time Between WRITES 6 ICY (Note 4) A.C. CHARACTERISTICS (Continued) OTHER TIMINGS Symbol Parameter Mln Max Unit Test ConditionstcY Clock Period 320 1350 ns (Note 5, 6)t* Clock High Pulse Width 120 tCY-90 ns«4 Clock Low Pulse Width 90 nstR.tp Clock Rise and Fall Time 20 ns*DTx TxO Delay from Falling Edge of 1 /IS TxC~*TX Transmitter Input Clock Frequency kHz 1x Baud Rate 16x Baud Rate 64x DC DC 64 kHz Baud Rate DC 310 615 kHz MICROPROCESSORS LAB 230
    • ELECTRONICS & COMMUNICATION ENGINEERING Symbol Parameter Mln Max Unit Test ConditionstTPW Transmitter Input Clock Pulse Width 12 1 *CY ix Baud Rate 16x and 64x Baud <CY RatetTPD Transmitter Input Clock Pulse Delay 15 3 ICY 1x Baud Rate 16x and 64x Baud tCY Rate*Rx Receiver I nput Clock Frequency 1x kHz Baud Rate 16x Baud Rate 64x Baud DC DC 64 310 kHz Rate DC 615 kHz*RPW Receiver Input Clock Pulse Width 1x 12 1 tCY Baud Rate 1 6x and 64x Baud Rate ICYIRPD Receiver Input Clock Pulse Delay 1x 15 3 *CY Baud Rate 16x and 64x Baud Rate tCYtTxRDY TxRDY Pin Delay from Center of 14 ICY (Note 7) Last BittTxRDY TxRDY I from Leading Edge of WR 400 ns (Note 7)CLEARtRxRDY RxRDY Pin Delay from Center of 26 ICY (Note 7) Last BittRxRDY RxRDY 4, from Leading Edge of RD 400 ns (Note 7)CLEAR Internal SYNDET Delay from Risingtis Edge of RxC 26 tCY (Note 7) External SYNDET Set-Up Time AftertES 16 ICY tRPD-tCY ns (Note 7) Rising Edge of RxCtTxEMPTY TxEMPTY Delay from Center of Last 20 tCY (Note 7) Bit Control Delay from Rising Edge oftwc 8 ICY (Note 7) WRITE (TxEn, DTR, RT3)tCR Control to READ Set-Up Time (D§R, 20 tCY (Note 7) CTS) •NOTE: For Extended Temperature EXPRESS, use MIL 8251A electrical parameters. MICROPROCESSORS LAB 231
    • ELECTRONICS & COMMUNICATION ENGINEERINGA.C. CHARACTERISTICS (Continued)TYPICAL OUTPUT DELAY VS. CAPACITANCE (pF)A.C. TESTING INPUT, OUTPUT WAVEFORM Figure 18WAVEFORMSSYSTEM CLOCK INPUTMICROPROCESSORS LAB 232
    • ELECTRONICS & COMMUNICATION ENGINEERINGWAVEFORMS (Continued)MICROPROCESSORS LAB 233
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 234
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 235
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 236
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 237
    • ELECTRONICS & COMMUNICATION ENGINEERING 2 Intel 8051 microcontroller ArchitectureMICROPROCESSORS LAB 238
    • ELECTRONICS & COMMUNICATION ENGINEERING8.8051 Microcontroller Architecture8051 Microcontroller is 8 bit microcontroller,it has on chip RAM -128bytes,on chipROM-4kb,four – parallel ports(each 8 i/o lines),one -serial port, two -16 bit timers,ALU size is 8 bit,RAM/ROM can be expanadable up to 64kb,Memory to Memorytransfer is possible,bitmanipulation can be done on the memory locations.8051 Microcontroller Signals & Pins: P1.0 1 40 Vcc P1.1 2 39 P0.0(AD0 P1.2 3 38 P0.1(AD1) ) P1.3 4 37 P0.2(AD2 P1.4 5 8051 36 P0.3(AD3) ) P1.5 6 35 P0.4(AD4) P1.6 7 (8031) 34 P0.5(AD5) P1.7 8 33 P0.6(AD6) RST 9 32 P0.7(AD7) (RXD)P3.0 10 31 EA/VPP (TXD)P3.1 11 30 ALE/PROG (INT0)P3.2 12 29 PSEN (INT1)P3.3 13 28 P2.7(A15) (T0)P3.4 14 27 P2.6(A14 (T1)P3.5 15 26 P2.5(A13 ) (WR)P3.6 16 25 P2.4(A12 ) (RD)P3.7 17 24 P2.3(A11 ) XTAL2 18 23 P2.2(A10) ) XTAL1 19 22 P2.1(A9) GND 20 21 P2.0(A8) Fig: 8051 Microcontroller pin diagramMICROPROCESSORS LAB 239
    • ELECTRONICS & COMMUNICATION ENGINEERING Fig : 8051 Microcontroller ArchitectureMICROPROCESSORS LAB 240
    • ELECTRONICS & COMMUNICATION ENGINEERING8051 Types of MemoryThe 8051 has three very general types of memory. They are: On-Chip Memory,External Code Memory, and External RAM.On-Chip Memory refers to any memory (Code, RAM, or other) that physicallyexists on the microcontroller itself.External Code Memory is code (or program) memory that resides off-chip.This is often in the form of an external EPROM.External RAM is RAM memory that resides off-chip. This is often in the form ofstandard static RAM or flash RAM.Code MemoryCode memory is the memory that holds the actual 8051 program that is to be run.This memory is limited to 64K and comes in many shapes and sizes: Code memorymay be found on-chip, either burned into the microcontroller as ROM or EPROM.Code may also be stored completely off-chip in an external ROM or, more commonly,an external EPROM. Flash RAM is also another popular method of storing aprogram. Various combinations of these memory types may also be used--that is tosay, it is possible to have 4K of code memory on-chip and 64k of code memoryoff-chip in an EPROM.External RAM External RAM is any random access memory which is found off-chip. Since thememory is off-chip it is not as flexible in terms of accessing, and is also slower. Forexample, to increment an Internal RAM location by 1 requires only 1 instruction and 1instruction cycle. To increment a 1-byte value stored in External RAM requires 4instructions and 7 instruction cycles. In this case, external memory is 7 times slower!What External RAM loses in speed and flexibility it gains in quantity. While InternalRAM is limited to 128 bytes (256 bytes with an 8052), the 8051 supports ExternalRAM up to 64K.MICROPROCESSORS LAB 241
    • ELECTRONICS & COMMUNICATION ENGINEERINGOn-Chip Memory8051 includes a certain amount of on-chip memory. On-chip memory is really one oftwo types: Internal RAM and Special Function Register (SFR) memory. The layout ofthe 8051s internal memory is presented in the following memory map:As is illustrated in this map, the 8051 has a bank of 128 bytes of Internal RAM. ThisInternal RAM is found on-chip on the 8051 so it is the fastest RAM available, and it isalso the most flexible in terms of reading, writing, and modifying its contents. InternalRAM is volatile, so when the 8051 is reset this memory is cleared.The 128 bytes of internal ram is subdivided as shown on the memory map. The first 8bytes (00h - 07h) are "register bank 0". By manipulating certain SFRs, a programmay choose to use register banks 1, 2, or 3. These alternative register banks arelocated in internal RAM in addresses 08h through 1Fh. Well discuss "register banks"more in a later chapter. For now it is sufficient to know that they "live" and are part ofinternal RAM.Bit Memory also lives and is part of internal RAM. Well talk more about bit memoryvery shortly, but for now just keep in mind that bit memory actually resides in internalRAM, from addresses 20h through 2Fh.The 80 bytes remaining of Internal RAM, from addresses 30h through 7Fh, may beused by user variables that need to be accessed frequently or at high-speed. Thisarea is also utilized by the microcontroller as a storage area for the operating stack.This fact severely limits the 8051s stack since, as illustrated in the memory map, thearea reserved for the stack is only 80 bytes--and usually it is less since this 80 byteshas to be shared between the stack and user variables.MICROPROCESSORS LAB 242
    • ELECTRONICS & COMMUNICATION ENGINEERINGRegister BanksThe 8051 uses 8 "R" registers which are used in many of its instructions. These "R"registers are numbered from 0 through 7 (R0, R1, R2, R3, R4, R5, R6, and R7).These registers are generally used to assist in manipulating values and moving datafrom one memory location to another. For example, to add the value of R4 to theAccumulator, we would execute the following instruction: ADD A,R4Thus if the Accumulator (A) contained the value 6 and R4 contained the value 3, theAccumulator would contain the value 9 after this instruction was executed.However, as the memory map shows, the "R" Register R4 is really part of InternalRAM. Specifically, R4 is address 04h. This can be see in the bright green section ofthe memory map. Thus the above instruction accomplishes the same thing as thefollowing operation: ADD A,04hThis instruction adds the value found in Internal RAM address 04h to the value of theAccumulator, leaving the result in the Accumulator. Since R4 is really Internal RAM04h, the above instruction effectively accomplished the same thing.Bit MemoryThe 8051, being a communications-oriented microcontroller, gives the user the abilityto access a number of bit variables. These variables may be either 1 or 0.There are 128 bit variables available to the user, numberd 00h through 7Fh. The usermay make use of these variables with commands such as SETB and CLR. Forexample, to set bit number 24 (hex) to 1 you would execute the instruction: SETB 24hIt is important to note that Bit Memory is really a part of Internal RAM. In fact, the 128bit variables occupy the 16 bytes of Internal RAM from 20h through 2Fh. Thus, if youwrite the value FFh to Internal RAM address 20h youve effectively set bits 00hthrough 07h. That is to say that: MOV 20h,#0FFh is equivalent to: SETB 00h SETB 01h SETB 02h SETB 03h SETB 04h SETB 05h SETB 06h SETB 07hMICROPROCESSORS LAB 243
    • ELECTRONICS & COMMUNICATION ENGINEERINGAs illustrated above, bit memory isnt really a new type of memory. Its really just asubset of Internal RAM. But since the 8051 provides special instructions to accessthese 16 bytes of memory on a bit by bit basis it is useful to think of it as a separatetype of memory. However, always keep in mind that it is just a subset of InternalRAM--and that operations performed on Internal RAM can change the values of thebit variables.Bit variables 00h through 7Fh are for user-defined functions in their programs.However, bit variables 80h and above are actually used to access certain SFRs on abit-by-bit basis. For example, if output lines P0.0 through P0.7 are all clear (0) andyou want to turn on the P0.0 output line you may either execute: MOV P0,#01h or you may execute: SETB 80hBoth these instructions accomplish the same thing. However, using the SETBcommand will turn on the P0.0 line without effecting the status of any of the other P0output lines. The MOV command effectively turns off all the other output lines which,in some cases, may not be acceptable.Special Function Register (SFR) MemorySpecial Function Registers (SFRs) are areas of memory that control specificfunctionality of the 8051 processor. For example, four SFRs permit access to the8051s 32 input/output lines. Another SFR allows a program to read or write to the8051s serial port. Other SFRs allow the user to set the serial baud rate, control andaccess timers, and configure the 8051s interrupt system.When programming, SFRs have the illusion of being Internal Memory. For example,if you want to write the value "1" to Internal RAM location 50 hex you would executethe instruction: MOV 50h,#01hSimilarly, if you want to write the value "1" to the 8051s serial port you would writethis value to the SBUF SFR, which has an SFR address of 99 Hex. Thus, to write thevalue "1" to the serial port you would execute the instruction: MOV 99h,#01hAs you can see, it appears that the SFR is part of Internal Memory. This is not thecase. When using this method of memory access (its called direct address), anyinstruction that has an address of 00h through 7Fh refers to an Internal RAM memoryaddress; any instruction with an address of 80h through FFh refers to an SFR controlregister.MICROPROCESSORS LAB 244
    • ELECTRONICS & COMMUNICATION ENGINEERINGWhat Are SFRs?The 8051 is a flexible microcontroller with a relatively large number of modesof operations. Your program may inspect and/or change the operating modeof the 8051 by manipulating the values of the 8051s Special Function Registers(SFRs).SFRs are accessed as if they were normal Internal RAM. The only difference is thatInternal RAM is from address 00h through 7Fh whereas SFR registers exist in theaddress range of 80h through FFh.Each SFR has an address (80h through FFh) and a name. The following chartprovides a graphical presentation of the 8051s SFRs, their names, and theiraddress.The address range of 80h through FFh offer 128 possible addresses, there are only21 SFRs in a standard 8051. All other addresses in the SFR range (80h through FFh)are considered invalid. Writing to or reading from these registers may produceundefined values or behavior.SFR Types SFRs related to the I/O ports: The 8051 has four I/O ports of 8 bits, for a total of 32I/O lines. Whether a given I/O line is high or low and the value read from the line arecontrolled by the SFRs in green.MICROPROCESSORS LAB 245
    • ELECTRONICS & COMMUNICATION ENGINEERINGSFRs which in some way control the operation or the configuration of some aspect ofthe 8051. For example, TCON controls the timers, SCON controls the serial port.The remaining SFRs, "other SFRs." These SFRs can be thought of as auxillarySFRs in the sense that they dont directly configure the 8051 but obviously the 8051cannot operate without them. For example, once the serial port has been configuredusing SCON, the program may read or write to the serial port using the SBUFregister.SFR DescriptionsP0 (Port 0, Address 80h, Bit-Addressable): This is input/output port 0. Each bit ofthis SFR corresponds to one of the pins on the microcontroller. For example, bit 0 ofport 0 is pin P0.0, bit 7 is pin P0.7. Writing a value of 1 to a bit of this SFR will send ahigh level on the corresponding I/O pin whereas a value of 0 will bring it to a lowlevel.SP (Stack Pointer, Address 81h): This is the stack pointer of the microcontroller.This SFR indicates where the next value to be taken from the stack will be read fromin Internal RAM. If you push a value onto the stack, the value will be written to theaddress of SP + 1. That is to say, if SP holds the value 07h, a PUSH instruction willpush the value onto the stack at address 08h. This SFR is modified by all instructionswhich modify the stack, such as PUSH, POP, LCALL, RET, RETI, and wheneverinterrupts are provoked by the microcontroller.DPL/DPH (Data Pointer Low/High, Addresses 82h/83h): The SFRs DPL and DPHwork together to represent a 16-bit value called the Data Pointer. The data pointer isused in operations regarding external RAM and some instructions involving codememory. Since it is an unsigned two-byte integer value, it can represent values from0000h to FFFFh (0 through 65,535 decimal).PCON (Power Control, Addresses 87h): The Power Control SFR is used to controlthe 8051s power control modes. Certain operation modes of the 8051 allow the 8051to go into a type of "sleep" mode which requires much less power. These modes ofoperation are controlled through PCON. Additionally, one of the bits in PCON is usedto double the effective baud rate of the 8051s serial port.TCON (Timer Control, Addresses 88h, Bit-Addressable): The Timer Control SFRis used to configure and modify the way in which the 8051s two timers operate. ThisSFR controls whether each of the two timers is running or stopped and contains aflag to indicate that each timer has overflowed. Additionally, some non-timer relatedbits are located in the TCON SFR. These bits are used to configure the way in whichthe external interrupts are activated and also contain the external interrupt flagswhich are set when an external interrupt has occured.TMOD (Timer Mode, Addresses 89h): The Timer Mode SFR is used to configurethe mode of operation of each of the two timers. Using this SFR your program mayconfigure each timer to be a 16-bit timer, an 8-bit autoreload timer, a 13-bit timer, ortwo separate timers. Additionally, you may configure the timers to only count whenan external pin is activated or to count "events" that are indicated on an external pin.MICROPROCESSORS LAB 246
    • ELECTRONICS & COMMUNICATION ENGINEERINGTL0/TH0 (Timer 0 Low/High, Addresses 8Ah/8Ch): These two SFRs, takentogether, represent timer 0. Their exact behavior depends on how the timer isconfigured in the TMOD SFR; however, these timers always count up. What isconfigurable is how and when they increment in value.TL1/TH1 (Timer 1 Low/High, Addresses 8Bh/8Dh): These twoSFRs, taken together, represent timer 1. Their exact behavior depends on how thetimer is configured in the TMOD SFR; however, these timers always count up. Whatis configurable is how and when they increment in value.P1 (Port 1, Address 90h, Bit-Addressable): This is input/output port 1.Each bit of this SFR corresponds to one of the pins on the microcontroller. Forexample, bit 0 of port 1 is pin P1.0, bit 7 is pin P1.7. Writing a value of 1 to a bit ofthis SFR will send a high level on the corresponding I/O pin whereas a value of 0 willbring it to a low level.SCON (Serial Control, Addresses 98h, Bit-Addressable): TheSerial Control SFR is used to configure the behavior of the 8051s on-board serialport. This SFR controls the baud rate of the serial port, whether the serial port isactivated to receive data, and also contains flags that are set when a byte issuccessfully sent or received.SBUF (Serial Control, Addresses 99h): The Serial Buffer SFR is usedto send and receive data via the on-board serial port. Any value written to SBUF willbe sent out the serial ports TXD pin. Likewise, any value which the 8051 receives viathe serial ports RXD pin will be delivered to the user program via SBUF. In otherwords, SBUF serves as the output port when written to and as an input port whenread from.P2 (Port 2, Address A0h, Bit-Addressable): This is input/output port 2.Each bit of this SFR corresponds to one of the pins on the microcontroller. Forexample, bit 0 of port 2 is pin P2.0, bit 7 is pin P2.7. Writing a value of 1 to a bit ofthis SFR will send a high level on the corresponding I/O pin whereas a value of 0 willbring it to a low level.IE (Interrupt Enable, Addresses A8h): The Interrupt Enable SFR is usedto enable and disable specific interrupts. The low 7 bits of the SFR are used toenable/disable the specific interrupts, where as the highest bit is used to enable ordisable ALL interrupts. Thus, if the high bit of IE is 0 all interrupts are disabledregardless of whether an individual interrupt is enabled by setting a lower bit.P3 (Port 3, Address B0h, Bit-Addressable): This is input/output port 3.Each bit of this SFR corresponds to one of the pins on the microcontroller. Forexample, bit 0 of port 3 is pin P3.0, bit 7 is pin P3.7. Writing a value of 1 to a bit ofthis SFR will send a high level on the corresponding I/O pin whereas a value of 0 willbring it to a low level.MICROPROCESSORS LAB 247
    • ELECTRONICS & COMMUNICATION ENGINEERINGIP (Interrupt Priority, Addresses B8h, Bit-Addressable): TheInterrupt Priority SFR is used to specify the relative priority of each interrupt. On the8051, an interrupt may either be of low (0) priority or high (1) priority. An interruptmay only interrupt interrupts of lower priority. For example, if we configure the 8051so that all interrupts are of low priority except the serial interrupt, the serial interruptwill always be able to interrupt the system, even if another interrupt is currentlyexecuting. However, if a serial interrupt is executing no other interrupt will be able tointerrupt the serial interrupt routine since the serial interrupt routine has the highestpriority.PSW (Program Status Word, Addresses D0h, Bit-Addressable): TheProgram Status Word is used to store a number of important bits that are set andcleared by 8051 instructions. The PSW SFR contains the carry flag, the auxiliarycarry flag, the overflow flag, and the parity flag. Additionally, the PSW registercontains the register bank select flags which are used to select which of the "R"register banks are currently selected.ACC (Accumulator, Addresses E0h, Bit-Addressable): The Accumulator isone of the most-used SFRs on the 8051 since it is involved in so many instructions.The Accumulator resides as an SFR at E0h, which means the instruction MOVA,#20h is really the same as MOV E0h,#20h. However, it is a good idea to use thefirst method since it only requires two bytes whereas the second option requiresthree bytes.B (B Register, Addresses F0h, Bit-Addressable): The "B" register is used intwo instructions: the multiply and divide operations. The B register is also commonlyused by programmers as an auxiliary register to temporarily store values.Other SFRsA common practice when semiconductor firms wish to develop a new 8051 derivativeis to add additional SFRs to support new functions that exist in the new chip.For example, the Dallas Semiconductor DS80C320 is upwards compatible with the8051. This means that any program that runs on a standard 8051 should run withoutmodification on the DS80C320. This means that all the SFRs defined above alsoapply to the Dallas component.8051 Basic RegistersThe AccumulatorThe Accumulator, as its name suggests, is used as a general register toaccumulate the results of a large number of instructions. It can hold an 8-bit(1-byte) value and is the most versatile register the 8051 has due to the shearnumber of instructions that make use of the accumulator. More than half of the 8051s255 instructions manipulate or use the accumulator in some way.For example, if you want to add the number 10 and 20, the resulting 30 will be storedin the Accumulator. Once you have a value in the Accumulator you may continueprocessing the value or you may store it in another register or in memory.MICROPROCESSORS LAB 248
    • ELECTRONICS & COMMUNICATION ENGINEERINGThe "R" registersThe "R" registers are a set of eight registers that are named R0, R1, etc. up to andincluding R7.These registers are used as auxillary registers in many operations. To continue withthe above example, perhaps you are adding 10 and 20. The original number 10 maybe stored in the Accumulator whereas the value 20 may be stored in, say, registerR4. To process the addition you would execute the command: ADD A,R4After executing this instruction the Accumulator will contain the value 30.You may think of the "R" registers as very important auxillary, or "helper", registers.The Accumulator alone would not be very useful if it were not for these "R" registers.The "R" registers are also used to temporarily store values. For example, lets sayyou want to add the values in R1 and R2 together and then subtract the values of R3and R4. One way to do this would be: MOV A,R3 ;Move the value of R3 into the accumulator ADD A,R4 ;Add the value of R4 MOV R5,A ;Store the resulting value temporarily in R5 MOV A,R1 ;Move the value of R1 into the accumulator ADD A,R2 ;Add the value of R2 SUBB A,R5 ;Subtract the value of R5 (which now contains R3 + R4)The "B" RegisterThe "B" register is very similar to the Accumulator in the sense that it may hold an 8-bit (1-byte) value. The "B" register is only used by two 8051 instructions: MUL ABand DIV AB. Thus, if you want to quickly and easily multiply or divide A by anothernumber, you may store the other number in "B" and make use of these twoinstructions. Aside from the MUL and DIV instructions, the "B" register is often usedas yet another temporary storage register much like a ninth "R" register.The Data Pointer (DPTR)The Data Pointer (DPTR) is the 8051s only user-accessable 16-bit (2-byte) register.The Accumulator, "R" registers, and "B" register are all 1-byte values. DPTR, as thename suggests, is used to point to data. It is used by a number of commands whichallow the 8051 to access external memory. When the 8051 accesses externalmemory it will access external memory at the address indicated by DPTR. WhileMICROPROCESSORS LAB 249
    • ELECTRONICS & COMMUNICATION ENGINEERINGDPTR is most often used to point to data in external memory, many programmersoften take advantge of the fact that its the only true 16-bit register available. It is oftenused to store 2-byte values which have nothing to do with memory locations.The Program Counter (PC)The Program Counter (PC) is a 2-byte address which tells the 8051 where the nextinstruction to execute is found in memory. When the 8051 is initialized PC alwaysstarts at 0000h and is incremented each time an instruction is executed. It isimportant to note that PC isnt always incremented by one. Since some instructionsrequire 2 or 3 bytes the PC will be incremented by 2 or 3 in these cases.The Stack Pointer (SP)The Stack Pointer, like all registers except DPTR and PC, may hold an 8-bit (1-byte)value. The Stack Pointer is used to indicate where the next value to be removed fromthe stack should be taken from. When you push a value onto the stack, the 8051 firstincrements the value of SP and then stores the value at the resulting memorylocation. When you pop a value off the stack, the 8051 returns the value from thememory location indicated by SP, and then decrements the value of SP.This order of operation is important. When the 8051 is initialized SP will be initializedto 07h. If you immediately push a value onto the stack, the value will be stored inInternal RAM address 08h. This makes sense taking into account what wasmentioned two paragraphs above: First the 8051 will increment the value of SP (from07h to 08h) and then will store the pushed value at that memory address (08h).SP is modified directly by the 8051 by six instructions: PUSH, POP, ACALL,LCALL, RET, and RETI. It is also used intrinsically whenever an interrupt istriggered (more on interrupts later. Dont worry about them for now!).InterruptsAn interrupt is a special feature which allows the 8051 to provide the illusion of "multi-tasking," although in reality the 8051 is only doing one thing at a time. The word"interrupt" can often be subsituted with the word "event."An interrupt is triggered whenever a corresponding event occurs. When the eventoccurs, the 8051 temporarily puts "on hold" the normal execution of the program andexecutes a special section of code referred to as an interrupt handler. The interrupthandler performs whatever special functions are required to handle the event and thenreturns control to the 8051 at which point program execution continues as if it hadnever been interrupted.TimersMICROPROCESSORS LAB 250
    • ELECTRONICS & COMMUNICATION ENGINEERING 8051 has two timers which each function essentially the same way. One timer isTIMER0 and the other is TIMER1. The two timers share two SFRs (TMOD andTCON) which control the timers, and each timer also has two SFRs dedicated solelyto itself (TH0/TL0 and TH1/TL1).SFR Name Description SFR AddressTH0 Timer 0 High Byte 8ChTL0 Timer 0 Low Byte 8AhTH1 Timer 1 High Byte 8DhTL1 Timer 1 Low Byte 8BhTCON Timer Control 88hTMOD Timer Mode 89hThe TMOD SFRThe individual bits of TMOD have the following functions:Four bits (two for each timer) are used to specify a mode of operation. The modes ofoperation are:MICROPROCESSORS LAB 251
    • ELECTRONICS & COMMUNICATION ENGINEERING13-bit Time Mode (mode 0):Timer mode "0" is a 13-bit timer. This is a relic that waskept around in the 8051 to maintain compatability with its predecesor, the 8048.Generally the 13-bit timer mode is not used in new development.When the timer is in 13-bit mode, TLx will count from 0 to 31. When TLx isincremented from 31, it will "reset" to 0 and increment THx. Thus, effectively, only 13bits of the two timer bytes are being used: bits 0-4 of TLx and bits 0-7 of THx. Thisalso means, in essence, the timer can only contain 8192 values. If you set a 13-bittimer to 0, it will overflow back to zero 8192 machine cycles later.16-bit Time Mode (mode 1):Timer mode "1" is a 16-bit timer. This is a very commonlyused mode. It functions just like 13-bit mode except that all 16 bits are used.TLx is incremented from 0 to 255. When TLx is incremented from 255, it resets to 0and causes THx to be incremented by 1. Since this is a full 16-bit timer, the timermay contain up to 65536 distinct values. If you set a 16-bit timer to 0, it will overflowback to 0 after 65,536 machine cycles.8-bit Time Mode (mode 2)Timer mode "2" is an 8-bit auto-reload mode. When a timer is in mode 2, THx holdsthe "reload value" and TLx is the timer itself. Thus, TLx starts counting up. When TLxreaches 255 and is subsequently incremented, instead of resetting to 0 (as in thecase of modes 0 and 1), it will be reset to the value stored in THx.For example, letssay TH0 holds the value FDh and TL0 holds the value FEh. If we were to watch thevalues of TH0 and TL0 for a few machine cycles this is what wed see:The auto-reload mode is very commonly used for establishing a baud rate which wewill talk more about in the Serial Communications chapter.MICROPROCESSORS LAB 252
    • ELECTRONICS & COMMUNICATION ENGINEERINGSplit Timer Mode (mode 3):Timer mode "3" is a split-timer mode. When Timer 0 isplaced in mode 3, it essentially becomes two separate 8-bit timers. That is to say,Timer 0 is TL0 and Timer 1 is TH0. Both timers count from 0 to 255 and overflowback to 0. All the bits that are related to Timer 1 will now be tied to TH0.While Timer 0 is in split mode, the real Timer 1 (i.e. TH1 and TL1) can be put intomodes 0, 1 or 2 normally--however, you may not start or stop the real timer 1 sincethe bits that do that are now linked to TH0. The real timer 1, in this case, will beincremented every machine cycle no matter what.The only real use I can see of using split timer mode is if you need to have twoseparate timers and, additionally, a baud rate generator. In such case you can usethe real Timer 1 as a baud rate generator and use TH0/TL0 as two separate timers.The TCON SFRSFR that controls the two timers and provides valuable information about them. TheTCON SFR has the following structure:SETB TF1 :This has the benefit of setting the high bit of TCON without changing thevalue of any of the other bits of the SFR. Usually when you start or stop a timer youdont want to modify the other values in TCON, so you take advantage of the fact thatthe SFR is bit-addressable.Initializing a Timer:First initialize the TMOD SFR. Working with timer 0 we will be using the lowest 4 bitsof TMOD. The first two bits, GATE0 and C/T0 are both 0 since we want the timer tobe independent of the external pins. 16-bit mode is timer mode 1 so we must clearT0M1 and set T0M0. Effectively, the only bit we want to turn on is bit 0 of TMOD.Thus to initialize the timer we execute the instruction:MOV TMOD,#01hTimer 0 is now in 16-bit timer mode. However, the timer is not running. To start thetimer running we must set the TR0 bit We can do that by executing the instruction:SETB TR0Upon executing these two instructions timer 0 will immediately begin counting, beingincremented once every machine cycle (every 12 crystal pulses).MICROPROCESSORS LAB 253
    • ELECTRONICS & COMMUNICATION ENGINEERINGReading the Timer: There are two common ways of reading the value of a 16-bittimer; which you use depends on your specific application. You may either read theactual value of the timer as a 16-bit number, or you may simply detect when the timerhas overflowed.Reading the value of a Timer: If Timer is in an 8-bit mode--that is, either 8-bitAutoReload mode or in split timer mode--then reading the value of the timer issimple. You simply read the 1-byte value of the timer and youre done.Serial CommunicationOne of the 8051s many powerful features is its integrated UART, otherwise known asa serial port. The fact that the 8051 has an integrated serial port means that you mayvery easily read and write values to the serial port. If it were not for the integratedserial port, writing a byte to a serial line would be a rather tedious process requringturning on and off one of the I/O lines in rapid succession to properly "clock out" eachindividual bit, including start bits, stop bits, and parity bits.Setting the Serial Port Mode:First, lets present the "Serial Control" (SCON) SFRand define what each bit of the SFR represents:Additionally, it is necessary to define the function of SM0 and SM1 by an additionaltable:(*) Note: The baud rate indicated in this table is doubled if PCON.7 (SMOD) is set.MICROPROCESSORS LAB 254
    • ELECTRONICS & COMMUNICATION ENGINEERINGThe SCON SFR allows us to configure the Serial Port. Thus, well go through each bitand review its function.The first four bits (bits 4 through 7) are configuration bits.Bits SM0 and SM1 let us set the serial mode to a value between 0 and 3, inclusive.The four modes are defined in the chart immediately above. As you can see,selecting the Serial Mode selects the mode of operation (8-bit/9-bit, UART or ShiftRegister) and also determines how the baud rate will be calculated. In modes 0 and 2the baud rate is fixed based on the oscillators frequency. In modes 1 and 3 the baudrate is variable based on how often Timer 1 overflows.The next bit, SM2, is a flag for "Multiprocessor communication." Generally, whenevera byte has been received the 8051 will set the "RI" (Receive Interrupt) flag. This letsthe program know that a byte has been received and that it needs to be processed.However, when SM2 is set the "RI" flag will only be triggered if the 9th bit receivedwas a "1". That is to say, if SM2 is set and a byte is received whose 9th bit is clear,the RI flag will never be set. This can be useful in certain advanced serialapplications. For now it is safe to say that you will almost always want to clear this bitso that the flag is set upon reception of any character.The next bit, REN, is "Receiver Enable." This bit is very straightforward: If you wantto receive data via the serial port, set this bit. You will almost always want to set thisbit.The last four bits (bits 0 through 3) are operational bits. They are used when actuallysending and receiving data--they are not used to configure the serial port.The TB8 bit is used in modes 2 and 3. In modes 2 and 3, a total of nine data bits aretransmitted. The first 8 data bits are the 8 bits of the main value, and the ninth bit istaken from TB8. If TB8 is set and a value is written to the serial port, the datas bitswill be written to the serial line followed by a "set" ninth bit. If TB8 is clear the ninth bitwill be "clear."The RB8 also operates in modes 2 and 3 and functions essentially the same way asTB8, but on the reception side. When a byte is received in modes 2 or 3, a total ofnine bits are received. In this case, the first eight bits received are the data of theserial byte received and the value of the ninth bit received will be placed in RB8.TI means "Transmit Interrupt." When a program writes a value to the serial port, acertain amount of time will pass before the individual bits of the byte are "clocked out"the serial port. If the program were to write another byte to the serial port before thefirst byte was completely output, the data being sent would be garbled. Thus, the8051 lets the program know that it has "clocked out" the last byte by setting the TI bit.When the TI bit is set, the program may assume that the serial port is "free" andready to send the next byte.Finally, the RI bit means "Receive Interrupt." It funcions similarly to the "TI" bit, but itindicates that a byte has been received. That is to say, whenever the 8051 hasMICROPROCESSORS LAB 255
    • ELECTRONICS & COMMUNICATION ENGINEERINGreceived a complete byte it will trigger the RI bit to let the program know that it needsto read the value quickly, before another byte is read.Reading the Serial Port:Reading data received by the serial port is equally easy. Toread a byte from the serial port one just needs to read the value stored in the SBUF(99h) SFR after the 8051 has automatically set the RI flag in SCON.For example, ifyour program wants to wait for a character to be received and subsequently read itinto the Accumulator, the following code segment may be used:JNB RI,$ ;Wait for the 8051 to set the RI flagMOV A,SBUF ;Read the character from the serial portThe first line of the above code segment waits for the 8051 to set the RI flag; again,the 8051 sets the RI flag automatically when it receives a character via the serialport. So as long as the bit is not set the program repeats the "JNB" instructioncontinuously.Once the RI bit is set upon character reception the above condition automatically failsand program flow falls through to the "MOV" instruction which reads the value.9. 8051 Addressing Modes:An "addressing mode" refers to how you are addressing a given memory location. Insummary, the addressing modes are as follows, with an example of each: Immediate Addressing MOV A,#20h Direct Addressing MOV A,30h Indirect Addressing MOV A,@R0 External Direct MOVX A,@DPTR Code Indirect MOVC A,@A+DPTREach of these addressing modes provides important flexibility.Immediate AddressingImmediate addressing is so-named because the value to be stored in memoryimmediately follows the operation code in memory. That is to say, the instructionitself dictates what value will be stored in memory.For example, the instruction: MOV A,#20hThis instruction uses Immediate Addressing because the Accumulator will be loadedwith the value that immediately follows; in this case 20 (hexidecimal).MICROPROCESSORS LAB 256
    • ELECTRONICS & COMMUNICATION ENGINEERINGImmediate addressing is very fast since the value to be loaded is included in theinstruction. However, since the value to be loaded is fixed at compile-time it is notvery flexible.Direct AddressingDirect addressing is so-named because the value to be stored in memory is obtainedby directly retrieving it from another memory location. For example: MOV A,30hThis instruction will read the data out of Internal RAM address 30 (hexidecimal) andstore it in the Accumulator.Direct addressing is generally fast since, although the value to be loaded isntincluded in the instruction, it is quickly accessable since it is stored in the 8051sInternal RAM. It is also much more flexible than Immediate Addressing since thevalue to be loaded is whatever is found at the given address--which may be variable.Also, it is important to note that when using direct addressing any instruction whichrefers to an address between 00h and 7Fh is referring to Internal Memory. Anyinstruction which refers to an address between 80h and FFh is referring to the SFRcontrol registers that control the 8051 microcontroller itself.Indirect AddressingIndirect addressing is a very powerful addressing mode which in many casesprovides an exceptional level of flexibility. Indirect addressing is also the only way toaccess the extra 128 bytes of Internal RAM found on an 8052.Indirect addressing appears as follows: MOV A,@R0This instruction causes the 8051 to analyze the value of the R0 register. The 8051will then load the accumulator with the value from Internal RAM which is found at theaddress indicated by R0.For example, lets say R0 holds the value 40h and Internal RAM address 40h holdsthe value 67h. When the above instruction is executed the 8051 will check the valueof R0. Since R0 holds 40h the 8051 will get the value out of Internal RAM address40h (which holds 67h) and store it in the Accumulator. Thus, the Accumulator endsup holding 67h.Indirect addressing always refers to Internal RAM; it never refers to an SFR. Thus, ina prior example we mentioned that SFR 99h can be used to write a value to the serialport. Thus one may think that the following would be a valid solution to write thevalue 1 to the serial port: MOV R0,#99h ;Load the address of the serial port MOV @R0,#01h ;Send 01 to the serial port -- WRONG!!This is not valid. Since indirect addressing always refers to Internal RAM these twoinstructions would write the value 01h to Internal RAM address 99h on an 8052. OnMICROPROCESSORS LAB 257
    • ELECTRONICS & COMMUNICATION ENGINEERINGan 8051 these two instructions would produce an undefined result since the 8051only has 128 bytes of Internal RAM.External DirectExternal Memory is accessed using a suite of instructions which use what I call"External Direct" addressing. I call it this because it appears to be direct addressing,but it is used to access external memory rather than internal memory.There are only two commands that use External Direct addressing mode: MOVX A,@DPTR MOVX @DPTR,AAs you can see, both commands utilize DPTR. In these instructions, DPTR must firstbe loaded with the address of external memory that you wish to read or write. OnceDPTR holds the correct external memory address, the first command will move thecontents of that external memory address into the Accumulator. The secondcommand will do the opposite: it will allow you to write the value of the Accumulatorto the external memory address pointed to by DPTR.External IndirectExternal memory can also be accessed using a form of indirect addressing which Icall External Indirect addressing. This form of addressing is usually only used inrelatively small projects that have a very small amount of external RAM. An exampleof this addressing mode is: MOVX @R0,AOnce again, the value of R0 is first read and the value of the Accumulator is writtento that address in External RAM. Since the value of @R0 can only be 00h throughFFh the project would effectively be limited to 256 bytes of External RAM. There arerelatively simple hardware/software tricks that can be implemented to access morethan 256 bytes of memory using External Indirect addressing; however, it is usuallyeasier to use External Direct addressing if your project has more than 256 bytes ofExternal RAM.MICROPROCESSORS LAB 258
    • ELECTRONICS & COMMUNICATION ENGINEERING 10. Intel 8051 microcontroller instruction set 8051 INSTRUCTION SETThe instruction set is divided in to 5 categories. They are as follows: 1. Arithmetic instructions. 2. Logic instructions. 3. Data transfer instructions. 4. Boolean variable manipulation instruction. 5. Program and machine control instruction.MICROPROCESSORS LAB 259
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 260
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 261
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 262
    • ELECTRONICS & COMMUNICATION ENGINEERINGMICROPROCESSORS LAB 263
    • ELECTRONICS & COMMUNICATION ENGINEERING11. DOS functions summary DOS Function CallsMSDOS provided a wealth of function calls by which a programmer could ask the system for helpin dealing with I/O and certain aspects of system resources. These included calls for the keyboard,serial port, screen, printer port, disk drives, and support for generic devices that were yet to bedefined. With the introduction of the IBM PC/AT in 1984, PCDOS 3.1 provided networking and filelocking calls. The IBM PS/2 systems in 1987 standardized a mouse interface and providedextended error diagnostic calls as well.In addition to the DOS calls, which form an Application Program Interface or API that we can usedirectly, the IBM PC-style system also provides a lower-level series of calls to the computersBIOS, or Basic I/O System. These are routines stored in the systems BIOS ROMs and may differfrom the original as various makers create their own BIOS code for their own hardware. See thatpage for more information.To use a DOS call, simply place a function byte into the AH register and setup other registers asrequired. If data is to be fetched or sent to memory, that area must also be setup by the callingprogram. Once ready, the programs executes and INT 21H to the Function Dispatcher which thentakes over and executes the request. If errors are encountered, some calls will return a carry bitset or other indication.As the development of the system progressed, calls were added to accommodate later hardwareand system requirements. Early calls have been abandoned in favor of some of the more efficientlater ones. The list below is strictly a sample - many calls have not been included becausethey are either absolete or outside the need of the Computer Technology 46 requirement.Our objective is to illustrate the methods and procedures of using Assembly Language to controlcomputer hardware. These skills are essential in a wide range of job descriptions and improve atechnicians chances of understanding his technical world more quickly. Other APIs are providedfor writing into GUIs and other systems. 00H - Terminate Program On Entry: AH = 00H On Exit: Back to DOS Notes: Obsolete - use function 4CH 01H - Read Keyboard On Entry: AH = 01H On Exit: AL = ASCII Character from keyboard Notes: If AL = 0, this is a function key and you must call the function a second time.MICROPROCESSORS LAB 264
    • ELECTRONICS & COMMUNICATION ENGINEERING 02H - Write to STDOUT AH = 02H On Entry: AL = ASCII Character to be displayed On Exit: Character appears on screen. Notes: STDOUT defaults to the screen. 05H - Write to Printer AH = 05H On Entry: DL = Character to be printed. On Exit: Character sent to printer. Notes: 06H - Direct Console Read/Write On AH = 06H Entry: DL = either 0FFH or ASCII Character On AL = ASCII Character Exit: If DL = 0FFH, console expects an incoming character and sets the Z flag if no key was entered. If a key was entered, the ASCII character for that key is returned in AL. If the content of AL = 0, the key was a Notes: function key and the call must be repeated. The function does not wait for a key depression. The character is not echoed to the screen. If DL = ASCII code, that character is immediately sent to the console screen. 08H - Read STDIN Without Echo On Entry: AH = 08H On Exit: AL = Incoming ASCII Character Notes: Reads a character from the keyboard, but waits until it arrives before returning. 09H - Display Character String AH = 09H On Entry: DS:DX = Address of character string. On Exit: String appears on screen. Notes: String must end with a dollar sign ($), 24H.0AH - Buffered Keyboard Input On AH = 0AH Entry: DS:DX = Address of keyboard input buffer. On Buffer has incoming data. Exit: The buffer has a byte for each expected character, preceded by two bytes. The first is the number of bytes we are willing to accept, including the CR at the end from the ENTER key. The second is initially blank, but Notes: returns with the number of bytes actually received. If the user attempts to enter more bytes that the buffer has space, the system will reject them waiting for the ENTER, which consumes the last byte of the buffer. 25H - Set Interrupt Vector AH = 25H On Entry: AL = Interrupt Vector Number, 0 to 0FFH. DS:DX = Address of new interrupt procedure. On Exit: Vector is changed. Notes: Use function 35H first to save current contents of vector before changing it.MICROPROCESSORS LAB 265
    • ELECTRONICS & COMMUNICATION ENGINEERING 2AH - Read System Date On Entry: AH = 2AH AL = Day of the week CX = Year (1980 - 2099) On Exit: DH = Month DL = Day of the Month Day of the week is encoded starting wtih 00H = Sunday. Notes: Year is a binary count based at 1980. 2BH - Set System Date AH = 2BH CX = Year (binary, base of 1980) On Entry: DH = Month DL = Day of the Month On Exit: System date is changed. Notes: 2CH -Read System Time On Entry: AH = 2CH CH = Hours (0 - 23) CL = Minutes On Exit: DH = Seconds DL = Hundredths of seconds Notes: 2DH - Set System Time AH = 2DH CH = Hours On Entry: CL = Minutes DH = Seconds DL = Hundredths of seconds On Exit: System time is updated. Notes: 35H - Read Interrupt Vector AH = 35H On Entry: AL = Interrupt number On Exit: ES:BX = Address stored at that vector. Notes: 36H - Determine Free Disk Space AH = 36H On Entry: DL = Drive number AX = 0FFFH if drive is invalid or AX = Number of sectors per cluster On Exit: BX = Number of free clusters CX = Bytes per sector DX = Number of clusters on drive Notes: Default drive is 00H, drive A = 01H, drive B = 02H, etc.MICROPROCESSORS LAB 266
    • ELECTRONICS & COMMUNICATION ENGINEERING 39H - Create Subdirectory AH = 39H On Entry: DS:DX = Address of ASCIZ string subdirectory name On Exit: AX = Error code if Carry bit is set Notes: String is of any reasonable length ending with a byte of 00H. 3AH - Remove Subdirectory AH = 3AH On Entry: DX:DX = Address of ASCIZ string subdirectory name On Exit: AX = Error code if Carry bit is set Notes: 3BH - Change Subdirectory AH = 3BH On Entry: DS:DX = Address of ASCIZ string with new subdirectory On Exit: AX = Error code if Carry bit is set Notes: 3CH - Create File AH = 3CH On Entry: CX = Attribute bits for new file (normally 00H) DS:DX = Address of ASCIZ string with new file name and directory AX = Error code if Carry bit is set On Exit: AX = File Handle if Carry bit is clear Attribute byte can contains these bits: 01H = Read Only 02H = Hidden file 04H = System file Notes: 08H = Volume label 10H = Subdirectory 20H = Archive bit A file handle is a 16 bit binary value that is used to identify the new file in subsequent calls. If file with same name already exists, it will be reclaimed and set to 0 length, loosing old data. 3DH - Open File AH = 3DH On Entry: AL = Access code DS:DX = Address of ASCIZ string file name and directory AX = Error Code if Carry bit is set On Exit: AX = File Handle if Carry bit is clear Notes: Access code corresponds to attribute bits in function 3CH. 3EH - Close File AH = 3EH On Entry: BX = File Handle On Exit: AX = Error Code if Carry bit is set Notes:MICROPROCESSORS LAB 267
    • ELECTRONICS & COMMUNICATION ENGINEERING 3FH - Read File AH = 3FH BX = File Handle On Entry: CX = Number of bytes to read DS:DX = Address of buffer to store data from drive AX = Error Code if Carry bit is set On Exit: AX = Number of bytes read if Carry bit is clear Notes: 40H - Write File AH = 40H BX = File Handle On Entry: CX = Number of bytes to be written DS:DX = Address of data to be written AX = Error Code if Carry bit is set On Exit: AX = Number of bytes actually written if Carry bit is clear Notes: 41H - Delete File AH = 41H On Entry: DS:DX = Address of ASCIZ string with file name and directory On Exit: AX = Error Code if Carry bit is set Notes: File must be closed before it is deleted. 42H - Move File Pointer AH = 42H AL = Move method On Entry: BX = File Handle CX:DX = Number of bytes to move pointer (DX contains least significant 16 bits) AX = Error Code if Carry bit is set On Exit: AX:DX = Number of bytes pointer was moved if Carry bit is clear (DX contains LSBs) Move methods: 00H = move from beginning of file Notes: 01H = move from current location within file 02H = move from end of file 43H - Read/Write File Attributes AH = 43H AL = 00H to read file attributes On Entry: AL = 01H to write file attributes CX = attributes from function 3CH DS:DX = Address of ASCIZ string with file name and directory AX = Error Code if Carry bit is set On Exit: CX = Attributes if Carry bit is clear Notes: 47H - Read Current Directory AH = 47H On Entry: DL = Drive number DS:SI = Buffer to hold directory name On Exit: DS:SI = Name of current directory Notes:MICROPROCESSORS LAB 268
    • ELECTRONICS & COMMUNICATION ENGINEERING 4CH - Terminate Process AH = 4CH On Entry: AL = Error Code On Exit: Returns control of the system to DOS engine Notes: Error code indicates to system whether the program ended normally. It is usually 0.MICROPROCESSORS LAB 269