1. Chapter 2: Hardware and
Software Architecture
Slides to Accompany
Assembly Language for Intel-Based Computers,
Third Edition
Copyright 1999-2001, Kip R. Irvine. All rights
2. Simplified CPU Design
Data Registers
Address Registers
Control
Unit
Arithmetic
Logic Unit
Status
Flags
Address Bus
Data Bus
Memory
Copyright 1999-2001, Kip R. Irvine. All rights
3. Intel 16-bit Registers
Index
BP
SP
SI
DI
Segment
CS
SS
DS
ES
General Purpose
AH
BH
CH
AL
BL
CL
DH DL
Status and Control
Flags
IP
AX
BX
CX
DX
Copyright 1999-2001, Kip R. Irvine. All rights
4. Flags Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
x
Bit
Position
x x x O D I T S Z x A x P x C
= Overflow
= Direction
= Interrupt
= Trap
= undefined
OD
I
T
x
= Sign
= Zero
= Auxiliary Carry
= Parity
= Carry
S
Z
AP
C
Each flag corresponds to a single bit in the Flags
register.
Copyright 1999-2001, Kip R. Irvine. All rights
5. 16-Bit Register Set
(Intel 8086, 8088, 80286)
• Data Registers
– AX,BX,CX,DX,AL,AH,BL,BH,CL,CH,DL,DH
• Segment Registers
– CS (code), DS (data), SS (stack), ES (extra data)
more...
Copyright 1999-2001, Kip R. Irvine. All rights
6. 16-Bit Register Set
• Index Registers
– BP (base pointer), SP (stack pointer), SI (source
index), DI (destination index)
• Instruction Pointer (IP)
• Flags Register
– Status: (overflow, sign, zero, carry, parity,
aux.carry)
– Control: (direction, interrupt, trap)
Copyright 1999-2001, Kip R. Irvine. All rights
7. Instruction Execution Cycle
• Fetch the next instruction
– place in queue
– update program counter
• Decode the instruction
– perform address translation
– fetch operands
• Execute the instruction
– perform required operation
– store the results in memory and/or registers
– update status flags attached to CPU
more...
Copyright 1999-2001, Kip R. Irvine. All rights
8. Instruction Execution Cycle
PC Program (RAM)
I-1 I-2 I-3 I-4
I-1
Instruction
Queue
op1
Data op2
(RAM)
fetch
registers
ALU
store the output
decode
execute
Copyright 1999-2001, Kip R. Irvine. All rights
9. 32-bit Register Set (Intel386, Intel486, Pentium)
General Purpose Index
31 0 EBP BP
ESP SP
ESI
EDI
Segment
CS
SS
DS
ES
AX
BX
CX
DX
Status and Control
Flags
IP
EAX
EBX
ECX
EDX
EFLAGS
EIP
FS
GS
SI
DI
code
stack
Copyright 1999-2001, Kip R. Irvine. All rights
data
10. Interrupt Vector Table
DOS Data Area
Software BIOS
DOS Kernel, Device Drivers, Etc.
Resident part of COMMAND.COM
(Availible RAM for
transient programs)
Transient part of COMMAND.COM
Video Graphics Buffer
MDA Text Buffer
Color Text Buffer
Reserved
ROM BIOS
(end of address space)
Address
00000
00400
9FFFF
A0000
B0000
B8000
C0000
F0000
FFFFF
Copyright 1999-2001, Kip R. Irvine. All rights
640K RAM
Map of the First
Megabyte of PC
Memory
11. O ffse t
(S e gm en t 0 4 0 0 )
D e sc r ip tio n
0 00 0 - 00 0 7
0 00 8 – 00 0F
0 01 0 - 00 1 1
0 01 2
0 01 3 – 00 14
0 01 5 – 00 16
0 01 7 – 00 18
0 01 9
0 01A – 00 1B
0 01C – 00 1D
0 01E – 00 3D
0 03E – 00 4 8
0 04 9
0 04A – 00 4B
0 04C – 00 4D
0 04E – 00 4 F
0 05 0 – 00 5F
0 06 0
0 06 1
0 06 2
0 06 3 - 00 6 4
0 06 5
0 06 6
0 06 7 – 00 6B
0 06C – 00 7 0
Po rt ad d resses, COM1 – COM4
Po rt ad d resses, L PT1 – LPT 4
In stalled h ardware list
In itializatio n flag
Mem o ry size, in Kb y tes
Mem o ry in I/O chan nel
Keyb o ard statu s flag s
Alternate key en try sto rag e
Keyb o ard bu ffer p oin ter (head)
Keyb o ard bu ffer p oin ter (tail)
Keyb o ard ty peah ead bu ffer
Diskette data area
C urren t v ideo m o de
Num ber of screen co lum ns
Reg en buffer leng th, in b y tes
Reg en buffer startin g o ffset
C ursor po sitio ns, v id eo pag es 1 - 8
C ursor en d lin e
C ursor start lin e
C urren tly disp lay ed video p age n um ber
Active d isp lay b ase ad dress
C RT mo d e register (MDA , CG A )
Reg ister fo r CG A
C assette d ata area
Timer data area
Map of the BIOS
Data Area
Copyright 1999-2001, Kip R. Irvine. All rights
12. Segmented Memory Architecture
(real mode)
• A segment addresses 64K of memory
• A segment register contains the starting
location of a segment
– the absolute location of a segment can be
obtained by appending a hexadecimal zero
• An offset is the distance from the beginning
of a segment to a particular instruction or
variable
Copyright 1999-2001, Kip R. Irvine. All rights
14. Example Using Index Register
Logical address (segment/of f set)
DS SI
OA16 0005
EPROM
(unused)
DRAM
(X 16)
1 MB
0A165
0A160
Copyright 1999-2001, Kip R. Irvine. All rights
00000
15. Intel Microprocessor Family
• Intel 8080
– 8-bit registers, 8-bit external data path
– addresses 64K memory
• Intel 8086
– 16-bit registers, 16-bit external data path
– addresses 1MB memory
– supports real mode
• Intel 8088
– identical to 8086, except with 8-bit external
data path
Copyright 1999-2001, Kip R. Irvine. All rights
16. Intel Microprocessor Family
• Intel 8087 coprocessor
– executes only floating-point instructions
• Intel 80286
– addresses 16MB of memory
– supports real mode and protected mode
• Intel 80287 coprocessor
– executes only floating-point instructions
Copyright 1999-2001, Kip R. Irvine. All rights
17. Intel Microprocessor Family
• Intel386 (Intel 80386)
– 32-bit registers, 32-bit external data path
– addresses 4GB of memory
– supports real mode, protected mode and
virtual mode
Copyright 1999-2001, Kip R. Irvine. All rights
18. Intel Microprocessor Family
• Intel486
– parallel instruction execution, modeled after
competing RISC processors
– integrated floating-point unit
– internal 8K high-speed cache
Copyright 1999-2001, Kip R. Irvine. All rights
19. Intel Microprocessor Family
• Intel Pentium (Intel586)
– early 90MHz model was at least 90% faster
than Intel486
– superscalar architecture (two instruction
pipelines)
– 64-bit internal data path
– 16K internal cache (8K data, 8K code)
Copyright 1999-2001, Kip R. Irvine. All rights
20. Intel Microprocessor Family
• Intel Pentium II
– 500 MHz clock speeds
– branch prediction logic
– out-of-order instruction execution
– larger internal cache
Copyright 1999-2001, Kip R. Irvine. All rights
21. Types of Memory
• ROM (read-only memory)
– used for BIOS (basic input-output system)
– write-once memory
– EPROM can be erased with ultraviolet light
• Static RAM (random access memory)
– may be rewritten unlimited number of times
– requires no refresh signal
• Dynamic RAM
– must be refreshed constantly
– cheaper than static RAM
Copyright 1999-2001, Kip R. Irvine. All rights
22. Cache Memory
• Holds the most recently used instructions
and data
– faster access than conventional memory
• Level-1 cache: Inside the CPU
• Level-2 cache: Connected to the CPU
– usually 256K to 1MB
Copyright 1999-2001, Kip R. Irvine. All rights
23. Conventional Memory
• SDRAM
– Synchronous Dynamic Random-Access Memory
• Slower than CPU registers and cache
memory
– limited by the bus cycle speed
– travels greater distances
– requires freuqent refreshes
Copyright 1999-2001, Kip R. Irvine. All rights
24. Video Memory
• VRAM (video RAM)
– located on video controller.
– dual-ported, allowing continuous refresh while
writing new data
• WRAM (windows graphics RAM)
– optimized for video graphics, better than VRAM
• SGRAM (synchronous graphics RAM)
– used on video accelerator cards
– suited to 3D applications
Copyright 1999-2001, Kip R. Irvine. All rights
25. Secondary Storage Devices
• Fixed disk (up to 100GB)
• 1.44MB diskette drive
• 600MB CDROM drive
• Removable disks (magnetic or optical)
• Magnetic tape backup (sequential storage)
Copyright 1999-2001, Kip R. Irvine. All rights
26. Fixed Disk Controllers
• IDE (intelligent drive electronics)
– usually two connectors on the motherboard
– each cable supports master and slave drive
• EIDE (enhanced IDE)
– supports more than two drives, & CDROM
– originally up to 8GB drives
• SCSI (small computer system interface)
– intelligent controller for multiple drives
– for high performance drives
Copyright 1999-2001, Kip R. Irvine. All rights
27. Input-Output Ports
• Serial
– sends one bit at a time
– used for telephone modems
• Parallel
– sends 8, 16, 32, or 64 bits at a time
– unidirectional or bidirectional
• USB (universal serial bus)
– intelligent connector, bidirectional
– supports plug-and-play installation of up to 128
devices (with USB hub)
Copyright 1999-2001, Kip R. Irvine. All rights
28. DEBUG Examples
Experimenting with the Carry, Overflow,
Sign, and Zero flags
Copyright 1999-2001, Kip R. Irvine. All rights
29. Essential Status Flags
• Zero
– set if the result of the last operation was equal to
zero
• Carry
– set if the result of the last unsigned arithmetic
operation generated an invalid value
• Sign
– set if the result of the last operation was negative
• Overflow
– set if the result of the last signed arithmetic
operation generated an invalid value
Copyright 1999-2001, Kip R. Irvine. All rights
30. DEBUG Flag Mnemonics
• Carry flag: CY=set, NC=clear
• Overflow flag: OV=set, NV=clear
• Sign flag: NG=set, PL=clear
• Zero flag: ZR=set, NZ=clear
Copyright 1999-2001, Kip R. Irvine. All rights
31. Testing the Carry Flag
0100 mov ax,FFFF
0103 add ax,1 ; CY, AX=0000
0106 sub ax,1 ; CY, AX=FFFF
Adding 1 to FFFF sets the Carry flag because
the unsigned sum is too large for the 16-bit
register. Subtracting 1 from 0000 also sets the
Carry flag because the unsigned result cannot
be equal to -1.
Copyright 1999-2001, Kip R. Irvine. All rights
32. Testing the Carry Flag
0100 mov ax,23FF
0103 add al,1 ; CY, AX=2300
0106 sub ax,1 ; NC, AX=22FF
Adding 1 to FF in AL sets the Carry flag
because the unsigned sum is too large for the
8-bit register. Subtracting 1 from 2300 clears
the Carry flag because the result (22FF) is still
a valid unsigned integer.
Copyright 1999-2001, Kip R. Irvine. All rights
33. Testing the Overflow Flag
0100 mov ax,FFFF
0103 add ax,1 ; NV, AX=0000
0106 sub ax,1 ; NV, AX=FFFF
Adding 1 to -1 (FFFF) in AX clears the
Overflow flag because the signed sum (0) is
perfectly valid. Subtracting 1 from 0 clears the
Overflow flag because the result (-1) is a valid
signed result.
Copyright 1999-2001, Kip R. Irvine. All rights
34. Testing the Sign Flag
0100 mov ax,7FFF
0103 add ax,1 ; NG, AX=8000
0106 sub ax,1 ; PL, AX=7FFF
Adding 1 to 7FFF in AX sets the Sign flag
because the sum in AX is negative (the high bit
equals 1). Subtracting 1 from 8000 returns AX
to a positive value, so the Sign flag is cleared.
Copyright 1999-2001, Kip R. Irvine. All rights
35. Testing the Zero Flag
0100 mov ax,FFFF
0103 add ax,1 ; ZR, AX=0000
0106 add ax,1 ; NZ, AX=0001
Adding 1 to FFFF in AX sets the Zero flag
because the sum in AX is 0000. Adding 1 to
0000 clears the Zero flag because the sum
(0001) is not equal to Zero.
Copyright 1999-2001, Kip R. Irvine. All rights