Computer organization PRA
Direct Memory Access
21P61A1233
D.SAI TEJA IT-A
Introduction of
Direct Memory Access (DMA)
Why is DMA?
 It is wasteful to feed data into a controller register 1 bytes at
a time. (PIO)
 The DMA unit is word.
 In the high loading environment, a system with DMA has
better improvement.
DMA transfer
5. DMA controller transfers bytes
to buffer X, increasing memory
address and decreasing C until C=0
6. when C=0, DMA interrupts CPU
to signal transfer completion
PCI bus
CPU memory bus Memory buffer
DMA/bus/
interrupt
controller
cache
CPU
1. device driver told to transfer disk
data to buffer at address X
2. device driver tells disk controller to
transfer C bytes from disk to buffer at
address X
3. disk controller initiates
DMA transfer
4. disk controller sends each
byte to DMA controller
IDE disk
controller
disk
disk
disk
disk
X
DMA Progress
 To initiate a DMA transfer, the host writes a DMA command
into memory:
 A pointer to the source of a transfer
 A count of the number of bytes to be transferred
 ……..
 The CPU writes the address of the DMA command block to
the DMA controller.
DMA Progress (cont.)
 The DMA controller proceeds to operate the memory bus
directly without CPU help.
 Handshaking exists between DMA controller and device
controller.
 When the entire transfer is finished, the DMA controller will
interrupts the CPU.
Handshaking
 DMA-request and DMA_acknowledge
 When a word of data is available, the device controller places a
signal on the DMA-request wire.
 The signal causes the DMA controller to seize the memory bus,
 To place the desired address on the memory-address wire
 To place a signal on the DMA-acknowledge wire
Handshaking (cont.)
 When the device controller receives the DMA-acknowledge
signal,
 it transfer the word of data to memory
 and remove the DMA_request signal.
THANK YOU

Direct Memory Access (DMA).ppt

  • 1.
    Computer organization PRA DirectMemory Access 21P61A1233 D.SAI TEJA IT-A
  • 2.
  • 3.
    Why is DMA? It is wasteful to feed data into a controller register 1 bytes at a time. (PIO)  The DMA unit is word.  In the high loading environment, a system with DMA has better improvement.
  • 4.
    DMA transfer 5. DMAcontroller transfers bytes to buffer X, increasing memory address and decreasing C until C=0 6. when C=0, DMA interrupts CPU to signal transfer completion PCI bus CPU memory bus Memory buffer DMA/bus/ interrupt controller cache CPU 1. device driver told to transfer disk data to buffer at address X 2. device driver tells disk controller to transfer C bytes from disk to buffer at address X 3. disk controller initiates DMA transfer 4. disk controller sends each byte to DMA controller IDE disk controller disk disk disk disk X
  • 6.
    DMA Progress  Toinitiate a DMA transfer, the host writes a DMA command into memory:  A pointer to the source of a transfer  A count of the number of bytes to be transferred  ……..  The CPU writes the address of the DMA command block to the DMA controller.
  • 7.
    DMA Progress (cont.) The DMA controller proceeds to operate the memory bus directly without CPU help.  Handshaking exists between DMA controller and device controller.  When the entire transfer is finished, the DMA controller will interrupts the CPU.
  • 9.
    Handshaking  DMA-request andDMA_acknowledge  When a word of data is available, the device controller places a signal on the DMA-request wire.  The signal causes the DMA controller to seize the memory bus,  To place the desired address on the memory-address wire  To place a signal on the DMA-acknowledge wire
  • 10.
    Handshaking (cont.)  Whenthe device controller receives the DMA-acknowledge signal,  it transfer the word of data to memory  and remove the DMA_request signal.
  • 11.