![XDK 4L
H103358
[45] VREGS, CPU OUTPUT PHASE 1 & 2
[38] CONN, RJ45 USB AUX COMBO +BORON +PWR
[39] CONN, USB +MEMPORTS +TOSLINK +WAVEPORT
REV A
CORONA
[43] VREGS, INPUT + OUTPUT FILTERS
[44] VREGS, CPU CONTROLLER
[27] KSB, ETHERNET + AUDIO + SATA
[26] KSB, FLASH + USB + SPI
[25] KSB, SMC
[24] KSB, PCIEX + SMM GPIO + JTAG
[23] KSB, VIDEO + FAN + AUDIO
[22] KSB, CLOCKS + STRAPPING
[21] MEMORY PARTITION D, BOTTOM
[20] MEMORY PARTITION D, TOP
[19] MEMORY PARTITION C, BOTTOM
[18] MEMORY PARTITION C, TOP
[17] MEMORY PARTITION B, BOTTOM
[14] MEMORY PARTITION A, TOP
[13] GCPU, MEMORY CONTROLLER C + D
[12] GCPU, MEMORY CONTROLLER A + B
[41] CONN, ODD + HDD
[40] CONN, HDMI
[47] VREGS, V5P0
[15] MEMORY PARTITION A, BOTTOM
[63] DEBUG BOARD, GPU CONN + TERM
[66] DEBUG BOARD, SPYDER CONN
16.) REV AND FAB ARE SET USING CUSTOM VARIABLES. TOOLS>OPTIONS>VARIABLES
3.) ORDER OF PAGES=CHIP INTERFACES, TERMINATION, POWER, DECOUPLING
[30] KSB, STANDBY POWER + GROUND
[29] KSB, BULK DECOUPLING
[28] KSB, DECOUPLING
[53] VREGS, STANDBY SWITCHERS
[58] MARGIN,VGPUPCIE+VCPUPLL+V1P8+V12P0+TEMP
[59] MARGIN, STANDBY SWITCHERS
[64] DEBUG TEST POINTS
[65] XDK, DEBUG TITAN
[69] SYSTEM BLOCK DIAGRAM
[72] I2C REFERENCE TABLES
[36] CONN, FAN
[37] CONN, AVIP
[46] VREGS, V5P0DUAL
[54] BOARD, DECOUPLING
[61] EXTERNAL TEMPERATURE SENSORS
[67] LABELS & MOUNTING
[68] POWER ARCHITECTURE
[49] VREGS, VEDRAM
[50] VREGS, VMEM
[51] VREGS, VCS
[4] GCPU, VIDEO + PCIEX
[6] GCPU, PLL PWR + FSB PWR
[8] GCPU, PWR
CONTENTS
[1] COVER PAGE
[2] GCPU, SETUP
[60] MARGIN, V1P2
[62] XDK, DEBUG CONN
[31] KSB, MAIN POWER
[32] KSB OUT, MMC + FLASH
[48] VREGS, V3P3
[33] KSB OUT, AUDIO
9.) UNNAMED NETS ARE NAMED WITH /2 TEXT SIZE
10.) SUFFIX _N FOR ACTIVE LOW OR N JUNCTION
5.) LANED SIGNALS ARE GROUPED ON SYMBOLS
15.) PWRGD FOR POWER GOOD
13.) SUFFIX _EN FOR ENABLE
12.) SUFFIX _P FOR P JUNCTION
14.) 'CLK' FOR CLOCKS, 'RST' FOR RESETS
[PAGE_TITLE=COVER PAGE]
[9] GCPU, DECOUPLING
CONTENTS
[7] GCPU, PWR
RULES: (APPLIED WHEN POSSIBLE)
1.) MSB TO LSB IS TOP TO BOTTOM
PAGE
[5] GCPU, EEPROM + JTAG
[3] GCPU, DEBUG BUS
PAGE
8.) SUFFIX _DP AND _DN ARE USED FOR DIFFERIENTAL PAIRS
7.) SUFFIX V_ IS USED FOR VOLTAGE RAIL SIGNAL NAMES
6.) TRANSIMITTER NAME USED AS PREFIX WITH RX AND TX CONNECTIONS
4.) AVOID USING OFF PAGE CONNECTORS FOR ON PAGE CONNECTIONS
2.) WHEN POSSIBLE: INPUTS ON LEFT, OUTPUTS ON RIGHT
[16] MEMORY PARTITION B, TOP
[10] GCPU, DECOUPLING
[35] INFARED + SWITCHES
[34] KSB OUT, FLASH
[52] VREGS, LINEARS
[55] MARGIN, VMEM + VEDRAM
[56] MARGIN, V3P3 + V5P0
[57] MARGIN, VREFS + VCS
[70] SYSTEM RESET DIAGRAM
[42] VREGS, BLEEDERS
[73] DOC TRACKING
[11] GCPU, DECOUPLING
[71] COMPONENT STUFFING TABLES
CORONA_XDK_4L
REV 1.01
FAB E
CR-1 : @CORONA_LIB.CORONA(SCH_1):PAGE1
1/87 1.01
E
Thu Feb 17 21:37:16 2011
DRAWING
FAB
PROJECT NAME
CONFIDENTIAL
MICROSOFT REV
PAGE
A
C
D
B
A
C
B
D
8 7 6 5 4 3 2 1
7 6 5 4 3 2 1
8](https://image.slidesharecdn.com/xbox360coronaschematic-240118222643-d62738b7/85/xbox-360-corona-schematic-motherboard-repair-1-320.jpg)
![6 LAYER ONLY; TP ONLY
6 LAYER ONLY
VGATE RESISTORS SHOULD BE ADJUSTED
SET VGATE=1.20V
WHEN V_CPUPLL=1.83V
GPU_DBG_RST_EN
INTERNAL PULLDN
N: IF V_CPUPLL CHANGES
CPU_DBG_RST_EN
INTERNAL PULLDN
CORE_HF_BGR_PLL
CPU_LIMIT_BYPASS
CPU_PLL_BYPASS
CPU_CORE_HF_CLKOUT_DP
CPU_EXT_CLK_EN
CPU_VDDS0_DP
CPU_VDDS0_DN
CPU_DLL_SNIF_OUT
[PAGE_TITLE=GCPU SETUP]
6 LAYER ONLY; TP ONLY, INTERNAL PULLDN
6 LAYER ONLY; TP ONLY, INTERNAL PULLDN
6 LAYER ONLY
6 LAYER ONLY; TP ONLY, INTERNAL PULLDN
CPU_VDDS1_DP
CPU_VDDS1_DN
RESISTOR0_DP
RESISTOR0_DN
EDRAM_PSRO_DOUT
6 LAYER ONLY
6 LAYER ONLY
6 LAYER ONLY
6 LAYER ONLY
6 LAYER ONLY
6 LAYER ONLY; TP ONLY
6 LAYER ONLY; TP ONLY
CPU_CORE_HF_CLKOUT_DN
ACTUAL=1.202V
6 LAYER ONLY SIGNALS
6 LAYER ONLY; TP ONLY
GCPU SETUP
CR-2 : @CORONA_LIB.CORONA(SCH_1):PAGE2
2/87 1.01
CORONA_XDK_4L E
Thu Feb 17 10:12:25 2011
V_CPUCORE
200 OHM
402
CH
5%
402 CH
1%
1.27 KOHM
CH
1%
402
2 KOHM
EMPTY
402
100 OHM
5%
0 OHM
402 CH
5%
5%
CH
402
0 OHM
50 V
EMPTY
360 PF
5%
603
1.07 KOHM
1%
CH
402
CH
562 OHM
1%
402
V_CPUPLL
IC
BGA_2
X818336-001
14 OF 17
50 V
603
360 PF
EMPTY
5%
5%
402
CH
10 KOHM
I114
I113
I112
100 OHM
402
EMPTY
5%
CH
5%
200 OHM
402
R3E10
DB4R2
DB4R3
R4R23
R4R20
R4R21
R4P5
R4P4
R4D2
R4D1
R5T9
R5T8
U5E1
C5R11
FT3T10
FT7P3
FT7P4
FT7P5
FT7P7
FT7P6
FT7P8
R4R22
C5R66
FT3T11
25
25
22
22
43
43
43
43
43
43
51
52
63
63
CPU_VGATE
CPU_DBG_RST_EN
CPU_CLK_DN_R2
CPU_PWRGD
CPU_RST_N
CPU_CLK_DP_R2
GPU_DBG_RST_EN
EDRAM_PSRO_DOUT
CPU_PSRO0_OUT
CPU_CLK_DP
RESISTOR0_DN
RESISTOR0_DP
CPU_CLK_DN
CPU_TINIT
CPU_EXT_CLK_EN
CPU_TE
CPU_VREG_APS6
CPU_VREG_APS4
CPU_VREG_APS3
CPU_VREG_APS1
CPU_VREG_APS2
CPU_VREG_APS5
CPU_LIMIT_BYPASS
CPU_PLL_BYPASS
CPU_SRVID
VREG_EFUSE_EN
CORE_HF_BGR_PLL
CPU_CHECKSTOP_N
CPU_RST_V1P1_N
2
1
1
1
2
1
2
1
2
1
1
2
2
1
1
2
1
2
2
1
2
1
C24
B24
A24
C23
B23
A23
V6
J7
E7
A3
L7
M7
J6
N6
G7
T5
F8
D5
R5
F7
C1
P5
P2
P1
M6
E5
2
1
1
1
1
1
1
1
1
2
1
2
1
1
DRAWING
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
IN
IN
IN
OUT
OUT
GCPU VERSION 1
TI_39_TINIT
CPU_CLK_DP
CPU_CLK_DN
CPU_DBG_RST_EN<DN>
GPU_DBG_RST_EN<DN>
PSRO0_OUT
PSRO_DOUT
RESISTOR0_DP
RESISTOR0_DN
V_GATE
EXT_CLK_EN<DN>
EFU_POWERON
SRVID
TE
<DN>PULSE_LIMIT_BYPASS
<DN>PLL_BYPASS
CORE_HF_BGR_PLL
CHECKSTOP_B
VID5
VID4
VID2
VID1
VID6
POWER_GOOD
HARD_RESET_B
VID3
IN
FTP
FTP
FTP
FTP
FTP
FTP
FTP
FTP
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
FAB
PROJECT NAME
CONFIDENTIAL
MICROSOFT REV
PAGE
A
C
D
B
A
C
B
D
8 7 6 5 4 3 2 1
7 6 5 4 3 2 1
8](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)
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- 1. XDK 4L H103358 [45] VREGS, CPU OUTPUT PHASE 1 & 2 [38] CONN, RJ45 USB AUX COMBO +BORON +PWR [39] CONN, USB +MEMPORTS +TOSLINK +WAVEPORT REV A CORONA [43] VREGS, INPUT + OUTPUT FILTERS [44] VREGS, CPU CONTROLLER [27] KSB, ETHERNET + AUDIO + SATA [26] KSB, FLASH + USB + SPI [25] KSB, SMC [24] KSB, PCIEX + SMM GPIO + JTAG [23] KSB, VIDEO + FAN + AUDIO [22] KSB, CLOCKS + STRAPPING [21] MEMORY PARTITION D, BOTTOM [20] MEMORY PARTITION D, TOP [19] MEMORY PARTITION C, BOTTOM [18] MEMORY PARTITION C, TOP [17] MEMORY PARTITION B, BOTTOM [14] MEMORY PARTITION A, TOP [13] GCPU, MEMORY CONTROLLER C + D [12] GCPU, MEMORY CONTROLLER A + B [41] CONN, ODD + HDD [40] CONN, HDMI [47] VREGS, V5P0 [15] MEMORY PARTITION A, BOTTOM [63] DEBUG BOARD, GPU CONN + TERM [66] DEBUG BOARD, SPYDER CONN 16.) REV AND FAB ARE SET USING CUSTOM VARIABLES. TOOLS>OPTIONS>VARIABLES 3.) ORDER OF PAGES=CHIP INTERFACES, TERMINATION, POWER, DECOUPLING [30] KSB, STANDBY POWER + GROUND [29] KSB, BULK DECOUPLING [28] KSB, DECOUPLING [53] VREGS, STANDBY SWITCHERS [58] MARGIN,VGPUPCIE+VCPUPLL+V1P8+V12P0+TEMP [59] MARGIN, STANDBY SWITCHERS [64] DEBUG TEST POINTS [65] XDK, DEBUG TITAN [69] SYSTEM BLOCK DIAGRAM [72] I2C REFERENCE TABLES [36] CONN, FAN [37] CONN, AVIP [46] VREGS, V5P0DUAL [54] BOARD, DECOUPLING [61] EXTERNAL TEMPERATURE SENSORS [67] LABELS & MOUNTING [68] POWER ARCHITECTURE [49] VREGS, VEDRAM [50] VREGS, VMEM [51] VREGS, VCS [4] GCPU, VIDEO + PCIEX [6] GCPU, PLL PWR + FSB PWR [8] GCPU, PWR CONTENTS [1] COVER PAGE [2] GCPU, SETUP [60] MARGIN, V1P2 [62] XDK, DEBUG CONN [31] KSB, MAIN POWER [32] KSB OUT, MMC + FLASH [48] VREGS, V3P3 [33] KSB OUT, AUDIO 9.) UNNAMED NETS ARE NAMED WITH /2 TEXT SIZE 10.) SUFFIX _N FOR ACTIVE LOW OR N JUNCTION 5.) LANED SIGNALS ARE GROUPED ON SYMBOLS 15.) PWRGD FOR POWER GOOD 13.) SUFFIX _EN FOR ENABLE 12.) SUFFIX _P FOR P JUNCTION 14.) 'CLK' FOR CLOCKS, 'RST' FOR RESETS [PAGE_TITLE=COVER PAGE] [9] GCPU, DECOUPLING CONTENTS [7] GCPU, PWR RULES: (APPLIED WHEN POSSIBLE) 1.) MSB TO LSB IS TOP TO BOTTOM PAGE [5] GCPU, EEPROM + JTAG [3] GCPU, DEBUG BUS PAGE 8.) SUFFIX _DP AND _DN ARE USED FOR DIFFERIENTAL PAIRS 7.) SUFFIX V_ IS USED FOR VOLTAGE RAIL SIGNAL NAMES 6.) TRANSIMITTER NAME USED AS PREFIX WITH RX AND TX CONNECTIONS 4.) AVOID USING OFF PAGE CONNECTORS FOR ON PAGE CONNECTIONS 2.) WHEN POSSIBLE: INPUTS ON LEFT, OUTPUTS ON RIGHT [16] MEMORY PARTITION B, TOP [10] GCPU, DECOUPLING [35] INFARED + SWITCHES [34] KSB OUT, FLASH [52] VREGS, LINEARS [55] MARGIN, VMEM + VEDRAM [56] MARGIN, V3P3 + V5P0 [57] MARGIN, VREFS + VCS [70] SYSTEM RESET DIAGRAM [42] VREGS, BLEEDERS [73] DOC TRACKING [11] GCPU, DECOUPLING [71] COMPONENT STUFFING TABLES CORONA_XDK_4L REV 1.01 FAB E CR-1 : @CORONA_LIB.CORONA(SCH_1):PAGE1 1/87 1.01 E Thu Feb 17 21:37:16 2011 DRAWING FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 2. 6 LAYER ONLY; TP ONLY 6 LAYER ONLY VGATE RESISTORS SHOULD BE ADJUSTED SET VGATE=1.20V WHEN V_CPUPLL=1.83V GPU_DBG_RST_EN INTERNAL PULLDN N: IF V_CPUPLL CHANGES CPU_DBG_RST_EN INTERNAL PULLDN CORE_HF_BGR_PLL CPU_LIMIT_BYPASS CPU_PLL_BYPASS CPU_CORE_HF_CLKOUT_DP CPU_EXT_CLK_EN CPU_VDDS0_DP CPU_VDDS0_DN CPU_DLL_SNIF_OUT [PAGE_TITLE=GCPU SETUP] 6 LAYER ONLY; TP ONLY, INTERNAL PULLDN 6 LAYER ONLY; TP ONLY, INTERNAL PULLDN 6 LAYER ONLY 6 LAYER ONLY; TP ONLY, INTERNAL PULLDN CPU_VDDS1_DP CPU_VDDS1_DN RESISTOR0_DP RESISTOR0_DN EDRAM_PSRO_DOUT 6 LAYER ONLY 6 LAYER ONLY 6 LAYER ONLY 6 LAYER ONLY 6 LAYER ONLY 6 LAYER ONLY; TP ONLY 6 LAYER ONLY; TP ONLY CPU_CORE_HF_CLKOUT_DN ACTUAL=1.202V 6 LAYER ONLY SIGNALS 6 LAYER ONLY; TP ONLY GCPU SETUP CR-2 : @CORONA_LIB.CORONA(SCH_1):PAGE2 2/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:25 2011 V_CPUCORE 200 OHM 402 CH 5% 402 CH 1% 1.27 KOHM CH 1% 402 2 KOHM EMPTY 402 100 OHM 5% 0 OHM 402 CH 5% 5% CH 402 0 OHM 50 V EMPTY 360 PF 5% 603 1.07 KOHM 1% CH 402 CH 562 OHM 1% 402 V_CPUPLL IC BGA_2 X818336-001 14 OF 17 50 V 603 360 PF EMPTY 5% 5% 402 CH 10 KOHM I114 I113 I112 100 OHM 402 EMPTY 5% CH 5% 200 OHM 402 R3E10 DB4R2 DB4R3 R4R23 R4R20 R4R21 R4P5 R4P4 R4D2 R4D1 R5T9 R5T8 U5E1 C5R11 FT3T10 FT7P3 FT7P4 FT7P5 FT7P7 FT7P6 FT7P8 R4R22 C5R66 FT3T11 25 25 22 22 43 43 43 43 43 43 51 52 63 63 CPU_VGATE CPU_DBG_RST_EN CPU_CLK_DN_R2 CPU_PWRGD CPU_RST_N CPU_CLK_DP_R2 GPU_DBG_RST_EN EDRAM_PSRO_DOUT CPU_PSRO0_OUT CPU_CLK_DP RESISTOR0_DN RESISTOR0_DP CPU_CLK_DN CPU_TINIT CPU_EXT_CLK_EN CPU_TE CPU_VREG_APS6 CPU_VREG_APS4 CPU_VREG_APS3 CPU_VREG_APS1 CPU_VREG_APS2 CPU_VREG_APS5 CPU_LIMIT_BYPASS CPU_PLL_BYPASS CPU_SRVID VREG_EFUSE_EN CORE_HF_BGR_PLL CPU_CHECKSTOP_N CPU_RST_V1P1_N 2 1 1 1 2 1 2 1 2 1 1 2 2 1 1 2 1 2 2 1 2 1 C24 B24 A24 C23 B23 A23 V6 J7 E7 A3 L7 M7 J6 N6 G7 T5 F8 D5 R5 F7 C1 P5 P2 P1 M6 E5 2 1 1 1 1 1 1 1 1 2 1 2 1 1 DRAWING OUT OUT OUT OUT IN IN OUT OUT IN IN IN OUT OUT GCPU VERSION 1 TI_39_TINIT CPU_CLK_DP CPU_CLK_DN CPU_DBG_RST_EN<DN> GPU_DBG_RST_EN<DN> PSRO0_OUT PSRO_DOUT RESISTOR0_DP RESISTOR0_DN V_GATE EXT_CLK_EN<DN> EFU_POWERON SRVID TE <DN>PULSE_LIMIT_BYPASS <DN>PLL_BYPASS CORE_HF_BGR_PLL CHECKSTOP_B VID5 VID4 VID2 VID1 VID6 POWER_GOOD HARD_RESET_B VID3 IN FTP FTP FTP FTP FTP FTP FTP FTP OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 3. GCPU, DEBUG BUS ALL POST IN'S HAVE INTERNAL PULLUPS [PAGE_TITLE=GCPU, DEBUG BUS] CR-3 : @CORONA_LIB.CORONA(SCH_1):PAGE3 3/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:25 2011 402 EMPTY 200 OHM 5% 3 14 15 13 10 11 5% 200 OHM EMPTY 402 12 9 8 5 6 7 4 3 0 4 1 2 0 1 2 4 3 IC X818336-001 BGA_2 15 of 17 1 0 2 4 3 6 7 5 8 9 10 12 11 14 13 15 0 3 2 1 4 402 EMPTY 200 OHM 5% 0 402 200 OHM 5% EMPTY 1 200 OHM EMPTY 402 5% 2 FT5R12 FT5R9 FT5R13 FT5R16 FT5R11 FT5R10 FT5R15 FT5R14 FT5R2 FT5R1 FT5R4 FT5R3 FT5R5 FT5R8 FT5R7 FT5R6 FT4R9 FT4R7 FT4R8 FT4R4 FT4R6 FT5P2 FT5P1 U5E1 R4R13 R4R6 R4R8 R4R3 R4R5 3 3 CPU_DBG_TBCLK0 CPU_DBG_TBCLK1 CPU_DLL_SNIF_OUT CPU_DBG15_GPUCLK1 CPU_DBG14_GPUCLK0 CPU_DBG12_CPUCLK0 CPU_DBG11_GPU_HB CPU_DBG10_RST2 CPU_DBG9_RST1 CPU_DBG7_POST7 CPU_DBG6_POST6 CPU_DBG5_POST5 CPU_DBG4_POST4 CPU_DBG3_POST3 CPU_DBG2_POST2 CPU_DBG1_POST1 CPU_DBG0_POST0 CPU_DBG<0..15> CPU_DBG8_RST0 CPU_DBG13_CPUCLK1 CPU_DBG<0..15> POST_IN<0..4> 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B5 A4 A8 D8 C5 A5 B6 C6 A6 C7 A7 B9 D7 E8 D6 D9 C8 B8 B27 H6 J4 K7 L4 AJ30 AP26 AP7 F6 G6 G5 F5 H5 W6 2 1 2 1 2 1 2 1 2 1 DRAWING OUT FTP FTP FTP FTP FTP FTP FTP FTP FTP FTP FTP FTP FTP FTP FTP FTP IN FTP FTP FTP FTP FTP OUT OUT FTP FTP GCPU VERSION 1 SPARE0 DLL_SNIF_OUT TBCLK1 TBCLK0 SPARE1 SPARE2 SPARE3 SPARE4 SPARE5 SPARE6 SPARE7 TB14_GPUCLK0 TB15_GPUCLK1 TB12_CPUCLK0 TB13_CPUCLK1 TB11_GPU_HB TB7_POST_OUT7 TB9_RESET1 TB10_RESET2 TB8_RESET0 TB6_POST_OUT6 TB3_POST_OUT3 TB4_POST_OUT4 TB5_POST_OUT5 TB2_POST_OUT2 TB1_POST_OUT1 TB0_POST_OUT0 <UP>POST_IN3 <UP>POST_IN4 <UP>POST_IN0 <UP>POST_IN2 <UP>POST_IN1 OUT FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 4. GCPU, VIDEO + PCIEX VIDEO DECOUPLING [PAGE_TITLE=GCPU, VIDEO + PCIEX] CR-4 : @CORONA_LIB.CORONA(SCH_1):PAGE4 4/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:25 2011 5% 402 CH 1 KOHM CH 402 5% 1 KOHM 0.1 UF 402 6.3 V 10% X5R 402 CH 1% 240 OHM 240 OHM 402 CH 1% 6.3 V 0.1 UF 402 10% X5R X5R 6.3 V 0.1 UF 402 10% 0.1 UF 6.3 V 402 X5R 10% 1 0 2 3 4 6 5 7 8 9 10 12 11 14 13 V_MEM 1 KOHM CH 5% 402 V_MEM EMPTY X801851-001 402 CH 5% 1 KOHM CH 402 5% 1 KOHM CH 402 1 KOHM 5% 0.1 UF 6.3 V 10% X5R 402 0.1 UF 6.3 V 10% 402 X5R CH 5% 402 0 OHM CH 0 OHM 5% 402 X818336-001 BGA_2 IC 5 OF 17 4.99 KOHM 402 1% CH V_MEM 6.3 V X5R 10% 0.1 UF 402 R6U6 U5U2 R7R6 R7T7 R5U6 C4E1 C4E2 R4E2 R4E1 U5E1 FT3T2 FT3R17 R5T1 R7E2 R6F6 R6T3 R6T6 C5T36 C5E3 C5E4 C5E1 C5E2 23 15 17 19 21 25 24 24 24 24 23 23 14 16 18 20 14 15 16 17 18 19 20 21 14 15 16 17 18 19 20 21 24 62 24 62 24 62 24 62 25 22 22 61 61 61 61 61 61 23 22 22 GPU_PIX_CLK_1X MEM_SCAN_BOT_EN GPU_RST_N PEX_SB_GPU_L1_DP PEX_SB_GPU_L0_DP PEX_SB_GPU_L0_DN PEX_SB_GPU_L1_DN GPU_CLK_DN_C GPU_HSYNC_OUT GPU_VSYNC_OUT MEM_SCAN_TOP_EN MEM_SCAN_EN MEM_RST MEM_SCAN_BOT_EN_N PEX_GPU_SB_L0_DN_C PEX_GPU_SB_L1_DN_C GPU_CLK_DN_R2 PEX_GPU_SB_L0_DN PEX_GPU_SB_L0_DP_C PEX_GPU_SB_L1_DN PEX_GPU_SB_L0_DP PEX_GPU_SB_L1_DP GPU_RST_DONE PEX_GPU_SB_L1_DP_C MEM_CALB MEM_CALA PEX_RCAL PIX_CLK_2X_DN PIX_CLK_2X_DP GPU_CLK_DP_C CPU_TEMP_P CPU_TEMP_N EDRAM_TEMP_N EDRAM_TEMP_P GPU_TEMP_N GPU_TEMP_P PIX_DATA<14..0> GPU_CLK_DN GPU_CLK_DP GPU_CLK_DP_R2 2 1 4 5 3 1 2 2 1 2 1 2 1 2 1 2 1 2 1 2 1 M1 D2 U6 H3 H2 H1 J1 K3 K2 K1 L2 F2 F1 F3 G2 G1 L1 M3 J2 N1 N2 U2 U1 W2 W1 T2 T1 V2 V1 V3 P4 P3 R2 R1 AE7 AF7 AB33 AD27 AG18 W27 M2 V4 V5 M5 L5 1 1 1 2 1 2 1 2 1 2 1 2 2 1 2 1 2 1 2 1 DRAWING OUT OUT IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT NC A VCC GND Y OUT OUT OUT IN OUT GCPU VERSION 1 ED_THERMD_N CPU_THERMD_P CPU_THERMD_N ED_THERMD_P NB_THERMD_P NB_THERMD_N MEM_CALA MEM_CALB PEX_RCAL PIX_CLK_IN_DP PIX_CLK_IN_DN PEX_RX0_DN PEX_RX0_DP PEX_RX1_DN PEX_RX1_DP RST_IN_N* NB_CLK_DN NB_CLK_DP MEM_SCAN_OEN_B MEM_SCAN_OEN_A MEM_SCAN_EN MEM_RST HSYNC_OUT VSYNC_OUT PIX_DATA0 PIX_DATA2 PIX_DATA1 PIX_DATA3 PIX_DATA5 PIX_DATA4 PIX_DATA6 PIX_DATA7 PIX_DATA8 PIX_DATA10 PIX_DATA9 PIX_DATA11 PIX_DATA12 PIX_DATA13 PIX_DATA14 PIX_CLK_OUT PEX_TX0_DN PEX_TX0_DP PEX_TX1_DN PEX_TX1_DP RST_DONE OUT OUT OUT FTP FTP OUT OUT FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 5. GCPU, EEPROM + JTAG [PAGE_TITLE=GCPU, EEPROM + JTAG] CR-5 : @CORONA_LIB.CORONA(SCH_1):PAGE5 5/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:26 2011 10 KOHM 5% EMPTY 402 V_MEM CH 402 1 KOHM 5% 10% 0.01 UF EMPTY 16 V 402 EMPTY 100 OHM 5% 402 100 OHM 402 EMPTY 5% 5% 200 OHM 402 EMPTY 402 0 OHM CH 5% CH 5% 1 KOHM 402 CH 402 5% 1 KOHM X818336-001 17 of 17 BGA_2 IC TP V_MEM 100 OHM 402 5% EMPTY V_MEM V_MEM V_MEM 10% 6.3 V X5R 402 0.1 UF EMPTY X800552-001 V_MEM 402 CH 10 KOHM 5% C3C5 R3C26 R4C8 R4C3 R3C15 FT4P7 FT4P4 FT4P5 FT4P6 FT4P10 FT4R11 FT4P8 U5E1 DB4R1 R4R2 C4P5 U4P1 R4R12 R4R10 R4P6 R4R11 R4R7 63 63 63 63 63 63 63 63 63 63 63 63 63 CPU_TDI GPU_SROM_SCLK_R GPU_SROM_CS_N_R GPU_SROM_WP_N GPU_SROM_SI GPU_SROM_EN CPU_TCLK GPU_SROM_SCLK GPU_SROM_SO_R GPU_SROM_SO GPU_SROM_CS CPU_TDO CPU_TMS CPU_TRST_N CPU_TRST_N_R GPU_TRST_ED_N GPU_TRST_N 2 1 2 1 2 1 2 1 1 2 1 1 1 1 1 1 1 E2 E1 D3 E3 D1 U5 R6 A2 B4 B1 B2 C2 1 1 2 2 1 3 8 2 5 6 7 4 1 1 2 2 1 2 1 2 1 2 1 DRAWING OUT IN IN IN IN OUT OUT OUT FTP FTP FTP FTP FTP FTP FTP GCPU VERSION 1 GPU_TRST_B<DN> GPU_TRST_ED_B<DN> CPU_TCLK<UP> CPU_TDO<UP> CPU_TRST_B<UP> <DN>SROM_EN <UP>SROM_CS <DN>SROM_SCLK <DN>SROM_SO <DN>SROM_SI CPU_TDI<UP> CPU_TMS<UP> OUT OUT OUT OUT OUT AT25020A SDI SCK HOLD_N* CS_N* WP_N* VCC SDO GND FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 6. GCPU, PLL POWER + FSB POWER [PAGE_TITLE=GCPU, PLL POWER + FSB POWER] CR-6 : @CORONA_LIB.CORONA(SCH_1):PAGE6 6/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:26 2011 V_EFUSE 6.3 V 10 UF 20% 805 X5R 603 4.7 UF 6.3 V X5R 10% 6.3 V 10 UF 20% 805 X5R 6.3 V 10 UF 20% 805 X5R V_CPUPLL 603 FB 0.2A 0.5 DCR V_CPUEDRAM V_GPUPCIE 603 FB 0.5 DCR 0.2A 4.7 UF 603 10% X5R 6.3 V 603 FB 0.2A 0.5 DCR 6.3 V 10 UF 20% 805 X5R 402 X5R 6.3 V 0.1 UF 10% 603 FB 0.2A 0.5 DCR FB 603 0.2A 0.5 DCR 20% 805 X5R 6.3 V 10 UF FB 603 0.2A 0.5 DCR 6.3 V 10 UF 20% 805 X5R 603 0.5 DCR 0.2A FB 603 FB 0.2A 0.5 DCR 16 of 17 IC X818336-001 BGA_2 DB5R5 FB5T1 C5T4 ST5R2 FB5R2 C5R17 C5T6 ST5R3 FB5R3 C5R31 ST5R4 FB5R4 C5R42 ST5R5 ST5T2 ST5T1 ST5R1 U5E1 C5R54 C5T13 C5T9 C5R14 FB5R1 FB5R5 FB5T3 FB5T2 V_CPU_PVSSA_HS V_CPU_VDD_VTTA V_CPU_PVSSA_ED V_CPU_PVDDA_ED CPU_VDDS1_DN CPU_VDDS0_DN V_CPU_PVDDA_MEM V_CPU_PVSSA_PEX V_CPU_GNDA_RNG CPU_CORE_HF_CLKOUT_DP CPU_CORE_HF_CLKOUT_DN V_CPU_CORE_HF_GNDA_PLL CPU_VDDS0_DP V_CPU_PVSSA_MEM V_CPU_PVDDA_PEX CPU_VDDS1_DP V_CPU_PVDDA_HS V_CPU_CORE_HF_VDDA_PLL V_GPU_VDDA_PLL V_GPU_GNDA_PLL V_CPU_VDDA_RNG 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 H25 J26 P7 N7 E4 N4 R4 R3 U4 C4 B3 W4 U3 D4 C3 W5 G4 H4 N3 J5 K5 L6 K6 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 DRAWING OUT OUT OUT OUT OUT OUT SHORT SHORT SHORT SHORT SHORT SHORT SHORT GCPU VERSION 1 VDD_VTT GPU_GNDA_PLL VDD_VTTA PVSSA_ED GPU_VDDA_PLL VDDS1_DN VDDS1_DP VDDE CORE_HF_GNDA_PLL CORE_HF_VDDA_PLL GNDA_RNG VDDA_RNG PVDDA_ED PVSSA_HS PVDDA_HS PVSSA_PEX PVDDA_PEX PVSSA_MEM VDDS0_DP VDDS0_DN PVDDA_MEM CORE_HF_CLKOUT_DP CORE_HF_CLKOUT_DN FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 7. GCPU, POWER [PAGE_TITLE=GCPU, POWER] CR-7 : @CORONA_LIB.CORONA(SCH_1):PAGE7 7/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:26 2011 V_CPUCORE V_CPUCORE V_CPUCORE V_CPUVCS V_CPUVCS X818336-001 BGA_2 6 OF 17 IC V_CPUEDRAM V_CPUEDRAM V_MEM X818336-001 BGA_2 8 OF 17 IC X818336-001 BGA_2 7 OF 17 IC IC BGA_2 10 OF 17 X818336-001 X818336-001 BGA_2 9 OF 17 IC V_MEM V_CPUCORE U5E1 U5E1 U5E1 U5E1 U5E1 N9 P10 P8 R9 T10 T8 U9 A11 A9 B10 C11 C9 D10 E11 E9 F10 V10 G11 G9 H10 H8 J9 K10 K8 L9 M10 M8 V8 W9 F28 G31 G29 G27 G25 H32 H28 H26 J32 J29 AM19 K27 L31 L28 M30 M27 N29 P31 P29 R27 T32 AM16 T28 V31 V27 W32 W29 Y27 AA31 AA28 AB30 AB27 AM9 AC29 AD31 AD29 AE8 AE4 AF32 AF28 AF27 AF6 AF3 AM7 AG31 AG28 AG25 AG23 AG20 AG17 AG15 AG13 AG10 AG7 AM5 AG4 AH32 AH29 AH27 AH24 AH19 AH14 AH9 AH8 AH6 AM3 AH3 AJ31 AJ28 AJ26 AJ22 AJ21 AJ16 AJ12 AJ11 AJ7 AN33 AJ4 AK32 AK23 AK13 AK3 AL31 AL29 AL27 AL24 AL21 AN1 AL17 AL14 AL11 AL8 AL6 AL4 AM34 AM30 A33 B34 AM28 C31 C29 C27 D32 D30 D28 D25 E31 E26 F32 AM26 AP34 AP2 AD11 AD10 AD8 AD6 AD4 R7 T6 U7 W7 Y11 Y10 Y8 Y6 AD2 Y4 Y2 Y1 AA11 AA10 AA9 AA8 AA7 AA6 AA5 AD1 AA4 AA3 AA2 AA1 AB10 AB8 AB6 AB4 AB2 AC11 AE11 AC10 AC9 AC8 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AE9 AF10 P24 P22 P20 P18 P16 P14 P12 R25 A21 A19 A17 A15 A13 B22 B20 B18 B16 B14 B12 C21 C19 C17 C15 C13 D24 D22 D20 D18 D16 D14 D12 E23 E21 E19 E17 E15 E13 F24 F22 F20 F18 F16 F14 F12 G23 G21 G19 G17 G15 G13 H24 H22 H20 H18 H16 H14 H12 J25 J23 J21 J19 J17 J15 J13 J11 K26 K24 K22 K20 K18 K16 K14 K12 L25 L23 L21 L19 L17 L15 L13 L11 M26 M24 M22 M20 M18 M16 M14 M12 N25 N23 N21 N19 N17 N15 N13 N11 P26 R23 R21 AE15 R19 R17 R15 R13 R11 T26 T24 T22 T20 T18 AE13 T16 T14 T12 U25 U23 U21 U19 U17 U15 U13 AF26 U11 V26 V24 V22 V20 V18 V16 V14 V12 W25 AF24 W23 W21 W19 W17 W15 W13 W11 Y26 Y24 Y22 AF22 Y20 Y18 Y16 Y14 Y12 AA25 AA23 AA21 AA19 AA17 AF20 AA15 AA13 AB26 AB24 AB22 AB20 AB18 AB16 AB14 AB12 AF18 AC25 AC23 AC21 AC19 AC17 AC15 AC13 AD26 AD24 AD22 AF16 AD20 AD18 AD16 AD14 AD12 AE25 AE23 AE21 AE19 AE17 AF14 AF12 DRAWING GCPU VERSION 1 V_CS21 V_CS23 V_CS22 V_CS24 V_CS25 V_CS26 V_CS27 V_CS28 V_CS0 V_CS1 V_CS2 V_CS3 V_CS4 V_CS5 V_CS6 V_CS7 V_CS8 V_CS9 V_CS10 V_CS11 V_CS12 V_CS13 V_CS14 V_CS15 V_CS16 V_CS17 V_CS18 V_CS19 V_CS20 GCPU VERSION 1 V_MEM57 V_MEM58 V_MEM60 V_MEM59 V_MEM61 V_MEM62 V_MEM63 V_MEM65 V_MEM64 V_MEM67 V_MEM68 V_MEM66 V_MEM69 V_MEM70 V_MEM73 V_MEM72 V_MEM71 V_MEM74 V_MEM75 V_MEM76 V_MEM77 V_MEM78 V_MEM79 V_MEM80 V_MEM81 V_MEM83 V_MEM82 V_MEM86 V_MEM85 V_MEM84 V_MEM87 V_MEM88 V_MEM91 V_MEM90 V_MEM89 V_MEM92 V_MEM93 V_MEM94 V_MEM96 V_MEM95 V_MEM97 V_MEM98 V_MEM99 V_MEM101 V_MEM100 V_MEM102 V_MEM103 V_MEM104 V_MEM106 V_MEM105 V_MEM109 V_MEM107 V_MEM108 V_MEM111 V_MEM110 V_MEM0 V_MEM56 V_MEM1 V_MEM2 V_MEM3 V_MEM4 V_MEM5 V_MEM6 V_MEM7 V_MEM8 V_MEM9 V_MEM10 V_MEM11 V_MEM12 V_MEM13 V_MEM14 V_MEM15 V_MEM16 V_MEM17 V_MEM18 V_MEM19 V_MEM20 V_MEM21 V_MEM22 V_MEM23 V_MEM24 V_MEM25 V_MEM26 V_MEM27 V_MEM28 V_MEM29 V_MEM30 V_MEM31 V_MEM32 V_MEM33 V_MEM34 V_MEM35 V_MEM36 V_MEM37 V_MEM38 V_MEM39 V_MEM40 V_MEM41 V_MEM42 V_MEM43 V_MEM44 V_MEM45 V_MEM46 V_MEM47 V_MEM48 V_MEM49 V_MEM50 V_MEM51 V_MEM52 V_MEM53 V_MEM54 V_MEM55 GCPU VERSION 1 V_EDRAM44 V_EDRAM43 V_EDRAM42 V_EDRAM41 V_EDRAM47 V_EDRAM45 V_EDRAM46 V_EDRAM39 V_EDRAM38 V_EDRAM37 V_EDRAM36 V_EDRAM35 V_EDRAM34 V_EDRAM33 V_EDRAM32 V_EDRAM31 V_EDRAM30 V_EDRAM20 V_EDRAM19 V_EDRAM18 V_EDRAM17 V_EDRAM16 V_EDRAM15 V_EDRAM14 V_EDRAM13 V_EDRAM12 V_EDRAM11 V_EDRAM10 V_EDRAM9 V_EDRAM8 V_EDRAM29 V_EDRAM7 V_EDRAM28 V_EDRAM6 V_EDRAM27 V_EDRAM5 V_EDRAM26 V_EDRAM4 V_EDRAM25 V_EDRAM3 V_EDRAM24 V_EDRAM23 V_EDRAM2 V_EDRAM22 V_EDRAM1 V_EDRAM21 V_EDRAM0 V_EDRAM40 GCPU VERSION 1 VDD_CORE144 VDD_CORE145 VDD_CORE146 VDD_CORE147 VDD_CORE149 VDD_CORE148 VDD_CORE150 VDD_CORE151 VDD_CORE152 VDD_CORE154 VDD_CORE153 VDD_CORE155 VDD_CORE156 VDD_CORE157 VDD_CORE158 VDD_CORE159 VDD_CORE161 VDD_CORE160 VDD_CORE162 VDD_CORE163 VDD_CORE164 VDD_CORE165 VDD_CORE167 VDD_CORE166 VDD_CORE168 VDD_CORE169 VDD_CORE170 VDD_CORE172 VDD_CORE171 VDD_CORE174 VDD_CORE173 VDD_CORE175 VDD_CORE176 VDD_CORE177 VDD_CORE178 VDD_CORE179 VDD_CORE180 VDD_CORE182 VDD_CORE181 VDD_CORE183 VDD_CORE184 VDD_CORE185 VDD_CORE186 VDD_CORE187 VDD_CORE188 VDD_CORE189 VDD_CORE137 VDD_CORE136 VDD_CORE135 VDD_CORE134 VDD_CORE133 VDD_CORE132 VDD_CORE131 VDD_CORE130 VDD_CORE129 VDD_CORE128 VDD_CORE127 VDD_CORE126 VDD_CORE125 VDD_CORE124 VDD_CORE123 VDD_CORE122 VDD_CORE121 VDD_CORE120 VDD_CORE119 VDD_CORE118 VDD_CORE117 VDD_CORE116 VDD_CORE115 VDD_CORE114 VDD_CORE113 VDD_CORE112 VDD_CORE111 VDD_CORE110 VDD_CORE109 VDD_CORE108 VDD_CORE107 VDD_CORE106 VDD_CORE105 VDD_CORE104 VDD_CORE103 VDD_CORE102 VDD_CORE101 VDD_CORE100 VDD_CORE99 VDD_CORE98 VDD_CORE97 VDD_CORE143 VDD_CORE96 VDD_CORE142 VDD_CORE95 VDD_CORE141 VDD_CORE94 VDD_CORE140 VDD_CORE93 VDD_CORE139 VDD_CORE92 VDD_CORE138 GCPU VERSION 1 VDD_CORE0 VDD_CORE46 VDD_CORE1 VDD_CORE47 VDD_CORE2 VDD_CORE48 VDD_CORE3 VDD_CORE49 VDD_CORE4 VDD_CORE50 VDD_CORE5 VDD_CORE51 VDD_CORE52 VDD_CORE6 VDD_CORE53 VDD_CORE7 VDD_CORE54 VDD_CORE8 VDD_CORE55 VDD_CORE9 VDD_CORE10 VDD_CORE56 VDD_CORE11 VDD_CORE57 VDD_CORE12 VDD_CORE58 VDD_CORE13 VDD_CORE59 VDD_CORE14 VDD_CORE60 VDD_CORE15 VDD_CORE61 VDD_CORE16 VDD_CORE62 VDD_CORE17 VDD_CORE63 VDD_CORE18 VDD_CORE64 VDD_CORE19 VDD_CORE65 VDD_CORE20 VDD_CORE66 VDD_CORE21 VDD_CORE67 VDD_CORE22 VDD_CORE68 VDD_CORE23 VDD_CORE69 VDD_CORE24 VDD_CORE70 VDD_CORE25 VDD_CORE71 VDD_CORE26 VDD_CORE72 VDD_CORE27 VDD_CORE73 VDD_CORE28 VDD_CORE74 VDD_CORE29 VDD_CORE75 VDD_CORE30 VDD_CORE76 VDD_CORE31 VDD_CORE77 VDD_CORE32 VDD_CORE78 VDD_CORE33 VDD_CORE79 VDD_CORE34 VDD_CORE80 VDD_CORE35 VDD_CORE81 VDD_CORE36 VDD_CORE82 VDD_CORE37 VDD_CORE83 VDD_CORE38 VDD_CORE84 VDD_CORE39 VDD_CORE85 VDD_CORE40 VDD_CORE86 VDD_CORE41 VDD_CORE87 VDD_CORE42 VDD_CORE88 VDD_CORE43 VDD_CORE89 VDD_CORE44 VDD_CORE90 VDD_CORE45 VDD_CORE91 FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 8. [PAGE_TITLE=GCPU, POWER] GCPU, POWER CR-8 : @CORONA_LIB.CORONA(SCH_1):PAGE8 8/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:27 2011 X818336-001 BGA_2 13 OF 17 IC X818336-001 BGA_2 11 OF 17 IC X818336-001 12 OF 17 BGA_2 IC U5E1 U5E1 U5E1 A34 A22 A20 A18 A16 A14 A12 A10 B33 B21 B19 B17 B15 B13 B11 B7 C28 C25 C22 C20 C18 C16 C14 C12 C10 D31 D29 D27 D23 D21 D19 D17 D15 D13 D11 E32 E24 E22 E20 E18 E16 E14 E12 E10 E6 F31 F29 F27 F23 F21 F19 F17 F15 F13 F11 F9 F4 G32 G28 G24 G22 G20 G18 G16 G14 G12 G10 G8 G3 H31 H29 H27 H23 H21 H19 H17 H15 H13 H11 H9 H7 J31 J27 J24 J22 J20 J18 J16 J14 J12 J10 J8 J3 AC16 AC14 AC12 AD32 AD25 AD23 AD21 AD19 AD17 AD15 AM24 AD13 AD9 AD7 AD5 AD3 AE29 AE27 AE26 AE24 AE22 AM21 AE20 AE18 AE16 AE14 AE12 AE10 AE6 AE3 AF31 AF25 AM14 AF23 AF21 AF19 AF17 AF15 AF13 AF11 AF9 AF8 AF4 AM11 AG32 AG29 AG27 AG26 AG24 AG22 AG21 AG19 AG16 AG14 AM8 AG12 AG11 AG9 AG8 AG6 AG3 AH31 AH28 AH7 AH4 AM6 AJ32 AJ29 AJ27 AJ25 AJ20 AJ17 AJ15 AJ10 AJ8 AJ6 AM4 AJ3 AK31 AK18 AK4 AL32 AL30 AL28 AL26 AL22 AL19 AN34 AL16 AL12 AL9 AL7 AL5 AL3 Y3 AM33 AA32 AA27 AA26 AA24 AA22 AA20 AA18 AA16 AA14 AA12 AM31 AB25 AB23 AB21 AB19 AB17 AB15 AB13 AB11 AB9 AB7 AM29 AB5 AB3 AB1 AC31 AC27 AC26 AC24 AC22 AC20 AC18 AM27 AP33 AP1 K29 K25 K23 K21 K19 K17 K15 K13 K11 K9 K4 L32 L27 L26 L24 L22 L20 L18 L16 L14 L12 L10 L8 L3 M25 M23 M21 M19 M17 M15 M13 M11 M9 M4 N31 N27 N26 N24 N22 N20 N18 N16 N14 N12 N10 N8 N5 P32 P27 P25 P23 P21 P19 P17 P15 P13 P11 P9 P6 R29 R26 R24 R22 R20 R18 R16 R14 R12 R10 R8 T31 T27 T25 T23 T21 T19 T17 T15 T13 T11 T9 T7 T4 T3 U30 U27 U26 U24 U22 U20 U18 U16 U14 U12 U10 U8 V29 V25 V23 V21 V19 V17 V15 V13 V11 V9 V7 W31 W26 W24 W22 W20 W18 W16 W14 W12 W10 W8 W3 Y29 Y25 Y23 Y21 Y19 Y17 Y15 Y13 Y9 Y7 Y5 DRAWING GCPU VERSION 1 VSS354 VSS353 VSS352 VSS351 VSS349 VSS350 VSS348 VSS347 VSS346 VSS345 VSS344 VSS343 VSS341 VSS342 VSS340 VSS339 VSS338 VSS337 VSS336 VSS335 VSS334 VSS333 VSS331 VSS332 VSS330 VSS329 VSS328 VSS326 VSS327 VSS325 VSS323 VSS324 VSS322 VSS321 VSS320 VSS319 VSS318 VSS317 VSS316 VSS315 VSS314 VSS313 VSS312 VSS311 VSS310 VSS309 VSS308 VSS307 VSS306 VSS305 VSS304 VSS303 VSS302 VSS301 VSS300 VSS299 VSS298 VSS297 VSS296 VSS295 VSS294 VSS293 VSS292 VSS291 VSS290 VSS289 VSS288 VSS287 VSS286 VSS285 VSS284 VSS283 VSS282 VSS281 VSS280 VSS279 VSS278 VSS277 VSS276 VSS275 VSS274 VSS273 VSS272 VSS271 VSS270 VSS269 VSS268 VSS267 VSS266 VSS265 VSS264 VSS263 VSS261 GCPU VERSION 1 VSS65 VSS130 VSS64 VSS129 VSS63 VSS128 VSS62 VSS127 VSS61 VSS126 VSS60 VSS125 VSS59 VSS124 VSS58 VSS123 VSS57 VSS122 VSS56 VSS121 VSS55 VSS120 VSS54 VSS119 VSS53 VSS118 VSS52 VSS117 VSS51 VSS116 VSS50 VSS115 VSS49 VSS114 VSS48 VSS113 VSS47 VSS112 VSS46 VSS111 VSS45 VSS110 VSS44 VSS109 VSS43 VSS108 VSS42 VSS107 VSS41 VSS106 VSS40 VSS105 VSS39 VSS104 VSS38 VSS103 VSS37 VSS102 VSS36 VSS101 VSS35 VSS100 VSS99 VSS34 VSS98 VSS33 VSS97 VSS32 VSS96 VSS31 VSS95 VSS30 VSS94 VSS29 VSS93 VSS28 VSS92 VSS27 VSS91 VSS26 VSS90 VSS25 VSS89 VSS24 VSS88 VSS23 VSS87 VSS22 VSS86 VSS21 VSS85 VSS20 VSS84 VSS19 VSS83 VSS18 VSS82 VSS17 VSS81 VSS16 VSS80 VSS15 VSS79 VSS14 VSS78 VSS13 VSS77 VSS12 VSS76 VSS11 VSS75 VSS10 VSS9 VSS74 VSS8 VSS73 VSS72 VSS7 VSS71 VSS6 VSS70 VSS5 VSS69 VSS4 VSS68 VSS3 VSS67 VSS2 VSS66 VSS1 VSS0 GCPU VERSION 1 VSS260 VSS195 VSS259 VSS194 VSS258 VSS193 VSS257 VSS192 VSS256 VSS191 VSS255 VSS190 VSS254 VSS189 VSS253 VSS188 VSS252 VSS187 VSS251 VSS186 VSS250 VSS185 VSS249 VSS184 VSS248 VSS183 VSS247 VSS182 VSS246 VSS181 VSS245 VSS180 VSS244 VSS179 VSS243 VSS178 VSS242 VSS177 VSS241 VSS176 VSS240 VSS175 VSS239 VSS174 VSS238 VSS173 VSS237 VSS172 VSS236 VSS171 VSS235 VSS170 VSS234 VSS169 VSS233 VSS168 VSS232 VSS167 VSS231 VSS166 VSS230 VSS165 VSS229 VSS164 VSS228 VSS163 VSS227 VSS162 VSS226 VSS161 VSS225 VSS160 VSS224 VSS159 VSS223 VSS158 VSS222 VSS157 VSS221 VSS156 VSS220 VSS155 VSS219 VSS154 VSS218 VSS153 VSS217 VSS152 VSS216 VSS151 VSS215 VSS150 VSS214 VSS149 VSS213 VSS148 VSS212 VSS147 VSS211 VSS146 VSS210 VSS145 VSS209 VSS144 VSS208 VSS143 VSS207 VSS142 VSS206 VSS141 VSS205 VSS140 VSS204 VSS139 VSS203 VSS138 VSS202 VSS137 VSS201 VSS136 VSS200 VSS135 VSS199 VSS134 VSS198 VSS133 VSS197 VSS132 VSS196 VSS131 FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 9. [PAGE_TITLE=GCPU, DECOUPLING] GCPU, DECOUPLING CR-9 : @CORONA_LIB.CORONA(SCH_1):PAGE9 9/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:27 2011 10% 6.3 V X5R 4.7 UF 603 6.3 V X5R 10% 4.7 UF 603 4.7 UF 10% 6.3 V X5R 603 10% 6.3 V X5R 4.7 UF 603 6.3 V X5R 10% 4.7 UF 603 4.7 UF 6.3 V 10% X5R 603 V_CPUCORE 6.3 V 10% X5R 4.7 UF 603 6.3 V 10% X5R 4.7 UF 603 6.3 V X5R 10% 4.7 UF 603 6.3 V 10% X5R 4.7 UF 603 603 4.7 UF X5R 6.3 V 10% 10% X5R 4.7 UF 6.3 V 603 10% X5R 6.3 V 4.7 UF 603 4.7 UF X5R 6.3 V 10% 603 X5R 10% 4.7 UF 6.3 V 603 10% 4.7 UF 6.3 V X5R 603 10% X5R 4.7 UF 6.3 V 603 6.3 V 10% 4.7 UF X5R 603 6.3 V X5R 10% 4.7 UF 603 6.3 V X5R 10% 4.7 UF 603 10% X5R 6.3 V 4.7 UF 603 6.3 V X5R 10% 4.7 UF 603 4.7 UF 6.3 V X5R 10% 603 10% 603 4.7 UF 6.3 V X5R X5R 10% 4.7 UF 6.3 V 603 10% X5R 4.7 UF 6.3 V 603 10% X5R 4.7 UF 6.3 V 603 603 X5R 4.7 UF 10% 6.3 V 603 10% 4.7 UF 6.3 V X5R 603 X5R 6.3 V 10% 4.7 UF 603 4.7 UF X5R 6.3 V 10% 10% X5R 4.7 UF 6.3 V 603 603 X5R 4.7 UF 6.3 V 10% 603 X5R 4.7 UF 10% 6.3 V 603 X5R 4.7 UF 10% 6.3 V 603 4.7 UF X5R 10% 6.3 V 603 4.7 UF 6.3 V X5R 10% 603 6.3 V X5R 4.7 UF 10% 4.7 UF X5R 6.3 V 10% 603 X5R 6.3 V 4.7 UF 10% 603 4.7 UF X5R 6.3 V 10% 603 X5R 10% 4.7 UF 6.3 V 603 4.7 UF X5R 6.3 V 10% 603 402 X5R 0.1 UF 6.3 V 10% 402 X5R 0.1 UF 6.3 V 10% X5R 402 6.3 V 10% 0.1 UF X5R 402 0.1 UF 6.3 V 10% X5R 402 6.3 V 0.1 UF 10% X5R 402 6.3 V 10% 0.1 UF 10% X5R 402 6.3 V 0.1 UF 6.3 V 402 X5R 0.1 UF 10% 603 X5R 10% 4.7 UF 6.3 V 0.1 UF 402 X5R 6.3 V 10% X5R 402 6.3 V 0.1 UF 10% V_CPUEDRAM 402 X5R 0.1 UF 6.3 V 10% 0.1 UF 10% X5R 402 6.3 V 0.1 UF X5R 402 10% 6.3 V 0.1 UF 10% 402 X5R 6.3 V 402 X5R 6.3 V 0.1 UF 10% 0.1 UF X5R 10% 402 6.3 V V_CPUVCS 10% 6.3 V X5R 4.7 UF 603 6.3 V 10% X5R 4.7 UF 603 6.3 V X5R 10% 4.7 UF 603 6.3 V X5R 10% 4.7 UF 603 10% 4.7 UF 6.3 V X5R 603 6.3 V X5R 10% 4.7 UF 603 6.3 V 10% X5R 4.7 UF 603 4.7 UF 6.3 V 10% X5R 603 10% X5R 4.7 UF 6.3 V 603 X5R 10% 4.7 UF 6.3 V 603 10% X5R 4.7 UF 6.3 V 603 C6T23 C6T22 C5T33 C4T4 C4T3 C5E9 C5E8 C5E6 C5E5 C5T35 C5E7 C5T34 C5T43 C5D1 C5R4 C5D4 C5R1 C5T21 C5T25 C5T20 C5T23 C5T22 C5T27 C5T31 C5T24 C5T32 C5T26 C5T1 C5R50 C5T7 C5R43 C5R58 C5R35 C5R2 C5R3 C5R5 C6R5 C6D1 C5R13 C6D2 C6D6 C5D11 C5D10 C6R3 C6R2 C5R10 C5D12 C5R15 C6R4 C5R16 C6R7 C6R1 C5D3 C5R7 C5R12 C5R18 C5D9 C5D5 C5R6 C5D8 C5D2 C5D14 C5D13 C6D3 C5D6 C5D7 C5R9 C6D5 C6D4 C6R6 C5R8 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 DRAWING FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 10. [PAGE_TITLE=GCPU, DECOUPLING] GCPU, DECOUPLING CR-10 : @CORONA_LIB.CORONA(SCH_1):PAGE10 10/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:27 2011 10% 0.1 UF 6.3 V 402 X5R 6.3 V 10% 0.1 UF X5R 402 6.3 V 10% 0.1 UF X5R 402 6.3 V 10% 0.1 UF X5R 402 6.3 V 10% X5R 402 0.1 UF 6.3 V 10% 0.1 UF 402 X5R 402 6.3 V 10% 0.1 UF X5R 10% 6.3 V 0.1 UF X5R 402 6.3 V 10% X5R 402 0.1 UF 6.3 V X5R 10% 402 0.1 UF 10% 6.3 V X5R 402 0.1 UF 10% 0.1 UF 6.3 V X5R 402 6.3 V 10% 0.1 UF 402 X5R 6.3 V 10% 0.1 UF X5R 402 6.3 V 10% 0.1 UF X5R 402 6.3 V 10% X5R 402 0.1 UF 6.3 V 10% 0.1 UF X5R 402 V_CPUCORE 6.3 V 10% 402 X5R 0.1 UF 10% 6.3 V X5R 402 0.1 UF 10% 0.1 UF 6.3 V X5R 402 0.1 UF 10% 6.3 V X5R 402 6.3 V 10% 402 X5R 0.1 UF 10% 6.3 V 0.1 UF 402 X5R 10% 6.3 V 0.1 UF X5R 402 6.3 V 10% 0.1 UF X5R 402 10% 0.1 UF 6.3 V 402 X5R 10% 6.3 V 0.1 UF X5R 402 10% 6.3 V 0.1 UF X5R 402 10% 0.1 UF 6.3 V 402 X5R 10% 6.3 V 0.1 UF X5R 402 10% 6.3 V 0.1 UF 402 X5R 10% 0.1 UF 6.3 V X5R 402 10% 0.1 UF 6.3 V X5R 402 6.3 V 10% 0.1 UF X5R 402 10% 6.3 V 0.1 UF X5R 402 6.3 V 10% 0.1 UF X5R 402 0.1 UF 10% 6.3 V 402 X5R 6.3 V 10% X5R 402 0.1 UF 10% 6.3 V 0.1 UF X5R 402 6.3 V 10% 0.1 UF 402 X5R 10% 6.3 V 0.1 UF X5R 402 10% 0.1 UF 6.3 V X5R 402 6.3 V 10% X5R 402 0.1 UF 10% 6.3 V 0.1 UF X5R 402 6.3 V 10% X5R 402 0.1 UF 6.3 V 10% 402 X5R 0.1 UF 10% 0.1 UF 6.3 V X5R 402 6.3 V 10% 402 X5R 0.1 UF 10% 0.1 UF 6.3 V 402 X5R 6.3 V 10% 0.1 UF X5R 402 C5R59 C6T7 C5R33 C5R36 C6T14 C5R45 C5R38 C6R28 C6T6 C5R32 C5R40 C5R39 C6T20 C5R61 C5R60 C5R46 C5R57 C6R37 C6R25 C5T12 C5R26 C6T11 C6R20 C6R18 C6R17 C6R21 C6T8 C6R45 C5R51 C5R55 C5R62 C6R33 C5R37 C5R28 C6R42 C6T12 C6R15 C5T11 C6R44 C5R27 C6R43 C6R38 C6R31 C5T8 C5T10 C5R63 C5R49 C5T17 C6R36 C5R64 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 DRAWING FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 11. [PAGE_TITLE=GCPU, DECOUPLING] GCPU, DECOUPLING CR-11 : @CORONA_LIB.CORONA(SCH_1):PAGE11 11/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:27 2011 6.3 V 10% X5R 0.1 UF 402 6.3 V 10% 402 X5R 0.1 UF 10% 6.3 V 0.1 UF 402 X5R 10% 6.3 V X5R 402 0.1 UF 6.3 V 0.1 UF 10% X5R 402 10% 6.3 V 402 X5R 0.1 UF 10% 6.3 V X5R 402 0.1 UF 6.3 V X5R 10% 0.1 UF 402 10% 0.1 UF 6.3 V X5R 402 10% 6.3 V 402 X5R 0.1 UF 10% 6.3 V 402 X5R 0.1 UF 6.3 V X5R 0.1 UF 402 10% 10% 6.3 V 402 X5R 0.1 UF 10% 6.3 V 0.1 UF 402 X5R 10% 6.3 V 0.1 UF X5R 402 6.3 V 10% 402 X5R 0.1 UF 6.3 V 10% 0.1 UF 402 X5R 10% 6.3 V X5R 402 0.1 UF 6.3 V 10% 0.1 UF 402 X5R 6.3 V 10% X5R 402 0.1 UF 10% 6.3 V 0.1 UF X5R 402 10% 0.1 UF 6.3 V X5R 402 10% 6.3 V 0.1 UF X5R 402 10% 0.1 UF 6.3 V 402 X5R 6.3 V 10% X5R 402 0.1 UF 10% 6.3 V 402 X5R 0.1 UF 10% 6.3 V X5R 402 0.1 UF X5R 10% 6.3 V 402 0.1 UF 10% 6.3 V 402 X5R 0.1 UF 6.3 V 10% X5R 402 0.1 UF 10% 6.3 V 402 X5R 0.1 UF 10% 6.3 V X5R 402 0.1 UF 10% 6.3 V X5R 402 0.1 UF 6.3 V 10% X5R 402 0.1 UF 10% 0.1 UF 6.3 V X5R 402 6.3 V 10% X5R 402 0.1 UF 10% 6.3 V 402 X5R 0.1 UF 6.3 V 10% 0.1 UF 402 X5R 6.3 V 10% 0.1 UF 402 X5R 6.3 V 10% X5R 402 0.1 UF 10% 6.3 V 0.1 UF X5R 402 6.3 V 402 X5R 10% 0.1 UF 6.3 V 10% 402 X5R 0.1 UF 10% 0.1 UF 6.3 V 402 X5R 6.3 V 10% 402 X5R 0.1 UF 10% 6.3 V 402 X5R 0.1 UF 6.3 V 402 10% X5R 0.1 UF 6.3 V 10% X5R 402 0.1 UF 402 6.3 V 10% X5R 0.1 UF 6.3 V 10% 402 X5R 0.1 UF 10% 0.1 UF 6.3 V X5R 402 6.3 V 402 X5R 10% 0.1 UF 6.3 V 10% 402 X5R 0.1 UF 10% 6.3 V 402 X5R 0.1 UF 6.3 V 10% 402 X5R 0.1 UF 10% 6.3 V 0.1 UF X5R 402 10% 6.3 V 0.1 UF X5R 402 V_CPUCORE 10% 6.3 V X5R 0.1 UF 402 10% 6.3 V X5R 402 0.1 UF C5R23 C5R22 C5R19 C5R20 C6R10 C6R9 C6T18 C5T19 C6T15 C5R25 C5R29 C6T4 C6R29 C6R32 C6R30 C5T18 C5R56 C5R24 C5T29 C5T30 C6R26 C5R48 C5R47 C6T2 C6R24 C5R44 C6R22 C6R35 C5R41 C5T28 C5T15 C6R41 C6R40 C6T24 C6T17 C6R12 C6T25 C6T19 C5T16 C6T13 C5T5 C6R14 C5R34 C6R13 C5T3 C5T2 C6T16 C5R53 C6R8 C6T3 C6R39 C5R52 C5R30 C5R21 C6T5 C6T9 C5T14 C6R19 C6R34 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 DRAWING FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 12. N: GPU VREF SET INTERNALLY BY DEFAULT. EXTERNAL RESISTOR DIVIDER USED TO MANUALLY SET GPU VREF VOLTAGE. MEMORY CONTROLLER B, DECOUPLING GPU, MEMORY CONTROLLER 0 PARTITION A & B NEED NEW VREF RESISTORS WITH MEM TEAM FOR USAGE. 73% 1.47KOHM 72% 1.40KOHM TO CHANGE GPU VREF, CHANGE THESE RESISTORS TO MATCH THE TABLE THESE ARE THE GPU VREFS NEEDED FOR VARIOUS MEMORIES. CONSULT R6T4, R6T1, R5T3, R5T4 MEM VREF RESISTOR VALUE 70% 1.27KOHM 74% 1.54KOHM [PAGE_TITLE=GPU, MEMORY CONTROLLER A + B] MEMORY CONTROLLER A, DECOUPLING CR-12 : @CORONA_LIB.CORONA(SCH_1):PAGE12 12/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:19 2011 1% EMPTY 402 549 OHM EMPTY 402 1.27 KOHM 1% V_MEM 603 X5R 6.3 V 10% 4.7 UF V_MEM 0.1 UF 6.3 V 402 X5R 10% 6.3 V X5R 0.1 UF 10% 402 402 6.3 V 0.1 UF X5R 10% 0.1 UF 6.3 V X5R 10% 402 0.1 UF 6.3 V 10% X5R 402 0 1 2 2 0 1% CH 402 4.75 KOHM 1 CH 1% 402 4.75 KOHM 1% 4.75 KOHM 402 CH 4.75 KOHM CH 402 1% 3 BGA_2 X818336-001 3 OF 17 IC 4 OF 17 BGA_2 X818336-001 IC 4 5 7 6 9 8 11 10 402 1.27 KOHM 1% EMPTY 402 549 OHM 1% EMPTY V_MEM V_MEM 0.1 UF 402 6.3 V 10% X5R 402 X5R 6.3 V 10% 0.1 UF 0.1 UF 6.3 V 10% 402 X5R 0.1 UF 6.3 V X5R 10% 402 0 1 2 1 0 2 3 4 5 6 7 9 8 11 10 R6R2 R6R1 R6T7 R6T8 U5E1 U5E1 R6T4 R6T5 C6T27 C6T10 C6T32 C6T29 R6T2 R6T1 C6T30 C6R27 C6R11 C6R16 C6R23 C6R46 14 14 15 16 17 14 12 14 15 12 14 15 12 14 15 12 14 15 12 16 17 12 16 17 12 16 17 12 16 17 16 16 17 16 17 16 17 15 14 15 14 15 16 17 16 17 16 16 17 14 15 14 15 14 15 17 14 15 14 15 14 15 14 15 14 15 14 15 14 15 14 15 14 15 14 15 14 15 14 15 14 15 14 15 14 15 14 15 14 15 14 15 14 15 14 15 12 14 15 14 15 14 15 14 15 14 15 14 15 14 15 14 15 12 14 15 14 15 14 15 14 15 14 15 14 15 14 15 12 14 15 14 15 14 15 12 14 15 14 15 14 15 14 15 14 15 14 15 12 16 17 16 17 16 17 16 17 16 17 16 17 12 16 17 16 17 16 17 16 17 12 16 17 16 17 16 17 16 17 16 17 16 17 16 17 16 17 16 17 16 17 16 17 16 17 16 17 16 17 16 17 16 17 16 17 16 17 16 17 16 17 16 17 16 17 16 17 16 17 16 17 16 17 16 17 16 17 12 16 17 16 17 16 17 16 17 16 17 14 15 16 17 14 15 16 17 MA_CLK0_DN MA_CLK0_DP MA_CLK1_DN MB_DQ20 MB_VREF0 MA_CS0_N MA_WDQS1 MA_DQ12 MA_WDQS0 MA_DQ4 MB_DQ12 MB_WDQS0 MB_WDQS1 MB_DQ4 MB_CS0_N MB_CS1_N MB_RAS_N MB_CAS_N MA_CLK1_DP MA_CAS_N MA_CS1_N MA_VREF0 MB_WE_N MB_CKE MB_CLK0_DN MB_CLK0_DP MB_CLK1_DP MA_WE_N MA_CKE MA_RAS_N MB_CLK1_DN MA_DQ29 MA_WDQS3 MA_RDQS3 MA_DM3 MA_DQ31 MA_DQ30 MA_DQ28 MA_DQ27 MA_DQ26 MA_DQ25 MA_DQ24 MA_DQ23 MA_DQ22 MA_DQ21 MA_DQ19 MA_DQ20 MA_DQ18 MA_WDQS2 MA_RDQS2 MA_DM2 MA_WDQS1 MA_RDQS1 MA_DM1 MA_DQ17 MA_DQ16 MA_DQ15 MA_DQ14 MA_DQ13 MA_DQ12 MA_DQ11 MA_DQ10 MA_DQ9 MA_DQ8 MA_DQ7 MA_DQ6 MA_WDQS0 MA_RDQS0 MA_DM0 MA_DQ4 MA_DQ5 MA_DQ3 MA_DQ2 MA_DQ1 MA_DQ0 MB_WDQS1 MB_RDQS1 MB_DM1 MB_DQ7 MB_DQ6 MB_DQ5 MB_DQ4 MB_DQ3 MB_DQ2 MB_DQ1 MB_WDQS0 MB_RDQS0 MB_DM0 MB_DQ31 MB_DQ30 MB_DQ28 MB_DQ29 MB_DQ27 MB_DQ26 MB_DQ25 MB_DQ24 MB_RDQS3 MB_DQ22 MB_DQ23 MB_DQ21 MB_DQ19 MB_WDQS3 MB_DM3 MB_DQ17 MB_DQ18 MB_DQ16 MB_RDQS2 MB_DQ15 MB_DQ14 MB_DQ13 MB_WDQS2 MB_DM2 MB_DQ11 MB_DQ12 MB_DQ10 MB_DQ9 MB_DQ8 MB_DQ0 MA_BA<2..0> MB_BA<2..0> MA_A<11..0> MB_A<11..0> 2 1 2 1 2 1 2 1 B26 E34 N33 E30 N32 P34 J33 L34 G33 L29 D26 G30 F30 K30 P28 K28 P30 H33 G34 M28 H34 F34 K31 D34 K32 C34 M32 M34 M31 M33 N30 K33 N34 K34 P33 J28 C33 J30 D33 F33 E33 M29 N28 J34 L33 H30 L30 A28 A26 B32 A32 B31 A31 A27 C26 E28 B28 E27 E29 B30 B29 A30 C32 A29 E25 G26 C30 F25 A25 B25 F26 AF29 R34 AA34 T30 AC32 AB34 U32 Y31 V30 AA29 AH30 U29 U28 Y30 AD28 Y28 AD30 T34 T33 AB28 U31 R33 U33 R32 V33 R31 Y34 Y33 Y32 AA33 AC30 W33 AB31 V34 AB32 W28 R30 W30 R28 V28 T29 AB29 AC28 U34 W34 V32 AA30 AF30 AE31 AE28 AE30 AC33 AC34 AJ33 AG30 AE34 AE32 AK34 AG34 AD33 AF34 AE33 AD34 AF33 AG33 AH33 AL33 AH34 AL34 AK33 AJ34 2 1 2 1 2 1 2 1 DRAWING OUT OUT IN BI OUT BI BI BI BI BI BI BI OUT IN OUT BI BI BI BI BI OUT BI BI BI OUT OUT IN BI BI BI BI BI BI OUT OUT OUT BI BI OUT IN OUT BI OUT BI BI BI BI BI BI BI OUT OUT BI OUT OUT BI BI OUT OUT BI GCPU VERSION 1 MB_VREF0 MB_DM0 MB_RDQS0 MB_WDQS0 MB_DQ0 MB_DQ1 MB_DQ2 MB_CS0_N* MB_DQ3 MB_CS1_N* MB_DQ4 MB_DQ5 MB_RAS_N* MB_CAS_N* MB_DQ6 MB_DQ7 MB_WE_N* MB_CKE MB_DM1 MB_BA0 MB_RDQS1 MB_BA1 MB_WDQS1 MB_BA2 MB_DQ8 MB_DQ9 MB_A0 MB_DQ10 MB_A1 MB_DQ11 MB_A2 MB_DQ12 MB_A3 MB_DQ13 MB_A4 MB_DQ14 MB_A5 MB_DQ15 MB_A6 MB_A7 MB_DM2 MB_A8 MB_RDQS2 MB_A9 MB_WDQS2 MB_A10 MB_DQ16 MB_A11 MB_DQ17 MB_A12 MB_DQ18 MB_DQ19 MB_CLK0_DN MB_DQ20 MB_CLK0_DP MB_DQ21 MB_CLK1_DN MB_DQ22 MB_CLK1_DP MB_DQ23 MB_DM3 MB_RDQS3 MB_WDQS3 MB_DQ24 MB_DQ25 MB_DQ26 MB_DQ27 MB_DQ28 MB_DQ29 MB_DQ30 MB_DQ31 GCPU VERSION 1 MA_VREF0 MA_DM0 MA_RDQS0 MA_WDQS0 MA_DQ0 MA_DQ1 MA_DQ2 MA_CS0_N* MA_DQ3 MA_CS1_N* MA_DQ4 MA_DQ5 MA_RAS_N* MA_CAS_N* MA_DQ6 MA_DQ7 MA_WE_N* MA_CKE MA_DM1 MA_BA0 MA_RDQS1 MA_BA1 MA_WDQS1 MA_BA2 MA_DQ8 MA_DQ9 MA_A0 MA_DQ10 MA_A1 MA_DQ11 MA_A2 MA_DQ12 MA_A3 MA_DQ13 MA_A4 MA_DQ14 MA_A5 MA_DQ15 MA_A6 MA_A7 MA_DM2 MA_A8 MA_RDQS2 MA_A9 MA_WDQS2 MA_A10 MA_DQ16 MA_A11 MA_DQ17 MA_A12 MA_DQ18 MA_DQ19 MA_CLK0_DN MA_DQ20 MA_CLK0_DP MA_DQ21 MA_CLK1_DN MA_DQ22 MA_CLK1_DP MA_DQ23 MA_DM3 MA_RDQS3 MA_WDQS3 MA_DQ24 MA_DQ25 MA_DQ26 MA_DQ27 MA_DQ28 MA_DQ29 MA_DQ30 MA_DQ31 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IN BI OUT BI BI BI BI BI BI BI OUT IN OUT BI BI BI BI BI BI BI BI OUT OUT IN BI BI BI BI BI BI BI BI OUT IN BI OUT BI BI BI BI BI BI BI OUT OUT OUT FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 13. MEMORY CONTROLLER D, DECOUPLING MEMORY CONTROLLER C, DECOUPLING GPU, MEMORY CONTROLLER 1 PARTITION C & D GPU MEM VREF RESISTOR VALUE R6T4, R6T1, R5T3, R5T4 NEED TO VREF RESISTOR VALUES 74% 1.54KOHM 73% 1.47KOHM 72% 1.40KOHM WITH MEM TEAM FOR USAGE. 70% 1.27KOHM [PAGE_TITLE=[GPU, MEMORY CONTROLLER C + D] TO CHANGE GPU VREF, CHANGE THESE RESISTORS TO MATCH THE TABLE THESE ARE THE GPU VREFS NEEDED FOR VARIOUS MEMORIES. CONSULT N: GPU VREF SET INTERNALLY BY DEFAULT. EXTERNAL RESISTOR DIVIDER USED TO MANUALLY SET GPU VREF VOLTAGE. CR-13 : @CORONA_LIB.CORONA(SCH_1):PAGE13 13/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:19 2011 1% 1.27 KOHM EMPTY 402 549 OHM 1% EMPTY 402 11 V_MEM 11 402 X5R 6.3 V 10% 0.1 UF 6.3 V 10% X5R 402 0.1 UF X5R 402 10% 6.3 V 0.1 UF 6.3 V 10% 402 X5R 0.1 UF 10% 6.3 V X5R 402 0.1 UF 402 X5R 6.3 V 10% 0.1 UF X5R 402 6.3 V 10% 0.1 UF 402 X5R 6.3 V 10% 0.1 UF V_MEM 1 0 0 2 1 402 CH 1% 4.75 KOHM 2 402 4.75 KOHM CH 1% 4.75 KOHM 402 CH 1% 5 X818336-001 BGA_2 1 OF 17 IC IC BGA_2 X818336-001 2 OF 17 3 4 7 1% EMPTY 402 1.27 KOHM 1% 549 OHM 402 EMPTY 6 9 10 V_MEM 8 6.3 V 10% X5R 402 0.1 UF 10% 6.3 V X5R 402 0.1 UF 603 6.3 V X5R 10% 4.7 UF 402 X5R 6.3 V 0.1 UF 10% 402 X5R 6.3 V 10% 0.1 UF 6.3 V X5R 402 10% 0.1 UF 402 X5R 0.1 UF 6.3 V 10% 6.3 V 10% X5R 402 0.1 UF 10% 402 X5R 0.1 UF 6.3 V V_MEM 1 0 2 0 1 2 5 4 3 7 6 9 10 8 R6T9 R5T7 R5T6 U5E1 U5E1 R5T3 R5T2 C5T50 C5T46 C5U2 C5T37 C6T33 C5T47 C5T41 C6T28 C5T49 R5T4 R5T5 C6T26 C5T42 C5T45 C5T48 C5T39 C5T44 C6T31 C5T38 18 18 19 19 18 19 18 19 18 19 18 19 18 19 18 13 20 21 13 20 21 13 18 19 13 18 19 13 18 19 20 20 21 20 21 20 21 20 21 20 21 21 20 20 21 13 18 19 18 19 18 19 13 18 19 18 19 18 19 18 19 13 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 18 19 13 18 19 18 19 18 19 18 19 18 19 13 18 19 18 19 18 19 18 19 18 19 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 13 20 21 20 21 20 21 20 21 20 21 13 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 20 21 18 19 18 19 MC_CLK0_DN MC_CLK0_DP MC_CLK1_DN MC_CLK1_DP MC_CKE MC_WE_N MC_CAS_N MC_RAS_N MC_CS1_N MC_CS0_N MD_DQ12 MD_WDQS1 MC_WDQS1 MC_DQ4 MC_WDQS0 MD_VREF0 MD_CLK0_DN MD_CAS_N MD_CKE MD_WE_N MD_CS1_N MD_CS0_N MD_CLK1_DP MD_CLK1_DN MD_CLK0_DP MD_RAS_N MC_VREF0 MC_DQ12 MC_DQ6 MC_DQ5 MC_DQ4 MC_DQ2 MC_DQ1 MC_DQ0 MC_WDQS0 MC_RDQS0 MC_DM0 MC_DQ31 MC_DQ30 MC_DQ29 MC_DQ28 MC_DQ26 MC_DQ27 MC_DQ25 MC_DQ24 MC_WDQS3 MC_RDQS3 MC_DM3 MC_DQ23 MC_DQ22 MC_DQ20 MC_DQ21 MC_DQ19 MC_DQ18 MC_DQ17 MC_DQ16 MC_RDQS2 MC_WDQS2 MC_DM2 MC_DQ14 MC_DQ15 MC_DQ13 MC_DQ12 MC_DQ11 MC_DQ8 MC_DQ9 MC_DQ10 MC_WDQS1 MC_DM1 MC_RDQS1 MC_DQ7 MC_DQ3 MD_DQ0 MD_WDQS0 MD_RDQS0 MD_DM0 MD_DQ30 MD_DQ31 MD_DQ29 MD_DQ28 MD_DQ27 MD_DQ25 MD_DQ26 MD_DQ24 MD_WDQS3 MD_RDQS3 MD_DM3 MD_DQ23 MD_DQ22 MD_DQ21 MD_DQ20 MD_DQ19 MD_DQ18 MD_DQ17 MD_DQ16 MD_WDQS2 MD_RDQS2 MD_DM2 MD_DQ15 MD_DQ13 MD_DQ14 MD_DQ12 MD_DQ11 MD_DQ10 MD_DQ9 MD_DQ8 MD_WDQS1 MD_RDQS1 MD_DM1 MD_DQ7 MD_DQ6 MD_DQ5 MD_DQ4 MD_DQ3 MD_DQ2 MD_DQ1 MD_BA<2..0> MD_A<11..0> MC_BA<2..0> MC_A<11..0> 2 1 2 1 2 1 AP28 AN24 AM18 AH22 AH15 AN17 AN23 AP20 AK20 AK17 AP31 AH21 AM22 AH18 AJ14 AJ18 AK14 AM23 AL23 AM17 AP23 AP24 AP22 AN25 AN21 AP25 AN19 AP19 AN20 AL18 AK15 AL20 AP18 AP21 AN18 AJ19 AH23 AK19 AJ23 AK21 AK22 AK16 AH16 AN22 AM20 AH20 AH17 AK28 AP27 AJ24 AK24 AL25 AM25 AP30 AP29 AK27 AN28 AK29 AK26 AK25 AN26 AH26 AH25 AN27 AP32 AN29 AK30 AN31 AN32 AM32 AN30 AH5 AP16 AP10 AH12 AN4 AE5 AN14 AP12 AK10 AK7 AF5 AH11 AM12 AN8 AN2 AK8 AN3 AP15 AM15 AN6 AN15 AL15 AL13 AN16 AM13 AP17 AP11 AL10 AN11 AM10 AK5 AN13 AN10 AP13 AN9 AJ9 AJ13 AK9 AH13 AK11 AK12 AK6 AN5 AP14 AN12 AH10 AN7 AJ5 AM2 AP9 AP8 AP6 AP5 AG1 AG5 AL2 AM1 AF2 AJ2 AP4 AK1 AL1 AP3 AK2 AJ1 AH2 AE1 AH1 AE2 AF1 AG2 2 1 1 2 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 DRAWING OUT IN OUT BI BI OUT BI BI BI BI BI BI OUT OUT IN BI BI BI BI BI BI BI BI OUT IN OUT BI BI OUT OUT OUT OUT OUT BI BI BI BI BI BI OUT IN OUT OUT BI BI BI BI BI BI BI BI OUT OUT OUT BI OUT OUT BI BI GCPU VERSION 1 MD_DM2 MD_DQ15 MD_DQ13 MD_DQ12 MD_A4 MD_A5 MD_WDQS2 MD_WDQS1 MD_RDQS1 MD_DM1 MD_A3 MD_A2 MD_A1 MD_A0 MD_BA2 MD_BA1 MD_BA0 MD_DQ29 MD_VREF0 MD_DM0 MD_RDQS0 MD_WDQS0 MD_DQ0 MD_DQ1 MD_DQ2 MD_CS0_N* MD_DQ3 MD_CS1_N* MD_DQ4 MD_DQ5 MD_RAS_N* MD_DQ6 MD_DQ7 MD_WE_N* MD_CKE MD_DQ8 MD_DQ9 MD_DQ10 MD_DQ11 MD_DQ14 MD_A6 MD_A7 MD_A8 MD_RDQS2 MD_A9 MD_A10 MD_DQ16 MD_A11 MD_DQ17 MD_A12 MD_DQ18 MD_DQ19 MD_CLK0_DN MD_DQ20 MD_CLK0_DP MD_DQ21 MD_DQ22 MD_DQ23 MD_RDQS3 MD_WDQS3 MD_DQ24 MD_DQ25 MD_DQ26 MD_DQ27 MD_DQ28 MD_DQ30 MD_DQ31 MD_DM3 MD_CLK1_DN MD_CLK1_DP MD_CAS_N* GCPU VERSION 1 MC_VREF0 MC_DM0 MC_RDQS0 MC_WDQS0 MC_DQ0 MC_DQ1 MC_DQ2 MC_CS0_N* MC_DQ3 MC_CS1_N* MC_DQ4 MC_DQ5 MC_RAS_N* MC_CAS_N* MC_DQ6 MC_DQ7 MC_WE_N* MC_CKE MC_DM1 MC_BA0 MC_RDQS1 MC_BA1 MC_WDQS1 MC_BA2 MC_DQ8 MC_DQ9 MC_A0 MC_DQ10 MC_A1 MC_DQ11 MC_A2 MC_DQ12 MC_A3 MC_DQ13 MC_A4 MC_DQ14 MC_A5 MC_DQ15 MC_A6 MC_A7 MC_DM2 MC_A8 MC_RDQS2 MC_A9 MC_WDQS2 MC_A10 MC_DQ16 MC_A11 MC_DQ17 MC_A12 MC_DQ18 MC_DQ19 MC_CLK0_DN MC_DQ20 MC_CLK0_DP MC_DQ21 MC_CLK1_DN MC_DQ22 MC_CLK1_DP MC_DQ23 MC_DM3 MC_RDQS3 MC_WDQS3 MC_DQ24 MC_DQ25 MC_DQ26 MC_DQ27 MC_DQ28 MC_DQ29 MC_DQ30 MC_DQ31 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IN BI BI BI BI OUT OUT BI BI BI BI BI BI BI IN OUT OUT BI BI BI BI BI IN BI OUT OUT BI BI BI BI BI BI IN BI OUT OUT BI BI BI BI BI BI BI BI OUT OUT FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 14. [PAGE_TITLE=MEMORY PARTITION A, TOP] WITH MEM TEAM FOR USAGE. FOR VARIOUS MEMORIES. CONSULT THESE ARE THE MEM VREFS NEEDED 72% 1.40KOHM 69% 1.21KOHM R7T4, R7E7, R7R4, R7D5, R5U4, R5F2, R6U4, R6F2 MEMORY PARTITION A, TOP PARTITION A DECOUPLING MEMORY A, TOP, DECOUPLING MEM VREF RESISTOR VALUE 70% 1.27KOHM MX_CS1_N CONNECTED TO J3 TO SUPPORT 1G RAM CONFIGS. CHIP SELECT = 0, MIRROR FUNCTION = 0 TO CHANGE MEM VREF, CHANGE THESE RESISTORS TO MATCH THE TABLE CR-14 : @CORONA_LIB.CORONA(SCH_1):PAGE14 14/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:21 2011 402 CH 1% 60.4 OHM V_MEM 402 CH 60.4 OHM 1% 603 10% 4.7 UF 6.3 V X5R V_MEM V_MEM 402 X5R 10% 6.3 V 0.1 UF 6.3 V 10% X5R 402 0.1 UF X802980-019 IC 6.3 V X5R 402 10% 0.1 UF 6.3 V 10% X5R 402 0.1 UF 402 X5R 10% 6.3 V 0.1 UF 6.3 V 10% X5R 402 0.1 UF 402 X5R 10% 6.3 V 0.1 UF 6.3 V 10% X5R 402 0.1 UF V_MEM 1% 402 CH 1.27 KOHM 6.3 V 402 X5R 10% 0.1 UF CH 549 OHM 1% 402 V_MEM 1 0 IC X802980-019 2 0 2 1 4 3 5 7 6 9 8 10 11 CH 402 243 OHM 1% R7T4 C7T7 R7T5 U7E1 R7E8 R7E5 R7E4 C7E8 C7E14 C7E11 U7E1 C7E6 C7E5 C7E13 C7E10 C7E4 C7E7 12 12 15 12 15 12 15 12 15 12 15 12 15 12 12 12 15 12 15 4 12 15 12 15 12 15 12 15 14 15 12 15 12 15 12 12 15 12 12 15 12 15 14 12 15 12 15 12 12 15 12 15 12 15 12 15 12 15 12 15 12 15 12 15 12 12 15 12 15 12 15 12 12 15 12 15 12 15 12 12 12 15 12 15 12 15 4 4 12 12 12 15 12 12 12 12 12 MA_CKE MA_DQ12 MA_DQ11 MA_DQ10 MA_DQ9 MA_DQ8 MA_WDQS1 MA_RDQS1 MA_DM1 MA_DQ6 MA_DQ1 MEM_RST MA_DQ23 MA_DQ22 MA_DQ21 MA_DQ19 MEM_A_VREF1 MA_DQ7 MA_DQ3 MA_DM0 MA_ZQ_TOP MA_DQ0 MA_WDQS0 MA_DQ4 MA_DQ5 MEM_A_VREF1 MA_DQ20 MA_CS0_N MA_RDQS0 MA_DQ26 MA_DQ27 MA_DQ25 MA_DQ2 MA_DQ13 MA_DQ14 MA_DQ15 MA_DM2 MA_RDQS2 MA_DQ16 MA_DQ17 MA_DQ18 MA_WDQS3 MA_DQ29 MA_DQ30 MA_DQ31 MA_RAS_N MA_CAS_N MA_DQ24 MA_WDQS2 MA_RDQS3 MEM_A_VREF0 MEM_SCAN_EN MEM_SCAN_TOP_EN MA_CS1_N MA_DM3 MA_DQ28 MA_CLK0_DP MA_CLK0_DN MA_WE_N MA_BA<2..0> MA_A<11..0> 2 1 2 1 A4 H9 P2 P11 D11 D2 H1 H12 V4 V9 P3 P10 D10 D3 H3 A9 B10 B11 G3 F2 F3 E2 T3 T2 C3 R3 R2 M3 N2 L3 M2 T10 T11 R10 R11 C2 M10 N11 L10 M11 G10 F11 F10 E11 C10 C11 B3 B2 N3 N10 E10 E3 F9 J3 J11 J10 H4 F4 H10 G9 G4 M9 K11 L9 K10 H11 K9 M4 K3 J2 L4 K2 H2 K4 2 1 2 1 2 1 2 1 T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1 J12 J1 V3 L12 L1 G12 G1 A10 V10 A3 V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1 K12 K1 V2 M12 M1 V11 F12 F1 A11 A2 DRAWING BI OUT IN IN IN OUT IN BI BI BI BI BI BI BI BI BI BI BI BI IN OUT IN IN OUT IN BI IN BI BI BI BI BI BI GDDR136 (1Gbit) MF=0 VDDQ<21> VSSQ<18> VDDQ<18> VDDQ<11> VDDQ<16> VSSQ<16> VSSQ<19> VSS<0> VSS<1> VSS<2> VSS<3> VSS<4> VSS<5> VSS<6> VSS<7> VSSQ<0> VSSQ<1> VSSQ<2> VSSQ<3> VSSQ<4> VSSQ<5> VSSQ<6> VSSQ<7> VSSQ<8> VSSQ<9> VSSQ<10> VSSQ<11> VSSQ<12> VSSQ<13> VSSQ<14> VSSQ<15> VSSQ<17> VSSA<0> VSSA<1> VDDA<0> VDDA<1> VDD<0> VDD<1> VDD<2> VDD<3> VDD<4> VDD<5> VDD<6> VDD<7> VDDQ<0> VDDQ<1> VDDQ<2> VDDQ<3> VDDQ<4> VDDQ<5> VDDQ<6> VDDQ<7> VDDQ<8> VDDQ<9> VDDQ<10> VDDQ<12> VDDQ<13> VDDQ<14> VDDQ<15> VDDQ<17> VDDQ<19> VDDQ<20> IN OUT IN IN IN IN IN IN IN IN IN IN IN IN IN GDDR136 (1Gbit) MF=1 RESET CLK_DP CLK_DN SCAN_EN VREF1 VREF0 A11/A7 A10/A8 A9/A3 A8/A10 A7/A11 A6/A2 A5/A1 A4/A0 A3/A9 A2/A6 A1/A5 A0/A4 BA2/RAS_N BA1/BA0 BA0/BA1 CKE/WE_N WE_N/CKE CAS_N/CS_N RAS_N/BA2 CS_N/CAS_N MF DQ31 DQ30 DQ29 DQ28 DQ24 WDQS3 RDQS3 DM3 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WDQS1 RDQS1 DM1 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0 ZQ DQ25 DQ27 DQ26 A12 (1Gbit only, dual-load) CS1_N (1Gbit only, single-load) BI BI BI BI BI BI BI BI BI BI BI BI FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 15. MEMORY PARTITION A, BOTTOM [PAGE_TITLE=MEMORY PARTITION A, BOTTOM] CHIP SELECT = 1, MIRROR FUNCTION = 1 MEMORY A, BOTTOM, DECOUPLING CR-15 : @CORONA_LIB.CORONA(SCH_1):PAGE15 15/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:21 2011 1% 402 CH 1.27 KOHM CH 549 OHM 1% 402 V_MEM X5R 6.3 V 0.1 UF 10% 402 X5R 402 6.3 V 10% 0.1 UF 0 X802980-019 EMPTY 1 0 1 2 4 2 3 6 5 402 10% X5R 6.3 V 0.1 UF 7 8 9 11 10 402 243 OHM 1% CH X5R 402 6.3 V 10% 0.1 UF 6.3 V X5R 10% 402 0.1 UF X5R 10% 402 6.3 V 0.1 UF 6.3 V 402 X5R 10% 0.1 UF 402 60.4 OHM CH 1% V_MEM 402 60.4 OHM 1% CH V_MEM 6.3 V X5R 402 10% 0.1 UF 6.3 V X5R 402 10% 0.1 UF X802980-019 EMPTY V_MEM R7E7 R7E6 C7E9 U7T1 R7T6 R7T3 R7T2 C7T12 C7T9 U7T1 C7T5 C7T4 C7T11 C7T8 C7T3 C7T6 14 15 14 15 4 12 12 12 4 12 14 12 14 12 12 4 12 14 12 14 12 14 12 14 12 14 12 14 14 12 12 12 14 12 14 12 14 12 14 12 14 12 14 12 14 12 14 12 14 12 12 12 14 12 14 12 14 12 14 12 14 12 14 12 14 12 14 12 12 14 12 14 12 14 12 14 12 14 12 14 12 14 12 12 14 12 14 12 14 12 12 12 12 12 12 12 MEM_A_VREF0 MEM_A_VREF1 MEM_A_VREF0 MEM_SCAN_EN MA_CS1_N MA_CKE MA_CLK1_DN MEM_RST MA_DQ21 MA_WDQS2 MA_RDQS0 MA_WDQS0 MEM_SCAN_BOT_EN MA_DQ23 MA_DQ22 MA_DQ19 MA_DQ18 MA_DQ17 MA_DQ16 MA_RDQS2 MA_DM2 MA_DQ31 MA_DQ30 MA_DQ29 MA_DQ28 MA_DQ27 MA_DQ26 MA_DQ25 MA_DQ24 MA_WDQS3 MA_RDQS3 MA_DM3 MA_DQ7 MA_DQ6 MA_DQ5 MA_DQ4 MA_DQ3 MA_DQ2 MA_DQ1 MA_DQ0 MA_DM0 MA_DQ15 MA_DQ14 MA_DQ13 MA_DQ11 MA_DQ10 MA_DQ20 MA_DM1 MA_RDQS1 MA_DQ8 MA_DQ9 MA_DQ12 MA_ZQ_BOT MA_WE_N MA_CAS_N MA_RAS_N MA_WDQS1 MA_CLK1_DP MA_A<11..0> MA_BA<2..0> 2 1 2 1 A4 H9 P2 P11 D11 D2 H1 H12 V4 V9 P3 P10 D10 D3 H3 A9 B10 B11 G3 F2 F3 E2 T3 T2 C3 R3 R2 M3 N2 L3 M2 T10 T11 R10 R11 C2 M10 N11 L10 M11 G10 F11 F10 E11 C10 C11 B3 B2 N3 N10 E10 E3 F9 J3 J11 J10 H4 F4 H10 G9 G4 M9 K11 L9 K10 H11 K9 M4 K3 J2 L4 K2 H2 K4 2 1 2 1 2 1 T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1 J12 J1 V3 L12 L1 G12 G1 A10 V10 A3 V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1 K12 K1 V2 M12 M1 V11 F12 F1 A11 A2 DRAWING OUT IN IN IN IN IN IN IN IN IN IN IN IN IN GDDR136 (1Gbit) MF=1 RESET CLK_DP CLK_DN A5/A1 A4/A0 RAS_N/BA2 BA0/BA1 BA1/BA0 WE_N/CKE CKE/WE_N CS_N/CAS_N BA2/RAS_N CAS_N/CS_N SCAN_EN VREF1 VREF0 WDQS1 RDQS1 A7/A11 A8/A10 A3/A9 A10/A8 A11/A7 A2/A6 A1/A5 A0/A4 A9/A3 A6/A2 MF DQ31 DQ30 DQ29 DQ27 DQ26 DQ25 DQ24 WDQS3 RDQS3 DM3 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DM1 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0 ZQ DQ28 A12 (1Gbit only, dual-load) CS1_N (1Gbit only, single-load) BI IN OUT IN BI BI BI BI BI BI BI OUT IN BI BI BI BI IN BI BI BI BI IN BI BI BI OUT IN BI BI BI BI BI BI IN IN OUT BI IN BI BI BI BI BI BI GDDR136 (1Gbit) MF=0 VDDQ<21> VSSQ<19> VDDQ<20> VDDQ<19> VDDQ<11> VDDQ<12> VDDQ<10> VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VSS<0> VSS<1> VSS<2> VSS<3> VSS<4> VSS<5> VSS<6> VSS<7> VSSQ<0> VSSQ<1> VSSQ<2> VSSQ<3> VSSQ<4> VSSQ<5> VSSQ<6> VSSQ<7> VSSQ<8> VSSQ<9> VSSQ<10> VSSQ<11> VSSQ<12> VSSQ<13> VSSQ<14> VSSQ<15> VSSQ<16> VSSQ<17> VSSQ<18> VDD<3> VDD<4> VDD<5> VDD<6> VDD<7> VDDQ<0> VDDQ<1> VDDQ<2> VDDQ<3> VDDQ<4> VDDQ<5> VDDQ<13> VDDQ<14> VDDQ<15> VDDQ<16> VDDQ<17> VDDQ<18> VSSA<0> VSSA<1> VDDA<0> VDDA<1> VDD<0> VDD<1> VDD<2> FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 16. MEMORY PARTITION B, TOP [PAGE_TITLE=MEMORY PARITION B, TOP] CHIP SELECT = 0, MIRROR FUNCTION = 0 PARTITION B DECOUPLING MEMORY B, TOP, DECOUPLING CR-16 : @CORONA_LIB.CORONA(SCH_1):PAGE16 16/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:22 2011 6.3 V 0.1 UF 402 10% X5R V_MEM 10% 6.3 V 402 X5R 0.1 UF IC X802980-019 0 2 1 10% 6.3 V 402 X5R 0.1 UF 0 1 2 3 4 5 7 6 8 9 IC X802980-019 11 10 60.4 OHM CH 1% 402 V_MEM 60.4 OHM CH 1% 402 CH 1% 243 OHM 402 603 4.7 UF 6.3 V 10% X5R V_MEM X5R 402 6.3 V 10% 0.1 UF 6.3 V 10% 402 X5R 0.1 UF V_MEM 402 X5R 6.3 V 10% 0.1 UF 10% 6.3 V 402 X5R 0.1 UF 6.3 V X5R 402 10% 0.1 UF 402 1% CH 1.27 KOHM CH 549 OHM 1% 402 10% 6.3 V X5R 402 0.1 UF V_MEM R7R4 R7R2 C7R6 U7D1 R7D3 R7D2 R7E1 C7D11 C7D13 C7D9 C7E3 C7E2 C7D14 C7D10 C7D7 C7D8 U7D1 16 17 17 16 4 4 12 12 12 12 12 12 4 12 12 12 17 12 12 17 12 17 12 17 12 12 17 12 17 12 17 12 17 12 17 12 17 12 12 12 17 12 17 12 17 12 17 12 17 12 17 17 12 12 12 17 12 17 12 17 12 17 12 17 12 17 12 17 12 17 12 17 12 12 17 12 17 12 17 12 17 12 17 17 12 12 17 17 12 12 17 12 17 12 12 12 12 MEM_B_VREF1 MEM_B_VREF0 MEM_B_VREF1 MEM_SCAN_EN MEM_SCAN_TOP_EN MB_CS1_N MB_CS0_N MB_RAS_N MB_CAS_N MB_WE_N MB_CKE MEM_RST MB_DM0 MB_ZQ_TOP MB_DM2 MB_DQ13 MB_WDQS3 MB_DQ26 MB_DQ27 MB_DQ25 MB_WDQS0 MB_DQ0 MB_DQ1 MB_DQ2 MB_DQ5 MB_DQ6 MB_DQ7 MB_DM1 MB_WDQS1 MB_DQ9 MB_DQ10 MB_DQ11 MB_DQ12 MB_DQ14 MB_DQ15 MB_RDQS2 MB_WDQS2 MB_DQ16 MB_DQ17 MB_DQ18 MB_DQ19 MB_DQ20 MB_DQ21 MB_DQ22 MB_DQ23 MB_DM3 MB_RDQS3 MB_DQ24 MB_DQ28 MB_DQ29 MB_DQ30 MB_DQ31 MB_RDQS1 MB_DQ8 MB_RDQS0 MB_DQ3 MB_DQ4 MB_CLK0_DN MB_CLK0_DP MB_BA<2..0> MB_A<11..0> 2 1 2 1 A4 H9 P2 P11 D11 D2 H1 H12 V4 V9 P3 P10 D10 D3 H3 A9 B10 B11 G3 F2 F3 E2 T3 T2 C3 R3 R2 M3 N2 L3 M2 T10 T11 R10 R11 C2 M10 N11 L10 M11 G10 F11 F10 E11 C10 C11 B3 B2 N3 N10 E10 E3 F9 J3 J11 J10 H4 F4 H10 G9 G4 M9 K11 L9 K10 H11 K9 M4 K3 J2 L4 K2 H2 K4 2 1 2 1 2 1 2 1 T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1 J12 J1 V3 L12 L1 G12 G1 A10 V10 A3 V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1 K12 K1 V2 M12 M1 V11 F12 F1 A11 A2 DRAWING OUT IN IN IN IN IN IN IN IN IN IN IN IN IN GDDR136 (1Gbit) MF=1 RESET CLK_DP CLK_DN SCAN_EN VREF1 VREF0 A11/A7 A10/A8 A9/A3 A8/A10 A7/A11 A6/A2 A5/A1 A4/A0 A3/A9 A2/A6 A1/A5 A0/A4 BA2/RAS_N BA1/BA0 BA0/BA1 CKE/WE_N WE_N/CKE CAS_N/CS_N RAS_N/BA2 CS_N/CAS_N MF DQ31 DQ30 DQ29 DQ28 DQ24 WDQS3 RDQS3 DM3 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WDQS1 RDQS1 DM1 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0 ZQ DQ25 DQ27 DQ26 A12 (1Gbit only, dual-load) CS1_N (1Gbit only, single-load) GDDR136 (1Gbit) MF=0 VDDQ<21> VSSQ<18> VDDQ<18> VDDQ<11> VDDQ<16> VSSQ<16> VSSQ<19> VSS<0> VSS<1> VSS<2> VSS<3> VSS<4> VSS<5> VSS<6> VSS<7> VSSQ<0> VSSQ<1> VSSQ<2> VSSQ<3> VSSQ<4> VSSQ<5> VSSQ<6> VSSQ<7> VSSQ<8> VSSQ<9> VSSQ<10> VSSQ<11> VSSQ<12> VSSQ<13> VSSQ<14> VSSQ<15> VSSQ<17> VSSA<0> VSSA<1> VDDA<0> VDDA<1> VDD<0> VDD<1> VDD<2> VDD<3> VDD<4> VDD<5> VDD<6> VDD<7> VDDQ<0> VDDQ<1> VDDQ<2> VDDQ<3> VDDQ<4> VDDQ<5> VDDQ<6> VDDQ<7> VDDQ<8> VDDQ<9> VDDQ<10> VDDQ<12> VDDQ<13> VDDQ<14> VDDQ<15> VDDQ<17> VDDQ<19> VDDQ<20> IN IN OUT BI BI BI BI BI BI BI BI IN BI BI BI BI BI BI BI BI BI IN OUT IN BI BI BI BI BI BI BI IN IN OUT BI BI BI BI BI BI BI IN OUT IN BI IN FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 17. MEMORY PARTITION B, BOTTOM CHIP SELECT = 1, MIRROR FUNCTION = 1 MEMORY B, BOTTOM, DECOUPLING [PAGE_TITLE=MEMORY PARITION B, BOTTOM] CR-17 : @CORONA_LIB.CORONA(SCH_1):PAGE17 17/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:22 2011 402 1% 1.27 KOHM CH 402 0.1 UF 6.3 V 10% X5R 549 OHM CH 402 1% V_MEM 0.1 UF 6.3 V 10% 402 X5R 1 0.1 UF 10% 6.3 V 402 X5R 0 2 EMPTY X802980-019 0 2 1 4 3 5 6 0.1 UF 10% X5R 402 6.3 V 7 8 9 10 11 60.4 OHM 402 1% CH V_MEM 402 60.4 OHM 1% CH X802980-019 EMPTY 402 243 OHM 1% CH 0.1 UF 10% 402 X5R 6.3 V V_MEM 0.1 UF 402 X5R 10% 6.3 V 0.1 UF 10% X5R 6.3 V 402 0.1 UF 6.3 V X5R 402 10% 0.1 UF 402 X5R 10% 6.3 V V_MEM R7D5 C7D12 R7D4 U7R1 R7R1 R7R3 R7T1 C7R7 C7R4 C7T2 C7T1 C7R8 C7R5 C7R2 C7R3 U7R1 16 17 12 16 16 12 12 12 12 12 12 12 12 16 12 4 12 16 12 16 12 16 12 16 12 16 12 16 12 16 12 16 12 12 12 16 12 16 12 16 12 16 12 16 12 16 12 16 12 16 12 16 12 12 16 12 16 12 16 12 16 12 16 12 16 12 16 12 16 12 12 16 12 16 12 16 12 16 12 16 12 16 12 12 16 12 12 12 16 16 17 4 12 4 12 12 MEM_B_VREF0 MB_DQ8 MB_RDQS1 MB_ZQ_BOT MB_CLK1_DP MB_DM3 MB_CKE MB_WE_N MB_CAS_N MB_RAS_N MB_WDQS0 MB_RDQS0 MEM_SCAN_BOT_EN MB_DQ23 MB_DQ22 MB_DQ21 MB_DQ19 MB_DQ18 MB_DQ17 MB_DQ16 MB_WDQS2 MB_RDQS2 MB_DM2 MB_DQ31 MB_DQ30 MB_DQ29 MB_DQ28 MB_DQ27 MB_DQ26 MB_DQ25 MB_DQ24 MB_WDQS3 MB_RDQS3 MB_DQ7 MB_DQ6 MB_DQ5 MB_DQ4 MB_DQ3 MB_DQ2 MB_DQ1 MB_DQ0 MB_DM0 MB_DQ15 MB_DQ14 MB_DQ13 MB_DQ12 MB_DQ11 MB_DQ10 MB_DM1 MB_DQ20 MB_CS1_N MB_WDQS1 MB_DQ9 MEM_B_VREF1 MEM_B_VREF0 MEM_SCAN_EN MB_CLK1_DN MEM_RST MB_BA<2..0> MB_A<11..0> 2 1 2 1 A4 H9 P2 P11 D11 D2 H1 H12 V4 V9 P3 P10 D10 D3 H3 A9 B10 B11 G3 F2 F3 E2 T3 T2 C3 R3 R2 M3 N2 L3 M2 T10 T11 R10 R11 C2 M10 N11 L10 M11 G10 F11 F10 E11 C10 C11 B3 B2 N3 N10 E10 E3 F9 J3 J11 J10 H4 F4 H10 G9 G4 M9 K11 L9 K10 H11 K9 M4 K3 J2 L4 K2 H2 K4 2 1 2 1 2 1 T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1 J12 J1 V3 L12 L1 G12 G1 A10 V10 A3 V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1 K12 K1 V2 M12 M1 V11 F12 F1 A11 A2 DRAWING OUT IN IN IN IN IN IN IN IN IN IN IN IN IN GDDR136 (1Gbit) MF=1 RESET CLK_DP CLK_DN A5/A1 A4/A0 RAS_N/BA2 BA0/BA1 BA1/BA0 WE_N/CKE CKE/WE_N CS_N/CAS_N BA2/RAS_N CAS_N/CS_N SCAN_EN VREF1 VREF0 WDQS1 RDQS1 A7/A11 A8/A10 A3/A9 A10/A8 A11/A7 A2/A6 A1/A5 A0/A4 A9/A3 A6/A2 MF DQ31 DQ30 DQ29 DQ27 DQ26 DQ25 DQ24 WDQS3 RDQS3 DM3 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DM1 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0 ZQ DQ28 A12 (1Gbit only, dual-load) CS1_N (1Gbit only, single-load) IN GDDR136 (1Gbit) MF=0 VDDQ<21> VSSQ<19> VDDQ<20> VDDQ<19> VDDQ<11> VDDQ<12> VDDQ<10> VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VSS<0> VSS<1> VSS<2> VSS<3> VSS<4> VSS<5> VSS<6> VSS<7> VSSQ<0> VSSQ<1> VSSQ<2> VSSQ<3> VSSQ<4> VSSQ<5> VSSQ<6> VSSQ<7> VSSQ<8> VSSQ<9> VSSQ<10> VSSQ<11> VSSQ<12> VSSQ<13> VSSQ<14> VSSQ<15> VSSQ<16> VSSQ<17> VSSQ<18> VDD<3> VDD<4> VDD<5> VDD<6> VDD<7> VDDQ<0> VDDQ<1> VDDQ<2> VDDQ<3> VDDQ<4> VDDQ<5> VDDQ<13> VDDQ<14> VDDQ<15> VDDQ<16> VDDQ<17> VDDQ<18> VSSA<0> VSSA<1> VDDA<0> VDDA<1> VDD<0> VDD<1> VDD<2> OUT IN IN BI BI BI BI BI BI BI BI IN BI BI OUT IN BI BI BI BI BI BI BI BI IN OUT IN BI BI BI BI BI BI BI BI IN OUT BI BI BI BI BI IN BI FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 18. [PAGE_TITLE=MEMORY PARTITION C, TOP] CHIP SELECT = 0, MIRROR FUNCTION = 0 MC_CLK0 MEMORY C, TOP, DECOUPLING PARTITION C DECOUPLING STITCHING CAP MEMORY PARTITION C, TOP CR-18 : @CORONA_LIB.CORONA(SCH_1):PAGE18 18/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:22 2011 402 CH 1% 60.4 OHM V_MEM IC X802980-019 243 OHM 402 1% CH 0.1 UF X5R 402 10% 6.3 V 1 0 2 0 1 2 3 4 5 6 0.1 UF 6.3 V 10% 402 X5R 8 7 9 10 11 603 4.7 UF 6.3 V 10% X5R V_MEM 0.1 UF X5R 402 10% 6.3 V X802980-019 IC 0.1 UF 6.3 V 10% X5R 402 402 60.4 OHM 1% CH 0.1 UF 6.3 V 10% 402 X5R V_MEM 0.1 UF 6.3 V 10% X5R 402 0.1 UF X5R 402 10% 6.3 V X5R 6.3 V 10% 0.1 UF 402 V_MEM 402 1% 1.27 KOHM CH 6.3 V 0.1 UF 10% X5R 402 CH 549 OHM 402 1% V_MEM 0.1 UF 10% 6.3 V X5R 402 V_MEM C5U1 R5U4 C5U9 R5U5 R5F4 U5F1 R5F5 C5F10 R5F3 C6F10 C6F8 C6F4 C6F1 C6F2 C6F5 C6F7 U5F1 C6F9 18 19 13 19 13 19 13 19 4 4 13 13 13 13 13 19 13 19 13 19 13 19 13 19 13 19 13 13 13 19 13 19 13 19 13 19 13 19 13 19 13 13 19 13 19 13 19 13 19 13 19 13 19 13 19 13 13 13 19 13 19 13 19 13 19 13 19 13 19 13 13 19 13 19 13 18 13 19 13 19 13 19 13 19 13 13 19 13 19 13 19 13 13 4 13 13 13 MEM_C_VREF1 MC_DQ3 MC_DQ9 MC_DQ14 MEM_SCAN_EN MEM_SCAN_TOP_EN MC_CS0_N MC_WE_N MC_CAS_N MC_RAS_N MC_DQ31 MC_DQ30 MC_DQ29 MC_DQ28 MC_DQ24 MC_WDQS3 MC_RDQS3 MC_DM3 MC_DQ23 MC_DQ22 MC_DQ21 MC_DQ20 MC_DQ19 MC_WDQS2 MC_RDQS2 MC_DQ15 MC_DQ13 MC_DQ12 MC_DQ11 MC_DQ10 MC_DQ8 MC_WDQS1 MC_RDQS1 MC_DM1 MC_DQ7 MC_DQ6 MC_DQ5 MC_DQ4 MC_DQ2 MC_WDQS0 MC_RDQS0 MC_DQ27 MC_DQ26 MC_CS1_N MEM_C_VREF1 MC_CKE MEM_C_VREF0 MC_DQ16 MC_DQ17 MC_DQ25 MC_DM2 MC_DQ18 MC_DQ0 MC_DQ1 MC_CLK0_DN MC_ZQ_TOP MC_DM0 MEM_RST MC_CLK0_DP MC_A<11..0> MC_BA<2..0> 2 1 2 1 2 1 2 1 A4 H9 P2 P11 D11 D2 H1 H12 V4 V9 P3 P10 D10 D3 H3 A9 B10 B11 G3 F2 F3 E2 T3 T2 C3 R3 R2 M3 N2 L3 M2 T10 T11 R10 R11 C2 M10 N11 L10 M11 G10 F11 F10 E11 C10 C11 B3 B2 N3 N10 E10 E3 F9 J3 J11 J10 H4 F4 H10 G9 G4 M9 K11 L9 K10 H11 K9 M4 K3 J2 L4 K2 H2 K4 2 1 2 1 2 1 T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1 J12 J1 V3 L12 L1 G12 G1 A10 V10 A3 V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1 K12 K1 V2 M12 M1 V11 F12 F1 A11 A2 DRAWING IN IN IN IN IN IN IN IN IN IN IN IN IN IN OUT GDDR136 (1Gbit) MF=1 RESET CLK_DP CLK_DN SCAN_EN VREF1 VREF0 A11/A7 A10/A8 A9/A3 A8/A10 A7/A11 A6/A2 A5/A1 A4/A0 A3/A9 A2/A6 A1/A5 A0/A4 BA2/RAS_N BA1/BA0 BA0/BA1 CKE/WE_N WE_N/CKE CAS_N/CS_N RAS_N/BA2 CS_N/CAS_N MF DQ31 DQ30 DQ29 DQ28 DQ24 WDQS3 RDQS3 DM3 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WDQS1 RDQS1 DM1 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0 ZQ DQ25 DQ27 DQ26 A12 (1Gbit only, dual-load) CS1_N (1Gbit only, single-load) BI BI BI BI BI IN OUT IN BI BI BI BI BI BI IN OUT IN BI BI BI GDDR136 (1Gbit) MF=0 VDDQ<21> VSSQ<18> VDDQ<18> VDDQ<11> VDDQ<16> VSSQ<16> VSSQ<19> VSS<0> VSS<1> VSS<2> VSS<3> VSS<4> VSS<5> VSS<6> VSS<7> VSSQ<0> VSSQ<1> VSSQ<2> VSSQ<3> VSSQ<4> VSSQ<5> VSSQ<6> VSSQ<7> VSSQ<8> VSSQ<9> VSSQ<10> VSSQ<11> VSSQ<12> VSSQ<13> VSSQ<14> VSSQ<15> VSSQ<17> VSSA<0> VSSA<1> VDDA<0> VDDA<1> VDD<0> VDD<1> VDD<2> VDD<3> VDD<4> VDD<5> VDD<6> VDD<7> VDDQ<0> VDDQ<1> VDDQ<2> VDDQ<3> VDDQ<4> VDDQ<5> VDDQ<6> VDDQ<7> VDDQ<8> VDDQ<9> VDDQ<10> VDDQ<12> VDDQ<13> VDDQ<14> VDDQ<15> VDDQ<17> VDDQ<19> VDDQ<20> BI BI BI OUT IN IN BI BI BI BI BI BI BI IN OUT IN BI BI BI BI BI BI BI BI IN FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 19. MEMORY PARTITION C, BOTTOM CHIP SELECT = 1, MIRROR FUNCTION = 1 [PAGE_TITLE=MEMORY PARITION C, BOTTOM] MEMORY C, BOTTOM, DECOUPLING CR-19 : @CORONA_LIB.CORONA(SCH_1):PAGE19 19/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:23 2011 CH 549 OHM 1% 402 V_MEM 6.3 V 10% 402 X5R 0.1 UF 1 0 2 0 402 X5R 10% 6.3 V 0.1 UF 1 2 3 4 5 6 7 8 10 9 11 EMPTY X802980-019 CH 1% 243 OHM 402 X5R 402 6.3 V 10% 0.1 UF X5R 402 10% 6.3 V 0.1 UF EMPTY X802980-019 6.3 V 10% 402 X5R 0.1 UF 402 60.4 OHM 1% CH 6.3 V 10% 402 X5R 0.1 UF V_MEM 402 60.4 OHM 1% CH 6.3 V 10% X5R 402 0.1 UF X5R 402 10% 6.3 V 0.1 UF V_MEM 1% 402 1.27 KOHM CH X5R 10% 0.1 UF 402 6.3 V V_MEM R5F2 C5F1 R5F1 U5U1 R5U1 R5U3 R5U2 C6U9 C6U6 C6U3 C6U1 C6U2 C6U4 U5U1 C6U5 C6U8 18 19 4 13 13 13 13 19 13 18 13 13 18 13 18 13 18 13 18 13 18 13 18 13 18 13 13 13 18 13 18 13 18 13 18 13 18 13 18 13 18 13 18 13 18 13 13 13 18 13 18 13 18 13 18 13 18 13 18 13 18 13 18 13 13 18 13 18 13 18 13 18 13 18 13 18 13 18 13 18 13 13 18 13 18 13 18 13 4 13 18 13 13 4 13 13 MEM_C_VREF0 MEM_SCAN_BOT_EN MC_CKE MC_WE_N MC_CAS_N MC_RAS_N MEM_C_VREF0 MC_WDQS0 MC_RDQS0 MC_DQ23 MC_DQ22 MC_DQ21 MC_DQ19 MC_DQ18 MC_DQ16 MC_WDQS2 MC_RDQS2 MC_DM2 MC_DQ31 MC_DQ30 MC_DQ29 MC_DQ28 MC_DQ27 MC_DQ26 MC_DQ25 MC_DQ24 MC_WDQS3 MC_RDQS3 MC_DM3 MC_DQ7 MC_DQ6 MC_DQ5 MC_DQ4 MC_DQ3 MC_DQ2 MC_DQ1 MC_DQ0 MC_DM0 MC_DQ15 MC_DQ14 MC_DQ13 MC_DQ12 MC_DQ11 MC_DQ10 MC_DQ9 MC_DQ8 MC_WDQS1 MC_DQ20 MC_DQ17 MC_CS1_N MEM_C_VREF1 MC_CLK1_DN MEM_RST MC_CLK1_DP MC_RDQS1 MC_ZQ_BOT MC_DM1 MEM_SCAN_EN MC_BA<2..0> MC_A<11..0> 2 1 2 1 A4 H9 P2 P11 D11 D2 H1 H12 V4 V9 P3 P10 D10 D3 H3 A9 B10 B11 G3 F2 F3 E2 T3 T2 C3 R3 R2 M3 N2 L3 M2 T10 T11 R10 R11 C2 M10 N11 L10 M11 G10 F11 F10 E11 C10 C11 B3 B2 N3 N10 E10 E3 F9 J3 J11 J10 H4 F4 H10 G9 G4 M9 K11 L9 K10 H11 K9 M4 K3 J2 L4 K2 H2 K4 2 1 2 1 2 1 T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1 J12 J1 V3 L12 L1 G12 G1 A10 V10 A3 V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1 K12 K1 V2 M12 M1 V11 F12 F1 A11 A2 DRAWING IN IN IN IN IN IN IN IN IN IN IN IN IN IN OUT GDDR136 (1Gbit) MF=1 RESET CLK_DP CLK_DN A5/A1 A4/A0 RAS_N/BA2 BA0/BA1 BA1/BA0 WE_N/CKE CKE/WE_N CS_N/CAS_N BA2/RAS_N CAS_N/CS_N SCAN_EN VREF1 VREF0 WDQS1 RDQS1 A7/A11 A8/A10 A3/A9 A10/A8 A11/A7 A2/A6 A1/A5 A0/A4 A9/A3 A6/A2 MF DQ31 DQ30 DQ29 DQ27 DQ26 DQ25 DQ24 WDQS3 RDQS3 DM3 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DM1 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0 ZQ DQ28 A12 (1Gbit only, dual-load) CS1_N (1Gbit only, single-load) IN OUT BI IN BI BI BI BI BI BI BI IN IN OUT BI BI BI BI BI BI BI BI IN OUT IN GDDR136 (1Gbit) MF=0 VDDQ<21> VSSQ<19> VDDQ<20> VDDQ<19> VDDQ<11> VDDQ<12> VDDQ<10> VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VSS<0> VSS<1> VSS<2> VSS<3> VSS<4> VSS<5> VSS<6> VSS<7> VSSQ<0> VSSQ<1> VSSQ<2> VSSQ<3> VSSQ<4> VSSQ<5> VSSQ<6> VSSQ<7> VSSQ<8> VSSQ<9> VSSQ<10> VSSQ<11> VSSQ<12> VSSQ<13> VSSQ<14> VSSQ<15> VSSQ<16> VSSQ<17> VSSQ<18> VDD<3> VDD<4> VDD<5> VDD<6> VDD<7> VDDQ<0> VDDQ<1> VDDQ<2> VDDQ<3> VDDQ<4> VDDQ<5> VDDQ<13> VDDQ<14> VDDQ<15> VDDQ<16> VDDQ<17> VDDQ<18> VSSA<0> VSSA<1> VDDA<0> VDDA<1> VDD<0> VDD<1> VDD<2> BI BI BI BI BI BI BI BI IN OUT BI IN BI BI BI BI BI BI BI FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 20. PARTITION D DECOUPLING [PAGE_TITLE=MEMORY PARTITION D, TOP] CHIP SELECT = 0, MIRROR FUNCTION = 0 MEMORY D, TOP, DECOUPLING MEMORY PARTITION D, TOP CR-20 : @CORONA_LIB.CORONA(SCH_1):PAGE20 20/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:23 2011 X802980-019 IC 0 1 2 0 1 2 3 4 5 7 6 8 9 10 11 60.4 OHM CH 1% 402 V_MEM 1% 60.4 OHM CH 402 CH 1% 243 OHM 402 603 6.3 V 4.7 UF X5R 10% V_MEM X5R 402 6.3 V 10% 0.1 UF X5R 402 6.3 V 10% 0.1 UF V_MEM IC X802980-019 10% 6.3 V 402 X5R 0.1 UF 402 X5R 10% 6.3 V 0.1 UF 402 X5R 6.3 V 10% 0.1 UF 402 X5R 10% 6.3 V 0.1 UF X5R 402 6.3 V 10% 0.1 UF X5R 402 10% 6.3 V 0.1 UF 402 1% CH 1.27 KOHM 0.1 UF 6.3 V X5R 402 10% CH 549 OHM 1% 402 V_MEM V_MEM R6U4 C6U7 R6U5 U6F1 R6F4 R6F3 R6F5 C6F11 C5F9 C5F7 U6F1 C5F4 C5F3 C5F2 C5F5 C5F6 C5F8 4 20 21 20 4 13 13 13 21 13 21 13 13 13 4 13 13 21 13 13 13 21 13 21 13 13 21 13 21 13 21 13 21 13 21 13 21 13 21 13 21 13 13 13 21 13 21 13 21 13 21 13 21 13 21 13 21 13 21 21 13 13 13 21 13 21 13 21 13 21 13 21 13 21 13 21 13 13 21 13 21 13 21 13 21 13 21 13 21 13 13 21 13 13 21 13 13 MEM_SCAN_EN MEM_D_VREF1 MEM_D_VREF1 MEM_SCAN_TOP_EN MD_CS1_N MD_RAS_N MD_DQ3 MD_CAS_N MEM_D_VREF0 MD_CS0_N MD_WE_N MD_CKE MEM_RST MD_CLK0_DN MD_CLK0_DP MD_ZQ_TOP MD_RDQS0 MD_DM0 MD_DQ1 MD_DQ0 MD_WDQS0 MD_DQ26 MD_DQ27 MD_DQ2 MD_DQ4 MD_DQ5 MD_DQ6 MD_DQ7 MD_DM1 MD_RDQS1 MD_WDQS1 MD_DQ8 MD_DQ9 MD_DQ10 MD_DQ11 MD_DQ12 MD_DQ13 MD_DQ14 MD_DQ15 MD_RDQS2 MD_WDQS2 MD_DQ17 MD_DQ19 MD_DQ20 MD_DQ21 MD_DQ22 MD_DQ23 MD_DM3 MD_RDQS3 MD_DQ24 MD_DQ28 MD_DQ29 MD_DQ30 MD_DQ31 MD_DQ25 MD_WDQS3 MD_DQ18 MD_DM2 MD_DQ16 MD_A<11..0> MD_BA<2..0> 2 1 2 1 A4 H9 P2 P11 D11 D2 H1 H12 V4 V9 P3 P10 D10 D3 H3 A9 B10 B11 G3 F2 F3 E2 T3 T2 C3 R3 R2 M3 N2 L3 M2 T10 T11 R10 R11 C2 M10 N11 L10 M11 G10 F11 F10 E11 C10 C11 B3 B2 N3 N10 E10 E3 F9 J3 J11 J10 H4 F4 H10 G9 G4 M9 K11 L9 K10 H11 K9 M4 K3 J2 L4 K2 H2 K4 2 1 2 1 2 1 2 1 T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1 J12 J1 V3 L12 L1 G12 G1 A10 V10 A3 V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1 K12 K1 V2 M12 M1 V11 F12 F1 A11 A2 DRAWING IN IN IN IN IN IN IN IN IN IN BI IN IN IN GDDR136 (1Gbit) MF=1 RESET CLK_DP CLK_DN SCAN_EN VREF1 VREF0 A11/A7 A10/A8 A9/A3 A8/A10 A7/A11 A6/A2 A5/A1 A4/A0 A3/A9 A2/A6 A1/A5 A0/A4 BA2/RAS_N BA1/BA0 BA0/BA1 CKE/WE_N WE_N/CKE CAS_N/CS_N RAS_N/BA2 CS_N/CAS_N MF DQ31 DQ30 DQ29 DQ28 DQ24 WDQS3 RDQS3 DM3 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 WDQS1 RDQS1 DM1 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0 ZQ DQ25 DQ27 DQ26 A12 (1Gbit only, dual-load) CS1_N (1Gbit only, single-load) BI IN BI OUT IN IN BI BI BI BI BI BI BI BI BI IN BI BI BI BI OUT IN BI BI BI BI BI BI IN OUT IN BI BI BI BI BI BI BI IN OUT IN GDDR136 (1Gbit) MF=0 VDDQ<21> VSSQ<18> VDDQ<18> VDDQ<11> VDDQ<16> VSSQ<16> VSSQ<19> VSS<0> VSS<1> VSS<2> VSS<3> VSS<4> VSS<5> VSS<6> VSS<7> VSSQ<0> VSSQ<1> VSSQ<2> VSSQ<3> VSSQ<4> VSSQ<5> VSSQ<6> VSSQ<7> VSSQ<8> VSSQ<9> VSSQ<10> VSSQ<11> VSSQ<12> VSSQ<13> VSSQ<14> VSSQ<15> VSSQ<17> VSSA<0> VSSA<1> VDDA<0> VDDA<1> VDD<0> VDD<1> VDD<2> VDD<3> VDD<4> VDD<5> VDD<6> VDD<7> VDDQ<0> VDDQ<1> VDDQ<2> VDDQ<3> VDDQ<4> VDDQ<5> VDDQ<6> VDDQ<7> VDDQ<8> VDDQ<9> VDDQ<10> VDDQ<12> VDDQ<13> VDDQ<14> VDDQ<15> VDDQ<17> VDDQ<19> VDDQ<20> BI IN BI OUT BI FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 21. MEMORY PARTITION D, BOTTOM CHIP SELECT = 1, MIRROR FUNCTION = 1 MEMORY D, BOTTOM, DECOUPLING MEMORY D, BOTTOM, DECOUPLING [PAGE_TITLE=MEMORY PARTITION D, BOTTOM] CR-21 : @CORONA_LIB.CORONA(SCH_1):PAGE21 21/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:23 2011 0 1 2 EMPTY X802980-019 X5R 402 10% 6.3 V 0.1 UF 0 2 1 3 5 4 7 6 8 10 EMPTY X802980-019 9 11 1% 60.4 OHM 402 CH 1% 402 60.4 OHM CH V_MEM 402 X5R 10% 6.3 V 0.1 UF 6.3 V 10% 402 X5R 0.1 UF 1% 243 OHM CH 402 V_MEM 402 X5R 10% 6.3 V 0.1 UF 6.3 V 10% 402 X5R 0.1 UF 10% 402 6.3 V X5R 0.1 UF 6.3 V 10% X5R 402 0.1 UF 6.3 V 10% 402 X5R 0.1 UF 6.3 V 10% 402 X5R 0.1 UF 402 X5R 10% 6.3 V 0.1 UF V_MEM 402 X5R 10% 6.3 V 0.1 UF 6.3 V 10% 402 X5R 0.1 UF 6.3 V 10% 402 X5R 0.1 UF 402 X5R 10% 6.3 V 0.1 UF 1% 402 CH 1.27 KOHM 402 0.1 UF 6.3 V 10% X5R 402 X5R 10% 6.3 V 0.1 UF CH 549 OHM 1% 402 V_MEM X5R 402 10% 6.3 V 0.1 UF V_MEM R6F2 C6F3 R6F1 U6U1 R6U2 R6U3 C5U12 C6U10 R6U1 C6F6 C7E12 C7T10 C7E1 C7D15 C7R9 C5U8 C5U5 C5U4 C5U3 C5U6 C5U7 C5U11 C5U10 U6U1 20 21 13 20 13 13 20 13 13 13 20 13 20 13 20 13 20 13 20 13 20 13 13 20 13 20 13 20 13 20 13 20 13 20 20 13 13 13 20 13 20 13 20 13 20 13 20 13 20 13 20 20 13 13 13 20 13 20 13 20 13 20 13 20 13 20 20 13 13 21 13 13 13 13 13 13 13 20 13 20 20 4 4 13 20 20 13 13 20 13 13 20 13 4 13 13 MEM_D_VREF0 MD_DQ6 MD_DM2 MD_DQ20 MD_DM1 MD_WDQS1 MD_DQ9 MD_DQ11 MD_DQ12 MD_DQ13 MD_DQ14 MD_DQ15 MD_DM0 MD_DQ0 MD_DQ1 MD_DQ2 MD_DQ3 MD_DQ5 MD_DQ7 MD_RDQS3 MD_WDQS3 MD_DQ24 MD_DQ25 MD_DQ26 MD_DQ27 MD_DQ28 MD_DQ29 MD_DQ31 MD_RDQS2 MD_WDQS2 MD_DQ16 MD_DQ17 MD_DQ18 MD_DQ21 MD_DQ22 MD_DQ23 MD_RDQS0 MD_WDQS0 MEM_D_VREF0 MD_RAS_N MD_WE_N MD_CKE MD_ZQ_BOT MD_CLK1_DP MD_CS1_N MD_CAS_N MD_DQ30 MD_DQ19 MEM_D_VREF1 MEM_SCAN_BOT_EN MEM_SCAN_EN MD_DQ8 MD_RDQS1 MD_DQ10 MD_DM3 MD_DQ4 MD_CLK1_DN MEM_RST MD_BA<2..0> MD_A<11..0> 2 1 2 1 A4 H9 P2 P11 D11 D2 H1 H12 V4 V9 P3 P10 D10 D3 H3 A9 B10 B11 G3 F2 F3 E2 T3 T2 C3 R3 R2 M3 N2 L3 M2 T10 T11 R10 R11 C2 M10 N11 L10 M11 G10 F11 F10 E11 C10 C11 B3 B2 N3 N10 E10 E3 F9 J3 J11 J10 H4 F4 H10 G9 G4 M9 K11 L9 K10 H11 K9 M4 K3 J2 L4 K2 H2 K4 2 1 2 1 2 1 T12 T9 T4 T1 P12 P9 P4 P1 L11 L2 G11 G2 D12 D9 D4 D1 B12 B9 B4 B1 J12 J1 V3 L12 L1 G12 G1 A10 V10 A3 V1 R12 R9 R4 R1 N12 N9 V12 N4 N1 J9 J4 E12 E9 E4 E1 C12 C9 C4 C1 A12 A1 K12 K1 V2 M12 M1 V11 F12 F1 A11 A2 DRAWING IN IN IN IN IN IN GDDR136 (1Gbit) MF=1 RESET CLK_DP CLK_DN A5/A1 A4/A0 RAS_N/BA2 BA0/BA1 BA1/BA0 WE_N/CKE CKE/WE_N CS_N/CAS_N BA2/RAS_N CAS_N/CS_N SCAN_EN VREF1 VREF0 WDQS1 RDQS1 A7/A11 A8/A10 A3/A9 A10/A8 A11/A7 A2/A6 A1/A5 A0/A4 A9/A3 A6/A2 MF DQ31 DQ30 DQ29 DQ27 DQ26 DQ25 DQ24 WDQS3 RDQS3 DM3 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 WDQS2 RDQS2 DM2 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DM1 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WDQS0 RDQS0 DM0 ZQ DQ28 A12 (1Gbit only, dual-load) CS1_N (1Gbit only, single-load) GDDR136 (1Gbit) MF=0 VDDQ<21> VSSQ<19> VDDQ<20> VDDQ<19> VDDQ<11> VDDQ<12> VDDQ<10> VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VSS<0> VSS<1> VSS<2> VSS<3> VSS<4> VSS<5> VSS<6> VSS<7> VSSQ<0> VSSQ<1> VSSQ<2> VSSQ<3> VSSQ<4> VSSQ<5> VSSQ<6> VSSQ<7> VSSQ<8> VSSQ<9> VSSQ<10> VSSQ<11> VSSQ<12> VSSQ<13> VSSQ<14> VSSQ<15> VSSQ<16> VSSQ<17> VSSQ<18> VDD<3> VDD<4> VDD<5> VDD<6> VDD<7> VDDQ<0> VDDQ<1> VDDQ<2> VDDQ<3> VDDQ<4> VDDQ<5> VDDQ<13> VDDQ<14> VDDQ<15> VDDQ<16> VDDQ<17> VDDQ<18> VSSA<0> VSSA<1> VDDA<0> VDDA<1> VDD<0> VDD<1> VDD<2> IN IN BI BI OUT IN BI BI BI BI BI BI BI IN OUT IN BI BI BI BI BI BI BI BI BI IN OUT BI BI BI BI IN BI BI BI BI BI IN BI BI OUT IN BI BI BI OUT IN IN IN IN IN IN IN FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 22. KSB, CLOCKS + STRAPPING + POR XTAL BYPASS: STUFF R3, R4, R5, AND C153 AND KEEP R5 CLOSE TO KSB CHIP WRITE 0011 100 0 0X38 0111 000 R/W HEX WRITE 0111 000 0 0X70 READ 0111 000 1 0X71 APPLY SQUARE WAVE TO XTAL_IN (VL=0V VH=1V) 0011 100 R/W HEX I2C ADDRESS READ 0011 100 1 0X39 0011 110 R/W HEX WRITE 0011 110 0 0X3C READ 0011 110 1 0X3D [PAGE_TITLE=KSB, CLOCKS + STRAPING] RESISTOR VALUES CHOSEN TO GIVE V_12P0_DET 1P8V NOMINAL CR-22 : @CORONA_LIB.CORONA(SCH_1):PAGE22 22/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:23 2011 5% CH 33 OHM 402 CH 33 OHM 5% 402 49.9 OHM 402 1% CH 402 49.9 OHM CH 1% 5% 33 OHM 402 CH 27 PF 5% 402 50 V COG XTAL SM 25 MHZ 402 NPO 22 PF 5% 50 V CH 1% 84.52 KOHM 402 V_12P0 402 5% CH 33 OHM CH 5% 402 33 OHM 60.4 OHM 402 CH 1% 60.4 OHM 402 CH 1% 402 5% 1 KOHM CH 5% 402 10 KOHM CH 1 KOHM 5% CH 402 CH 402 5% 10 KOHM CH 10 KOHM 1% 402 402 1% 10 KOHM CH V_3P3 49.9 OHM 1% 402 EMPTY 10% 0.01 UF 402 EMPTY 16 V 8.25 KOHM 1% EMPTY 402 EMPTY 402 1% 1.5 KOHM V_3P3STBY PBGA404 I155 IC KSB 1 OF 9 X850744-001 470 PF 402 EMPTY 50 V 5% 402 15 KOHM 1% CH CH 33 OHM 5% 402 CH 1% 49.9 OHM 402 49.9 OHM CH 1% 402 DB3R7 DB3R6 R3P16 R3P15 R3P2 R2P3 DB3D1 DB3D3 DB3D2 R3D29 R3D28 R3D26 C3D1 R3D17 R3D19 FT3R3 U3D1 R3D10 FT3P5 R3D13 R3D11 R3D8 R3D6 R3D9 R3D7 R3D12 C3D7 Y3D1 C3D8 DB2C2 R3R5 R3D3 R3D5 R3D4 R3D14 FT3R7 FT3R2 C3R55 R3R17 FT2P6 2 25 42 62 25 55 61 62 25 55 61 62 25 4 4 25 42 2 25 4 62 4 62 EXT_PCIEX_CLK_DN EXT_PCIEX_CLK_DP CPU_CLK_DP SMC_RST_N SMB_DATA PIX_CLK_2X_DN_R PIX_CLK_2X_DP_R V_12P0_DET CPU_CLK_DN_R EXT_CLK48_IN EXT_CLK48_SEL SMB_CLK POR_BYPASS SB_RST_N PIX_CLK_2X_DP PIX_CLK_2X_DN V12P0_PWRGD XTAL_OUT GPU_CLK_DN_R GPU_CLK_DP_R CPU_CLK_DN V_RST_OK XTAL_IN SB_MAIN_PWRGD SB_RST_N_R SMC_RST_N_R CPU_CLK_DP_R GPU_CLK_DP GPU_CLK_DN 1 1 2 1 2 1 2 1 2 1 1 1 1 2 1 2 1 2 1 2 1 2 1 2 1 1 AA22 AA21 AB21 V19 C5 W20 D7 A4 A5 C9 B4 U22 T22 Y15 AA15 V22 W22 C4 U21 V21 W19 Y20 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 2 1 2 1 2 1 2 1 1 1 2 1 2 1 1 DRAWING OUT OUT OUT OUT FTP BI OUT OUT IN IN BI FTP OUT FTP OUT FTP SMC_RST_N_OUT SB_RST_N* MAIN_PWR_OK V_RST_OK<DN> CPU_CLK_DP CPU_CLK_DN NB_CLK_DP NB_CLK_DN POR_BYPASS<DN> PCIEX_CLK_IN_DP PCIEX_CLK_IN_DN V_12P0_OK V_12P0_DET XTAL_VSS XTAL_IN XTAL_OUT PIX_CLK_OUT_DN PIX_CLK_OUT_DP CLK48<DN> CLK48_BYPASS<DN> SMB_CLK SMB_DATA OUT FTP FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 23. KSB, VIDEO + FAN [PAGE_TITLE=KSB, VIDEO + FAN] CUSTOM THERMAL REMAIN LOCKED LOCATION MUST CALIBRATION PADS CR-23 : @CORONA_LIB.CORONA(SCH_1):PAGE23 23/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:23 2011 10% 402 EMPTY 6.3 V 0.22 UF 1% 402 EMPTY 205 KOHM CH 402 5.11 KOHM 0.1% 0 5% 0 OHM EMPTY 402 EMPTY 402 0 OHM 5% 1 CH 1% 402 2 KOHM KSB 2 OF 9 PBGA404 IC X850744-001 100 PF 50 V 5% EMPTY 402 6.3 V 402 10% 0.1 UF EMPTY EMPTY 301 OHM 1% 603 EMPTY 0.1 UF 6.3 V 402 10% EMPTY 402 6.3 V 10% 0.1 UF EMPTY 1% 603 301 OHM EMPTY 1% 301 OHM 603 0.1 UF 10% 6.3 V EMPTY 402 301 OHM EMPTY 1% 603 EMPTY 3 4 5 8 7 6 9 10 11 13 12 14 2 FT3P1 R4G1 R4G2 R2P4 U3D1 C3R1 C3C3 R3C22 C3C2 C3C1 R3C21 R3C20 C3C4 R3C23 DB3R1 DB3P1 DB3R2 DB3P2 C3P2 ST3C1 ST3C3 ST3C4 ST3C2 ST3C5 R3P3 Q4G1 R3P11 25 40 40 40 4 4 40 40 37 40 55 37 40 55 61 36 40 40 40 37 37 37 37 37 37 40 23 61 61 64 61 64 61 64 23 61 61 64 61 64 61 64 36 38 61 4 4 SMC_PWM0 HDMI_TX2_DP HDMI_TXC_DN DAC_RSET HDMI_HPD KSB_RSET BRD_TEMP_P_DIODE GPU_HSYNC_OUT GPU_VSYNC_OUT HDMI_TX1_DP HDMI_TX1_DN HDMI_TX0_DP_R HDMI_TXC_DP_R HDMI_TX1_DP_R HDMI_DDC_CLK HDMI_DDC_DATA HDMI_TX2_DP_R BRD_TEMP_P FAN1_OUT HDMI_TX0_DN HDMI_TX0_DP HDMI_TX2_DN VID_DACD_DP VID_DACB_DP VID_DACA_DP VID_DACC_DP VID_HSYNC_OUT_R VID_VSYNC_OUT_R HDMI_TXC_DP CAL_TEMP_N BRD_TEMP_N_KSB EDRAM_TEMP_N_KSB GPU_TEMP_N_KSB CPU_TEMP_N_KSB CAL_TEMP_N BRD_TEMP_P_KSB EDRAM_TEMP_P_KSB CPU_TEMP_P_KSB GPU_TEMP_P_KSB CAL_TEMP_P FAN1_FDBK BRD_TEMP_N FAN_OP1_DP BRD_TEMP_N_DIODE PIX_DATA<14..0> GPU_PIX_CLK_1X 1 2 1 2 1 2 1 C19 M21 A16 B16 B13 C13 A14 B14 B15 C15 N21 N22 P20 P21 R21 P22 H4 H22 J21 J22 K21 K22 K20 L21 L22 G20 G21 G22 H20 H21 L20 M20 J20 B19 M22 D18 E21 F22 F21 B12 A12 D20 A20 F18 D22 H18 A21 G18 C22 G19 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 1 1 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 3 1 2 1 DRAWING OUT OUT IN OUT OUT OUT OUT OUT OUT IN IN IN IN IN IN SHORT SHORT OUT IN SHORT SHORT SHORT IN IN FTP IN OUT OUT OUT DAC_D_OUT_DP DAC_D_OUT_DN DAC_C_OUT_DP DAC_C_OUT_DN DAC_B_OUT_DP FAN_OP1_DN TEMP_N FAN_OP1_DP HDMI_HPD PIX_DATA3 HSYNC_IN PIX_DATA1 PIX_DATA0 PIX_DATA9 PIX_DATA10 PIX_DATA11 PIX_DATA12 PIX_DATA6 PIX_DATA4 PIX_DATA2 VSYNC_IN DAC_RSET PIX_DATA13 PIX_DATA14 PIX_CLK_IN PIX_DATA5 PIX_DATA7 PIX_DATA8 DAC_A_OUT_DN DAC_A_OUT_DP DAC_B_OUT_DN HSYNC_OUT VSYNC_OUT TMDS_TXC_DP TMDS_TXC_DN TMDS_TX2_DP TMDS_TX2_DN TMDS_TX0_DP TMDS_TX1_DN TMDS_TX1_DP TMDS_TX0_DN DDC_SDA DDC_SCK TEMP3_P FAN_OUT1 TEMP2_P TEMP1_P TEMP0_P TEMP4_P RSET OUT OUT OUT OUT OUT OUT OUT OUT BI BI IN IN OUT FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 24. SB_GPIO<2> NET NAME DEBUG BUS 0 DEBUG BUS BIT AUD_SPI_MISO_R AUD_SSB_R AUD_SPI_CLK_R AUD_RDY_BSBY_R SB_GPIO<3> SB_GPIO<4> SB_GPIO<5> WSS_CNTL0 FAN_TACH WSS_CNTL1 SCART_RGB 5 7 3 2 1 8 10 11 4 12 6 9 SB_GPIO<0> 1 DISABLE DEBUG OUTPUT GPIO<1> = 0 ENABLE DEBUG OUTPUT 010 JASPER GPIO<0,2,3> = 111 XENON 001 TRINITY 011 FALCON 000 CORONA [PAGE_TITLE=KSB, PCIEX + SMM GPIO + JTAG] 110 ZEPHYR A 101 ZEPHYR B 100 ZEPHYR C KSB, PCIEX + SMM GPIO + JTAG CR-24 : @CORONA_LIB.CORONA(SCH_1):PAGE24 24/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:24 2011 0.1 UF 10% 402 X5R 6.3 V 10% X5R 0.1 UF 6.3 V 402 0.1 UF X5R 402 6.3 V 10% 6.3 V 402 10% X5R 0.1 UF 402 CH 5% 0 OHM KSB X850744-001 4 OF 9 IC PBGA404 V_3P3STBY 5% 402 CH 10 KOHM 10 KOHM EMPTY 5% 402 402 5% CH 0 OHM V_3P3STBY 402 5% 10 KOHM CH 10 KOHM 402 EMPTY 5% 0 OHM 5% CH 402 402 10 KOHM 5% CH V_3P3STBY EMPTY 5% 402 10 KOHM 0 OHM 5% 402 CH 402 CH 5% 10 KOHM V_3P3STBY 10 KOHM 402 EMPTY 5% 5% CH 402 0 OHM V_3P3STBY 402 10 KOHM CH 5% CH 5% 402 0 OHM EMPTY 10 KOHM 402 5% CH 5% 47 OHM 402 5% 1 KOHM CH 402 0 EMPTY 402 5% 10 KOHM 402 1 KOHM 5% CH 402 CH 5% 1 KOHM 1 402 EMPTY 5% 10 KOHM 2 10 KOHM EMPTY 402 5% CH 1 KOHM 402 5% 3 EMPTY 402 5% 10 KOHM V_3P3 402 CH 5% 1 KOHM 5 10 KOHM 5% 402 EMPTY R2P9 DB3P3 U3D1 R3G20 R2C26 R2P5 R2G6 R2G7 R2G5 R3G3 R2C22 R2C23 R3G18 R2C24 R2C25 R3G19 R2C21 R2C1 FT3T8 FT3T7 FT3T6 FT3T4 FT3T5 R2C9 R2C13 R2C14 R2C11 R2C17 R2C12 R2C18 R2C15 R2C16 R2C19 R2C20 C3D3 C3D5 C3D4 C3D6 35 62 4 4 4 37 62 24 62 35 24 62 63 24 4 24 35 24 62 24 24 4 62 4 62 4 62 35 35 62 24 63 63 63 63 4 62 24 62 33 36 24 62 24 62 24 62 24 62 24 62 24 62 24 62 37 62 37 62 24 62 62 AUD_SPI_MOSI KER_DBG_RXD PEX_GPU_SB_L1_DN PEX_GPU_SB_L0_DP PEX_GPU_SB_L0_DN SCART_RGB SB_GPIO<4> AUD_SSB AUD_SPI_CLK_R PEX_SB_GPU_L1_DP_C SB_TDO AUD_SPI_MISO_R PEX_GPU_SB_L1_DP KER_DBG_TXD_R KSB_DEBUG AUD_SPI_MOSI_R AUD_SPI_MISO AUD_SPI_MISO_R AUD_SPI_CLK_R AUD_RDY_BSBY_R PEX_SB_GPU_L1_DP PEX_SB_GPU_L0_DP PEX_SB_GPU_L1_DN PEX_SB_GPU_L0_DP_C PEX_SB_GPU_L1_DN_C AUD_SPI_CLK AUD_RDY_BSBY KER_DBG_TXD AUD_SSB_R SB_TCLK SB_TDI SB_TRST SB_TMS PEX_SB_GPU_L0_DN PEX_SB_GPU_L0_DN_C AUD_SSB_R AUD_RST_N FAN_TACH SB_GPIO<5> AUD_SPI_MOSI_R AUD_RDY_BSBY_R SB_GPIO<3> SB_GPIO<2> SB_GPIO<1> SB_GPIO<0> WSS_CNTL1 FAN_TACH_SMM_R WSS_CNTL0 SB_GPIO<0..15> 2 1 1 A2 A3 E18 N19 U19 R19 R20 T19 AA19 AB19 AA17 AB17 Y18 AA18 Y16 AA16 G4 G3 D3 D4 E2 C1 C2 D1 F2 F3 E1 E4 E3 F4 B1 B2 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 1 1 1 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 DRAWING OUT OUT OUT OUT OUT IN IN IN IN OUT OUT IN BI BI IN OUT OUT OUT OUT UART0_TXD TST_PT GPIO15 PEX_TX1_DP PEX_TX0_DP PEX_TX1_DN PEX_TX0_DN PEX_RX1_DP PEX_RX1_DN PEX_RX0_DP PEX_RX0_DN GPIO13 GPIO14 GPIO12 GPIO11 GPIO10 GPIO8 GPIO9 GPIO6 GPIO7 GPIO5 GPIO3 GPIO4 GPIO1 GPIO2 GPIO0 UART0_RXD<UP> TCK<DN> TDO TDI<UP> TRST<DN> TMS<UP> IN IN OUT OUT OUT IN OUT IN OUT IN OUT IN OUT IN IN OUT IN IN FTP FTP FTP FTP FTP OUT OUT OUT OUT BI FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 25. 15 DEBUG BUS KSB PIN SMC_P1_GPIO1 FAN_TACH KSB, SMC DBG_LED0 PULLUP = SMC DEVELOPMENT MODE N: DBG_LED0 PULLDOWN = SMC PRODUCTION MODE SMC_P1_GPIO6 SMC_PWM0 14 SMC_P1,2,3,4 GPIOS ARE ON V3P3STBY. SMC_P0 GPIOS ARE ON 1P8VSTBY [PAGE_TITLE=KSB, SMC] 13 18 20 21 23 SMC_P3_GPIO2 17 16 22 SMC_P3_GPIO1 SMC_P2_GPIO5 SMC_P2_GPIO4 SMC_P2_GPIO3 SMC_P2_GPIO1 SMC_P2_GPIO0 DEBUG BUS BIT 19 PD: KSB JTM PU: EXT JTM CR-25 : @CORONA_LIB.CORONA(SCH_1):PAGE25 25/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:24 2011 100 KOHM 5% 402 CH 5% CH 402 100 KOHM V_1P8STBY EMPTY 402 5% 10 KOHM CH 402 5% 10 KOHM 5% 0 OHM 402 EMPTY 5% 1 KOHM 402 CH 1% 402 1.27 KOHM CH V_3P3STBY V_3P3STBY 402 1.27 KOHM 1% CH 10 KOHM CH 5% 402 10 KOHM 402 CH 5% 402 CH 5% 10 KOHM 10 KOHM 5% CH 402 10 KOHM 402 CH 5% CH 402 5% 33 OHM 402 CH 5% 0 OHM IC 5 OF 9 KSB PBGA404 X850744-001 I189 1% 402 2 KOHM EMPTY 2 KOHM 402 1% CH V_3P3STBY 5% 402 1 KOHM CH 10% 1 UF 16 V X5R 603 5% CH 402 47 OHM CH 402 5% 10 KOHM R3R12 R3R10 DB3R5 R2C27 DB1E2 DB2D1 FT2P4 R3C14 FT3P2 FT2P2 R2P1 R2P2 FT2P3 R2C5 DB2C1 R2M1 R3N5 R3C18 R3P4 R3C19 DB3C3 R3C3 DB2P1 DB3R3 DB3R4 DB5B4 DB2E3 DB2E2 DB3C1 U3D1 FT2P1 R2G4 R2G3 DB2G3 R3E6 C3P9 R3C16 R3E7 R3R7 R3R8 36 4 2 63 23 62 22 61 50 50 49 47 63 38 62 49 47 52 22 38 42 38 48 35 37 22 35 41 44 63 41 44 22 55 61 62 22 55 61 62 22 38 37 37 36 62 46 48 37 62 63 4 2 38 38 SMC_PWM1 GPU_RST_N CPU_PWRGD SMC_PWM0 AV_MODE2_R SMC_DBG_RXD SMC_RST_N EXT_TEMP_PWR_CTRL VREG_VMEM_PWRGD VREG_VMEM_EN VREG_VEDRAM_EN SMC_DBG_TXD_R VREG_V5P0_EN DBG_LED0 BINDSW_N SMC_DBG_TXD VREG_VEDRAM_PWRGD VREG_V5P0_PWRGD EXT_PWR_ON_N_R VREG_1P2_EN SB_RST_N TRAY_OPEN_R PSU_V12P0_EN PWRSW_N VREG_V3P3_EN TILTSW_N AV_MODE2 SB_MAIN_PWRGD IR_DATA TRAY_STATUS VREG_CPUCORE_PWRGD SMC_CPU_CHKSTOP_DETECT TRAY_OPEN VREG_CPU_EN SB_MAIN_PWRGD_R SMB_DATA SMB_CLK V12P0_PWRGD EJECTSW_N AV_MODE0 AV_MODE1 FAN_TACH SMC_DBG_EN AV_MODE1_R FAN_TACH_SMC_R AV_MODE0_R VREG_1P2_EN_R VREG_V5P0_SEL VREG_V3P3_PWRGD EXT_PWR_ON_N GPU_RST_DONE GPU_RST_DONE_R EXT_JTM_SEL SMC_P0_GPIO5 CPU_RST_N BORONFPM_CLK BORONFPM_DATA 2 1 2 1 1 2 1 1 1 1 2 1 1 1 2 1 2 1 1 2 1 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 1 1 1 1 1 A7 A6 D8 D10 D11 A8 B8 B7 C8 C6 A9 B5 B6 A11 C10 B11 B9 C11 C12 D12 B10 W12 W13 Y11 AB11 AB10 AA11 AA12 Y12 W11 V9 AA10 Y10 Y9 W10 AB9 W9 Y13 AA14 W14 AB15 AB13 AB14 Y14 AA13 W8 D6 1 2 1 2 1 1 2 1 2 1 2 1 2 1 2 1 DRAWING OUT OUT BI IN OUT IN OUT IN IN IN OUT FTP IN BI IN FTP OUT BI BI OUT FTP IN FTP IN IN OUT IN OUT OUT IN OUT IN OUT IN OUT IN BI OUT OUT IN IN SMC_DBG<DN> SMC_UART1_RXD<UP> SMC_UART1_TXD SMC_P2_GPIO7 SMC_P2_GPIO6 SMC_P2_GPIO5 SMC_P2_GPIO2 SMC_P2_GPIO4 SMC_P2_GPIO3 SMC_P2_GPIO0 SMC_P2_GPIO1 SMC_P1_GPIO7 SMC_P1_GPIO6 SMC_P1_GPIO5 SMC_P1_GPIO4 SMC_P1_GPIO2 SMC_P1_GPIO3 SMC_P1_GPIO1 SMC_P1_GPIO0 SMC_RST_N_IN* SMC_P4_GPIO7 SMC_P4_GPIO5 SMC_P4_GPIO6 SMC_P4_GPIO4 SMC_P0_GPIO7 SMC_P0_GPIO6 SMC_P4_GPIO2 SMC_P4_GPIO3 SMC_P4_GPIO1 SMC_P4_GPIO0 SMC_P3_GPIO7 SMC_P3_GPIO5 SMC_P3_GPIO6 SMC_P3_GPIO2 SMC_P0_GPIO0 SMC_PWM1 SMC_IR_IN SMC_P3_GPIO0 SMC_P3_GPIO1 SMC_P3_GPIO3 SMC_P3_GPIO4 SMC_PWM0 SMC_P0_GPIO2 SMC_P0_GPIO1 SMC_P0_GPIO3 SMC_P0_GPIO4 SMC_P0_GPIO5 OUT OUT IN FTP OUT IN OUT IN IN FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 26. STITCHING CAPS FOR USB ON PLANE SPLIT KSB, FLASH + USB + SPI N: ALL PORTS ARE DIFFERENTIAL USB PAIRS ON THIS PAGE [PAGE_TITLE=KSB, FLASH + USB + SPI] CR-26 : @CORONA_LIB.CORONA(SCH_1):PAGE26 26/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:24 2011 0.1 UF 6.3 V X5R 402 10% X5R 0.1 UF 6.3 V 402 10% 0.1 UF X5R 6.3 V 402 10% V_5P0STBY EMPTY TH 6 OF 9 KSB PBGA404 X850744-001 IC 33 OHM CH 5% 402 0 1 2 3 4 6 5 7 1% 10 OHM 402 CH 0.1 UF X5R 6.3 V 10% 402 0.1 UF 6.3 V X5R 10% 402 6.3 V 0.1 UF X5R 10% 402 R3R9 C2T3 C2T1 C2T2 C2R12 C2R11 C2R13 J1D1 U3D1 R2C8 39 32 34 63 32 34 34 34 34 39 39 38 39 39 39 39 39 39 39 38 38 34 63 32 34 38 62 62 39 39 62 62 32 63 34 47 WAVEPORT_DP FLSH_CE_N FLSH_CLE FLSH_CE_N_R FLSH_WE_N FLSH_ALE FLSH_RE_N GAMEPORT2_DP GAMEPORT2_DN BORONFPMPORT_DP WAVEPORT_DN V_VREG_V3P3_V5P0 EXPPORT_PORT3_DP EXPPORT_PORT3_DN EXPPORT_PORT2_DP EXPPORT_PORT2_DN EXPPORT_PORT1_DP EXPPORT_PORT1_DN EXPPORT_RJ45_DP EXPPORT_RJ45_DN FLSH_READY FLSH_WP_N BORONFPMPORT_DN SPI_CLK SPI_MOSI GAMEPORT1_DP GAMEPORT1_DN SPI_MISO SPI_SS_N SPI_MISO_R USBB_D1_DP USBB_D1_DN FLSH_DATA<7..0> 2 1 2 1 2 1 2 1 2 1 2 1 2 1 5 4 3 2 1 U2 U1 N2 N1 T3 T2 P3 P2 R2 R1 J2 J1 M3 M2 K3 K2 L2 L1 W5 W4 W7 W6 AB5 Y5 AB2 AB3 Y6 AA6 AB6 Y7 AA7 Y8 AA8 AB8 AB4 AA5 AA4 2 1 DRAWING 1X5HDR SPI_MISO FLSH_DATA1 USBA_D1_DP USBA_D1_DN USBA_D0_DP USBA_D0_DN USBA_D2_DP USBA_D2_DN USBA_D3_DP USBA_D3_DN FLSH_READY FLSH_WP_N* USBB_D0_DN USBB_D0_DP USBB_D1_DN USBB_D2_DN USBB_D1_DP USBB_D2_DP USBB_D3_DN USBB_D3_DP USBB_D4_DN USBB_D4_DP FLSH_DATA0 FLSH_DATA2 FLSH_DATA4 FLSH_DATA3 FLSH_DATA5 FLSH_DATA6 FLSH_DATA7 SPI_SS_N*<UP> SPI_CLK SPI_MOSI FLSH_ALE FLSH_WE_N* FLSH_RE_N* FLSH_CE_N* FLSH_CLE BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI OUT OUT OUT OUT OUT OUT IN OUT BI IN IN IN FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 27. [PAGE_TITLE=KSB, ETHERNET + AUDIO + SATA] KSB, ETHERNET + AUDIO + SATA STITCHING CAPS FOR I2S SIGNALS,PARTICULARLY MCLK. PLACE AS CLOSE AS POSSIBLE TO I2S_MCLK, I2S_BCLK, I2S_SD, AND I2S_WS. CR-27 : @CORONA_LIB.CORONA(SCH_1):PAGE27 27/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:25 2011 X5R 0.1 UF 10% 6.3 V 402 V_1P2STBY V_3P3STBY 0.1 UF 402 10% 6.3 V X5R X5R 10% 6.3 V 0.1 UF 402 402 X5R 6.3 V 0.1 UF 10% 0 OHM CH 402 5% PBGA404 IC X850744-001 KSB 7 OF 9 CH 5% 402 10 KOHM CH 10 KOHM 402 5% 10 KOHM CH 402 5% 47 OHM 402 5% CH 402 47 OHM 5% CH CH 5% 47 OHM 402 402 CH 47 OHM 5% C3P35 C3P34 C3P33 C3P32 R3P20 U3D1 R3P13 R3P12 R3P19 R3P8 R3P10 R3P9 R3P14 37 39 41 41 41 41 41 41 38 41 33 33 33 41 38 33 38 38 SPDIF_OUT SPDIF_OUT_R I2S_BCLK_R I2S_SD_R I2S_WS_R ODD_RX_DN ODD_RX_DP ODD_TX_DN ODD_TX_DP HDD_TX_DN HDD_RX_DN ENET_TX_DN HDD_TX_DP I2S_MCLK I2S_SD I2S_WS HDD_RX_DP ENET_RX_DP I2S_BCLK I2S_MCLK_R ENET_TX_DP ENET_RX_DN 2 1 2 1 2 1 2 1 2 1 D16 AA2 AA1 Y2 Y3 W2 W1 V2 V3 H3 G2 H2 G1 C17 A17 B18 B17 2 1 2 1 2 1 DRAWING SATA0_TX_DN SATA0_TX_DP SATA1_TX_DN SATA1_TX_DP MDIN1 MDIP1 SATA0_RX_DP SATA0_RX_DN SATA1_RX_DN SATA1_RX_DP SPDIF_OUT I2S_WS I2S_SD I2S_MCLK_OUT I2S_BCLK_OUT MDIN0 MDIP0 BI BI BI BI IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 28. [PAGE_TITLE=KSB, DECOUPLING] KSB,DECOUPLING CR-28 : @CORONA_LIB.CORONA(SCH_1):PAGE28 28/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:24 2011 VAA_3P3_VDAC VAA_3P3STBY_USB 6.3 V 402 X5R 10% 0.1 UF 402 6.3 V 10% 0.1 UF X5R 0.1 UF 402 6.3 V X5R 10% 402 6.3 V 10% X5R 0.1 UF 402 X5R 0.1 UF 10% 6.3 V 402 0.1 UF 6.3 V X5R 10% X5R 0.1 UF 10% 6.3 V 402 10% 0.01 UF 16 V X7R 402 X7R 16 V 10% 402 0.01 UF V_3P3_ANA V_3P3STBY_ANA V_1P8_ANA V_1P2STBY V_3P3STBY 402 0.01 UF 16 V X7R 10% 0.01 UF 402 10% 16 V X7R 10% 402 16 V X7R 0.01 UF X7R 402 0.01 UF 10% 16 V 402 X7R 16 V 10% 0.01 UF 16 V 0.01 UF 10% X7R 402 402 X7R 16 V 0.01 UF 10% 0.1 UF 6.3 V 402 X5R 10% 0.1 UF X5R 6.3 V 402 10% 0.1 UF X5R 6.3 V 10% 402 0.1 UF X5R 6.3 V 402 10% 0.1 UF X5R 6.3 V 402 10% 0.1 UF X5R 6.3 V 10% 402 0.1 UF X5R 6.3 V 10% 402 X5R 6.3 V 0.1 UF 402 10% 402 0.01 UF 10% X7R 16 V 10% 0.01 UF 16 V X7R 402 402 X7R 10% 16 V 0.01 UF 0.01 UF 16 V 402 X7R 10% 0.01 UF 402 X7R 10% 16 V 16 V X7R 402 10% 0.01 UF 0.01 UF 16 V 402 X7R 10% 10% 0.01 UF X7R 16 V 402 0.01 UF 16 V X7R 402 10% 0.01 UF X7R 16 V 10% 402 0.01 UF X7R 16 V 10% 402 X7R 0.01 UF 16 V 402 10% 16 V 0.01 UF X7R 402 10% 6.3 V X5R 0.1 UF 402 10% 6.3 V 0.1 UF 10% X5R 402 0.1 UF 402 X5R 6.3 V 10% 0.1 UF X5R 6.3 V 402 10% 6.3 V 402 X5R 10% 0.1 UF 0.1 UF 402 X5R 6.3 V 10% 0.1 UF 10% 6.3 V X5R 402 0.1 UF 402 X5R 6.3 V 10% V_3P3 402 16 V 0.01 UF 10% X7R 0.01 UF 10% 16 V X7R 402 402 X7R 16 V 0.01 UF 10% 10% 0.01 UF 16 V X7R 402 0.01 UF 16 V 10% X7R 402 0.01 UF 402 X7R 10% 16 V 0.01 UF 10% 16 V 402 X7R 0.01 UF 10% 402 X7R 16 V 16 V 402 0.01 UF 10% X7R 16 V 0.01 UF 10% X7R 402 0.01 UF 16 V 10% X7R 402 0.01 UF 16 V X7R 402 10% 6.3 V 402 10% X5R 0.1 UF 0.1 UF 10% 402 X5R 6.3 V 402 6.3 V X5R 10% 0.1 UF 0.1 UF 10% 402 X5R 6.3 V 6.3 V 10% 0.1 UF 402 X5R 402 0.1 UF 6.3 V X5R 10% X5R 10% 0.1 UF 6.3 V 402 X5R 402 0.1 UF 6.3 V 10% X5R 402 6.3 V 10% 0.1 UF 0.1 UF 10% X5R 402 6.3 V 6.3 V 10% 0.1 UF X5R 402 0.1 UF 6.3 V X5R 10% 402 6.3 V 402 X5R 0.1 UF 10% 0.1 UF 6.3 V X5R 402 10% 0.1 UF 6.3 V 402 X5R 10% 6.3 V 10% 0.1 UF 402 X5R 402 X5R 6.3 V 10% 0.1 UF V_1P8 V_1P2 C2R7 C3R28 C3R38 C3R21 C3R11 C2R5 C3R50 C3P16 C3P7 C3R30 C3P31 C3R3 C3R12 C3R10 C3R13 C3R17 C3R5 C3P27 C3R6 C3R14 C3R23 C3R9 C3R18 C3R24 C3P28 C3R22 C3P30 C3R25 C3R27 C3P29 C3R29 C3R20 C3R7 C3R8 C3R39 C3R15 C3P24 C3R16 C3R19 C3R37 C3P20 C3R36 C3R31 C3P12 C3P22 C3P18 C3P14 C3P10 C3R41 C3P21 C3R34 C3R43 C3R40 C3P23 C3P17 C3P19 C2P3 C3R42 C3P25 C3R32 C3P15 C3P13 C3P11 C2R8 C3R45 C3R44 C2R10 C2R2 C3P26 C3R46 C2R4 C2R1 C3R2 C3R26 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 DRAWING FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 29. [PAGE_TITLE=KSB, BULK DECOUPLING] KSB, BULK DECOUPLING CR-29 : @CORONA_LIB.CORONA(SCH_1):PAGE29 29/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:25 2011 6.3 V X5R 10% 603 4.7 UF V_1P2STBY 6.3 V X5R 603 4.7 UF 10% 603 X5R 6.3 V 10% 4.7 UF 6.3 V 4.7 UF 10% 603 X5R 6.3 V X5R 4.7 UF 10% 603 V_3P3STBY 6.3 V X5R 4.7 UF 10% 603 6.3 V X5R 4.7 UF 10% 603 V_3P3 10% 6.3 V X5R 4.7 UF 603 X5R 6.3 V 4.7 UF 10% 603 6.3 V X5R 4.7 UF 10% 603 6.3 V X5R 4.7 UF 10% 603 V_1P2 603 X5R 6.3 V 10% 4.7 UF X5R 6.3 V 4.7 UF 10% 603 4.7 UF 10% 6.3 V X5R 603 C3P36 C3P1 C3T1 C3R53 C3T2 C3R54 C2P1 C3N43 C2P2 C3N44 C3N42 C3C8 C4C2 C4C6 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 DRAWING FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 30. KSB, STANDBY POWER + GROUND [PAGE_TITLE=KSB, STANDBY POWER] CR-30 : @CORONA_LIB.CORONA(SCH_1):PAGE30 30/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:17 2011 V_3P3STBY_ANA V_3P3STBY V_1P2STBY V_1P8STBY 6.3 V 0.1 UF 10% X5R 402 V_5P0STBY AO3414L SOT23 FET 10 KOHM 5% CH 402 EMPTY 402 0 OHM 5% KSB 9 OF 9 IC PBGA404 X850744-001 0 OHM 402 CH 5% X850744-001 8 OF 9 IC KSB PBGA404 4.7 UF 10% 603 6.3 V X5R V_3P3STBY 603 6.3 V 4.7 UF 10% X5R 4.7 UF 10% 6.3 V X5R 603 0.5A 0.1DCR 603 FB X5R 603 4.7 UF 6.3 V 10% V_3P3STBY 4.7 UF 6.3 V X5R 603 10% VAA_3P3STBY_USB 603 FB 0.5 DCR 0.2A CH 5% 0 OHM 402 Q2R1 R2R4 R2R3 U3D1 R3R6 U3D1 C3R52 C2R6 FB2R1 C2R3 C3R51 FB3R1 C3R35 C3R47 R3R2 VAA_3P3STBY_USB_FET VDD_3P3_LDO18 VDD18_OUT_CAP VAA_3P3STBY_USB_FET_EN 2 3 1 2 1 2 1 AB22 R22 Y21 T21 U20 N20 P19 M19 K19 J19 AB18 W18 T18 L18 A18 V17 AB16 W16 C16 R15 N15 L15 H15 A15 P14 N14 M14 L14 K14 J14 E14 D14 C14 R13 P13 N13 M13 L13 K13 J13 A13 AB12 V12 P12 N12 M12 L12 K12 J12 H12 E12 P11 N11 M11 L11 K11 J11 H11 R10 P10 N10 M10 L10 K10 J10 A10 AA9 P9 N9 M9 L9 K9 J9 D9 R8 N8 L8 H8 AB7 E7 C7 V5 T5 R5 M5 K5 D5 Y4 U4 R4 N4 L4 J4 B3 D2 AB1 Y1 V1 T1 P1 M1 K1 H1 F1 A1 2 1 V13 V18 V11 E11 E10 V7 V6 U18 M18 V10 E9 V8 E8 U5 P5 N5 L5 J5 V14 V15 Y22 T4 P4 M4 K4 U3 R3 N3 L3 J3 AB20 P18 F19 H5 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 DRAWING VSS[97] VSS[99] VSS[101] VSS[102] VSS[0] VSS[47] VSS[51] VSS[50] VSS[52] VSS[49] VSS[48] VSS[45] VSS[46] VSS[44] VSS[42] VSS[43] VSS[41] VSS[40] VSS[39] VSS[103] VSS[104] VSS[100] VSS[98] VSS[95] VSS[96] VSS[94] VSS[92] VSS[93] VSS[37] VSS[38] VSS[36] VSS[34] VSS[35] VSS[33] VSS[32] VSS[31] VSS[29] VSS[30] VSS[28] VSS[27] VSS[26] VSS[24] VSS[25] VSS[23] VSS[22] VSS[21] VSS[20] VSS[19] VSS[18] VSS[17] VSS[16] VSS[14] VSS[15] VSS[13] VSS[11] VSS[12] VSS[9] VSS[10] VSS[8] VSS[6] VSS[7] VSS[4] VSS[5] VSS[3] VSS[2] VSS[1] VSS[90] VSS[91] VSS[89] VSS[87] VSS[88] VSS[85] VSS[86] VSS[84] VSS[83] VSS[82] VSS[80] VSS[81] VSS[79] VSS[77] VSS[78] VSS[75] VSS[76] VSS[74] VSS[72] VSS[73] VSS[71] VSS[70] VSS[69] VSS[67] VSS[68] VSS[66] VSS[64] VSS[65] VSS[63] VSS[62] VSS[61] VSS[59] VSS[60] VSS[57] VSS[58] VSS[56] VSS[55] VSS[54] VSS[53] AVDD_33S_USB[1] AVDD_33S_USB[2] AVDD_33S_USB[3] VDD_33S_LDO18 VDD_33S[0] VDD_33S[1] VDD_33S[2] VDD_33S[5] VDD_12S[0] VDD_12S[1] VDD_12S[2] VDD_12S[3] VDD_12S[5] VDD_12S[4] VDD_12S[6] VDD_12S[7] VDD_12S[8] VDD_12S[9] VDD_12S[10] LDO18_CAP VDD18S_IN AVDD_33S_USB[0] AVDD_33S_USB[5] AVDD_33S_USB[8] AVDD_33S_FAN AVDD_33S_JTM AVDD_33S_BG AVDD_33S_USB[7] AVDD_33S_USB[6] AVDD_33S_USB[4] AVDD_33S_XTAL AVDD_33S_PLLB VDD_33S[4] VDD_33S[3] FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 31. [PAGE_TITLE=KSB, MAIN POWER] KSB, MAIN POWER CR-31 : @CORONA_LIB.CORONA(SCH_1):PAGE31 31/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:18 2011 EMPTY SOT23 AO3414L V_5P0 0 OHM 402 CH 5% 402 EMPTY 10 KOHM 5% EMPTY 5% 10 KOHM 402 0 CH 603 0 OHM VAA_3P3_VDAC V_3P3 603 6.3 V X5R 10% 4.7 UF 300 0.45 OHM 603 FB 603 X5R 10% 6.3 V 4.7 UF 0 603 CH 0 OHM 0 OHM 5% 402 CH V_2P5 0 OHM 5% CH 402 V_3P3_ANA V_3P3 4.7 UF 10% 603 X5R 6.3 V V_3P3 603 4.7 UF 6.3 V X5R 10% V_1P2 V_1P8 0.1 UF X5R 10% 6.3 V 402 X5R 6.3 V 603 4.7 UF 10% 0.1DCR 0.5A FB 603 X5R 4.7 UF 6.3 V 10% 603 V_1P8_ANA V_1P8 603 4.7 UF X5R 10% 6.3 V 0.5 DCR 0.2A 603 FB X5R 10% 6.3 V 4.7 UF 603 IC KSB 3 OF 9 X850744-001 PBGA404 Q2P1 R2P6 R2P7 R2P8 R3P17 C3P6 FB3P1 C3P4 R3R4 R3R3 R3R1 C3R33 C3R48 C3R49 C2R9 FB3P2 C3P5 C3R4 FB3P3 C3P8 U3D1 47 VAA_3P3_HDMI VAA_3P3_HDMI_FET_EN VAA_3P3_LDO25 VSS_PLLA VSS_PLLB V_VREG_V3P3_V5P0 VDD25_OUT_CAP 2 3 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 E22 A22 D21 C21 B21 F20 B20 E19 D19 AA20 E17 C18 D17 E6 F5 E5 C3 L19 H19 R18 N18 K18 J18 P15 M15 K15 J15 R14 H14 H13 R12 R11 H10 R9 H9 P8 M8 K8 J8 W17 Y19 Y17 W15 B22 E20 C20 A19 V4 AA3 W3 E16 V16 E15 D15 G5 W21 V20 T20 E13 D13 DRAWING IN AVDD_33_CLK[0] AVDD_33_SATA[2] AVDD_33_SATA[1] VDD_33[3] VDD_33[4] VDD_33[5] VDD_33[2] VDD_33[1] VDD_33[0] VDD_18[5] VDD_18[4] VDD_18[2] VDD_18[3] VDD_18[1] VDD_18[0] VDD_12[15] VDD_12[14] VDD_12[13] VDD_12[12] VDD_12[11] VDD_12[10] VDD_12[9] VDD_12[8] VSS_PLLB VSS_PLLA VSS_VDAC[8] VSS_VDAC[7] VSS_VDAC[6] VSS_VDAC[4] VSS_VDAC[5] VSS_VDAC[3] VSS_VDAC[2] VSS_VDAC[1] VSS_VDAC[0] VDD_12[7] VDD_12[6] VDD_12[5] VDD_12[4] VDD_12[3] VDD_12[2] VDD_12[0] VDD_12[1] AVDD_18_HDMI[1] AVDD_18_HDMI[0] AVDD_33_LDO25 AVDD_33_VDAC[3] AVDD_33_VDAC[2] AVDD_33_VDAC[0] AVDD_33_VDAC[1] AVDD_33_CLK[1] AVDD_33_CLK[2] AVDD_33_SATA[0] AVDD_33_ENET AVDD_33_HDMI[0] AVDD_33_HDMI[1] AVDD_33_PLLA LDO25_CAP AVDD_PEX[2] AVDD_PEX[1] AVDD_PEX[0] FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 32. PULL DOWN RESISTOR AS A PROVISION TO PREVENT CLK GLITCHES IF NEEDED [PAGE_TITLE=MMC + FLASH] GND IN FUTURE REVISIONS NC IN DATASHEET BUT MAYBE REMOVE IN FUTURE FAB REVISIONS DECOUPLING FOR TOSHIBA NAND ONLY ALL COMPONENTS ON THIS PAGE IS FOR MMC MODE. TO BE STUFFED/UNSTUFFED AT CONFIG LEVEL MMC + FLASH CR-32 : @CORONA_LIB.CORONA(SCH_1):PAGE32 32/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:18 2011 CH 49.9 KOHM 402 1% CH 49.9 KOHM 1% 402 CH 1% 402 49.9 KOHM CH 402 1% 49.9 KOHM V_3P3STBY CH 1% 49.9 KOHM 402 0 2 1 3 4 5 6 7 X853492-001 IC CH 5% 1 KOHM 402 X853009-001 LGA51 IC CH 2.2 KOHM 5% 402 0.1 UF 6.3 V X5R 402 10% 0.1 UF 402 X5R 6.3 V 10% 603 10% 4.7 UF 6.3 V X5R 6.3 V 402 X5R 0.1 UF 10% 4 3 2 1 7 5 6 0 V_3P3STBY V_3P3STBY V_3P3STBY 5% 0 OHM 402 CH 5% CH 0 OHM 402 0 OHM 5% CH 402 V_3P3STBY V_3P3STBY 10% 6.3 V 0.1 UF 402 X5R 402 6.3 V 10% 0.1 UF X5R 402 0.1 UF 10% 6.3 V X5R 402 10% 6.3 V 0.1 UF X5R 0.1 UF 10% X5R 6.3 V 402 402 1% EMPTY 10 KOHM 10% 6.3 V X5R 603 2.2 UF 603 X5R 2.2 UF 10% 6.3 V 6.3 V 10% 402 X5R 0.1 UF CH 49.9 KOHM 402 1% V_3P3STBY CH 402 1% 49.9 KOHM CH 49.9 KOHM 1% 402 CH 402 49.9 KOHM 1% 6.3 V 402 X5R 10% 0.1 UF R1E4 R1E3 R1E2 C1E11 C1E6 C2E9 C1E13 R1R10 C1E8 DB1R1 R1R2 R2R2 R1R5 R1R9 R1R4 R1R8 R1R3 R1R7 R1R6 U1T1 FT1R3 FT1R4 R1R1 U1E3 R1E1 C2E1 C1E12 C1E16 C1E10 C1E7 C1E15 C1E9 C1E14 63 26 63 26 26 26 63 26 32 63 34 26 32 63 34 MMC_SD_SEL MMC_DV_CARD MMC_EMBED_SEL MMC_RST_N FLSH_WP_N MMC_RSTCLK MMC_ISOLT FLSH_CE_N MMC_FLSH_RE_N MMC_FLSH_ALE MMC_FLSH_DATA3 MMC_FLSH_DATA2 MMC_FLSH_DATA1 FLSH_CLE MMC_FLSH_DATA0 MMC_FLSH_CE0_N MMC_FLSH_CLE FLSH_WP_N MMC_FLSH_WP_N MMC_FLSH_READY MMC_FLSH_DATA4 MMC_FLSH_DATA5 MMC_FLSH_DATA6 MMC_FLSH_DATA7 MMC_V12 MMC_FLSH_CE1_N MMC_FLSH_WE_N FLSH_DATA<7..0> FLSH_DATA<7..0> 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 19 18 36 13 37 12 8 6 7 21 20 15 14 11 5 4 48 47 46 45 40 39 38 3 35 34 33 28 27 26 25 24 23 22 2 1 44 43 42 41 32 31 30 29 16 10 9 17 1 1 2 1 10 9 19 49 3 18 14 39 51 47 50 48 29 20 40 11 12 38 37 36 35 41 42 43 44 33 34 8 13 45 46 1 2 4 5 6 7 31 32 30 28 23 24 17 15 26 27 21 22 16 25 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 DRAWING BI NAND 2 CE NC19 VCC1 VCC0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 CE2_N* CE1_N* RE_N* WE_N* WP_N* ALE CLE VSS1 VSS0 RDY2 RDY1 NC26 NC25 NC24 NC23 NC22 NC21 NC20 NC18 NC17 NC16 NC15 NC14 NC13 NC12 NC11 NC10 NC9 NC8 NC7 NC6 NC5 NC4 NC3 NC2 NC1 NC0 FTP FTP IN PHISON PS8200 V1 FBD3 MMC_SD_SEL DV_CARD EMBED_SEL LOCK_RST_N* FAWRB_N* FAWP_N* FAALE FARDB_N* FACLE NC VIOM VCC3IOM VCC3IO TEST_ISOLT GNDA VCCK VDT_FLH TEST_RSTCLK TEST_MODE CLK CMD DAT7 DAT6 DAT5 DAT4 DAT3 DAT2 DAT1 DAT0 FBD6 FBD5 FBD4 FBD2 FBD1 FBD0 FAD6 FAD5 FAD4 FAD3 FAD2 FAD1 FAD0 FARDY FCEB1 FCEB0 XRST_FCEB2 XCLK_FCEB3 FBD7 FAD7 VCCAH BI IN IN OUT IN FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 33. [PAGE_TITLE=PSB OUT, AUDIO] KSB OUT, AUDIO DBPADS ON I2S TO BE PLACED AS CLOSE TO AUDIO DAC AS POSSIBLE CR-33 : @CORONA_LIB.CORONA(SCH_1):PAGE33 33/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:20 2011 402 CH 5% 1 KOHM CH 10 KOHM 1% 402 CH 402 10 KOHM 1% 1 UF X5R 10% 16 V 603 X5R 10% 10 UF 10 V 805 805 % 0 OHM CH 1.33 KOHM 402 CH 1% 1.33 KOHM 402 1% CH 603 0.7DCR 0.2 402 X7R 10% 1000 PF 50 V 402 X7R 10% 50 V 1000 PF 0.2 0.7DCR 603 X5R 10 V 10% 402 0.15 UF 10 UF 10% 10 V X5R 805 603 6.3 V 10% X5R 2.2 UF 10% 603 X5R 1 UF 16 V 10% X5R 0.15 UF 402 10 V X5R 6.3 V 10% 603 2.2 UF 6.3 V 603 10% X5R 2.2 UF 10% 603 X5R 6.3 V 2.2 UF 402 X5R 10% 0.1 UF 6.3 V 6.3 V 402 X5R 10% 0.1 UF 402 6.3 V 10% 0.1 UF X5R V_3P3 IC QFN25 X851154-002 AUDIODAC_CSS4354_WM1824 DB3A3 DB3A2 DB3A4 DB3B1 R3A11 R3A10 C3M6 C3M3 FT3N3 R3B22 R3A9 R3A8 FB3A2 C3A4 C3A3 FB3A1 C3A10 C3M2 C3A9 C3M4 C3A8 C3N41 C3A6 C3B11 C3B12 C3A5 C3A7 R3M6 U3A1 24 37 37 27 27 27 27 AUD_RST_N V_AUD_FILT_N AUD_R_OUT AUD_VOUTR_R AUD_VOUTL_R AUD_L_OUT V_AUD_FLYN_N V_AUD_FLYN_P AUD_VOUTR AUD_VOUTL V_AUD_FLYP_N V_AUD_FLYP_P V_AUD_FILT_P V_AUD_BIAS V_AUD I2S_MCLK I2S_BCLK I2S_WS I2S_SD 1 1 1 1 2 1 2 1 2 1 2 1 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 3 8 12 6 18 17 24 1 19 22 25 2 23 7 5 9 11 4 21 10 13 15 14 16 20 DRAWING IN FTP IN OUT OUT IN IN IN DEM NC PS_N/LJ AIFMODE RESET MUTE LRCK LRCLK SCLK BCLK SDIN DACDAT MCLK MCLK 1_2VRMS NC VL DBVDD VCP LINEVDD VA AVDD CPGND LINEGND ME GNDPAD DGND NC AGND AGND FLYN CPCB VFILT CPVOUTN FLYN_P CPCA AOUT_REF NC AOUTB LINEVOUTR AOUTA LINEVOUTL FLYP NC FLYP_P NC VFILT_P NC VBIAS VMID FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8
- 34. ALL COMPONENTS ON THIS PAGE IS FOR MAMD MODE. TO BE STUFFED/UNSTUFFED AT CONFIG LEVEL 0X0 0.5KB, 16KB BLOCKS, 128MBIT 0X1 0.5KB, 16KB BLOCKS, 512MBIT 0X2 2KB PAGES, 128KB BLOCKS, 1/2/4 GBIT 0X3 4KB PAGES, 256KB BLOCKS, 2/4/8 GBIT XDK XDK RETAIL NAND BOOTSTRAP FOR KSB FLSH_DATA[1:0] FLASH CONFIGURATION RETAIL N: STUFFED AT CONFIG LEVEL KSB OUT, FLASH [PAGE_TITLE=PSB OUT, FLASH] CR-34 : @CORONA_LIB.CORONA(SCH_1):PAGE34 34/87 1.01 CORONA_XDK_4L E Thu Feb 17 10:12:25 2011 V_3P3STBY I97 402 I96 CH 5% 2.2 KOHM 5% CH 402 10 KOHM 3 5 4 7 6 V_3P3STBY CH 5% 402 10 KOHM 402 5% CH 10 KOHM EMPTY 402 10 KOHM 5% EMPTY 5% 402 10 KOHM 0 OHM 402 EMPTY 5% CH 5% 402 10 KOHM 402 CH 5% 10 KOHM 5% 402 CH 10 KOHM 5% 10 KOHM CH 402 CH 5% 10 KOHM 402 10 KOHM 402 5% CH 603 4.7 UF 10% 6.3 V X5R IC X818098-001 TSOP 10 KOHM 5% CH 402 402 10% X5R 6.3 V 0.1 UF X5R 402 6.3 V 10% 0.1 UF 0 2 1 R2R1 R1D1 FT1R1 FT2T12 FT2T11 FT2T10 FT2T8 FT2T5 FT2T4 FT2T3 FT2T2 R1D2 R2T14 R2T11 R2T8 R2T1 R2T2 R2T6 R2T7 R2T9 R2T10 C1D1 U1E2 C1E17 C2T18 R2T13 R2T12 26 26 26 26 26 63 26 26 26 32 63 FLSH_RE_N FLSH_WE_N FLSH_ALE FLSH_CLE FLSH_WP_N FLSH_CE_N FLSH_READY FLSH_NC38 FLSH_DATA<7..0> 1 2 2 1 1 1 1 1 1 1 1 1 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 19 18 36 13 6 37 12 8 7 38 48 47 46 45 40 39 35 34 33 28 27 26 25 24 23 22 21 20 15 14 11 10 5 4 3 2 1 44 43 42 41 32 31 30 29 16 9 17 2 1 2 1 2 1 2 1 DRAWING FTP FTP FTP FTP FTP FTP FTP FTP FTP NAND FLASH VCC1 VCC0 DATA<7> DATA<6> DATA<5> DATA<4> DATA<3> DATA<2> DATA<1> DATA<0> WE_N* WP_N* ALE VSS0 VSS1 VSS/NC CLE RE_N* NC<0> NC<1> NC<2> NC<3> NC<4> NC<5> NC<6> NC<7> NC<8> NC<9> NC<10> NC<11> NC<12> NC<13> NC<14> NC<15> NC<16> NC<17> NC<18> NC<19> NC<20> NC<21> NC<22> NC<23> NC<24> NC<25> NC<26> NC<27> RDY CE_N* IN IN IN IN IN IN IN OUT FAB PROJECT NAME CONFIDENTIAL MICROSOFT REV PAGE A C D B A C B D 8 7 6 5 4 3 2 1 7 6 5 4 3 2 1 8