Verilog has blocking and non-blocking statements. Blocking statements complete assignments immediately and block execution flow until finished. Non-blocking statements evaluate assignments immediately but postpone assignments until other evaluations are complete, allowing execution flow to continue without blocking. Examples show blocking statements updating values immediately while non-blocking statements use old values since assignments are postponed.

1. Topic: Blocking and Non-Blocking Statements
Submitted by
Upendra
VERILOG PROJECT

2. The = represents a blocking procedural assignment.
• Evaluated and assigned in a single step.
• Execution flow within the procedure is blocked until the assignment is
completed.
• Evaluations of concurrent statements in the same time step are blocked
until the assignment is completed.
Blocking statements:
always@(posedge clk)begin
Q1=d;//Q1 gets updated immediately with a value of d
Q2=Q1;//Q2 gets updated immediately with the value of Q1
Q3=Q2;//Q3 gets updated immediately with the value of Q2
end
Example:

3. Non-Blocking Statement:
The <= token represents a token represents non-blocking blocking assignment
assignment
• Evaluated and assigned in two steps: Evaluated and assigned in two steps:
① The right The right-hand side is evaluated immediately hand side is
evaluated immediately
② The assignment to the left The assignment to the left-hand side is
postponed until the hand side is postponed until other evaluations in the
current time step are completed other evaluations in the current time step
are completed
• Execution flow within the procedure continues until Execution flow within
the procedure continues until a timing control is encountered (flow is not
blocked).

4. Example:
reg Q1,Q2,Q3;
always@(posedge clk)begin
Q1<=d;//Q1 in this statement will not get updated immediately.
Q2<=Q1;//will use the old value of Q1.
Q3<=Q2;//will use the old value of Q2.
end