OpenCL-ready High Speed FPGA Network for Reconfigurable High Performance Comp...Ryohei Kobayashi
The document discusses the results of a study on the effects of a new drug on memory and cognitive function in older adults. The double-blind study involved 100 participants aged 65-80 and found that those given the drug performed significantly better on memory and problem-solving tests than the placebo group after 6 months. The drug was found to be safe and well-tolerated with no serious side effects reported.
A High-speed Verilog HDL Simulation Method using a Lightweight TranslatorRyohei Kobayashi
The document discusses the benefits of exercise for mental health. Regular physical activity can help reduce anxiety and depression and improve mood and cognitive functioning. Exercise causes chemical changes in the brain that may help protect against mental illness and improve symptoms.
OpenCL-ready High Speed FPGA Network for Reconfigurable High Performance Comp...Ryohei Kobayashi
The document discusses the results of a study on the effects of a new drug on memory and cognitive function in older adults. The double-blind study involved 100 participants aged 65-80 and found that those given the drug performed significantly better on memory and problem-solving tests than the placebo group after 6 months. The drug was found to be safe and well-tolerated with no serious side effects reported.
A High-speed Verilog HDL Simulation Method using a Lightweight TranslatorRyohei Kobayashi
The document discusses the benefits of exercise for mental health. Regular physical activity can help reduce anxiety and depression and improve mood and cognitive functioning. Exercise causes chemical changes in the brain that may help protect against mental illness and improve symptoms.
FACE: Fast and Customizable Sorting Accelerator for Heterogeneous Many-core S...Ryohei Kobayashi
The document describes a proposed sorting accelerator for heterogeneous many-core systems. The accelerator uses a sorting network and merge sorter tree to sort data in parallel. It reads unsorted data from DRAM, processes it through the sorting network and merge sorter tree on an FPGA, and writes the sorted data back to DRAM. An example is provided of sorting 256 elements step-by-step through the sorting network and merge sorter tree to fully sort the data.
3bOS: A flexible and lightweight embedded OS operated using only 3 buttonsRyohei Kobayashi
This presentation describes 3bOS, a simple and customizable embedded operating system that runs on the MieruEMB educational kit using only three push buttons. 3bOS is designed for educational purposes, with around 800 lines of code, making it easy for users to understand and modify. It loads programs from an SD card filesystem and runs them, restoring the operating system interface after they exit. Key aspects of the 3bOS design include its small memory footprint, simple input/output interfaces, and support for executing ELF files from the SD card.
Hystor is a hybrid storage system that manages both SSDs and HDDs as a single block device with minimal changes to existing OS kernels. It monitors I/O access patterns at runtime to identify high-cost data blocks, such as those resulting in long latencies or containing critical metadata. It uses these blocks to effectively leverage the performance advantages of SSDs. The paper presents Hystor's design and implementation in the Linux kernel, which can identify high-cost blocks using a metric based on access frequency and request size, and maintain detailed access histories efficiently using a block table structure.
CMPP 2012 held in conjunction with ICNC’12Ryohei Kobayashi
The document describes a proposed method for parallelizing 2D stencil computations across multiple FPGAs. The key points are:
1) The data set is divided into blocks and assigned to each FPGA, with boundary values communicated between neighbors.
2) Computation is performed in parallel by updating grid points in a specific order that increases the acceptable communication latency between FPGAs.
3) This method ensures a margin of about one iteration between communications, allowing latency to scale with problem size.
4) The architecture and implementation are described, including how the data subset is stored in block RAM memory and computed in parallel using multiply-add (MADD) units over 8 cycles per stencil point.
FACE: Fast and Customizable Sorting Accelerator for Heterogeneous Many-core S...Ryohei Kobayashi
The document describes a proposed sorting accelerator for heterogeneous many-core systems. The accelerator uses a sorting network and merge sorter tree to sort data in parallel. It reads unsorted data from DRAM, processes it through the sorting network and merge sorter tree on an FPGA, and writes the sorted data back to DRAM. An example is provided of sorting 256 elements step-by-step through the sorting network and merge sorter tree to fully sort the data.
3bOS: A flexible and lightweight embedded OS operated using only 3 buttonsRyohei Kobayashi
This presentation describes 3bOS, a simple and customizable embedded operating system that runs on the MieruEMB educational kit using only three push buttons. 3bOS is designed for educational purposes, with around 800 lines of code, making it easy for users to understand and modify. It loads programs from an SD card filesystem and runs them, restoring the operating system interface after they exit. Key aspects of the 3bOS design include its small memory footprint, simple input/output interfaces, and support for executing ELF files from the SD card.
Hystor is a hybrid storage system that manages both SSDs and HDDs as a single block device with minimal changes to existing OS kernels. It monitors I/O access patterns at runtime to identify high-cost data blocks, such as those resulting in long latencies or containing critical metadata. It uses these blocks to effectively leverage the performance advantages of SSDs. The paper presents Hystor's design and implementation in the Linux kernel, which can identify high-cost blocks using a metric based on access frequency and request size, and maintain detailed access histories efficiently using a block table structure.
CMPP 2012 held in conjunction with ICNC’12Ryohei Kobayashi
The document describes a proposed method for parallelizing 2D stencil computations across multiple FPGAs. The key points are:
1) The data set is divided into blocks and assigned to each FPGA, with boundary values communicated between neighbors.
2) Computation is performed in parallel by updating grid points in a specific order that increases the acceptable communication latency between FPGAs.
3) This method ensures a margin of about one iteration between communications, allowing latency to scale with problem size.
4) The architecture and implementation are described, including how the data subset is stored in block RAM memory and computed in parallel using multiply-add (MADD) units over 8 cycles per stencil point.