Principles of-mobile-communication-2011

Summer Training
Principles of Mobile
Communication

Sub ‐ Sections
Principles of
Mobile
Communication
1 PCM30 Basics
2 PDH Basics
3 SDH Basics
4 Introduction to data
5 GSM Introduction
6 CDMA Overview
7 GPRS Introduction

1 Introduction to PCM Pages (1-5)
2 Fundamentals of PCM Pages (1-14)
3
2 Mbit/s Frame and Signaling
Pulse Frame
Pages (1-13)
4
Baseband Transmission of Digital
Signals
Pages (1-18)
5
Block Diagram of a Primary
Multiplexer
Pages (1-5)
6 Appendix Pages (1-5)
Sub ‐ Sections

PCM30 Basics
This document consists of 60 pages.

Chapter 1: Introduction to PCM
1
Aim of study
This chapter introduces advantages of digital transmission.
Contents Pages
1 Introduction 2
2 Advantages of Digital Transmission 5

2
Chapter 1
Introduction to PCM
1 Introduction
When telephone communication began individual connecting paths were used,
i.e. a separate pair of wires was used for every telephone connection. This was
known as space-division multiplex (SDM) on account of the fact that a
multitude of lines were arranged physically next to each other. Since a
particularly large proportion of capital is invested in the line plant, efforts were
made at an early stage to make multiple use of at least those lines used for long-
range communications. This led to the introduction of frequency-division
multiplex (FDM). FDM is used in analog systems.
It is not the only way of making multiple use of lines however. Another
possibility is offered by time-division multiplex (TDM). Here the transmitted
telephone signals are separated in time. Fig. 1 shows a period containing 32 time
slots. This subdivision is repeated every 125 μs in consecutive periods. One time
slot in each of the consecutive periods is allocated to each telephone signal.
Fig. 1 Time-division multiplex

3
Sampling Theorem
The principle of time-division multiplex is based on the theory that a complete
waveform is not required in order to transmit signals such as those encountered
in telephony. It is sufficient to sample the waveform at regular intervals and to
only transmit these samples. When a waveform is sampled, a train of short
pulses is produced. The amplitude of each pulse represents the amplitude of the
waveform at the specific sampling instants. This conversion is known as pulse
amplitude modulation (PAM). The envelope of the PAM signal reflects the
original form of the curve.
Relatively large intervals occur between each sample. These intervals can be
used for transmitting other PAM signals, i.e. the samples of several different
telephone signals can be transmitted one after the other in repeated cycles.
Fig. 2 Periodic sampling of the analog telephone signal a

4
Fig. 3 PAM signal consisting of the samples of analog telephone signal a
Pulse Code Modulation
If the waveform samples, i.e. the pulses with differing amplitudes, are converted
to binary character signals, the term pulse code modulation (PCM) is used.
During this process the pulse-like samples are quantized and coded - 8 bits are
normally used here.
When the PCM signals of several telephone signals are interleaved they produce
a PCM time-division multiplex signal. PCM time-division multiplex signals
permit the multiple use of lines and electronic circuits. Moreover, owing to the
digital nature of the information, PCM signals are much less sensitive to
interference than are analog signals (e.g. PAM signals).

5
Progress in recent years in semiconductor technology has made pulse code
modulation economically attractive for telephone switching equipment. It has
thus become possible to replace the "analog" switching equipment used up to
now with fully electronic "digital" telephone systems.
2 Advantages of Digital Transmission
• Digital telephone systems offer the following advantages over analog
systems:
digital technology used throughout the system (high noise immunity).
• Multiple use of lines and exchange equipment by means of time-division
multiplex.
• Each speech direction has a separate channel (corresponding to the 4-wire
circuits used for analog systems).
• Low space requirements.
• Switching network with high traffic capacity, and negligible internal
blocking.
• Several services can be integrated within a single network: telephony, all
types of data transmission and high-speed telecopying e.g.
Advantages of Digital Telephones
• Separate digital channel for each speech direction right up to the
subscriber. This creates more favorable conditions for facilities such as
those required for hands-free operation.
• A signaling channel is always available in both directions between the
telephone and the public exchange. Features such as calling subscriber
number display, letter box function, mixed communication, etc., will thus
be possible in the all digital networks of the future.

Chapter 2 : Fundamentals of PCM
1
Chapter 2: Fundamentals of PCM
Aim of study
This chapter introduces sampling theorem, analog-to-digital conversion & quantizing error.
Contents Pages
1 Fundamentals of PCM 2
2 Quantizing Error 6
3 Exercise 14

2
Chapter 2
Fundamentals of PCM
1 Fundamentals of PCM
1.1 Sampling Theorem
The sampling theorem is used to determine the minimum rate at which an
analog signal can be sampled without information being lost when the original
signal is recovered.
The sampling frequency (fA) must be more than twice the highest frequency
contained in the analog signal (fS):
fA > 2 fS
1.2 Analog-to-Digital Conversion
1.2.1 Sampling
A sampling frequency (fA) of 8000 Hz has been specified internationally for the
frequency band (300 Hz to 3400 Hz) used in telephone systems, i.e. the
telephone signal is sampled 8000 times per second. The interval between two
consecutive samples from the same telephone signal (sampling interval = TA) is
calculated as follows:
Fig. 1 shows how the telephone signal is fed via a low-pass filter to an electronic
switch. The low-pass filter limits the frequency band to be transmitted; it
suppresses frequencies higher than half the sampling frequency.

3
The electronic switch - driven at the sampling frequency of 8000 Hz - takes
samples from the telephone signal once every 125 μs. A pulse amplitude
modulated signal is thus obtained at the output of the electronic switch: a PAM
signal.
Fig. 1 Generation of a PAM signal
1.2.2 Quantizing
The pulse amplitude modulated signal (PAM signal) still represents the
telephone signal in analog from. The samples can, however, be transmitted and
further processed much more easily in digital form. The first stage in the
conversion to a digital signal - in this case a pulse code modulated signal (PCM
signal) – is quantizing. The whole range of possible amplitude values is divided
into quantizing intervals.

4
The quantizing principle is shown in fig. 2. In order to simplify the explanation
only 16 equal quantizing intervals are numbered + 1 to + 8 in the positive range
of the telephone signal and - 1 to - 8 in the negative range.
The appropriate quantizing interval is determined for each sample. Decision
values form the boundaries between adjacent quantizing intervals. On the
transmit side, therefore, several different analog values fall within the same
quantizing interval. On the receive side one signal value, corresponding to the
midpoint of the quantizing interval, is recovered for each quantizing interval.
This causes small discrepancies to occur between the original telephone signal
samples on the transmit side and the recovered values. The discrepancy for each
sample can be up to half a quantizing interval. The quantizing distortion which
may arise on the receive side as a result of this manifests itself as noise
superimposed on the useful signal. Quantizing distortion decreases as the
number of quantizing intervals are increased. If the quantizing intervals are
made sufficiently small the distortion will be minimal and the noise
imperceptible.

5
Fig. 2 Uniform quantizing of the samples of an analog telephone signal
If equally large quantizing intervals are used over the whole amplitude range,
relatively large discrepancies will occur in the case of small signal amplitudes
(uniform quantizing,). These discrepancies might be of the same order of
magnitude as the input signals themselves and the signal-to-quantizing noise
ratio would not be large enough. For this reason 256 unequal quantizing
intervals are therefore used in the practice (non-uniform quantizing):

6
• Small quantizing intervals for lower signal values.
• Larger quantizing intervals for higher signal values.
The ratio of the input signal to the possible discrepancy as a result of quantizing
is therefore approximately the same for all input signal values.
Non-uniform quantizing is specified with the aid of characteristics. The CCITT
recommends two such characteristics in G.711:
a) The "13 segment characteristic"
(A-law, e.g. for the PCM30 transmission system in Europe).
b) The "15 segment characteristic"
(μ-law, e.g. for the PCM24 transmission system in the USA).
2 Quantizing Error
Fig. 3

7
Quantizing Error
Fig. 4
Quantizing and Coding for Basic Speech Transmission Systems
The particularities of non-linear quantizing are determined by specific
characteristics described in the CCITT-recommendation G.711:

8
The 13-segment characteristic is made up of six linear sections in the positive
and negative area. The two segments located at the relative point zero form
together a linear segment. Thus, the characteristic comprises a total of 13
segments. In the proximity of point zero there are two Nr. 1 levels, a positive
and a negative one. The transmission therefore requires in all 2 x 128 = 256
levels. The 13-segment characteristic (also called A-law) is used, for example,
for the 30 channel system PCM mainly in Europe.
Each quantizing level is allocated a 8-bit code word. The first transmitted bit
determines the positive or negative sign of a sample. The following 3 bits (23 =
8) indicate one of the 7 or 8 segments. The remaining 4 bits (24 = 16) form the
code words for the linear levels within a segment.
Systems in accordance with G.711 have a sampling frequency of 8 kHz. Since
every 125 μs = 64000 bit/s = 64 kbit/s.
Load Capacity
Fig. 5

9
13-Segment Characteristic (A-Law)
Fig. 6

10
13-Segment Characteristic (A-Law)
Fig. 7

11
Conversion of the 12 bit Word into the 8 bit PCM Word
Fig. 8

12
Summary
Transmitting End
1. VF Band-pass-filter
2. Sampling (PA;
3. Quantizing, Encoding (PCM)
Fig. 9
Fig. 10

13
Summary
Receiving end
4. Decoding (PAM)
5. Holding circuit
6. VF-low pass filter
Fig. 11
PCM: Receiving End
Fig. 12

14
3 Exercise
1. What is the sampling frequency for a voice channel?
2. How many samples per voice channel are transmitted per second?
3. How many bits per sample are transmitted in a data channel?
4. How many bit/s are transmitted in a data channel?
5. How many bits are transmitted in a voice channel?
6. What is the disadvantage of uniform quantizing?
7. Is the uniform or non-uniform quantizing method used for the coding of
PCM30 voice channels?
8. What does quantizing distortion mean?
9. Name the technical terms of the quantizing methods.
10.Which quantizing method is applied for transforming a VF signal into a
PCM signal?
Why is this method used for?
11.What are the four essential steps for transforming a VF voice signal into a
PCM signal?
12. Is there any possibility for decoding a PCM30 coded signal into a PCM24
primary multiplexer; if not, why not?

Chapter 3: 2 Mbit/s Frame and Signaling Pulse Frame
1
Chapter 3: 2 Mbit/s Frame and Signaling Pulse
Frame
Aim of study
This chapter introduces HDSL structure of the 2 Mbit/s frame, structure of the signaling pulse
frame & PCM transmission systems.
Contents Pages
1
Structure of the 2 Mbit/s Frame According to CCITT
Recommendation G.704
2
2
Structure of the Signaling Pulse Frame According to
CCITT Recommendation G.704
4
3 CRC4-Synchronization for Primary Multiplexer 6
4 Alarms 8
5 PCM Transmission Systems 10
6 Connecting Options of the Primary Multiplexer PCM30 11
7 Interfaces of PCM30H 12
8 Exercise 13

2
Chapter 3
2 Mbit/s Frame and Signaling Pulse
1 Structure of the 2 Mbit/s Frame According to CCITT
2-Mbit/s-Pulse frame
In the direction of transmission the primary multiplexer PCM30 transforms up
to 30 signals with different features into 64-kbit/s-digital signals and then
combines them by the time division multiplexing procedure to a 2048-kbit/s (2-
Mbit/s)-signal, as shown in the pulse frame of fig. 1. The individual signals can
be either LF-speech signals converted by pulse code modulation, or digital
signals (e.g. data). In the receive direction a demultiplexer isolates the individual
signals out of the 2 Mbit/s signal. The 64-kbit/s-digital signals are then
converted again into analog signals.
The 2-Mbit/s pulse frame accord. to CCITT-recommendation G.704 consists of
32 time intervals with 8 bits each (octets). In the intervals 1 to 15 and 17 to 31
speech or digital signals are transmitted. Interval 16 contains the channel-
associated signaling information (CAS) combined in one multiframe or,
optionally, an additional device specific data channel. In the interval 0 there is
an alternate transmission of a frame alignment signal (FAS) or a service word
(SVW).
In order to isolate the individual signals out of the pulse frame the FAS is
searched for in the received 2-Mbit/s-signal. As soon as the bit pattern is
recognized, the demultiplexer part of the central multiplexer synchronizes itself
to time interval 0.

3
To additionally ensure the synchronization the CRC4-procedure, which will be
described in the following, is applied. The service word is used for the
transmission of urgent and non-urgent alarms (bit A and bit Sa4), for loop
commands (bits Sa6 and Sa7) (CCITT-Redbook: bits D, N and Y1 to Y3).
Fig. 1

4
2 Structure of the Signaling Pulse Frame According to CCITT
Signaling pulse frame
If analog signal insets are used the PCM30 transmits up to 30 speech signals in
the time intervals 1 to 15 and 17 to 31 of the 2-Mbit/s-pulse frame. It has to be
ensured that the 64-kbit/s-signals in the time intervals 17 to 31 are counted as
channels 16 to 30. The individual channel-associated signaling information is
coded with 4 bits (a, b, c, d) separate from the speech signal. The signaling of 30
channels can therefore be combined in 15 octets, which are supplemented by a
code and service word of 8 bits, to a multiframe (signaling pulse frame). This
multiframe is transmitted in time interval 16 by 16 consecutive 2-Mbit/s-pulse
frames (R0 to R15). The code and service word contained in interval R0 is
necessary for the multiframe synchronization and for alarm messages.

5
Fig. 2

6
3 CRC4-Synchronization for Primary Multiplexer
With the data transmission of synchronous 64 kbit/s digital signals it is possible
that the bit patterns of the FAS and the SVW are transmitted (either randomly or
on purpose) in the time intervals defined for user signals. If there is a
synchronization of the receive side demultiplexer to this bit pattern, an isolation
of the individual signals is impossible. Therefore, the CRC4-procedure (Cyclic
Redundancy Check by 4 bits) described in CCITT-recommendation G.704 is
used in addition, to ensure the synchronization.
For this, 16 consecutive 2-Mbit/s frames are combined to a CRC4 multiframe
consisting of 2 data blocks and of the multiframe parts I and II. The highest
rating bits of the service words in the first twelve 2-Mbit/s frames form the
multiframe code word ('001011'). Here, the synchronization is based on two
criteria: finding the FAS of the 2-Mbit/s frame and the FAS of a CRC4
multiframe.
To continually supervise the synchronization, a data block (e.g. block I) is
modified in a data transmitter accord. to a certain algorithm, whereby a rest of 4
bits (the control bits C1 and C4) is left over. These bits are transmitted as
highest rating bits in the 2- Mbit frame alignment words of the following data
block (block II). The data receiver processes the incoming data block according
to the same algorithm as the transmitter. Again, a rest of 4 bits is left over,
which are compared individually to the control bits received in the next data
block (block II). In case of a correspondence, block I is considered to be error-
free.
If 915 or more out of 1000 checked blocks were found to be faulty, a new
synchronization is started.

7
A CRC4-error is indicated by two E-bits (CCITT-Redbook: Si-bits) at the
transmit side; these two E-bits are transmitted as highest rating bits of the
service words in the 2-Mbit/s frames 13 and 15 of the CRC4 multiframe. The
BER of the 2-Mbit/s-signal can be derived from the number of faulty blocks.
Thus, for example, a number of 512 or more faulty blocks within a measuring
interval of 1 s results in a BER > 10-3.
Fig. 3 2-Mbit/s-pulse frame and CRC4-multiframe

8
4 Alarms
4.1 AIS Alarm Indication Signal
D-Bit Service bit
AIS: Alarm indication signal
The AIS is an all-one-signal which, if an error occurs, is inserted as
"replacement signal" only in forward direction.
• If a low bit rate signal (64 kbit/s) is lacking at the input, the AIS is
inserted in the corresponding time slot of the highest bit rate signal (2
Mbit/s), i.e. all other time slots of the higher bit rate signal remain
unaffected.
• If a faulty signal is received at the higher bit rate interface (2 Mbit/s), the
AIS is inserted into all lower bit rate signals (64 kbit/s). A blocking signal
evaluated by the operator is inserted into telephone channels.
The higher bit rate signal is considered to be faulty if there is no signal
available, the synchronizing word is not recognized (synchr. with the FAS
or optionally with CRC4), or if the BER > 10-3.
In this case the D-bit is transmitted at the 2-Mbit/s output as feedback for
the distant end station (frame (SVW) TS0, bit 3).
• AIS can also be inserted if a device internal fault arises, such as an error
in the transmission clock. The error is determined device-specifically.
• If at the higher bit rate interface (2 Mbit/s) a signal with BER > 10-5/-6 is
received, the N-bit can be transmitted optionally (i.e. device-specifically)
at the 2 Mbit/s output as feedback for the distant end station (frame
(SVW) TS0, bit 4). In this case, no AIS is inserted.

9
• If the higher bit rate interface receives an AIS, this is through-connected
to the lower bit rate signals (64 kbit/s) and the D-bit transmitted in
backward direction.
• If the signaling multiplexer is out of order, it is possible to insert the AIS
in time slot 16 (multiframe AIS).
• If a multiframe AIS is received, the DK-bit is transmitted in backward
direction.
• If the multiframe signaling word (TS0) (=TS16 of the frame) is not
recognized, the speech signals are blocked and the DK-bit transmitted in
backward direction (multiframe TS0, bit 6).
• In case of a seizure acknowledgment alarm, the NK-bit is transmitted in
backward direction (multiframe TS0, bit 7). This alarm occurs if the
exchange receives no appropriate acknowledgment after a telephone
channel has been seized.
AIS Alarm Indication Signal
D-Bit Service bit D
Transmission of AIS and bit D
Fig. 4

10
5 PCM Transmission Systems
The transmission systems recommended by the CCITT and described below are
the PCM30 system, with 2048 kbit/s (CCITT Recommendation G.732), and the
PCM24 system, with 1544 kbit/s (CCITT Recommendations G.733); these
combine 30 and 24 telephone channels per transmission direction respectively to
form a time-division multiplex signal. PCM30 transmission systems are used
throughout Europe and in may non-European countries; PCM24 transmission
systems have been installed mainly in the USA, Canada and Japan. PCM30 and
PCM24 are also known as "primary transmission systems" or basic systems.
Their most important features are given in the figure.
Fig. 5 Characteristics of the PCM30 and PCM24 Transmission Systems

11
6 Connecting Options of the Primary Multiplexer PCM30
Fig. 6

12
7 Interfaces of PCM30H
Fig. 7

13
8 Exercise
1. How many time slots does a frame consist of?
2. In which time slot is the voice channel 14 transmitted?
In which time slot is the data channel 25 transmitted?
3. What does the time slot 16 serve e for?
4. What does the time slot 0 serve for?
5. What does the D-bit serve for?
6. How many bits does the synchronization word contain and in which time slots
is it transmitted?
7. What is the duration for the transmission of one multi-frame?
8. What is the duration of one frame?
9. How many multi-frames are transmitted per second?
10. In which part of the multi-frame are the signaling bits of voice channel 22
transmitted?
11. What does CRC4 mean?
12. What is the CRC4 code used for?
13. Is it possible to synchronize a primary multiplexer without CRC4 code?

Chapter 4: Baseband Transmission of Digital Signals
1
Aim of study
This chapter introduces codirectional operation mode, contradirectional operation mode &
important PCM interfaces.
Contents Pages
1 Introduction 2
2 Interface Codes 3
3 Digital Signal Regeneration 7
4 Reasons for Bit Errors 10
5 Codirectional Operation Mode 14
6 Contradirectional Operation Mode 16
7 Important PCM Interfaces 17
8 Exercise 18

2
Chapter 4
Baseband Transmission of Digital Signals
1 Introduction
Digital signal devices process the signals as purely binary information, i.e. the
signal level does not change between bits with the same logical state. For this
reason, these so-called NRZ signals (no return to zero) can only be processed
together with the corresponding clock, which enables the identification of
individual bit positions.
This separate clock is not available for the transmission of data signals and thus it
has to be possible to derive (i.e. regenerate) the clock from the data signal on the
receiving side. It is obvious that for a NRZ code this is very complicated, if not
virtually impossible. A further disadvantage of the NRZ code is that it carries a
certain amount of dc-voltage which excludes the signal's galvanic isolation at the
interface (transformer etc.). Due to these disadvantages, various interface codes
have been developed, all of which comply with the following requirements:
• Good clock retrieval features.
• No dc-component.
Fig. 1 Processing of NRZ signals with the aid of separate clock

3
2 Interface Codes
A suitable interface code has a maximum of transitions between the different
signal levels, even for the transmission of lengthy sequences of identical logical
states; it has no dc-component. The survey shows the development of individual
codes.
A rather important advantage of the interface code is the possibility it offers to
detect transmission errors by supervising the coding rules. With the HDB3 code,
for example, the receiving of four zero bits would represent the violation of a
coding rule, i.e. at least one bit error must have been occurred during
transmission.

4
The standardization of interface codes only refers to device interfaces. The codes
for conductor-bound transmission paths are manufacturer-dependent and are
generally adapted to the requirements of the respective terminating unit.
Digital Interface Codes
Fig. 2
Fig. 3 shows the amplitude spectrum of various interface codes. For codes
without a dc-component the maximum energy is within the range of a frequency
which corresponds to half of the bitrate value. This is obvious when comparing
the definitions of frequency and bitrate respectively.

5
Fig. 3 Amplitude spectrum of various codes
The bit sequence represented in fig. 4 shall serve as an example. One signal
period covers 2 bits and corresponds to the basic wave of the data signal. This
wave contains the greatest amount of energy and has a frequency which equals
half of the bitrate value. This is also the frequency that is indicated by a frequency
counter connected to a source of a digital signal.
Fig. 4 Bit sequence 0101...

6
HDB3-Coding rules
(Third-Order-High-Density-Bipolar-Code)
The HDB3-code is a modified version of the AMI-code. Binary signals or AMI-
code signals may contain lengthy "0" sequences, which hinder the clock retrieval
in the regenerative repeaters along digital transmission paths. The HDB3 code
enables the elimination of "0" sequences with more than 3 zeros.
1. If there are more than 4 consecutive "0"-signal elements, the fourth "0"-
signal element shall be replaced by a V-signal element (= "1"-signal
element) (000V). Hereby, the V-signal element takes on the same polarity
as the "1"-signal element. A V-signal element causes a Violation of the
AMI-rule.
2. If between the V-signal element, inserted according to the conditions
specified above (rule 1), and the preceding V-signal element there is an
even number of "1"-signal elements, then the first of four "0"-signal
elements shall be replaced by an A-signal element (= "1"-signal element).
The polarity of the A-signal element complies with the AMI rule. The last
of four "0"-signal elements becomes again a V-signal element (A00V). In
this case the A- and V-signal elements have the same polarity.

7
Fig. 5 Transformation of two binary signals into HDB3-signals
3 Digital Signal Regeneration
The digital signal regeneration is one of the advantages of the digital transmission
technique. Theoretically, it enables the signals to be transmitted via an unlimited
distance without any quality losses.
During transmission, a digital signal is attenuated and distorted, which results in a
reduction of the signal/noise ratio. The regeneration process has the task of
canceling such distortions and regenerate the originally sent signal from the
actually received signal. That is why every interface on the receiving side is
followed by a regeneration circuit.

8
Fig. 6 Principle of digital signal regeneration
Four basic function blocks are necessary for the digital signal regeneration:
• Amplification block (balancing of attenuation losses).
• Clock retrieval block.
• Amplitude decision block.
• Time decision block.

9
Fig. 7 Block diagram of a digital signal regenerator
These four functions are represented in fig. 7.
• The receiving signal is fed into an automatic gain controlled amplifier
(AGC) which keeps the amplitude of the outgoing signal at a constant
value over a wide range of incoming amplitudes. Thus, the attenuation of
the transmission path is balanced.
• The constant output level is a precondition for the functioning of the
amplitude decision block (AD) which follows. This AD decides on the
basis of an internal threshold value whether the level of incoming signal is
above or under this threshold value. Accordingly, a signal with the levels
Log. 0 or Log. 1 is emitted at the output. The output signal thus consists of
pulses, the width of which only depends on the period during which the
output signal exceeds the decision threshold.

10
• The time decision block (TD) has the task of generating signal pulses with
constant width. For this, it requires the regenerated receive signal clock
which samples the output signal of the amplitude decision block. If, at the
time of sampling the signal has a level of Log. 1, the time decision block
emits a pulse with constant width. Thus, incoming pulses of any width are
turned into pulses corresponding exactly to the bit width of the transmitted
signal. The time decision process is the final stage of regeneration.
• The clock retrieval CR block is in charge of regenerating the transmitted
signal clock from the receive signal clock. In order to effect this function, a
phase locked loop (PLL) is employed, basically consisting of a voltage-
controlled oscillator whose frequency can be changed by a control-voltage.
By adequate evaluation of the receiving signal it is now possible to reach a
control voltage which can set the oscillator to the exact clock frequency
value of the transmitting signal.
4 Reasons for Bit Errors
The decisive quality criteria for the transmission of digital signals is the bit error
rate (BER). This BER represents the proportion of bits which have been mutilated
(i.e. incorrectly recorded) during transmission, to the total amount of bits
transmitted within a certain interval. The BER directly influences the quality of
the transmitted services (e.g. voice channels, data channels, video signals). Two
significant BER are explained exemplary in the following:

11
BER = 10-6
This BER virtually cannot be perceived in a voice channel. For the transmission
of data channels, however, this value represents the maximum acceptable limit.
The transmission system is in a state of "degraded quality", which is indicated by
a degradation alarm (low priority) on the devices involved. The transmission path
remains, nevertheless, in operation.
BER = 10-3
This BER causes a strong interference noise in a voice channel. The operating
state is judged to be of "unacceptable quality", which is signaled by the devices
involved by the emission of a failure alarm (high priority). The transmission path
goes out of operation.
How do bit errors arise?
In the previous section it was mentioned that digital signals can be regenerated as
requested, i.e. a transmission without quality reduction is possible. This statement
is, however, only partially true, i.e. whenever the impairment of the transmission
signals is within limits which still permit the regeneration at the receiving side. The
reasons for the formation of bit errors are
• Low signal/noise ratio.
• Jitter.
• Intersymbol interference.
Low signal/noise proportion
Noise amplitudes which influence the amplitude decision process are
superimposed to the originally sent signal.

12
The superimposed interference peaks lead to an incorrect signal interpretation at
the receiving end. Reasons for a low S/N-ratio are:
a) Too strong signal attenuation during transmission.
b) External interference during transmission.
For transmission in cable sections (especially optical fiber) both reasons can be
largely eliminated by careful planning.
Fig. 8 Low S/N-proportion
Jitter
Due to jitter, the transitions between signal levels log. 0 and log. 1 do not take
place at periodically recurring points in time (characteristically moments) as for
undisturbed signals, which means that the transitions oscillate around the
characteristically moments.
Jitter is characterized by jitter amplitude (unit intervals UI) and jitter frequency.
One UI means that, because of deviation from the characteristically moments, the
signal edges are within a range equal to the width of 1 bit.

13
The jitter frequency is the number of oscillations around the characteristically
moment per one second. Jitter influences the time decision process in the
regenerator and causes bit errors for high jitter amplitudes and frequency.
Fig. 9 Representation of an Unit Interval (UI)
Jitter arises in the devices used for signal transmission (i.e. in regenerators and
demultiplexers = systematically jitter), or on the transmission path due to external
influences (non-systematic jitter).
Intersymbol interference
Is caused by a discrepancy between the band width of the transmission path and
the bandwidth required for the digital signal. This leads to a bit extension, so that
there is an overlap of bits which follow each other. Thus, bit errors occur, the
reasons of which can be traced back to the impairment of amplitude decision
process. For conductor-bound transmission of digital signals this effect can be
excluded by adequate planning. For transmission on radio paths this effect is of
fundamental importance as the frequency response of the transmission path can
change due to atmospherical influence.

14
5 Codirectional Operation Mode
Codirectional
Designation of an interface between two devices A and B where the clocks T and
T' are transmitted in the same direction as the digital signals S and S' to which
they belong (opposite term: contradirectional).
Fig. 10

15
Fig. 11 Interface code G.703 (64 kbit/s)

16
6 Contradirectional Operation Mode
Contradirectional
Designation of an interface between two devices A and B, where the clocks are
supplied only by the one device B. Thus the clock T' belonging to the signal S'
(from B to A) is transmitted in the same direction as the signal.
Remark: with a contradirectional interface the device B (e.g. PCM-multiplexer)
requests a digital signal from the device A (e.g. device which bundles switching
data).
Fig. 12

17
7 Important PCM Interfaces
LF interface F2:
Speech frequency band 300 to 3400 Hz
Resistance for 2-wire operation 850 Ω sym. or
900 Ω sym.
Resistance for 4-wire operation 600 Ω sym.
Level variable
64-kbit/s-, 128-kbit/s-data signal interface D2:
Codirectional operation (G. 703/1.2.1)
Bit rate 64 kbit/s 128 kbit/s
Baud rate 256 kbaud/s 512 kbaud/s
Code AMI
Resistance 120 Ω sym.
Amplitude at the output 1 Vs0
Contradirectional operation (G. 703/1.2.3)
Bit rate 64 kbit/s
Code AMI
Resistance 120 Ω sym.
Amplitude at the output 1 Vs0
Clock signal 64 kHz
Resistance (clock signal) 120 Ω sym.
Amplitude at the output (clock signal) 1 Vs0

18
2-Mbit/s-interface (G703/6) F1:
Bit rate 2048 kbit/s 50 ppm
Code HDB3
Resistance 120 Ω sym. or
75 Ω coaxial
Amplitude at the output 3 Vs0 sym. or
2.37 Vs0 coaxial
8 Exercise
1. What demands are made on the transmission codes?
2. Which two modes of operation are used for data channels?
3. Which symbol rate (baud/s) has the data thus transmitted?

Chapter 5: Block Diagram of a Primary Multiplexer
1
Aim of study
This chapter introduces transmit & receive side.
Contents Pages
1 Transmit Side 2
2 Receive Side 3
3 Exercise 5

2
Chapter 5
Block Diagram of a Primary Multiplexer
1 Transmit Side
The required functional entities of the DSMX 64 K/2F are accordingly
subdivided into a transmit section and a receive section. The transmit section
incorporates the transmit unit and transmit-side speech circuits in the telephone
channel units or the transmit-side circuits of the data channel units; the receive
section comprises the receive unit and the receive-side speech circuits in the
telephone channel units or the receive-side circuits of the data channel units.
Fig. 1 Block diagram of transmit side, showing functional blocks

3
Telephone Channel Unit
The transmit-side speech circuit takes over the telephone signals present on the
associated telephone lines (VF signals). The signals are band-limited from 300
Hz to 3400 Hz.
Depending on the required relative level setting, the signal is amplified or
attenuated before the A/D conversion. The relative level in transmit direction is
referred to the input of the A/D converter. Thus a relative level setting of -14
dBr means that the level before the amplifier is 14 dB less than at the input of
the A/D converter. With other terms the signal is amplified by 14 dB.
The resulting PAM values (pulse amplitude modulation) are converted into 8-bit
code words by the encoder. This non-linear quantizing is amplitude-dependent.
The encoding characteristic (A-law), which is symmetrical with respect to the
zero line, consists of 13 linear segments, giving an approximately logarithmic
response.
2 Receive Side
The 2 Mbit/s PCM-E signal is fed to all the channels and the signaling
multiplexer. The addressing, which is derived from the clock generator, ensures
that the individual 8-bit words are read into the associated channel units or the
signaling multiplexer with the correct timing.
The functional blocks synchronization and sections of the clock generator and
distributor are concentrated in a highly integrated I2L device mounted in the
transmit unit (PCM receive device).

4
Fig. 2 Block diagram of the receive side
Telephone Channel Unit
The PAM signal is generated from the 8-bit words in the decoder. A low-pass
filter with (sin x) / x equalization reconverts the sample-and-hold signal formed
from the sequence of PAM values to the VF signal.
Depending on the required relative level setting the signal is amplified or
attenuated after the D/A converter. The relative level in receive direction is
referred to the output of the D/A converter. Thus a relative level of 4 dBr means
that the level after the amplifier is 4 dB higher than at the output of the D/A
converter. With other terms the signal is amplified by 4 dB.

5
Data Channel Unit
The 8-bit words are read into a memory with the 2-MHz receive clock, undergo
serial-parallel conversion and are then read out again at 64 kHz. The 64 kbit/s
signal is then encoded and fed out from D2out at 256 kbaud.
3 Exercise
Which blocks of the primary multiplexer may be distinguished for the
application of voice channel transmission and data channel transmission?

Chapter 6: Appendix
1
Chapter 6: Appendix
Contents Pages
1 Levels 2
2 Formulas 2
3 Conversion from the Power Level to the Voltage Level
and Vice Versa
3

Chapter 6: Appendix
2
Chapter 6
Appendix
1 Levels
The Absolute Level
The absolute level is a logarithmic value which shows the difference between
the measured value and the reference value.
Reference Values (relative point zero)
2
2 Formulas
Absolute power level:
nPabs = lg (Pm/1 mW) [B]
nPabs = 10 lg (Pm/1 mW) [dBm]
B=Bel; Pm = measured power
Absolute voltage level:
nUabs = 20 lg (Um/0.775 V) [dBu]
10 lg (Pm/1 mW) = 10 lg ((Um
2
x600 Ω) (0.7752
V2
xRm))
20 lg (Um/0.775 V) + 10 lg (600 Ω/Rm)

Chapter 6: Appendix
3
Absolute current level:
nlabs = 20 lg (lm/1.29 mA) [dBi]
10 lg (Pm/1 mW) = 10 lg ((lm
2
xRm) / (1.292
mA2
x600 Ω)) =
20 lg (lm/1.29 mA) + 10 lg (Rm/600 Ω)
3 Conversion from the Power Level to the Voltage Level and
Vice Versa
10 lg (Pm/1 mW) = 20 lg (Vm/0.775 V) + 10 lg (600 Ω/Rm)
absolute absolute correction
power level voltage level factor level
TIP
With a resistance of 600 Ω, the absolute levels of voltage, current and power
have the same value - if the recommended standard values are used!
In the field, the absolute power level and the absolute voltage level are used for
telecommunication path measurements.
The absolute power level may be calculated with the voltage level and the level
correction factor according to the above formula.
Important level correction factors ncor:
Rm [Ω] ncor [dB]
3000 -6.989
2400 -6.0206
600 0 = 0
250 3.82
150 6.0206 = 6
75 9.0309 = 9
50 10.79
35 12.43

Chapter 6: Appendix
4
dB level relation (e.g. attenuation or gain)
dBr relative level
referred to the zero relative level point,
dBm absolute power level, referred to 1 mW
dBu/dBv absolute voltage level, referred to 0.775 V
dBm0 absolute power level
referred to the relative level (dBr),
relation: dBm0 = dBm - dBr
dBm = dBr + dBm0
dBv0 absolute voltage level
referred to the relative level (dBr),
relation: dBv0 = dBv - dBr
dBv = dBr + dBv0
dBmp absolute (noise) power level, referred to 1 mW
and CCITT weighted,
weighted = pondered
i.e. measured with a psophometer, A-filter
dBm0p absolute (noise) power level,
referred to the relative level and CCITT weighted
relation: dBm0p = dBmp - dBr
dBmp = dBr + dBm0p
dBrnc absolute noise level, "C-characteristic" weighted,
reference noise c-characteristic weighting
dBa absolute noise level, "FIA-characteristic" weighted,
adjusted weighting acc. to FIA characteristic
dBV absolute peak-to-peak voltage level
for TV signal measurements
relation: OdBV = 1 Vpp/75 Ω
= 2.2 dBm/75 Ω
= -6.8 dBv/75 Ω

Chapter 6: Appendix
5
dBvs absolute voltage level in the sound channel,
referred to 0.775 V
dBvps absolute (noise) voltage level in the sound channel
referred to 0.775 V and CCITT weighted
dBv0ps absolute (noise) voltage level in the sound channel,
referred to the relative level (dBr)
and CCITT weighted.

1
Application of Plesiochronous
Multiplex Systems
Pages (1-8)
2
Time‐Division Multiplexing of
Digital Signals
Pages (1-19)
3
Frame Structure of the Digital
Signal Hierarchies 2..4
Pages (1-8)
4
Functional Description of
Multiplexer/Demultiplexer
Pages (1-6)
5
Baseband Transmission of Digital
Signals
Pages (1-14)
Sub ‐ Sections

PDH Basics

Chapter 1: Application of Plesiochronous Multiplex Systems
1
Chapter 1: Application of Plesiochronous Multiplex
Systems
Aim of study
This chapter introduces digital signal hierarchies.
Contents Pages
1 Introduction 2
2 Digital Signal Hierarchies 3
3 Connecting Options for the Digital Multiplex Systems 5

2
Chapter 1
Application of Plesiochronous Multiplex Systems
1 Introduction
Digital multiplexers are applied wherever a high transmission capacity with
effective use of transmission paths to be realized.
The basic idea of multiplexing is the time-interleaving of digital signals of
different sources i order to form a common signal with a bitrate which is
correspondingly higher (multiplex process). On the system's receiving side the
appropriate separate signals are reobtained from the sum signal (demultiplex
process). This means that the original digital signals of the multiplexed signal
sources are available again at the output of such a system.
Example:
The output signals of four PCM30 systems are combined to a signal of 8 Mbit/s
and transmitted via a common transmission path to the receiving side (multiplex
procedure).
On the receiving side the sum signal is then distributed to the corresponding
input of PCM30 systems (demultiplex procedure).
In this example only one direction of transmission is shown.

3
Fig. 1
2 Digital Signal Hierarchies
2.1 Multiplex Hierarchy (CEPT)
The European plesiochronous digital hierarchy (CEPT-standard) is based on a
2048 kbit/s digital signal (stage 1) which may come for example from a PCM30
system, a digital exchange or from any other device in accordance with this
interface norm (standard). Starting from this signal the next higher hierarchies
are formed, each having a transmission capacity which is four times the previous
one.

4
The multiplying factor for the bitrates is greater than four, as for each hierarchy
level additional bits for pulse frame generation and other additional information
are inserted.
Fig. 2
2.2 Multiplex Hierarchy PCM24
The plesiochronous hierarchy used in USA and Japan is based on a 1544 kbit/s
digital signal (PCM24). From the table below the structure of superordinate
hierarchy levels can be seen.
Only the CEPT-hierarchy will be dealt with in the following.
Fig. 3

5
3 Connecting Options for the Digital Multiplex Systems
Each multiplexer normally has
• 4 inputs/outputs for the lower hierarchy level (Tributaries).
• One input/output for the higher hierarchy level. As to Siemens systems,
the lower hierarchy level is termed F2-side (secondary side), the higher
one F1-side (primary side).
The inputs/outputs 1 to 4 can be connected with any type of system which is in
accordance with the corresponding CCITT interface conditions.
Some examples for the connection of the individual multiplexers are represented
on the following pages.
Connecting Options for the Multiplex System 2/8 Mbit/s
Fig. 4

6
Connecting Options for the Digital Multiplex Device DSMX 8/34 Mbit/s
Fig. 5

7
Connecting Options for the Digital Multiplex Inset DSMX 2/34 Mbit/s
Fig. 6

8
Connecting Options for the Digital Multiplex Inset DSMX 34/140 Mbit/s
Fig. 7

Chapter 2: Time‐Division Multiplexing of Digital Signals
1
Chapter 2: Time-Division Multiplexing of Digital
Signals
Aim of study
This chapter introduces basic methods of multiplexing and basic pulse frame structure.
Contents Pages
1 Basic Methods of Multiplexing 2
2 Synchronization between Transmitting End and Receiving End 4
3 Definition of Plesiochronous Digital Signals 6
4 Clock Alignment of Plesiochronous Signals 9
5 Basic Pulse Frame Structure 11
6 Realization of the Positive Justification Method 13

2
Chapter 2
Time-Division Multiplexing of Digital Signals
1 Basic Methods of Multiplexing
For the generation of the sum signal out of the individual separate signals the
following two methods may be used:
Code word interleaving
With this method code words of the individual separate signals (i.e. bit
combinations having some kind of relation between each other) are arranged one
after the other in a time sequence. Such is the case for the generation of a 2-
Mbit/s-signal, where the 8 bit binary words of the coded PCM-voice channels
are transmitted sequentially in a 125 µs cycle.
This figure shows the code word interleaving of two separate signals with a
word length of four bits.
Fig. 1

3
Bit-by-bit interleaving
This method is used for all systems beyond the 2 Mbit/s hierarchy. Here a cyclic
transmission sequence is applied, where only one bit of each separate signal is
transmitted. This means that the signal of a certain multiplexer input appears
only in every fourth bit of the sum signal.
The figure shows the bit-by-bit interleaving of two separate signals.
Fig. 2
Two basic cases can be distinguished with multiplexing:
1. The original signals are synchronous, i.e. their clocks are exactly the same.
This is valid for a PCM30 system, where the clocks of the individual 64-
kbit/s-signals and the 2 Mbit/s-clock are derived from a central system
clock. In this case the multiplexing process is restricted to a simple
parallel-to-serial conversion of the 8 bit code words.

4
2. The original signals are not synchronous, i.e. their clocks come from
different sources. This is valid for the multiplexing of output signals,
originating from various PCM30 systems their clocks being generated in
each system in an autonomous way. Here it is necessary to take
appropriate measures in order to compensate the occurring clock
differences.
2 Synchronization between Transmitting End and Receiving
End
For each type of multiplexing it has to be ensured that the sum signal can be
resolved into the individual original signals (demultiplexing process). The
receiver of the sum signal thus has to know which bits are assigned to the
individual subsystems. To allow for this, a fixed bit combination, the so-called
frame alignment word (FAW) is inserted by the transmitting system in
periodically recurring intervals into the sum signal.
If the receiver detects the frame alignment word in the received signal it is
possible to perform the assignment of the following bits to the subsystems by
means of the regenerated receiving clock.
The time intervals between the beginning of a FAW and the beginning of the
following FAW are called pulse frames.

5
Fig. 3
2.1 Recovery of Frame Alignment
During recovery of frame alignment (e.g. during initial commissioning of a
system) the receiver continuously examines the incoming signal upon
occurrence of the FAW. If this FAW is detected for the first time, the receiver
expects a renewed occurrence only after the specified pulse frame period has
elapsed (counting of the receiving signal clocks). In this case the process will be
repeated; the synchronization is established. Otherwise, the system takes the
continuous searching up again. This procedure ensures that a synchronization to
a bit combination, which accidentally has the same content as the FAW, is
excluded.

6
2.2 Loss of Frame Alignment
Only if the FAW does not appear in the expected positions for several
consecutive times (e.g. four) the frame alignment is supposed to be lost. This
guarantees that in case of transmission errors the system does not perform an
immediate desynchronization.
For each faulty frame alignment word a pulse is produced, which can be used
for the estimation of the bit error rate (see also chapter 6, in-service
measurement of bit error rates).
3 Definition of Plesiochronous Digital Signals
Supposed a data source (S) transmits a digital signal with a bitrate fS to a data
drain (D). The data drain decides with the aid of an internally generated clock
frequency fR whether the incoming signal is zero or one in the moment of the
clock pulse. The two clock signals fS and fR are thus generated in different
places and although they do have the same nominal frequency, they will always
differ from each other to a certain extent.
Definition:
Data signals are termed plesiochronous if their clock rates have the same
nominal value, but may differ from each other within certain tolerance ranges.

7
Fig. 4
The effects of these clock deviations are represented in the two figures below:
Sampling clock fR > transmission clock fS
Two sampling instants are within one bit interval of the transmitting signal. The
data drain (D) interprets this situation as double transmission of bit a5.
Fig. 5

8
Sampling clock fR < transmission clock fS
One transmitted bit is between two sampling instants. Bit b5 not detected by the
data drain (D).
Fig. 6
Plesiochronism during Multiplexing Process
The multiplexing process may be represented with the aid of the following
figure.
A rotating pointer samples the feeder links (tributaries) for the separate signals
with a frequency which is four times higher than the nominal bitrate
fS (fR = 4 X fS), i.e. each digital signal is sampled with a nominal fS. As both, the
digital signal sources (S1...S4) as well as the sampling frequency (fR) are
generated by different clock sources, the result is a plesichronous state of
operation for every feeder link.

9
Example:
The signal sources (S1...S4) are PCM30 devices transmitting with their
individual transmission clock a 2 Mbit/s-signal with clock tolerances to the
inputs of a 2/8 multiplexer.
Fig. 7
4 Clock Alignment of Plesiochronous Signals
During multiplexing of plesiochronous digital signals the so-called positive
justification method is applied, which is based on the following principles:
• A bitrate for each subsystem is provided in the multiplex signal, which is
somewhat higher than the subsystem’s nominal bitrate. This means that
the transmission capacity is systematically higher than actually needed.
• The difference between the bitrate of the subsystem and the multiplex
bitrate per system is compensated for each channel by the justification
bitrate, which does not contain any information and serves only for the
compensation mentioned above.

10
• The justification bitrate is thus always adjusted to the difference between
the bitrate of the subsystem and the multiplex system and thereby
compensates for each channel the tolerance between the tributary signal
bitrates and multiplex signal bitrates.
Example:
Fig. 8
• The signal sources S1..S4 emit signals with a nominal value of 2048
kbit/s.
• The sampling pointer rotates with a frequency of fR = 2052 kHz, i.e. the
transmission capacity per channel is 4 kbit/s higher than the nominal
bitrate of the subsystem.
• Supposed the signal sources transmit the following actual bitrates:
S1 : fS1 = 2048.1 kbit/s
S2 : fS2 = 2048.05 kbit/s
S3 : fS3 = 2048.0 kbit/s
S4 : fS4 = 2047.9 kbit/s

11
This results in the following justification bitrates:
For channel 1: 2052 kbit/s - 2048.10 kbit/s = 3.90 kbit/s
channel 2 : 2052 kbit/s - 2048.05 kbit/s = 3.95 kbit/s
Thus, the resulting signals at the rotating pointer’s sampling points are
synchronous. The multiplexing procedure can be performed without the former
discussed problems of omission or double sampling of individual bits.
5 Basic Pulse Frame Structure
How is a variable justification bitrate realized?
The signals of higher hierarchy levels are transmitted within a predetermined
frame structure, the same as for the 2 Mbit/s signal of the first hierarchy level.
This frame begins with a frame alignment word of fixed length and content in
order to allow on the demultiplex side of the system an allocation of the
following bit-interleaved tributary bits to the appropriate channels. In addition,
the frames of the plesiochronous hierarchy contain one bit position per
individual signal, which is either used for the transmission of a tributary bit, or
not used at all. This bit position is called justification bit. By alternate use/non-
use of this bit position, the transmission capacity for the individual signals may
be varied to some extent.
This process is called positive pulse justification; thus, the non-use of the
justification bit position corresponds to an increase in the justification bitrate (=
decrease in the transmission capacity), whereas the use of the justification bit
position has the opposite effect.

12
Fig. 9
The receiving end of such signals requires information on how the justification
bit position has been used (non-information bit or tributary bit). To allow for
this, there are justification service bits arranged before the justification bits in
the time sequence. The content of the justification service bits indicates how the
following justification bit position has to be interpreted. If, for example, the
content of the justification service bit for channel 3 is a binary one, the receiver
ignores the following justification bit positions of channel 3. The other way
round (JS3 = 0), the position JB3 is interpreted as tributary bit.
Example:
The frame structure in a 8 Mbit/s pulse frame:
Frame duration: 100.38 µs
Overall number of bits in blocks TB1:200 bit, TB2:208 bit, TB3:208 bit,
TB4:204 bit or 208 bit.
This results is an actual bitrate/channel

13
This is the bitrate /channel if the justification bit position is always unused.
If every justification bit position is used for a tributary bit of the separate signal
the following actual bitrate/channel is calculated:
By alternate use/non-use of the justification bit position in the frames the
transmission capacity for the individual channels in this example may be varied
within a range of 9.962 kbit/s.
6 Realization of the Positive Justification Method
6.1 The Elastic Store (Multiplex-Side)
How can the justification process be realized?
An elastic store consists of a number of 1 bit memory cells (typ. 12) which can
be written in and read out independently of each other (i.e. at the same time it is
possible to write in one cell, while another is read out). The incoming separate
signal with its own clock is written in the cells 1...8, 1...8 etc. in a cyclic way.
The store is read out with a clock, generated in the multiplexer; a clock which is
systematically higher than the bitrate of the separate signal. The difference
between write address and read address is monitored by an address comparator.
It goes without saying that the write address always has to be ahead of the read
address. Due to the greater read out velocity the read address continually
approaches the write address. If the difference between the two becomes < 3
memory cells, the comparator releases a signal.

14
Then the following procedures are started:
If the justification service bit position in the frame is reached, the bit is set to
one. On reaching the justification bit position, the read address is maintained for
one clock period and the actual memory cell is read out once more. This is the
justification bit which is ignored at the receiving end. By maintaining the read
address during one clock cycle the difference between the addresses increases
and the whole procedure is repeated in the same way. Thus, the plesiochronous
clock rate of the channel is matched to the multiplex bitrate.
Between the initiation of the justification process (comparison of addresses) and
its execution there may be an interval of max. 1 frame period, within which the
read address approaches the write address more and more. That is why the
justification process is initiated already when the address spacing is smaller than
3, in order to ensure a reserve against memory overflow, e.g. an empty memory.
Each channel is assigned an elastic store. As the read out clock for all channels
come from the same clock supply (in the multiplexer), the output bitrates of the
elastic stores are synchronous. The actual multiplexing procedure is thereby
continued to a simple parallel-to-serial conversion of the output signals of the
elastic stores for the four separate signals.

15
Fig. 10 Principle of an elastic store

16
Fig. 11 Block diagram of an elastic store
Realization of the positive justification method
Positive justification method: f2 > f1
Fig. 12

17
Example (see also fig.12):
• The bitrate of the input signal shall be f1 = 2048 kbit/s.
• The pulse frame of the multiplex signal shall be 100, 38 µs and contains 1
justification bit per channel.
• The read out timing rate shall be 2052 kbit/s.
The reading pointer would overpass the writing pointer (2052 kHz-2048
kHz = 4 kHz) 4000 times per second. That is why on average one
justification bit is inserted every 250 µs (1/4 kHz = 250 µs). For a pulse
frame of 100, 38 µs, this means that one justification is effected on
average in every 2,5th frame (250 µs/ 100, 38 µs) (2 in 5 frames).
• The bitrate of the input signal shall now be T1 = 2047, 90 kbit/s.
Now the justification must be effected every 243, 90 µs, i.e. in every 2,4
pulse frame.
• The bitrate of the incoming signal shall be T1 = 2048, 10 kbit/s.
A justification is required every 256, 40 µs, i.e. in every 2, 56 frame
6.2 The Elastic Store (Demultiplex-Side)
The task of the demultiplexer is to distribute the sum signal in the right sequence
to the output of the separate signals. Therefore, the incoming multiplex signal is
divided into 4 separate signals by means of parallel-to-serial conversion. By
control of the frame alignment signal the 4 separate signals can be assigned to
the right channels. Besides, the justification service bits and justification bits can
be identified (by counting the bits transmitted since the beginning of the frame).
By means of this information the justification process is canceled, i.e. all bits
which do not come from the original signal are removed from the separate
signals.

18
Thus, a signal with timing gaps instead of the removed bit positions is
generated. In order to guarantee a continuous signal at the outputs, elastic stores
are used on the demux-side to smooth the signal.
For this, the incoming datas signal is written into the store with the gap timing
and read out of the store with a continuous timing which corresponds to the
average value of the gap timing; thus the signal is forwarded in a smoothed
condition to the outgoing subsystem interface.
Fig. 13 Principle of an elastic store (demultiplex-side)

19
A continuous timing is generated from the gap timing by means of a phase-
locked loop (PLL). For this, a voltage-controlled oscillator is synchronized to
the gap timing frequency. If the critical frequency of the control loop is selected
sufficiently low (low-pass filter) it is ensured that the voltage-controlled
oscillator adjusts itself to the average value of the gap timing frequency.
6.3 Jitter caused by Multiplexers
The gap in the write clock of the elastic store result in phase shifts on the input-
side of the PLL’s phase comparator, which are converted to voltage shifts. These
voltage shifts are smoothed by the low pass filter of the PLL, but they can never
be smoothed perfectly.
That is why the smoothed clock of the control voltage will vary accordingly also
at the output of the PLL circuit, i.e. jitter is generated. The jitter in the output
signal depends on the system. The highest jitter frequency is determined by the
limit frequency value of the PLL low-pass filter.

Chapter 3: Frame Structure of the Digital Signal Hierarchies 2..4
1
Chapter 3: Frame Structure of the Digital Signal
Hierarchies 2..4
Aim of study
This chapter introduces frame structure of 8, 34, 140 Mbit/s hierarchies.
Contents Pages
1 Frame Structure of 8, 34, 140 Mbit/s Hierarchies 2
2 Timing Sequence of the Multiplex Process 6
3 Transmission of Additional Data Channels with Y-Bits 8

2
Chapter 3
Frame Structure of the Digital Signal Hierarchies 2..4
1 Frame Structure of 8, 34, 140 Mbit/s Hierarchies
Alignment word
The frame of all hierarchy levels begin with the frame alignment word (FAW),
by means of which the receiving system (demultiplexer) detects the beginning of
the frame and is thus able to interpret the following bit positions correctly.
Besides, an in-service-supervision of the incoming signal’s bit error rate can be
performed by continuous evaluation of the FAW.
Signaling bits D, N
Immediately after the FAS the signaling bits D and N are transmitted. They
provide information about the state of the opposite transmission direction.
Hereby, urgent alarms (failure) are signaled via the D-bit (remote alarm
indication RAI), and non-urgent alarms (interference) via the N-bit. If it is
possible to renounce the backward transmission of non-urgent alarms, the N-bit
can be used for the asynchronous transmission of external data (so-called Y-data
channels via V.11 interface).
Blocks TB
Here the signals (tributary bits) of channels 1...4 are transmitted bit-by-bit
interleaved.

3
Blocks JS
These blocks consist of 4 bits and contain the justification service bits of
channels 1...4. In order to provide a protection against transmission errors, the
justification bits are transmitted in a redundant way and evaluated on the
receiving end by majority decision. The 3 JS blocks (5 at 140 Mbit/s) contain
the same information in the bit error-free state. If, due to a transmission error,
one of the justification service bits (2 at 140 Mbit/s) is wrongly detected, the
majority decision nevertheless allows the correct evaluation of the following
justification bit positions. A wrong interpretation of the justification bit position
would inevitably result in a desynchronization of the affected subsystem.
Fig. 1

4
Probability of a loss of synchronization depending on the bit error rate due to
• Loss of the justification information: (2 J) at 8 Mbit/s
(3 J) at 140 Mbit/s
• Loss of the frame alignment: (2) at 8 Mbit/s
(3) at 140 Mbit/s
Block JT
This block contains the justification bit positions (justifying bit or tributary bit)
and is integrated into a TB block. By use respectively non-use of this bit
position, the transmission capacity is matched of the individual channels (as
described in the previous sections).
8-Mbit/s-Pulse Frame
Fig. 2

5
34-Mbit/s-Pulse Frame
Fig. 3
140-Mbit/s-Pulse-Frame
Fig. 4

6
In addition to the service bits this frame has two data bits, which can be used for
the asynchronous transmission of external data signals with bitrates of up to
approx. 10 kbit/s.
2 Timing Sequence of the Multiplex Process
Fig. 5 Time sequence of the address difference in the elastic store depending on the frame
structure
The figure shows an example of the time sequence of the address difference
between write in respect. read out address of the elastic store along several
frames. The rising edges (reduction of the distance between addresses) occur in
the tributary information blocks, i.e. when the store is read out. Every time if no
tributary information is transmitted (with JS, FAS) the read out process is
interrupted (1 clock at JS, 3 clock at FAS) and the difference between the
addresses increases accordingly (1 address at JS, 3 addresses at FAS).

7
Despite of these interruptions of the read out process, the actual read out timing
frequency is higher than the write in frequency.
The necessity of the justification is determined in frame Nr. N (getting below the
difference of 3 bits). Then all justification service bits (JS) of the affected
channel are set to 1 in frame N + 1.
When the justification bit position (JT) in frame N + 1 is reached, the read-out
address is stopped during one clock cycle; the transmitted bit is interpreted as
justification bit and the difference between the addresses increases by one
address.
Example:
Let us look at a multiplex system 2/8 Mbit/s and at the structure of the 8 Mbit
frame. The nominal write in frequency is fE = 2048 kHz. The elastic store is read
out during the tributary information blocks with one fourth of the system clock:
This read out clock is interrupted by the JS, FAS blocks. The actual read out rate
results from the relation of tributary bits per frame to the overall number of bits:
The nominal justification bitrate fj can be calculated from the difference between
fM and fE.

8
3 Transmission of Additional Data Channels with Y-Bits
With the frame of the 8 and 34 Mbit/s hierarchy the N-alarm bits can be used for
transmission of external data channels. The 140 Mbit/s frame has two specially
designed bit positions (so-called Y-bits) for this purpose. The bitrate for one Y-
bit corresponds to the frame clock.
This bitrate cannot be used for the external signal, as for this a synchronization
to the frame clock would be necessary. Therefore, the maximum allowable
bitrate for the external data signal is restricted to approx. one fifth of the Y-
bitrate. One bit of the signal to be transmitted is then sampled several times by
the Y-bits (Oversampling).
The distortion of the transmitted signal results from the relation of the Y-bitrate
to the bitrate of the signal to be transmitted.

Chapter 4: Functional Description of Multiplexer/Demultiplexer
1
Chapter 4: Functional Description of
Multiplexer/Demultiplexer
Aim of study
This chapter introduces functional units of the multiplexer & the demultiplexer.
Contents Pages
1 Functional Units of the Multiplexer 2
2 Functional Units of the Demultiplexer 3
3 Supervision and Alarms 5

2
Chapter 4
Functional Description of Multiplexer/Demultiplexer
1 Functional Units of the Multiplexer
The incoming separate signals of inputs F2 are regenerated and the individual
line-code is decoded (D1..D4). Besides, the clock of the input signal is also
regenerated (T1 .. T4). With these clocks the digital signals are cyclically written
into the elastic store (ES) where the plesiochronous bitrates are matched to the
F1 clock (multiplex clock). The ES are read out by a central gap timing GT
which has an instantaneous frequency of one fourth of the multiplex bitrate and
shows extraction gaps in the time intervals for the FAS and the justification
service bits.
The output signal of the ES already contains the justification service bits and
justification bits and has gaps only for the FAS.
In the ensuing parallel-to-serial converter the synchronous output signals of the
ES are put together to form the multiplex signal. In addition, the FAS and the D-
bits respectively N-bits are inserted here into the timing gap of the ES output
signal. These D- and N-bits come from the supervision section of the
multiplexer and thus feeded from the outside.
The signal that has been formed in this way is transformed into the line code and
matched to the F1 interface.

3
Fig. 1 Functional diagram of the multiplexer
Fig. 2 Gap timing for the reading out of the ES (simplified representation)
2 Functional Units of the Demultiplexer
The incoming signal of input F1 is regenerated and decoded. The receiving
clock is recovered and controls all processes on the demux-side.

4
Then the signal is converted from serial to parallel and thus distributed
arbitrarily to the four outgoing lines. The following FAS detector performs two
tasks. First, it determines how the FAS is distributed to the four lines, and thus
allows an allocation of the lines to the channels. Secondly, it supervises the
periodical occurrence of the FAS, and thus allows a synchronization to the
transmitting signal. In the channel switch-over the four separate signals are
controlled by the FAS detector and distributed to the right channels. The
justification service bit evaluation forms the individual gap timings with the aid
of the frame clock and the regenerated receiving signals. For this the clock is
suppressed during the FAS-period and the JS bit positions. In addition, the data
signals D1...D4 are evaluated at the instant of the JS bitpositions. If the
evaluation result indicates that a justification position follows, the clock is
suppressed at the justification bit position for the individual channels
(GT1...GT4).
These gap timings GT1...GT4 ensure that only tributary information bits are
written into the ES. The ES are read out with the smoothed gap timing (PLL).
Before each output there is an encoder, which converts the signal into the
individual line codes.

5
Fig. 3 Functional diagram of the Demultiplexer
3 Supervision and Alarms
Multiplex systems have a section which supervises the system’s state of
operation and initiates alarm reactions in case of interference.
The supervision functions are as divided into three groups:
• Supervision of the incoming signals at the F2in interfaces.
• Supervision of the incoming signals at the F1in interfaces.
• Supervision of device internal functions.

6
Likewise, the alarm reactions can be divided into:
• Optical display of alarm at the system inset.
• Emission of an AIS signal.
• Forwarded of alarms to the local alarm system.
• Release of signaling bits to the remote station.
Fig. 4 shows at which position in the signal path the various criteria are
supervised, respect. Where AIS, D-and N-bits are inserted.
Fig. 4 Supervision functions in a multiplex system (see also next page)

1
Aim of study
This chapter introduces interface codes, digital signal regeneration & reasons for bit errors.
Contents Pages
1 Introduction 2
2 Interface Codes 3
3 Digital Signal Regeneration 7
4 Reasons for Bit Errors 11

2
Chapter 5
Baseband Transmission of Digital Signals
1 Introduction
Digital signal devices process the signals as purely binary information, i.e. the
signal level does not change between bits with the same logical state. For this
reason, these so-called NRZ-signals (No return to zero) can only be processed
together with the corresponding clock, which enables the identification of
individual bit positions.
Fig. 1 Processing of NRZ signals with the aid of separate clock
This clock is not separately transmitted and thus it has to be possible to derive
(i.e. regenerate) the clock from the data signal on the receiving side. It is
obvious that for a NRZ code this is very complicated, if not virtually impossible.
A further disadvantage of the NRZ code is that it carries a certain amount of dc-
voltage which excluded the signal’s galvanic isolation at the interface
(transformer etc.). Due to these disadvantages, various interface codes have been
developed; all of which comply with the following requirements:
• Good clock retrieval features.
• No dc-component.

3
2 Interface Codes
A suitable interface code has a maximum of transitions between the different
signal levels, even for the transmission of lengthy sequences of identical logical
states; it has no dc-component. The survey shows the development of individual
codes (fig. 2).
RZ Code A log. 1 is represented as half-bit with a change of signals levels
from Low High Low.
Advantage: Clock retrieval possible also for adjacent log.1 bits.
Disadvantage: No clock information for zero sequences, dc-
component.
AMI Code The state log. 1 is represented alternatively as positive or
negative signal level.
Advantage: Clock retrieval possible also for adjacent log.1
bits, no dc-component.
Disadvantage: No clock information for zero sequences.
HDB 3 Code Is derived form the AMI code? Here, four consequent zero bits
are replaced by a 1001 or 0001 combination. This is done in such
a way that the signal receiver detects the mutilation of
informational contents and cancels it.
Advantage: Maximum clock information, no dc-component.

4
Disadvantage: None this code is applied for the device
interfaces from 2 Mbit/s up to 34 Mbit/s
(baseband transmission). The exact coding rules
are enumerated in the following.
CMI Code Due to its easy generation with delay lines and simple gate
functions the CMI code is suited especially for interfaces with
high bitrates. Therefore, this code is standardized for the 140
Mbit/s device interfaces.
A further important advantage of the interface code is the possibility it offers to
detect transmission errors by supervising the coding rules. With the HDB3 code,
for example, the receiving of four zero bits would represent the violation of a
coding rule, i.e. at least one bit error must have been occurred during
transmission.
The standardization of interface codes only refers to device interfaces. The
codes for conductor-bound transmission paths are manufacturer-dependent and
are generally adapted to the requirements of the respective terming unit.

5
Digital Line Codes
Fig. 2
Fig. 3 Amplitude spectrum of various codes

6
Fig. 3 shows the amplitude spectrum of various interface codes. For codes
without a dc-component the maximum energy is within the range of a frequency
which corresponds to half of the bitrate value. This is obvious when comparing
the definitions of frequency and bitrate respectively.
Fig. 4 Bit sequences 0101....
The bit sequence represented in fig. 4 shall serve as an example. One signal
period covers 2 bits and corresponds to the basic wave of the data signal. This
wave contains the greatest amount of energy and has a frequency which equals
half of the bitrate value. This is also the frequency that is indicated by a
frequency counter connected to a source of a digital signal.
HDB3-Coding rules
(Third-Order-High-Density-Bipolar-Code)
The HDB3-code is a modified version of the AMI-code. Binary signals or AMI-
code signals may contain lengthy “0“ sequences, which hinder the clock
retrieval in the regenerative repeaters along digital transmission paths. The
HDB3 code enables the elimination of “0“ sequences with more than 3 zeros.
1. If there are more than 4 consecutive “0“-signal elements, the fourth “0“-
signal element shall be replaced by a V-signal element (=„1“-signal
element. A V-signal element causes a Violation of the AMI-rule.

7
2. If between the V-signal element, inserted according to the conditions
specified above (rule 1), and the preceding V-signal element there is an
even number of “1“-signal elements, then the first of four “0“-signal
elements shall be replaced by an A-signal element (=“1“-signal element).
The polarity of the A-signal element complies with the AMI-rule. The last
of four “0“-signal elements becomes again a V-signal element (A00V). In
this the A- and V-signal elements have the same polarity.
Fig. 5 Conversion of binary signals into HDB3-signals
3 Digital Signal Regeneration
The digital signal regeneration is one of the advantages of the digital
transmission technique. Theoretically, it enables the signals to be transmitted via
an unlimited distance without any quality loss.

8
During transmission, a digital signal is attenuated and distorted; which results in
a reduction of the signal /noise ratio. The regeneration process has the task of
canceling such distortions and regenerating the originally sent signal from the
actually received signal. That is why every interface on the receiving side is
followed by a regenerator.
Fig. 6 Principle of digital signal regeneration
Four basic function blocks are necessary for the digital signal regeneration:
• Amplification block (balancing of attenuation losses).
• Clock retrieval block.
• Amplitude decision block.
• Time decision block.

9
Fig. 7 Block diagram of a digital signal regenerator
These four functions are represented in next figure.
• The receiving signal is fed into a controlled amplifier (AGC) which keeps
the amplitude of the outgoing signal at a constant value over a wide range
of incoming amplitudes. Thus, the attenuation of the transmission path is
balanced.
• The constant output level is a precondition for the functioning of the
amplitude decision block (AD) which follows. This AD decides on the
basis of an internal threshold value whether the level of incoming signal is
above or below this threshold. Accordingly, a signal with the level Log. 1
or Log.0 is emitted at the output. The output signal thus consists of pulses,
the width of which only depends on the period during which the output
signal exceeds the decision threshold.

10
• The time decision block (TD) has the task of generating signal pulses with
constant width. For this, it requires the regenerated receive signal clock
which samples the output signal of the amplitude decision block. If, at the
time of sampling the signal has a level of Log. 1, the time decision block
emits a pulse with constant width. Thus, incoming pulses of any width are
turned into pulses corresponding exactly to the bit width of the transmitted
signal. The time decision process is the final stage of regeneration.
• The clock retrieval CR block is in charge of regenerating the transmitted
signal clock from the receive signal clock. In order to effect this function,
a phase locked loop (PLL) is employed, basically consisting of a voltage-
controlled oscillator whose frequency can be changed by a control-
voltage.
By adequate evaluation of the receiving signal it is now possible to reach a
control voltage which can set the oscillator to the exact clock frequency value of
the transmitting signal.
The following examples show a regenerator for HDB3 signals, as well as the
signal shape between individual function blocks.

11
Fig. 8 Regeneration of HDB3 signals
4 Reasons for Bit Errors
The decisive quality criterium for the transmission of digital signals is the so-
called bit error rate (BER). This BER represents the proportion of bits which
have been mutilated (i.e. incorrectly recorded) during transmission, to the total
amount of bits transmitted within a certain interval. The BER directly influences
the quality of the transmitted services (e.g. voice channels, data channels, video
signals). Two significant BER are explained exemplary in the following:

12
• BER = 10-6
This BER virtually cannot be perceived in a voice channel. For the
transmission of data channels, however, this value represents the maximum
acceptable limit. The transmission system is in a state of "degraded quality",
which is indicated by a degradation alarm (low priority) on the devices
involved. The transmission path remains, nevertheless, in operation.
• BER = 10-3
This BER causes a strong interference noise in a voice channel. The
operating state is judged to be of "unacceptable quality", which is signaled
by the devices involved by the emission of a failure alarm (high priority).
The transmission path goes out of operation.
How do bit errors arise?
In the previous section it was mentioned that digital signals can be regenerated as
requested, i.e. a transmission without quality reduction is possible. This statement
is, however, only partially true, i.e. whenever the impairment of the transmission
signals is within limits which still permit the regeneration at the receiving side. The
reasons for the formation of bit errors are
• Low signal/noise ration.
• Jitter.
• Intersymbol interference.
Low signal/noise ratio
Noise amplitudes which influence the amplitude decision process are
superimposed to the originally sent signal.

13
The superimposed interference peaks lead to an incorrect signal interpretation at
the receiving end. Reasons for a low S/N-ratio are:
1. Too strong signal attenuation during transmission.
2. External interference during transmission.
For transmission in cable sections (especially optical fiber) both reasons can be
largely eliminated by careful planning.
Fig. 9 Low S/N-ratio
Jitter
Due to jitter, the transitions between signal levels log. 0 and log. 1 do not take
place at periodically recurring points in time (characteristically moments) as for
undisturbed signals, which means that the transitions oscillate around the
characteristically moments.
Jitter is characterized by jitter amplitude (unit intervals UI) and jitter frequency.
One UI means that, because of deviation from the characteristically moments,
the signal edges are within a range equal to the width of 1 bit.

14
The jitter frequency is the number of oscillations around the characteristically
moment per one second. Jitter influences the time decision process in the
regenerator and causes bit errors for high jitter amplitudes and frequency.
Jitter arises in the devices used for signal transmission. (I.e. in regenerators and
demultiplexers = systematical jitter), or on the transmission path due to external
influences (non-systematic jitter).
Fig. 10 Representation of a Unit Interval (UI)
Intersymbol interference
Is caused by a discrepancy between the bandwidth of the transmission path and
the bandwidth required for the digital signal. This leads to a bit extension, so
that there is an overlap of bits which follow each other. Thus, bit errors occur,
the reasons of which can be traced back to the impairment of amplitude decision
process. For conductor-bound transmission of digital signals this effect can be
excluded by adequate planning. For transmission on radio paths this effect is of
fundamental importance as the frequency response of the transmission path can
change due to atmospherically influence.

1 PDH Multiplexing Pages (1-12)
2
Principles and Characteristics of
the SDH
Pages (1-16)
3 Basic Elements of STM‐1 Pages (1-7)
4 Mapping Pages (1-50)
5 Pointer Pages (1-16)
6 Overhead Pages (1-26)
7
Monitoring, Maintenance and
Control in the SDH
Pages (1-33)
8 Appendix Pages (1-25)
Sub ‐ Sections

SDH Basics

Chapter 1: PDH Multiplexing
1
Chapter 1 PDH Multiplexing
Aim of study
This chapter introduces principles of PDH multiplexing and multiplexing / demultiplexing
of PDH signals.
Contents Pages
1 Introduction 2
2 Principles of PDH Multiplexing 2
3 ANSI / CEPT Bit Rates 3
4 Frame Structure of a PDH Signal 7
5 Multiplexing / Demultiplexing of PDH Signals 7
6 Summary 10
7 Exercise 11
8 Solution 12

2
Chapter 1
PDH Multiplexing
1 Introduction
In the early 1970s, digital transmission systems began to appear, utilizing a
method known as Pulse Code Modulation (PCM), first proposed in 1937.
PCM allowed analog waveforms, such as the human voice, to be represented
in binary form, and using this method it was possible to represent a standard 4
kHz analog telephone signal as a 64 kbit/s digital bit stream. Engineers saw
the potential to produce more cost effective transmission systems by
combining several PCM channels and transmitting them down the same
copper twisted pair as had previously been occupied by a single analog signal.
In Europe, and subsequently in many other parts of the world, a standard
TDM scheme was adopted whereby thirty 64 kbit/s channels were combined,
together with two additional channels carrying control information, to produce
a channel with a bit rate of 2.048 Mbit/s.
2 Principles of PDH Multiplexing
PDH signals with a higher transmission rate are obtained by multiplexing
several lower rate signals. The term PDH will be defined in the next few
pages, however, let us consider the following concepts:
Multiplex Operation
Four input signals with the same nominal bit rate are combined to form one
multiplex signal and then relayed to the receive side via one common
transmission path.

3
De-multiplex Operation:
On the receive side, the sum signal is again distributed to the corresponding
outputs.
Fig. 1
3 ANSI / CEPT Bit Rates
As demand for voice telephony increased, and levels of traffic in the network
grew ever higher, it became clear that the standard 2 Mbit/s signal was not
sufficient to cope with the traffic loads occurring in the trunk network. In
order to avoid having to use excessively large numbers of 2 Mbit/s links, it
was decided to create a further level of multiplexing. The standard adopted in
Europe involved the combination of four 2 Mbit/s channels to produce a single
8 Mbit/s channel. This level of multiplexing differed slightly from the
previous in that the incoming signals were combined one bit at a time instead
of one byte at a time i.e. bit interleaving was used as opposed to byte
interleaving. As the need arose, further levels of multiplexing were added to
the standard at 34 Mbit/s, 140 Mbit/s, and 565 Mbit/s to produce a full
hierarchy of bit rates.

4
The multiplexing hierarchy described above appears simple enough in
principle but there are complications. When multiplexing a number of 2
Mbit/s channels they are likely to have been created by different pieces of
equipment, each generating a slightly different bit rate. Thus, before these 2
Mbit/s channels can be bit interleaved they must all be brought up to the same
bit rate (called "adaptation"), adding 'dummy' information bits, or 'justification
bits'. The justification bits are recognize as such when demultiplexing occurs,
and discarded, leaving the original signal. This process is known as
plesiochronous operation, from Greek, meaning "almost synchronous".
The same problems with synchronization, as described above, occur at every
level of the multiplexing hierarchy, so justification bits are added at each
stage.
The use of plesiochronous operation throughout the hierarchy has led to
adoption of the term "Plesiochronous Digital Hierarchy", or PDH.
Another Explanation to help define PDH is:
If two digital signals are Plesiochronous, their transitions occur at “almost” the
same rate, with any variation being constrained within tight limits. These
limits are set down in ITU-T recommendation G.703. For example, if two
networks need to interwork, their clocks may be derived from two different
PRCs. Although these clocks are extremely accurate, there’s a small frequency
difference between one clock and the other. This is known as a Plesiochronous
difference.
It may be useful to explain the term Asynchronous at this stage:

5
In Asynchronous signals, the transitions of the signals don’t necessarily occur
at the same nominal rate. Asynchronous, in this case, means that the
difference between two clocks is much greater than a Plesiochronous
difference.
Standardized Bit Rates in the "Plesiochronous Digital Hierarchy" (PDH)
Traditionally, digital transmission systems and hierarchies have been based on
multiplexing signals which are plesiochronous (running at almost the same
speed).Also, various parts of the world use different hierarchies which lead to
problems of international interworking; for example, between those countries
using 1.544 Mbit/s systems (U.S.A. and Japan) and those using the 2.048
Mbit/s system.
To recover a 64 kbit/s channel from a 140 Mbit/s PDH signal, it’s necessary to
demultiplex the signal all the way down to the 2 Mbit/s level before the
location of the 64 kbit/s channel can be identified. PDH requires “steps” (140-
34, 34-8, 8-2 demultiplex; 2-8, 8-34, 34- 140 multiplex) to drop out or add an
individual speech or data channel. This is due to the bit stuffing used at each
level.
Comparison of the ANSI and CEPT Hierarchies
We will consider only two hierarchies, even though Japan has its own
hierarchy it will not be studied in this course.
• PDH in accordance with ANSI (American National Standards Institute);
basic bit rate employed is 1,5 Mbit/s, e.g. USA.
• PDH in accordance with CEPT (Conférence Européene des
Administrations des Postes et des Telécommunications) basic bit rate
employed is 2 Mbit/s, e.g. Europe.

6
Fig. 2
Fig. 3 Plesiochronous digital hierarchy

7
4 Frame Structure of a PDH Signal
Every signal within a CEPT hierarchy level has a specific frame structure
which basically consists of the following blocks:
Fig. 4 Frame structure of a PDH signal
5 Multiplexing / Demultiplexing of PDH Signals
A multiplex sum signal is generated from the partial signals 1, 2. 3 and 4 (also
termed input, incoming, or sub signals) through the method of bit interleaving
==> bit-by-bit multiplexing.
Fig 5

8
Fig. 6
Here, the insertion of the Frame Alignment Signal (FAS), the justification bits,
etc. into the multisignal is not yet taken into consideration.
The bits of the frame alignment signals (FAS) contained in the input signals I
and II respectively are also inserted bit-by-bit into the multiplexed signal.
Fig. 7

9
Caution!
After the multiplex operation, the two FAS no longer form a joint unit. Beside
performing the bit interleaving, the multiplexer has also the function to create
a new CEPT frame for the multiplexed signal. Within this frame, the tributary
information is represented by the two complete CEPT frames of input signals I
and II.
Fig. 8

10
There is no phase relationship between the FAS of the multiplexed signal and
the individual frame alignment signals of the tributary signals 1 and 2. A new
frame for the multiplexed signal is created. This new frame has its own FAS.
Fig. 9
6 Summary
Principles of PDH Multiplexing:
• Bit rates in accordance with ANSI: 1,5 Mbit/s, 6 Mbit/s and 45 Mbit/s
• Bit rates in accordance with 2 Mbit/s, 8 Mbit/s, 34 Mbit/s and 140 Mbit/s
CEPT:
• Every signal has a separate frame structure.
• Bit-by-bit multiplexing.
• No frame synchronization of the tributary signal inputs.
• The input signals of the tributaries are plesiochronous to each other, i.e.
their clock rates have the same nominal value, but there is, however, a
slight amount of variation between the two.

11
7 Exercise
1. What are the bit rates of the CEPT Hierarchy?
2. What are the elements of PDH frames and what is their function?
3. How many different FAS do exist in a 140 Mbit frame?

12
8 Solution
1. What are the bit rates of the CEPT Hierarchy?
2 Mbit/s
8 Mbit/s
34 Mbit/s
140 Mbit/s
2. What are the elements of PDH frames and what is their function?
FAS Frame Alignment Signal
D+N bit Service bits
TB Tributary bits
CB Control bits for justification
JB Justification opportunity bit
3. How many different FAS do exist in a 140 Mbit frame?
4

Chapter 2: Principles and Characteristics of the SDH
1
Chapter 2 Principles and Characteristics of the
SDH
Aim of study
This chapter introduces introduction to the Synchronous Digital Hierarchy SDH.
Contents Pages
1 Introduction to the Synchronous Digital Hierarchy SDH 2
2 ITU-T and SDH, an Introduction 4
3 ITU-T Recommendations for SDH Bit Rates 6
4 Structure of an STM-1 Frame 7
5 Byte-by-Byte Multiplexing of SDH Signals 8
6 Synchronization of STM-1 Frames 9
7 Line Codes used in SDH 11
8 Summary 14
9 Exercise 15
10 Solution 16

Principles of-mobile-communication-2011

Principles of-mobile-communication-2011

Recommended

Recommended

More Related Content

What's hot

What's hot (20)

Similar to Principles of-mobile-communication-2011

Similar to Principles of-mobile-communication-2011 (20)

Principles of-mobile-communication-2011