Penguin Computing suggestions at Open Compute Project (OCP) Summit 2018 for changes to OCP specifications for greater high-performance computing (HPC) efficiency.
C* Summit 2013: Time-Series Metrics with Cassandra by Mike HeffnerDataStax Academy
This document discusses using Cassandra to store time-series metrics data. It describes how the schema was matched to storage by using a measurement column family with rows organized by metric ID and time. It also covers optimizing data expiration through techniques like TTL expiration, synchronized compactions, and leveraging immutable sstable modification times. Effective monitoring is emphasized as well, including dashboards to track the ring and using Cassandra log volumes to identify issues.
Regular session taking place at Connect for developers working on Linux distributions to share progress on ARM Linux platform support. Users are also welcome to share their experiences using Linux distributions on ARM. The goal of the discussion is to identify areas in which Linaro can help.
Ocp updating the ocp compute voltage step response specificationPenguin Computing
Penguin Computing suggestions at Open Compute Project (OCP) Summit 2018 for changes to OCP specifications for greater high-performance computing (HPC) efficiency.
The ASR-9006-DC-V2 is a Cisco router chassis that supports DC power. It has slots for line cards, route switch processors (RSPs), and field-replaceable power entry modules (PEMs) that hold power supplies. The chassis requires separate purchase of components like line cards, RSPs, fans, and power supplies to be fully functional. It supports up to 7 terabits per second of throughput and uses redundant RSPs and power supplies for high availability.
Find out more about Infineon on our Homepage: www.infineon.com
Find here all information about High power semiconductors
for your industrial applications from Infineon. With this brochure we offer an overview of our product range.
Intel has achieved a breakthrough in transistor technology by developing high-k + metal gate transistors for its 45 nm process. These transistors significantly reduce leakage power and are the biggest advancement since polysilicon gate MOS transistors were introduced in the 1960s. Intel has made working 45 nm microprocessors using these new transistors, which will deliver higher performance and greater energy efficiency. Intel's 45 nm products are on track to begin production in late 2007 with three factories manufacturing 45 nm by early 2008.
design and analysis of voltage controlled oscillatorvaibhav jindal
The document describes the design of a low power consumption and low phase noise voltage controlled oscillator (VCO). It aims to implement the design of a VCO presented in a base paper in 180nm technology and then 45nm technology to achieve lower phase noise results. The key steps include designing the schematic and layout of the VCO in Cadence Virtuoso, simulating and analyzing the power consumption and phase noise, and comparing the results to the base paper. The design uses a combination of cross-coupled and balanced VCO configurations along with a LC tank circuit to minimize phase noise. Future work involves completing the 180nm and 45nm designs and analyses to optimize for lower power and noise.
C* Summit 2013: Time-Series Metrics with Cassandra by Mike HeffnerDataStax Academy
This document discusses using Cassandra to store time-series metrics data. It describes how the schema was matched to storage by using a measurement column family with rows organized by metric ID and time. It also covers optimizing data expiration through techniques like TTL expiration, synchronized compactions, and leveraging immutable sstable modification times. Effective monitoring is emphasized as well, including dashboards to track the ring and using Cassandra log volumes to identify issues.
Regular session taking place at Connect for developers working on Linux distributions to share progress on ARM Linux platform support. Users are also welcome to share their experiences using Linux distributions on ARM. The goal of the discussion is to identify areas in which Linaro can help.
Ocp updating the ocp compute voltage step response specificationPenguin Computing
Penguin Computing suggestions at Open Compute Project (OCP) Summit 2018 for changes to OCP specifications for greater high-performance computing (HPC) efficiency.
The ASR-9006-DC-V2 is a Cisco router chassis that supports DC power. It has slots for line cards, route switch processors (RSPs), and field-replaceable power entry modules (PEMs) that hold power supplies. The chassis requires separate purchase of components like line cards, RSPs, fans, and power supplies to be fully functional. It supports up to 7 terabits per second of throughput and uses redundant RSPs and power supplies for high availability.
Find out more about Infineon on our Homepage: www.infineon.com
Find here all information about High power semiconductors
for your industrial applications from Infineon. With this brochure we offer an overview of our product range.
Intel has achieved a breakthrough in transistor technology by developing high-k + metal gate transistors for its 45 nm process. These transistors significantly reduce leakage power and are the biggest advancement since polysilicon gate MOS transistors were introduced in the 1960s. Intel has made working 45 nm microprocessors using these new transistors, which will deliver higher performance and greater energy efficiency. Intel's 45 nm products are on track to begin production in late 2007 with three factories manufacturing 45 nm by early 2008.
design and analysis of voltage controlled oscillatorvaibhav jindal
The document describes the design of a low power consumption and low phase noise voltage controlled oscillator (VCO). It aims to implement the design of a VCO presented in a base paper in 180nm technology and then 45nm technology to achieve lower phase noise results. The key steps include designing the schematic and layout of the VCO in Cadence Virtuoso, simulating and analyzing the power consumption and phase noise, and comparing the results to the base paper. The design uses a combination of cross-coupled and balanced VCO configurations along with a LC tank circuit to minimize phase noise. Future work involves completing the 180nm and 45nm designs and analyses to optimize for lower power and noise.
The N9K-C9364C is a Nexus 9364C ACI Spine switch with 64 40/100G QSFP28 ports and 2 1/10G SFP+ ports. It supports 12.84 Tbps bandwidth and has 32GB memory, 256GB SSD, and a Broadwell-DE 4-core CPU. It measures 3.38 x 17.37 x 22.27 inches and weighs 36.9 pounds with power supplies and fans installed. Power options include 1200W AC or 930W DC power supplies.
The document describes a Super Rotor Sifter from Pelleting Technology Nederland that uses a uniquely designed rotating and vibrating steel-wire sieve to efficiently sift materials. It generates a high-quality sifting result while taking up minimal space. The special sieve design combines eccentric and centrifugal movements for optimal sifting, and has 25% more throughput than perforated sheets while using less energy and requiring less maintenance. The sifter is available in single, double, or changeable deck configurations to meet different sifting needs.
The ultra-low-power IDT 9FGVxxxx (clock generators) and 9DBVxxxx (buffers) are the latest members of IDT's leading portfolio of PCI Express Gen1, Gen2 and Gen3 solutions, which also includes switches, bridges, signal repeaters, flash controllers and timing. The new PCIe timing devices consume less than 50 mW of power -- less than one-tenth the power required by previous solutions. The ultra-low power consumption reduces heat dissipation to ease cooling requirements in large-scale cloud computing applications. The new clock generators and buffers are available with a variety of termination options and features. Presented by Ron Wade, Technical Marketing Manager, Integrated Device Technology, Inc. For more information about IDT's PCI Express solutions, visit www.idt.com/go/PCIe.
PCTL Automation Ltd is an electrical engineering solutions provider that specializes in designing, manufacturing, and servicing electrical switchboards, automation systems, voltage regulators, and customized solutions for commercial and industrial environments. It has over 15 years of experience offering products and services across East Africa. The company aims to establish itself as a premier manufacturer and supplier of electrical distribution and control products by offering world-class electrical products at revolutionary prices.
Uses of Larsa 4 d and Lusas 4 D models for Implementation of Cable Stayed ...Rajesh Prasad
The paper deals with how an engineering challenge confronted in a busy yard due to presence of a distressed bridge(ROB) was replaced by a Cable Stayed Bridge by adopting safe practices with proper quality and within the time frame. The paper was presented today ie 18.08.17 in a lecture organised by IIBE at Institution of Engineers, Mumbai
The document discusses innovations on Masterpact circuit breakers from Schneider Electric. It summarizes that Masterpact breakers have a unique basic platform that can be used for all CEI, UL, and ANSI breakers. It also discusses over 60 patented solutions for the breakers. Specific innovations mentioned include reduced number of parts, universal connectors, segregated control unit functions, interfaces for control units, metallic filters, current sensors, combined auxiliary switches, reduced sizes for accessories and coils, and increased ratings and endurances.
TPS Rail Brochure - Final V3 (Spreads in low quality no bleeds)Ripa Begum
Turbo Power Systems (TPS) is a global company headquartered in the UK that designs and delivers power electronics systems for rail transportation. With over 30 years of experience in the rail industry, TPS provides auxiliary power supplies, battery chargers, and traction power converters. They have successfully delivered projects for light rail, metro, regional, intercity, and high-speed rail systems around the world. TPS prides itself on high reliability, efficiency, and engineering expertise to provide customized power solutions.
The Dyadic Systems Mechatronics Cylinder series is a versatile linear actuator system available from US$295. It integrates a motor, encoder, drive and program memory into a single package for high accuracy, long life and low cost. Models range from 10-50 kgf thrust and include standard and dust-proof options. This document provides an overview of the product specifications.
Mirko Damiani - An Embedded soft real time distributed system in Golinuxlab_conf
An embedded system usually involves low level languages like C and highly customized hardware. In this talk we will see a use case of a soft real time system which was developed taking a very different approach, written in Go. We will see what are the advantages of this choice, along with its limits.
K30 i K50 Touch to przyciski pojemnościowe wyposażone w duży, jasny i różnokolorowy wskaźnik LED. Wersja K50 posiada średnicę 5cm, a K30 – analogicznie 3cm.
This document describes the design and implementation of a two-stage complementary metal oxide semiconductor (CMOS) operational amplifier using 45nm technology. It aims to examine the operational amplifier's performance under various parameters. The design process involves calculating transistor width-to-length ratios (W/L) to achieve specifications such as a gain of 80dB, phase margin, and power dissipation of less than a certain amount. Simulations including DC analysis, AC analysis, transient analysis, temperature analysis, and power analysis are performed in Tanner Tool to validate that the operational amplifier meets requirements and is stable under variations. The results show that the designed two-stage CMOS operational amplifier achieves the targeted 80dB gain and phase margin at a unity
The WS-X6716-10G-3CXL is a 16-port 10GbE fiber module line card for Cisco Catalyst 6500 series switches equipped with 16 10GbE fiber ports, a 40Gbps switch fabric connection, and distributed forwarding capabilities to support up to 1 million routes. It is suited for campus aggregation and data center access, and can be configured in oversubscription or performance modes to support virtual switch links.
Cisco Live! :: Cisco ASR 9000 Architecture :: BRKARC-2003 | Milan Jan/2014Bruno Teixeira
The document discusses the Cisco ASR 9000 architecture, which is designed for longevity and common hardware/software across products. It has a modular, distributed operating system called Cisco IOS XR. The ASR 9000 includes various chassis including the ASR 9001, ASR 9006, ASR 9010 and ASR 9922, which provide scalable switching capacity up to 96 terabits per second. It discusses the system components including line cards, switch fabrics, power supplies and control processors.
The document introduces several mechatronics cylinder models from Dyadic Systems for linear actuation. Key points:
- Models range from $295 to $695 and provide thrusts from 10-50kg with strokes from 50-300mm.
- Features include integrated motor, encoder and drive for precision; optimized screw and nut mechanism for accuracy and longevity.
- Models include basic, standard, dust-proof, and slider types for different environments and applications.
transparent led film display (Solufarm company profile mar 2017)주식회사솔루팜
- Solufarm develops transparent LED display technology using transparent film and electrodes, making displays much lighter than glass-based LED displays.
- The transparent LED films can be cut and bonded to various sized surfaces, including curved surfaces. They are offered in different resolutions and sizes from 300x300mm to 480x480mm.
- Solufarm provides digital signage systems including transparent LED displays, smart mirrors, and kiosks. They have applied their technology in places like agriculture markets, subway stations, airports, and casinos for advertising, scheduling, and wayfinding.
The document provides specifications for the Cisco Catalyst 9300-24P-A switch, including:
- It is a 24-port PoE+ switch with a 715W power supply and 445W of available PoE power.
- Key features include stacking bandwidth of 480Gbps, 32,000 MAC addresses, and 8GB of DRAM.
- Dimensions are 1.73 x 17.5 x 17.5 inches and it has a mean time between failures of 299,000 hours.
- Contact information is provided for Hi-Network, which can provide global fast shipping for this and other networking equipment.
This document discusses optimizations for high performance and energy efficient implementations of the Smith-Waterman algorithm on FPGAs using OpenCL. It describes an architecture with a systolic array for parallel computation along anti-diagonals and compression techniques to address the memory-bound nature. Experimental results on two FPGA boards show up to 42.5 GCUPS performance with the best performance/power ratio compared to CPUs and other FPGA implementations.
QCT Ceph Solution - Design Consideration and Reference ArchitectureCeph Community
This document discusses QCT's Ceph storage solutions, including an overview of Ceph architecture, QCT hardware platforms, Red Hat Ceph software, workload considerations, benchmark testing results, and a collaboration between QCT, Red Hat, and Intel to provide optimized and validated Ceph solutions. Key reference architectures are presented targeting small, medium, and large storage capacities with options for throughput, capacity, or IOPS optimization.
QCT Ceph Solution - Design Consideration and Reference ArchitecturePatrick McGarry
This document discusses QCT's Ceph storage solutions, including an overview of Ceph architecture, QCT hardware platforms, Red Hat Ceph software, workload considerations, reference architectures, test results and a QCT/Red Hat whitepaper. It provides technical details on QCT's throughput-optimized and capacity-optimized solutions and shows how they address different storage needs through workload-driven design. Hands-on testing and a test drive lab are offered to explore Ceph features and configurations.
How Open Technology Helped DOE Labs Place Sixteen Supercomputers on the Top500Penguin Computing
Penguin Computing Senior Vice President for Federal Systems Sid Mair shares how open technology helped the Department of Energy Labs place sixteen supercomputers designed and built by Penguin Computing on the TOP500 List.
Pro Tips: Designing and Deploying End-to-End HPC and AI SolutionsPenguin Computing
High Performance Computing (HPC)*HPC on Demand*HPC Cloud*Storage*Networking*Artificial Intelligence (AI)*Supercomputing*Beowulf Clusters*Remote Desktop*Virtual Workstations*Scyld Cluster Mangement Software*Datacenters*IT Infrastrucutre*Professional Services*Managed Services*Open Compute Project (OCP)*Linux*Open Source -- Kevin Tubbs Ph.D., Sr. Director of Advanced Solutions Group for Penguin Computing, shared the best practices when designing and deploying end-to-end HPC and AI solutions.
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The document describes a Super Rotor Sifter from Pelleting Technology Nederland that uses a uniquely designed rotating and vibrating steel-wire sieve to efficiently sift materials. It generates a high-quality sifting result while taking up minimal space. The special sieve design combines eccentric and centrifugal movements for optimal sifting, and has 25% more throughput than perforated sheets while using less energy and requiring less maintenance. The sifter is available in single, double, or changeable deck configurations to meet different sifting needs.
The ultra-low-power IDT 9FGVxxxx (clock generators) and 9DBVxxxx (buffers) are the latest members of IDT's leading portfolio of PCI Express Gen1, Gen2 and Gen3 solutions, which also includes switches, bridges, signal repeaters, flash controllers and timing. The new PCIe timing devices consume less than 50 mW of power -- less than one-tenth the power required by previous solutions. The ultra-low power consumption reduces heat dissipation to ease cooling requirements in large-scale cloud computing applications. The new clock generators and buffers are available with a variety of termination options and features. Presented by Ron Wade, Technical Marketing Manager, Integrated Device Technology, Inc. For more information about IDT's PCI Express solutions, visit www.idt.com/go/PCIe.
PCTL Automation Ltd is an electrical engineering solutions provider that specializes in designing, manufacturing, and servicing electrical switchboards, automation systems, voltage regulators, and customized solutions for commercial and industrial environments. It has over 15 years of experience offering products and services across East Africa. The company aims to establish itself as a premier manufacturer and supplier of electrical distribution and control products by offering world-class electrical products at revolutionary prices.
Uses of Larsa 4 d and Lusas 4 D models for Implementation of Cable Stayed ...Rajesh Prasad
The paper deals with how an engineering challenge confronted in a busy yard due to presence of a distressed bridge(ROB) was replaced by a Cable Stayed Bridge by adopting safe practices with proper quality and within the time frame. The paper was presented today ie 18.08.17 in a lecture organised by IIBE at Institution of Engineers, Mumbai
The document discusses innovations on Masterpact circuit breakers from Schneider Electric. It summarizes that Masterpact breakers have a unique basic platform that can be used for all CEI, UL, and ANSI breakers. It also discusses over 60 patented solutions for the breakers. Specific innovations mentioned include reduced number of parts, universal connectors, segregated control unit functions, interfaces for control units, metallic filters, current sensors, combined auxiliary switches, reduced sizes for accessories and coils, and increased ratings and endurances.
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Turbo Power Systems (TPS) is a global company headquartered in the UK that designs and delivers power electronics systems for rail transportation. With over 30 years of experience in the rail industry, TPS provides auxiliary power supplies, battery chargers, and traction power converters. They have successfully delivered projects for light rail, metro, regional, intercity, and high-speed rail systems around the world. TPS prides itself on high reliability, efficiency, and engineering expertise to provide customized power solutions.
The Dyadic Systems Mechatronics Cylinder series is a versatile linear actuator system available from US$295. It integrates a motor, encoder, drive and program memory into a single package for high accuracy, long life and low cost. Models range from 10-50 kgf thrust and include standard and dust-proof options. This document provides an overview of the product specifications.
Mirko Damiani - An Embedded soft real time distributed system in Golinuxlab_conf
An embedded system usually involves low level languages like C and highly customized hardware. In this talk we will see a use case of a soft real time system which was developed taking a very different approach, written in Go. We will see what are the advantages of this choice, along with its limits.
K30 i K50 Touch to przyciski pojemnościowe wyposażone w duży, jasny i różnokolorowy wskaźnik LED. Wersja K50 posiada średnicę 5cm, a K30 – analogicznie 3cm.
This document describes the design and implementation of a two-stage complementary metal oxide semiconductor (CMOS) operational amplifier using 45nm technology. It aims to examine the operational amplifier's performance under various parameters. The design process involves calculating transistor width-to-length ratios (W/L) to achieve specifications such as a gain of 80dB, phase margin, and power dissipation of less than a certain amount. Simulations including DC analysis, AC analysis, transient analysis, temperature analysis, and power analysis are performed in Tanner Tool to validate that the operational amplifier meets requirements and is stable under variations. The results show that the designed two-stage CMOS operational amplifier achieves the targeted 80dB gain and phase margin at a unity
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Cisco Live! :: Cisco ASR 9000 Architecture :: BRKARC-2003 | Milan Jan/2014Bruno Teixeira
The document discusses the Cisco ASR 9000 architecture, which is designed for longevity and common hardware/software across products. It has a modular, distributed operating system called Cisco IOS XR. The ASR 9000 includes various chassis including the ASR 9001, ASR 9006, ASR 9010 and ASR 9922, which provide scalable switching capacity up to 96 terabits per second. It discusses the system components including line cards, switch fabrics, power supplies and control processors.
The document introduces several mechatronics cylinder models from Dyadic Systems for linear actuation. Key points:
- Models range from $295 to $695 and provide thrusts from 10-50kg with strokes from 50-300mm.
- Features include integrated motor, encoder and drive for precision; optimized screw and nut mechanism for accuracy and longevity.
- Models include basic, standard, dust-proof, and slider types for different environments and applications.
transparent led film display (Solufarm company profile mar 2017)주식회사솔루팜
- Solufarm develops transparent LED display technology using transparent film and electrodes, making displays much lighter than glass-based LED displays.
- The transparent LED films can be cut and bonded to various sized surfaces, including curved surfaces. They are offered in different resolutions and sizes from 300x300mm to 480x480mm.
- Solufarm provides digital signage systems including transparent LED displays, smart mirrors, and kiosks. They have applied their technology in places like agriculture markets, subway stations, airports, and casinos for advertising, scheduling, and wayfinding.
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- It is a 24-port PoE+ switch with a 715W power supply and 445W of available PoE power.
- Key features include stacking bandwidth of 480Gbps, 32,000 MAC addresses, and 8GB of DRAM.
- Dimensions are 1.73 x 17.5 x 17.5 inches and it has a mean time between failures of 299,000 hours.
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This document discusses QCT's Ceph storage solutions, including an overview of Ceph architecture, QCT hardware platforms, Red Hat Ceph software, workload considerations, reference architectures, test results and a QCT/Red Hat whitepaper. It provides technical details on QCT's throughput-optimized and capacity-optimized solutions and shows how they address different storage needs through workload-driven design. Hands-on testing and a test drive lab are offered to explore Ceph features and configurations.
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The document discusses designing for hyperscale computing. Hyperscale computing is defined as distributed infrastructure designed to handle increased demand for computing resources without additional physical space, cooling, or power. Key aspects of hyperscale include standardization, automation, redundancy, and high availability. When designing for hyperscale, the focus is on being cost-effective at large scale and allowing independent scaling of sections. The document recommends looking for partners with experience in open solutions, large AI systems management, and applying HPC discipline around areas like networking topology and latency, GPU acceleration, and infrastructure.
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Building a Raspberry Pi Robot with Dot NET 8, Blazor and SignalRPeter Gallagher
In this session delivered at NDC Oslo 2024, I talk about how you can control a 3D printed Robot Arm with a Raspberry Pi, .NET 8, Blazor and SignalR.
I also show how you can use a Unity app on an Meta Quest 3 to control the arm VR too.
You can find the GitHub repo and workshop instructions here;
https://bit.ly/dotnetrobotgithub
The Indian government has been working over the past few years to include elements of ITS in the transport sector. This standard ensures the optimal operation of the current transport infrastructure. It also increases the efficiency, safety, comfort, and quality of the system. That is why the government created the AIS-140 standard. Compliance with this standard means all vehicles used for public transit must have panic buttons and vehicle tracking modules installed. Nevertheless, in future in the standard protocol of AIS-140 you can expect fare collection and CCTV capabilities.
Get more information here: https://blog.watsoo.com/2023/12/27/all-about-prithvi-ais-140-gps-vehicle-tracker/
Google Calendar is a versatile tool that allows users to manage their schedules and events effectively. With Google Calendar, you can create and organize calendars, set reminders for important events, and share your calendars with others. It also provides features like creating events, inviting attendees, and accessing your calendar from mobile devices. Additionally, Google Calendar allows you to embed calendars in websites or platforms like SlideShare, making it easier for others to view and interact with your schedules.
3. A g e n d a
3
● About Penguin Computing (& why we care about OCP
standards)
● Open rack evolution
● Rack profile overview
● Notable rack profiles
● Optimization imperative
● Recommended Changes
● Conclusion
● Discussion
4. A b o u t P e n g u i n C o m p u t i n g
4
● Home to Scyld® Beowulf cluster software &
bare metal HPC on cloud Penguin Computing
On-Demand™
● Over 300 OCP racks delivered to date based on
Tundra™ Extreme Scale design
● Platinum OCP member, Penguin CTO Phil
Pokorny is HPC representative of the OCP
Incubation Committee
● U.S.-based 20 year old, global provider of HPC hardware,
software, and services
5. O p e n R a c k E v o l u t i o n
5
● Open Rack
○ Innovative standard since 2012
○ Enlarged rack unit and width
○ Cold aisle installation and service
● Key updates since latest version (v2.0)
o Two depths (800mm, 660mm)
o Two DC busbar voltages (12Vdc, 48Vdc)
● Multiple Options
○ (2) Depth x (2) Bus bar voltages x (2) Bus bar no. x
(2) Rack units x…..
Source: Open Rack Standard
6. R a c k P r o f i l e O v e r v i e w
6
Short (660mm) Deep (800mm) Short (660mm) Deep (800mm)
Short (660mm) Deep (800mm) Short (660mm) Deep (800mm)
Voltage
48V12V
II
DC Bus Bar
No.
3 1
I
IV III
Others
7. N o t a b l e R a c k P r o f i l e s
7
● 12Vdc + 1 DC Bus Bar
○ Open Rack v2
○ Deep depth (800mm)
● 12Vdc + 3 DC Bus Bar
o Open Rack v1
o High density, High power capacity, and
Robustness
o Deep depth (800mm)
● 48Vdc + 1 DC Bus Bar
○ Higher voltage for better power usage
effectiveness (PUE)
○ Both short (660mm) and deep (800mm) depths
8. O p t i m i z a t i o n I m p e r a t i v e
8
● The deduction of build cost is limited by
too many options, so is the acceptance of
OCP design
Infrastructure design optimization is
imperative to support increased demands
of efficiency, flexibility, and scalability
○ Determine the parameters that lead to
the best ‘performance’
○ Reduce waste
9. R e c o m m e n d e d C h a n g e s t o 4 8 V d c R a c k
9
● Maximize the density:
o Use specification executed in Tundra 1U server
with 3 busbars to support 100+ nodes per rack.
● Cost Effective
○ Easier (and cheaper) to deliver more than 33kw
with three bus bars instead of one.
○ Easier to distribute powers to the whole rack by
placing the power shelf in the middle.
● Flexibility
○ 3 busbar location is more flexible to adopting
existing IT devices.
10. C o n c l u s i o n
1
0
● Recommend to embrace three
bus bars design when moving to
48Vdc.
● 800mm depth to contain existing
IT gear and power shelves.
● Cheaper, more flexible way to
deliver >33kW