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ipad 3 full Schematic Diagram

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PROPRIETARY PROPERTY OF APPLE INC. 2 1 1245678 B D 6 5 4 3 C A NOTICE OF PROPRIETARY PROPERTY: PAGE THE INFORMATION CONTAINED HEREIN IS THE C A D R SHEET Apple Inc. THE POSESSOR AGREES TO THE FOLLOWING: DRAWING TITLE D SIZE REVISION DRAWING NUMBER BRANCH 7 B 3 II NOT TO REPRODUCE OR COPY IT I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE IV ALL RIGHTS RESERVED III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 8 10.0.0 051-8773 R5750 R35 R34 R33 R32 R0714 R0715 R0885 R0713 R0720 R3160 R12 R3107 R5502 R5501 R31 R5753 R1209 R1207 R1202 R1201 R1200 R5751 R11 R4 R3031 R3030 R3033 R3025 FL5750 FL9 FL0910 L4303 FL7500 L5610 R8216 R8222 R8282 R8218 R10234 R1720 R1020 R1621 R1620 C1129 C1131 C1137 C1136 C1195 C1181 C1197 C1196 C1108 C1110 C1138 C1111 C1135 C1198 C1130 C1166 C1134 C1161 C1160 C1132 C1194 C1020 C1021 C1710 C1109 C1133 C1174 C1165 C1173 C1164 C1163 C1159 C1162 C1023 C1182 C1183 C1177 C8210 C8169 C1199 C1176 C1190 C1184C1022 C1406 C1414 C1425 C1405 C1413 C1433 C1426 C1434 C7 C5782 C89 C3703 C3713 C0907 C3006 C39 C5804 C5805 C41 C5802 C5803 C5810 C5811 C5806 C5807 C82 C5808 C5809 C80 C81 C8212 C8204 C0903 C0908 C0956 C0910 C0909 C3050 C1404 C1430 C3110 C3108 C3106 C3109 C3031 C3030 C3041 C1410 C1424 C4213 C4211 C3105 C3604 C2251 C2250C2203 C4200 C5616 C2249 C2247 C2248 C2245 C2246 C2243 C2244 C2242 C86 C42 C47 C46 C7523 C7522 C69 C5 C75 C76 C4 C8 C74 C1251 C1250 C5500 C5501 C6 C43 C34 C85 C5766 C5765 C5712 C5711 C5710 C5708 C5707 C5706 C5705 C5703 C5702 C5701C5700 C5753 C36 C5752C5754C5755 C5751 C8164 C32 C38 D5703 D5700 D5701 L5700 L5701 L5501 L5600L5620 L5702 R0801 R1475 R0803 R0812 R0800 R0802 R0811 R0813 R0810 R1455 R0609 R0622 R0608 R0620 R1260 R0621 R0836 R0712 R0834 R0831 R0832 R3700 R3180 R3604 R3605 R2280 R2282 R2281 R2284 R2283 R2286 R2285 R2287 R0652 R0730 R0731 R0940 R1180 R0900 R0602 R0605 R0601 R0603 R0604 R0606 R0607 R3712R3702 R3713 R3703 R3603 R3621 R3601 R3602 R3608 C6100 C1661 C0957 C1652 C0950 C0621 C0632 C0952 C0631 C8137 C8207 C8206 C1188 C1760 C1750 C1105 C1125 C1104 C0634 C0609 C0601 C0602 C0603 C0600 C0635 C0953 C1752C1761 C1107 C1150 C0607 C1126 C1106C0612 C0604 C0615 C0633 C0608 C0630 C1650 C1660 C0930 C0931 C0924 C0923 C1193 C0620 C1145 C1146 C1142 C1144 C1151 C1141 C1143 C1152 C1140 C1102 C1715 C1154C1153C1155C1158 C1191 C1124 C1122 C1156 C1100 C1103C1117C1121 C3112 C2202 C0951 C0935 C0622 C8136 C8209 C8135 C8141 C8140 C8139 C8151 C8238 C50 C1170 C1172 C1171 C0614 C3618 C3617 J6000 U3 Y1 U9 U3700U3710 DZ5752 R4211 R4210 R1101R1100 R5909 R5908 R5900 R5905 R5906 R5907 R5904 R5720 R5721 R76 R28 R26 R5912 R5910 R5913 R5731 R5911 R5730 R5902 R5903 R5901 R8172 R0910 R0911 R1400 R1401 R3070 R3071 R3171 R3120 R3173 R4204 R7541 R5620 R5621 R5611 R2250 R4205 R5610 R3 R5700 R9000 R9001 R29 R27 R5710 R2290 R1252 R1253 R1250 R1251 R5740 R1452 R1453 R1472 R1473 R3101 R3032 FL5708 FL5711 FL5707 FL0600 R14 R13 R4203 R4202 R0612 R0613 R0722 R5752 R2205 R2 R7R15 R2211 R2210 R5915 R5914 R5916 R5917 R10 R9 R8265 R8227 R8232 R8261 R8257 R8239 R3190 R8130 R8173 R8116 R8203 R0956 R0955 R0957 R1454 R1474 R3066 R4213 R4212 R2203 R2204 R4201 L24 L15 L16 L23 L2 L5 L43 L12 L21 L22 L46 L10 L11 L20 L14 L5762 L17 L9 L6 L7 C87 C21 C11 C5760 C3701 C3702 C3712 C3711 C2204 C0640 C3 C4217 C7524 C5621 C5620 C2206 C563 C5623 C73 C71 C35C83 C84 C61 C77C33 C72 C44 C45 C63 C64C67 C68 C20C18 C37 C65 C66 C62 C60 C10 C8163 C2241 C2230 C2240 C7525 C5617 C5612 C2232 C5601 C5614 C0961 C0960 C4310 C3851 C3850 C8131 C8138 C1450 C1451 C1470 C1471 U4200 L2212L2222L2232L2202 FL1 U3600 J1 R5603 R5602 R5600 R5601 L5611 L5612 L5613 U3100 U8 U4 U1 FL7 U10 FL8 U6 FL10 U3003 U3101 U3009U3010 U3007 DZ5751 U1600 U1700 R2242 R2240 R2241 R5820 R5823 R0641 R1030 R6101 R6100 R3850 R3851 R1211 R1210 R3711R3701 R3801 R3800 R4312 R0702 R0705R0933 R0932 R0704 R0703 R0706 R0931 R0701 R0930 R1652 R1651 R1705 R1706 R1751 R1752 R1605 R1606 R0921 R0920 R8260 R0700 R0643 R0642 R0640 R1203 R1204 R1205 R1261 R1206 C3107 C3615 C3609 C3611 C3616 C8148 C8152 C8157 C8159 C8160 C8161 C8144 C8158 C8162 C8130 C8156 C3608 D5702 Q2200 DZ5710 DZ5711 C4216 C4212 C3803 C3801 C3802 C3607 C3601 C3602 C3852 C3605 C3854C3853 C3600 C8214 C8281 C8223 C8215 C8221 C8282 C8220 C8217 C3751 C3750 C3753 C3752 DZ8120 C0934 C0932 C0927 C0933 C0926 C0925 C8172 Q8104 R8100 R8219 D8230 DZ5720 DZ0600 L2242 L5601L5500 L5716 C2220 C2270 C2253 C2233 L2201 L2210 L2200 L5714 L5760 L5761 DZ5750 DZ5753 DZ5712 DZ5790 U5700 U5500 U5502 U5601 U5501 U5503 U5600 L4308 L4306 L4302 L4304 L4307 L4301 L5763 C3192 C1175 C1400 C1420 C3111 C3191 C4202 C4201 C3603 C3613 C3614 C1421 C1402 C1412 C1422 C1432 C1401 C8170 C8101 C8171 C8100 C3606 C5602 C5613 C5615 C5618 C3070 C3053 C3005 C3007 C1431 C1411 C8153 C8147 C8149 C8146C8167 C8150 C8168 C8240 C8145 C8266 C5780 C8201 C8251C8267 R8270 R8262 R8269 R8240 R8231 R8235 R5512 R5513 R5510 R5511 R5613 R5612 820-2996-11-BOT MLB
PROPRIETARY PROPERTY OF APPLE INC. 2 1 1245678 B D 6 5 4 3 C A NOTICE OF PROPRIETARY PROPERTY: PAGE THE INFORMATION CONTAINED HEREIN IS THE C A D R SHEET Apple Inc. THE POSESSOR AGREES TO THE FOLLOWING: DRAWING TITLE D SIZE REVISION DRAWING NUMBER BRANCH 7 B 3 II NOT TO REPRODUCE OR COPY IT I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE IV ALL RIGHTS RESERVED III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 8 10.0.0 051-8773 C8236 C5783 C1628C1629C1717 C1716C1702 C1729C1728 C1703 C17 C1616C1617 C1602 C1603 C3101 C3104 LED9000 C1720 C1701 C1714 C1727 C8155 C1620 C1601 C1627 C8154 C1614 C1192 C1157 C1123 C1101 C3009 J5900 U5730 Q2201 DZ5760 L8229 C8125 D8100 R3009 Q8123 L5757 D8228 D8258 Y8138 C1721 C1621 C1615 Y0602 C8165 C8166 C0650 C0651 C1709 C1719 C1735 C1723 C1609 C1301 C1635 C1619 C1623 C1630 C1058 C1056 C1084 C1085 C1722 C1704 C1762 C1754 C1095 C1096 C1730 C1756 C1763 C1731 C1705 C1654 C1604 C1622 C1662 C1057 C1605 C1656 C1663 C1631 C1054 J5400 J5401 J3011J3010 R0651 R5795 R0650 R5796 R1212 R1213 R1214 R1315 R1055 R1056 R1083R1084 R1754 R1753 R1095 R1096 R1755 R1756 R1654 R1653 R1053 R1655 R1656 R1054 R3181 R1320 R1372 R0804 L3000 D3000 C3000 C3001 U3000 C8124 U1410 U1400 U8100J2200 C49 C48 C70C58 C2 C1 L1 J2J3700 J7500 C8256 C8226 C8237 C3714C3704 C8265 C8264 C8263 C8262 C8235 C8234 C8233 C8232 C8122 C8121 C8120 C8119 C8118 C8117 C8108 C8107 C8103 C8102 U0600 U1300 C8143 C8142 C5722 C3700 C5750 C5721 C54 C78C53 C79 C3002 C3008 C3102 C3103 C0955 C1370 C1300 C59 C52 C56 C57 C55 C5730 C1718 C1618 C1611 C1633 C1607 C1626 C1606 C1610 C1632 C1625 C1612 C1613 C29 C1707 C1733 C1708 C1724 C1734 C1706 C1726 C1711 C1713 C1712 C1725 C1732 C1634 C1608 C1624 R0950 R1362 R1360 R1361 R1 R9002 R1021 R1022 R1721 R3012 R8280 R8281 L3700 FL6 FL4 FL2 R16 R5 R1208 R5790 R3155 R0711 R0708 R0710 R0709 L8112 L8100 L8101 L8105 L8107 L8110 L8115 L8116 L8119 L8121 L8128 L8255 L8225 820-2996-11-TOP MLB
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. PROPRIETARY PROPERTY OF APPLE INC. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. DESCRIPTION OF REVISION CK APPD 2 1 1245678 B D 6 5 4 3 C A NOTICE OF PROPRIETARY PROPERTY: PAGE THE INFORMATION CONTAINED HEREIN IS THE C A D DATE R SHEET Apple Inc. THE POSESSOR AGREES TO THE FOLLOWING: DRAWING TITLE D SIZE REVISION DRAWING NUMBER BRANCH REV ECN 7 B 3 II NOT TO REPRODUCE OR COPY IT I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE IV ALL RIGHTS RESERVED III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 8 TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM DRAWING TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM J2 MLB - DVT OK2FAB Schematic / PCB #’s 1 OF 48 2011-09-06ENGINEERING RELEASED 1 OF 157 10.0.0 051-8773 10 0001231154 LAST_MODIFIED=Tue Sep 6 17:35:11 2011 X26_WIFI_MIKE_BT 09/01/20116131 WLAN BB & POWER JOE 01/19/20116030 CONNECTOR: X26 JOE 01/19/20115929 IO FLEX: B2B CONNECTOR JOE 01/19/20115828 DISPLAY PORT MISC JOE 01/19/20115727 IO FLEX: DOCK COMPONENTS MARK 01/11/20115626 SENSOR PANEL FILTERS 2 MARK 01/11/20115525 SENSOR PANEL FILTERS 1 MARK 01/11/20115424 CONNECTOR: SENSOR KAVITHA 02/03/20114323 AUDIO: HP/MIC FILTERS KAVITHA 02/03/20114222 AUDIO: DETECT/MIC BIAS KAVITHA 02/03/20113821 AUDIO: HEADPHONE OUT KAVITHA 02/03/20113720 AUDIO: SPEAKER AMP KAVITHA 02/03/20113619 AUDIO: L63B CODEC RAMSIN 12/17/20103118 GRAPE: Z1, Z2 RAMSIN 12/17/20103017 GRAPE: GROUNDHOG,CONN,BOOST JOE 01/19/20112216 VIDEO: EDP CONNECTOR ALEX 09/30/20102115 MLB ALIASES/CONNECTIONS MIKE 06/21/20101714 DDR 2 AND 3 MIKE 06/21/20101613 DDR 0 AND 1 MIKE N/A1412 NAND CHOPIN 12/10/20101311 AP: VIDEO BUFFER,BB USB MUXES ALEX N/A1210 AP: MISC & ALIASES MIKE N/A119 AP: POWER MIKE N/A108 AP: DDR JOE 01/13/201197 AP: TV,DP,MIPI MIKE N/A86 AP: NAND JOE N/A75 AP: I/Os MIKE N/A64 AP: MAIN MIKE N/A43 BOM TABLES J2DEV N/A22 BLOCK DIAGRAM: SYSTEM 15748 01/21/2011FUNC TEST POINTS MIKE 15647 01/21/2011FUNC TEST POINTS MIKE 15546 01/21/2011CONSTRAINTS: DEBUG MIKE 15445 01/21/2011CONSTRAINTS: POWER / GND MIKE 15344 01/21/2011CONSTRAINTS: DDR/FMI MIKE 15243 01/21/2011CONSTRAINTS: DISPLAY/AUDIO MIKE 15142 01/21/2011CONSTRAINTS: LOW SPEED BUS MIKE 15041 01/21/2011CONSTRAINTS: MLB RULES MIKE 9340 10/04/2010FCT/ICT TEST/BRACKETS ALEX 9039 10/04/2010DEBUG AND MISC ALEX 8338 01/13/2011POWER: AMELIA VSS MADHAVI 8237 01/14/2011POWER: AMELIA PMU MLB 8136 01/13/2011POWER: AMELIA PMU MADHAVI 8035 01/13/2011POWER ALIASES MADHAVI 7534 01/13/2011POWER: BATTERY CONNECTOR MADHAVI 6333 09/01/2011WLAN 5GHZ AND TEST POINTS X26_WIFI_MIKE_BT SYNC MASTER DATECONTENTSCSAPDF DRAWING MLB MIKE NA11 Table of Contents 6232 09/01/2011WLAN 2.4GHZ AND ANT X26_WIFI_MIKE_BT PDF CONTENTSCSA DATESYNC MASTER SYNC_MASTER=MIKE SCH,J2,MLB SYNC_DATE=NA
Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT FF CAMERA VGA FLEX REAR CAMERA AUDIO UART3 UART6 MIPI1C DUAL-CORE ARM CORTEX-A9 W/ SMP HSIC1_1 ISP_I2C1 LPDDR2 HSIC0_1 AMP AMP BT_I2S CSA 61-64 CSA 60 VA5/8 FLEX VGA FLEX BUTTON FLEX HALL EFF PROX SENSOR AE2 GPU ARM A5 CPU QUAD-CORE IMG SGX543-MP2400MHZ/800MB/S 4X32-BIT 1 GBYTE EDP MIMO WIFI/BT ANT 2 WIFI ANT 1 FMI2FMI1 HSIC1 CELLULAR/GPS X26 950 MHZ H4G DWI UART5 DISPLAYPORT CSA 31 CSA 31CSA 30 CSA 75 CSA 14CSA 14 I2S2 VIDEO DAC FMI0 USB2.0 I2C0 I2C2 DOCK 30-PIN GYRO ACCELEROMETER ALS ISP_I2C0 SPI1 WIFI/BT MIPI0C USART IPCSPI2 I2C1 UART1 AMP ASP LINEOUT I2S0 Z2 AUDIO CODEC L63B TOUCH PANEL RESOLUTION: 2048X1536 GROUNDHOG Z1 VSP FMI3 XSP CSA 36 I2S3 I2C 8’H94 I2C 8’H76 PPN1.0 PPN1.0 NAND FLASHNAND FLASH CSA 57 UART0 SPEAKER PRIMARY CELLULAR ANT DIVERSITY CELLULAR ANT GPS ANT PMU AMELIA BATTERY DISPLAY/ BACKLIGHT SENSOR PANELSENSOR PANEL SENSOR PANEL SENSOR PANEL COMPASS CSA 81,82 I2C 8’H1C I2C 8’H78 I2C 8’H58 I2C 8’H72I2C 8’H32I2C 8’HD0 MIC EXT MIC MUX US/CHINA SYNC_DATE=N/ASYNC_MASTER=J2DEV BLOCK DIAGRAM: SYSTEM 051-8773 10.0.0 2 OF 157 2 OF 48
CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_5_ITEM TABLE_5_ITEM CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) TABLE_BOMGROUP_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD BOM OPTIONSBOM GROUP TABLE_BOMGROUP_HEAD TABLE_5_ITEM CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) TABLE_5_ITEM TABLE_5_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) TABLE_ALT_ITEM CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_ALT_ITEM CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_5_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_ALT_ITEM TABLE_5_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) TABLE_5_ITEM CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM NAND SDRAM SCH AND BOARD P/N DEVELOPMENT_JTAG_TAP Power aliases required by this page: INTERNAL_MIC DEVELOPMENT_JTAG 16GB_PROD (NONE) 32GB_PROD JTAG_DAP SPEAKER (NONE) ALTERNATE COMMON 64GB_PROD 128GB_PROD J2 MLB DEV NAND_IO_1V8 NAND_IO-3V3 SNOTE MECHANICAL PARTS BOM options provided by this page: BARCODE LABEL/EEEE CODES PMU 32GB FLASH CONFIGURATIONS 16GB FLASH CONFIGURATIONS 64GB FLASH CONFIGURATIONS 128GB FLASH CONFIGURATIONS Page Notes Signal aliases required by this page: ALL AVAIL BOM OPTIONS SOC DEV1DEV BOM,MLB,J2085-3058 ?1 PCB1PCBF,MLB,J2820-2996 ?1 CRITICAL SCH1SCH,MLB,J2051-8773 ?1 CRITICAL U0600IC,SOC,H4G,FCBGA1225343S0533 CRITICAL1 ? SYNC_MASTER=MIKE SYNC_DATE=N/A BOM TABLES 825-7691 CRITICAL1 EEEE_J2A_64GEEEE FOR 639-2827 (J2A 64G) EEEE_DRF5 1 CRITICALEEEE FOR 639-2826 (J2A 32G) EEEE_J2A_32G825-7691 EEEE_DRF6 EEEE FOR 639-2844 (J2A 16G) EEEE_DRJQ EEEE_J2A_16G825-7691 CRITICAL1 FENCE,LARGE,TOP,MLB,J2 PD_FENCE_LARGE806-1857 CRITICAL1 806-1860 PD_FENCE_BTM1FENCE,1,BTM,MLB,J21 CRITICAL 806-1865 FENCE,2,BTM,MLB,J2 CRITICALPD_FENCE_BTM21 FENCE,SMALLER,BTM,MLB,J2 CRITICALPD_FENCE_BTM31806-2352 AUDIO SPEAKER,INTERNAL_MIC U1400,U1410128GB_PROD335S0806 335S0814 TOSHIBA 24NM PPN1.0 128GB_PRODU1400,U14102 CRITICAL335S0814 HYNIX 26NM PPN1.0 64GB 64GB_PROD U1400,U1410335S0805 335S0782 TOSHIBA 24NM PPN1.0 CRITICAL 64GB_PROD2 U1400,U1410335S0782 HYNIX 26NM PPN1.0 32GB U1400,U141032GB_PROD335S0781335S0804 TOSHIBA 24NM PPN1.0 335S0804 335S0781 16GB_PROD U1400 TOSHIBA 24NM PPN1.0 16GB_PRODU1400HYNIX 26NM PPN1.0 16GB1335S0781 CRITICAL HYNIX 26NM PPN1.0 16GB335S0781 CRITICAL2 U1400,U1410 32GB_PROD U1600,U1700SDRAM,LPDDR2,512MB,SAMSUNG 46NM2333S0579 ?CRITICAL CRITICALU8100IC,PMU,AMELIA,D1974AB1343S0561 ? EEEE_J2_128GEEEE_DKQK1 CRITICALEEEE FOR 639-1870 (J2 128G)825-7691 825-7691 EEEE FOR 639-2352 (J1 16G)1 CRITICALEEEE_DNKT EEEE_J1_16G 825-7691 CRITICALEEEE_DM2N EEEE_J1_32G1 EEEE FOR 639-2058 (J1 32G) 825-7691 EEEE FOR 639-2059 (J1 64G)1 CRITICALEEEE_DM2P EEEE_J1_64G 825-7691 EEEE FOR 639-2353 (J2 16G)1 CRITICAL EEEE_J2_16GEEEE_DNKV 825-7691 EEEE FOR 639-1572 (J2 32G)1 CRITICAL EEEE_J2_32GEEEE_DHWV 825-7691 EEEE FOR 639-1871 (J2 64G)1 CRITICALEEEE_DKQL EEEE_J2_64G COMMON,ALTERNATEBASIC CRITICALFENCE,NAND,TOP,MLB,J2806-2105 1 PD_FENCE_NAND 806-2349 1 PD_FENCE_SMALL CRITICALFENCE,SMALLER,TOP,MLB,J2 LPDDR2,HYNIX 44NM333S0579 U1600,U1700333S0580 LPDDR2,ELPIDA 45NMU1600,U1700333S0579333S0581 051-8773 10.0.0 4 OF 157 3 OF 48
BI BI BI BI (1 OF 12) JTAG_TRST* XO0 XI0 WDOG USB11_DP1 USB11_DP0 USB11_DM1 USB11_DM0 USB_VDD330 USB_VBUS1 USB_VBUS0 USB_ID1 USB_ID0 USB_DVDD USB_DP0 USB_DM0 USB_BRICKID1 USB_BRICKID0 USB_ANALOGTEST1 USB_ANALOGTEST0 TST_STPCLK TST_CLKOUT TESTMODE RESET* PLL5_AVDD11 PLL4_AVDD11 PLL3_AVDD11 PLL2_AVSS11 PLL2_AVDD11 PLL1_AVSS11 PLL1_AVDD11 PLL0_AVSS11 PLL0_AVDD11 PLL_USB_AVSS11 PLL_USB_AVDD11 MIPI1D_VDD11_PLL JTAG_TRTCK JTAG_TMS JTAG_TDO JTAG_TDI JTAG_TCK JTAG_SEL HSIC1_VSS122 HSIC1_VSS121 HSIC1_VDD122 HSIC1_VDD121 HSIC1_STB2 HSIC1_STB1 HSIC1_DVSS HSIC1_DVDD HSIC1_DATA2 HSIC1_DATA1 HSIC0_VSS122 HSIC0_VSS121 HSIC0_VDD122 HSIC0_VDD121 HSIC0_STB2 HSIC0_STB1 HSIC0_DVSS HSIC0_DVDD HSIC0_DATA2 HOLD_RESET FUSE1_FSRC FAST_SCAN_CLK DDR3_CKEIN DDR2_CKEIN DDR1_CKEIN DDR0_CKEIN CFSB1 HSIC0_DATA1 USB_DM1 USB_DP1 USB_DVSS USB_VSSA0 USB_VSSAC PLL5_AVSS11 MIPI_VSS USB_REXT1 USB_REXT0 PLL4_AVSS11 PLL3_AVSS11 CFSB0 MIPI0D_VDD11_PLL (11 OF 12) VSS VSS IN IN IN OUT OUT IN OUT IN OUT OUT Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT 1 - DAISY CHAIN (FOR USE WITH 5-WIRE JTAG) 34MA 7MA 10MA 7MA 14MA 2.5MA EACH 2.5MA JTAGSEL 3.16V 1.75V 1.16V 28MA 34MA BB WLAN PER RADAR #6755237 0 - PARALLEL 01005 X5R 6.3V 0.01UF 10% 01005 0.01UF 10% X5R 6.3V 10% 01005 X5R 0.01UF 6.3V 0.01UF 01005 6.3V 10% X5R 3042 3042 1540 42 154042 5% 100K 1/32W 01005 5% 01005 100K 1/32W 01005 5% 100K 1/32W 01005 100K 1/32W MF 1% 1% 10K MF 01005 1/32W 1000PF 201 16V X7R 10% 01005 MF 1/32W 0.00 0% MLB 01005 0.01UF 10% X5R 6.3V H4G FCBGA OMIT H4G FCBGA OMIT 10 10 10 10 1042 104245 10 1% 44.2 201 MF 1/20W 201 MF 1/20W 1% 44.2 01005 0% 0.00 MF 1/32W 0% 0.00 MF 01005 1/32W 0.00 1/32W MF 0% 01005 0.00 0% 1/32W MF 01005 0.00 0% 1/32W 01005 MF 0% MF 01005 1/32W 0.00 1/32W 0% 01005 MF 0.00 0201 80-OHM-0.2A-0.4-OHM GDZ-0201 GDZT2R5.1B 100K 5% 1/32W MF 01005 DEVELOPMENT_JTAG_TAP 100K 5% 1/32W MF 01005 CRITICAL SM-2 24.000MHZ-16PF-60PPM 01005 1/32W 5% 22 MF 01005 22PF CERM 16V 5% 01005 5% 22PF CERM 16V 1.00M 010051/32W 1% MF 42.2K 1% MF 1/32W 01005 01005 1/32W MF 1% 82.5K 27303745 37 37 45 6.3V X5R 10% 01005 0.01UF 6.3V CERM 402 1UF 10% 6.3V X5R 10% 0.01UF 01005 0.01UF 6.3V X5R 10% 01005 01005 0.01UF 10% X5R 6.3V 6.3V 402 CERM 10% 1UF56PF NP0-C0G 01005 6.3V 5% 6.3V X5R 10% 0.01UF 01005 6.3V X5R 01005 10% 0.01UF 6.3V X5R 10% 0.01UF 01005 0.01UF 10% 6.3V X5R 01005 0.01UF 6.3V X5R 01005 10% 10% X5R 6.3V 0.01UF 01005 0.01UF 6.3V X5R 01005 10% 01005 0.01UF 6.3V X5R 10% SYNC_MASTER=MIKE AP: MAIN SYNC_DATE=N/A PP1V1_PL4_F VOLTAGE=1.1V MIN_LINE_WIDTH=0.2MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM MIN_NECK_WIDTH=0.1MM =PP1V1_PLL_H4 NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM PP1V1_MIPID_PLL_F VOLTAGE=1.1V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM MAX_NECK_LENGTH=3MM NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.2MM VOLTAGE=1.1V MIN_NECK_WIDTH=0.1MM PP1V1_PL1_F MIN_LINE_WIDTH=0.2MM VOLTAGE=1.1V MIN_NECK_WIDTH=0.1MM PP1V1_PL2_F NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM MIN_NECK_WIDTH=0.1MM PP1V1_PL3_F VOLTAGE=1.1V MIN_LINE_WIDTH=0.2MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM PP1V1_PL5_F MIN_LINE_WIDTH=0.2MM VOLTAGE=1.1V NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM MIN_NECK_WIDTH=0.1MM MAX_NECK_LENGTH=3MM NET_SPACING_TYPE=PWR PP1V1_PLL_USB_F VOLTAGE=1.1V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM RST_PMU_IN =PP1V8_H4 24M_O PPVBUS_USB =PP3V3_USB_H4 =PP1V1_PLL_H4 =PP1V1_USB_H4 =PP1V1_MIPI_PLL_H4 =PP1V8_H4 USB_REXT0 USB_REXT1 NC_USB_D1_P NC_USB_D1_N HSIC0_BB_DATA1 AP_DDR1_CKEIN_1V2 NC_HSIC0_DATA2 HSIC0_BB_STB1 NC_HSIC0_STB2 HSIC1_WLAN_DATA1 NC_HSIC1_DATA2 HSIC1_WLAN_STB1 NC_HSIC1_STB2 JTAG_AP_SEL JTAG_AP_TCK JTAG_AP_TDI JTAG_AP_TMS NC_JTAG_AP_TRTCK NC_USB_ANALOGTEST0 NC_USB_ANALOGTEST1 USB_BRICKID NC_USB_BRICKID1 USB_DK_D0_N USB_DK_D0_P NC_USB_ID0 NC_USB_ID1 USB_AP_VBUS0 USB11_MUX_D0_N NC_USB11_D1_N AP_WDOG XTAL_24M_I XTAL_24M_O =PP1V2_HSIC_H4 MIN_LINE_WIDTH=0.2MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.1MM PP1V1_PL0_F VOLTAGE=1.1V MAX_NECK_LENGTH=3MM =PP1V1_HSIC_H4 =PP1V1_USB_H4 =PP3V3_USB_H4 USB_AP_VBUS1 JTAG_AP_TDO JTAG_AP_TRST_L TP_AP_TST_CLKOUT AP_TST_STPCLK RST_AP_L AP_FAST_SCAN_CLK AP_HOLD_RESET AP_TESTMODE RST_AP_1V8_L USB11_MUX_D0_P NC_USB11_D1_P C06151 2 R06121 2 R06131 2 R0604 1 2 R0603 1 2 R0602 1 2 R0601 1 2 R0605 1 2 R0606 1 2 R0607 1 2 FL0600 1 2 DZ06001 2 R06091 2 R0608 1 2 Y0602 2 4 1 3 R0651 1 2 C06511 2 C06501 2 R0650 12 R06421 2 R06431 2 C06121 2 C06141 2 C06081 2 C06091 2 C06211 2 C06221 2 C06201 2 C06041 2 C06031 2 C06001 2 C06011 2 C06021 2 C06071 2 C06301 2 C06311 2 C06351 2 C06341 2 C06331 2 C06321 2 R0621 1 2 R0622 1 2 R0620 1 2 R06411 2 R06401 2 C06401 2 R0652 1 2 U0600 W6 AR32 L6 F9 AK10 AF6 AR33 M31 AN28 K35 K33 N31 N30 L35 L33 P29 P31 P28 P30 H35 H33 H32 H31 J35 J33 K30 J30 K29 J29 AK29 AN29 AN30 AP30 AJ27 AR27 AM27 F27 F30 H24 H25 H26 H27 H28 H29 V33 V32 U33 U32 T33 T32 R33 R32 P33 P32 N33 N32 M33 M32 AR30 AH27 AR29 AR28 R34 P35 T34 N35 R30 J28 T28 K31 T35 M34 U35 N34 U29 L30 U28 L31 T31 K32 R31 K28 T30 J32 R28 M28 T29 L28 R29 L29 AP29 W35 Y35 U0600 A1 A2 AA8 AN10 AN13 AN16 AP1 AP2 AP6 AP9 AP12 AP15 AP18 AA10 AP22 AP25 AP28 AP31 AP34 AP35 AR1 AR2 AR5 AR8 AA12 AR11 AR14 AR17 AR19 AR34 AR35 B1 B2 B4 B9 AA14 B12 B15 B34 B35 C7 C10 C13 C16 C30 C31 AA16 C32 C33 D3 D5 D8 D11 D14 D17 D30 D33 AA18 E1 E10 E21 E22 E24 E25 E26 E27 E28 E29 AA20 E30 E33 F2 F5 F16 F17 F21 F22 F24 F33 AA22 G3 G17 G18 G19 G20 G21 AA24 AA26 A5 AA35 AB1 AB4 AB8 AB9 AB11 AB13 AB15 AB17 AB19 A8 AB21 AB23 AB25 AB27 AC3 AC8 AC10 AC18 AC20 AC22 A11 AC24 AC28 AC32 AC34 AD2 AD8 AD9 AD11 AD19 AD21 A14 AD23 AD25 AD27 AD29 AE1 AE8 AE9 AE10 AE18 AE20 A17 AE22 AE24 AE26 AF3 AF8 AF9 AF27 AF30 AF32 AF34 A34 AG2 AG8 AG9 AH1 AH8 AH9 AH10 AH11 AH12 AH17 A35 AH22 AH25 AH26 AJ5 AJ13 AJ20 AJ29 AJ32 AJ34 AK2 AA2 AL1 AM3 AM8 AM19 AM22 AM25 AM28 AM32 AM34 AN7 051-8773 10.0.0 6 OF 157 4 OF 48 45435 4545 45 45 45 45 471035 42 36 45 435 4 35 4 35 35 471035 42 46 42 46 4246 4246 4246 42 46 10 2742 1042 2742 46 46 46 46 27 42 27 42 46 46 11 42 42 46 42 42 35 45 35 4 35 4 35 45 11 42 42 46
IN OUT IN OUT OUT OUT OUT IN OUT OUT OUT OUT IN OUT OUT OUT OUT IN IN IN IN BI OUT BI OUT BI OUT IN OUT OUT OUT IN OUT OUT IN IN IN IN OUT IN OUT IN IN IN IN OUT OUT OUT OUT (2 OF 12) UART5_RTXD UART3_TXD UART3_RXD UART3_RTSN UART3_CTSN UART6_TXD UART6_RXD UART6_RTSN UART6_CTSN UART4_TXD UART4_RXD UART4_RTSN UART4_CTSN UART2_TXD UART2_RXD UART2_RTSN UART2_CTSN GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32 GPIO31 GPIO30 GPIO3 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO2 GPIO19 GPIO18 GPIO17 GPIO16 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO1 GPIO0 GPIO_3V1 GPIO_3V0 UART1_TXD UART1_RXD UART1_RTSN UART0_TXD UART0_RXD TMR32_PWM2 TMR32_PWM1 TMR32_PWM0 EHCI_PORT_PWR2 GPIO9 GPIO10 UART1_CTSN EHCI_PORT_PWR1 EHCI_PORT_PWR0 SPI0_SSIN SPI0_SCLK SPI0_MOSI SPI0_MISO SWI_DATA SPI3_SSIN SPI3_SCLK SPI3_MOSI SPI3_MISO SPI2_SCLK SPI2_MOSI SPI1_SSIN SPI1_SCLK SPI1_MOSI SPI1_MISO SPDIF SDIO0_DATA3 SDIO0_DATA2 SDIO0_DATA1 SDIO0_DATA0 SDIO0_CMD SDIO0_CLK I2S3_MCK I2S3_LRCK I2S3_DOUT I2S3_DIN I2S3_BCLK I2S2_MCK I2S2_BCLK I2S1_MCK I2S1_LRCK I2S1_DIN I2S1_BCLK I2S0_MCK I2S0_DOUT I2S0_BCLK I2C2_SDA I2C2_SCL I2C1_SDA I2C1_SCL I2C0_SDA I2C0_SCL DWI_DO DWI_DI DWI_CLK I2S2_DOUT I2S2_DIN I2S2_LRCK I2S1_DOUT I2S0_LRCK I2S0_DIN VSSA18_TS VDDA18_TS SPI2_SSIN SPI2_MISO THERM_RES_EXT THERM_TEST_OUT (3 OF 12) IN OUT IN IN IN OUT IN OUT IN OUT OUT IN OUT IN IN IN OUT IN IN IN IN OUT OUT IN IN IN IN OUT IN OUT IN OUT IN OUT Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT CODEC ASP - BB -> H4G - BB_DIAGS_READY (RADAR #9179861) NOTE FOR GPIO12: - AP_MODEM_WAKE (RADAR #9179861) NOTE FOR GPIO24: - H4G -> BB BUT OPTION IS HERE IN CASE THEY NEED TO BE SEPARATE DEFAULT IS TO TIE HSIC_HOST_READY TO BOTH DEVICES TO BB NEW GPIO FOR J2. FILE A RADAR TO SENSOR BOARD (ALS) CODEC VSP & BT TO SENSOR BOARD TO CHARLESTON, CODEC AND PMU CODEC XSP NOT USED TO GRAPE 3.0V IO TO BT UART TO DOCK MUX TO BB USART 15 42 15 42 15 42 15 42 34 37 1% MF 01005 1/32W 33.2 1942 1942 1942 1942 1942 151942 151942 151942 151942 1942 1942 1942 1942 10 10 10 10 19 22 37 42 10 19 22 37 42 10 25 42 10 25 42 25 42 25 42 37 42 37 42 37 42 5% 201 220K 1/20W MF 5% MF 220K 1/20W 201 201 5% 220K 1/20W MF 201 MF 100K 1/20W 5% MF 100K 1/20W 5% 201 100K MF 1/20W 5% 201 MF 1/32W 01005 100K 5%5% 201 100K 1/20W MF 30 42 30 42 30 42 5 30 42 3042 24 24 30 537 3045 15 37 19 153045 201 100K 5% 1/20W MF NOSTUFF MF 100K 201 1% 1/20W 1742 1742 1742 1742 1/32W 0% 01005 MF 0.00 10% X5R 6.3V 0.01UF 01005 01005 MF 1/32W 1% 100K NOSTUFF 0% MF 01005 1/32W 0.00 MF 0% 1/32W 01005 0.00 MF 1/20W 5% 100K 201 542 OMIT H4G FCBGAOMIT H4G FCBGA 51542 15 42 15 42 52837 52437 530 3042 526 10 18 30 10 5 539 10 10 26 26 26 26 25 11 20 10 10 10 15 42 15 42 30 42 30 42 30 42 30 42 5 24 37 30 45 SYNC_MASTER=JOE SYNC_DATE=N/A AP: I/Os IRQ_CODEC_L NC_AP_GPIO7 NC_AP_GPIO8 PM_RADIO_ON RST_DET_L HSIC_BB_RDY ONOFF_L HOME_EMI_L GPIO42_BRD_REV2 IRQ_ALS_INT_L AUD_SPKRAMP_MUTE_L PORT_DOCK_VIDEO_AMP_EN RST_BB_L SRL_L NC_BOARD_ID_3 IRQ_ACCEL_INT1_L UART0_AP_TXD UART0_AP_RXD IRQ_PMU_L PM_BT_WAKE =PP1V8_VDDA18_TS HSIC_HOST_RDY =PP1V8_VDDIOD_H4 UART1_BB_RTS_L HSIC_HOST_READY_WLAN HSIC_HOST_RDY =PP1V8_S2R_MISC =PP1V8_ALWAYS =PP1V8_S2R_MISC SRL_L ONOFF_L HOME_EMI_L HSIC_WLAN_RDY HSIC_HOST_READY_WL GPIO40_BRD_REV0 GPIO41_BRD_REV1 UART1_BB_CTS_L NC_AP_GPIO185 NC_AP_GPIO186 TP_LED_STROBE_EN UART1_BB_RXD UART1_BB_TXD NC_AP_GPIO11 SPI2_IPC_SRDY NC_AP_GPIO13 AUD_VOL_DOWN_L GSM_TXBURST_IND IRQ_GYRO_INT2 BOOT_CONFIG_0 NC_AP_GPIO19 AUD_VOL_UP_L IRQ_GRAPE_HOST_INT_L PM_KEEPACT BB_EMERGENCY_DWLD IPC_GPIO_X26 BOOT_CONFIG_1 FORCE_DFU BOOT_CONFIG_2 BOOT_CONFIG_3 NC_AP_GPIO3 NC_UART2_RXD NC_UART2_TXD NC_UART4_CTS_L NC_UART4_RTS_L NC_UART4_RXD NC_UART4_TXD NC_UART6_CTSN NC_UART6_RTSN UART3_BT_CTS_L UART3_BT_RTS_L UART3_BT_RXD UART3_BT_TXD BATTERY_SWI TP_THERM_TEST_OUT THERM_RES_EXT SPI2_IPC_MISO PP1V8_VDDA18_TS NC_I2S1_DOUT I2S2_VSP_LRCK I2S2_VSP_DIN I2S2_VSP_DOUT DWI_AP_DI DWI_AP_DO I2C0_SCL_1V8 I2C0_SDA_1V8 I2C1_SCL_1V8 I2C2_SCL_3V0 I2C2_SDA_3V0NC_I2S1_BCLK NC_I2S1_DIN NC_I2S1_LRCK NC_I2S1_MCK I2S2_VSP_BCLK NC_I2S2_MCK I2S3_XSP_BCLK I2S3_XSP_DIN I2S3_XSP_DOUT I2S3_XSP_LRCK NC_I2S3_MCK NC_SDIO0_WL_CLK NC_SDIO0_WL_CMD NC_SDIO0_WL_DATA<0> NC_SDIO0_WL_DATA<1> NC_SDIO0_WL_DATA<2> NC_SDIO0_WL_DATA<3> NC_AP_GPIO216 SPI1_GRAPE_MISO SPI1_GRAPE_MOSI SPI1_GRAPE_SCLK SPI1_GRAPE_CS_L SPI2_IPC_MOSI SPI2_IPC_SCLK NC_SPI3_MISO NC_SPI3_MOSI NC_SPI3_SCLK NC_SPI3_CS_L NC_SWI_AP BOARD_ID_2 BOARD_ID_1 BOARD_ID_0 NC_SPI_FLASH_CS_L I2C1_SDA_1V8 DWI_AP_CLK IRQ_GYRO_INT1 IRQ_PROX_INT_L NC_AP_GPIO31 HSIC_HOST_READY_WL NC_AP_GPIO35 HSIC_WLAN_RDY NC_AP_GPIO3V1 DFU_STATUS IRQ_ACCEL_INT2_L UART6_WLAN_RXD UART6_WLAN_TXD PM_RADIO_ON DFU_STATUS FORCE_DFU IRQ_GYRO_INT2 PM_KEEPACT I2S0_ASP_MCK_R I2S0_ASP_BCLK I2S0_ASP_LRCK I2S0_ASP_DIN I2S0_ASP_DOUT I2S0_ASP_MCK R0700 1 2 R0708 1 2 R0709 1 2 R0710 1 2 R07151 2 R07141 2 R07131 2 R07121 2 R07111 2 R07201 2 R07221 2 R1180 1 2 C11881 2 R10301 2 R0730 1 2 R0731 1 2 R08851 2 U0600 AG26 AE15 AE16 AJ14 AK15 AG17 AD13 AK17 AE14 AL17 AF17 AL18 AK18 AJ18 AD12 AL16 AH18 AF18 AM18 AN18 AN19 AG18 AP20 AN20 AR20 AR21 AG14 AP21 AK19 AN21 AH19 AG19 AJ19 AR22 AL20 AM20 AN22 AP19 AH13 AH16 AE13 AE12 AH15 AN31 AP32 AD16 AD14 AC12 AH14 AG15 AP23 AL21 AG21 AF21 U5 T7 U8 T5 AG22 AJ21 AR24 AR23 Y6 Y7 W7 Y5 AL22 U9 V6 U7 V7 U0600 AN25 AM24 AG23 AJ23 AK23 AN24 AR25 AH21 AK21 AG24 AK25 AL25 AP26 AR26 AC17 AC16 AF26 AC14 AC15 AF24 AG25 AM26 AN26 AK27 AN27 AK26 AL26 AF25 AP27 AL27 AR31 AK28 AL28 AM29 AM30 AG27 U6 W5 T6 W8 AF20 AF19 AG20 AM21 AF23 AL23 AH23 AM23 AL30 AL29 AN32 AP33 AC13 AK16 AJ16 AF16 AG16 051-8773 10.0.0 7 OF 157 5 OF 48 46 46 46 35 935 15 42 53042 5273539 35 5273539 52437 52437 52837 51542 542 46 46 46 46 46 46 46 46 46 46 46 46 46 46 45 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 5 30 5 5 39 5 26 5 37 42
BI BI BI BI OUT OUT OUT OUT OUT OUT BI BI BI BI BI BI BI BI OUT OUT OUT OUT OUT OUT FMI0_ALE FMI3_IO7 FMI3_IO6 FMI3_IO5 FMI3_IO4 FMI3_IO1 FMI3_IO0 FMI3_DQS FMI3_CLE FMI3_CEN7 FMI3_CEN6 FMI3_CEN5 FMI3_CEN4 FMI3_CEN3 FMI3_CEN2 FMI3_CEN1 FMI3_CEN0 FMI2_WEN FMI2_REN FMI2_IO7 FMI2_IO6 FMI2_IO5 FMI2_IO4 FMI2_IO3 FMI2_IO2 FMI2_DQS FMI2_CLE FMI2_CEN7 FMI2_CEN6 FMI2_CEN4 FMI2_CEN3 FMI2_CEN2 FMI2_CEN1 FMI2_CEN0 FMI2_ALE FMI1_IO7 FMI1_IO4 FMI1_IO3 FMI1_IO2 FMI1_IO1 FMI1_IO0 FMI1_DQS FMI1_CLE FMI1_CEN1 FMI1_CEN0 FMI1_ALE FMI0_WEN FMI0_IO7 FMI0_IO6 FMI0_IO5 FMI0_IO4 FMI0_IO3 FMI0_IO2 FMI0_IO1 FMI0_IO0 FMI0_DQS FMI0_CEN7 FMI0_CEN6 FMI0_CEN5 FMI0_CEN4 FMI0_CEN3 FMI0_CEN1 FMI0_CEN0 FMI1_CEN2 FMI1_CEN3 FMI1_CEN4 FMI1_CEN7 FMI1_CEN6 FMI1_CEN5 FMI2_IO1 FMI2_IO0 FMI0_CEN2 FMI2_CEN5 FMI0_CLE FMI0_REN FMI3_ALE FMI1_IO5 FMI1_IO6 FMI3_IO3 FMI3_IO2 FMI1_REN FMI1_WEN FMI3_REN FMI3_WEN (4 OF 12) (12 OF 12) VSSVSS IN OUT OUT BI OUT OUT OUT BI BI BI Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT CHECK WITH GRAPE ON VOLTAGE FOR THESE TWO SIGNALS CHECK CONNECTION FOR VSSA18_TS FMI2-3_CEN IS 3.0V NEW GPIO FOR J2. FILE A RADAR 1244 1244 1244 1244 61244 61244 61244 61244 61244 61244 1244 1244 1244 1244 1244 1244 1244 1244 61244 61244 61244 61244 1244 1244 MF 1/32W 5% 100K 01005 NOSTUFF 01005 100K 5% 1/32W MF NOSTUFF MF 1/32W 5% 100K 01005 NOSTUFF MF 1/32W 5% 100K 01005 NOSTUFF 100K 5% 1/32W MF 01005 NOSTUFF 01005 100K 5% 1/32W MF NOSTUFF MF 1/32W 5% 100K 01005 NOSTUFF MF 1/32W 5% 100K 01005 NOSTUFF OMIT H4G FCBGA H4G FCBGA OMIT 100K 5% 1/32W MF 01005 20 01005 100K 5% 1/32W MF 01005 100K 5% 1/32W MF 01005 100K 5% 1/32W MF 100K 5% 1/32W MF 01005 17 45 16 1244 61244 17 61244 1244 1244 1244 SYNC_DATE=N/A AP: NAND SYNC_MASTER=MIKENC_FMI3_WE_LFMI1_WE_L FMI1_CLE FMI1_AD<7> FMI1_AD<6> FMI1_AD<5> FMI1_AD<4> NC_FMI2_CE1_L RST_GRAPE_L FMI0_ALE NC_FMI3_AD<7> NC_FMI3_AD<6> NC_FMI3_AD<5> NC_FMI3_AD<4> NC_FMI3_AD<1> NC_FMI3_AD<0> NC_FMI3_DQS NC_FMI3_CLE NC_FMI3_CE7_L NC_FMI3_CE6_L NC_FMI3_CE5_L NC_FMI3_CE4_L NC_FMI3_CE3_L NC_FMI3_CE2_L NC_FMI3_CE1_L NC_FMI3_CE0_L NC_FMI2_WE_L NC_FMI2_AD<7> NC_FMI2_AD<6> NC_FMI2_AD<5> NC_FMI2_AD<4> NC_FMI2_AD<3> NC_FMI2_AD<2> NC_FMI2_DQS NC_FMI2_CLE NC_FMI2_CE3_L NC_FMI2_CE2_L NC_FMI2_ALE FMI1_AD<3> FMI1_AD<2> FMI1_AD<1> FMI1_AD<0> FMI1_DQS_P FMI1_CE1_L FMI1_CE0_L FMI1_ALE FMI0_WE_L FMI0_AD<7> FMI0_AD<6> FMI0_AD<4> FMI0_AD<3> FMI0_AD<2> FMI0_AD<1> FMI0_AD<0> FMI0_DQS_P NC_FMI0_CE7_L NC_FMI0_CE6_L NC_FMI0_CE5_L NC_FMI0_CE4_L NC_FMI0_CE3_L FMI0_CE1_L FMI0_CE0_L NC_FMI1_CE2_L NC_FMI1_CE3_L NC_FMI1_CE4_L NC_FMI1_CE7_L NC_FMI1_CE6_L NC_FMI1_CE5_L NC_FMI2_AD<1> NC_FMI0_CE2_L NC_FMI2_CE5_L FMI0_CLE FMI0_RE_N NC_FMI3_ALE NC_FMI3_AD<3> NC_FMI3_AD<2> FMI1_RE_N NC_FMI3_RE_L NC_FMI2_RE_L GRAPE_FW_DNLD_EN_L NC_FMI2_AD<0> FMI0_AD<5> PM_LCDVDD_PWREN FMI1_CLE FMI0_CLE FMI1_ALE FMI1_RE_N FMI1_WE_L FMI0_RE_N PPIO_NAND_H4 FMI0_WE_L FMI0_ALE SPK_ID =PP3V0_IO_MISC FMI1_CE0_L FMI0_CE0_L FMI1_CE1_L PPIO_NAND_H4 FMI0_CE1_L R08341 2 R08311 2 R08361 2 R08321 2 R08031 2 R08021 2 R08011 2 R08001 2 R08131 2 R08121 2 R08111 2 R08101 2 U0600 AE32 AH31 AF31 AD28 AG29 Y29 AH28 AG28 AM31 AF33 AG33 AG35 AF35 AH35 AH33 AG31 AG32 AG34 AH32 AE33 AH34 AN34 AJ33 AN33 AD30 AE30 AJ31 AJ30 AL31 AK31 AK35 AL34 AL32 AN35 AK32 AK33 AL33 AK34 AM33 AJ35 AL35 AM35 AB34 AE35 AB28 AA28 AB30 AE28 AF28 AA29 AB31 AB32 AC33 AC31 AB33 AC35 AE34 AD34 AD32 AD35 AD31 AD33 AB35 Y33 W31 W28 W29 V30 AG30 AC30 AH30 AE31 W30 Y32 AA34 W33 AA33 V34 AA30 V31 W32 Y30 AA31 AA32 U0600 G22 G23 G30 H1 H4 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H30 H34 J2 J8 J9 J10 J11 J12 J14 J16 J18 J20 J22 J24 J26 J31 J34 K3 K8 K9 K10 K11 K13 K15 K17 K19 K21 K23 K25 K27 K34 L32 L1 L4 L8 L10 L12 L14 L16 L18 L20 L22 L24 L26 M2 M3 M8 M9 M11 M13 M15 M17 M19 M21 M23 M25 M27 M30 L34 N3 N8 N10 N12 N14 N16 N18 N20 N22 N24 N26 M35 P1 P8 P9 P11 P13 P15 P17 P19 P21 P23 P25 P27 R2 R8 R10 R12 R14 R16 R18 R20 R22 R24 R26 P34 T3 T9 T11 T13 T15 T17 T19 T21 T23 T25 T27 R35 U1 U10 U12 U14 U16 U18 U20 U22 U24 U26 U30 U31 V9 V11 V13 V15 V17 V19 V21 V23 V25 V27 V29 U34 V35 W1 W3 W10 W12 W14 W16 W18 W20 W22 W24 W26 W34 Y9 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y25 Y27 Y28 Y31 Y34 R08041 2 051-8773 10.0.0 8 OF 157 6 OF 48 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 61244 61244 61244 61244 61244 61244 6945 61244 61244 2835 61244 61244 61244 6945 61244
OUT OUT OUT OUT OUT OUT IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT BI BI OUT OUT OUT OUT (5 OF 12) DAC_VREF DP_PAD_TX0P DP_PAD_AUXN DP_PAD_AUXP EDP_PAD_TX0P DP_PAD_AVSS_AUX EDP_PAD_AVSS DAC_AVSS30D DP_PAD_AVDDX DP_PAD_TX2P DP_PAD_TX1N DP_PAD_TX1P DAC_AVSS30A1 DAC_AVSS30A2 DAC_IREF DAC_OUT1 DAC_OUT3 DP_HPD DP_PAD_DC_TP DP_PAD_R_BIAS DP_PAD_TX2N DP_PAD_TX3N DP_PAD_TX3P EDP_HPD EDP_PAD_AUXN EDP_PAD_AUXP EDP_PAD_AVSSP0 EDP_PAD_AVSSX EDP_PAD_DVDDEDP_PAD_DVSS EDP_PAD_R_BIAS EDP_PAD_TX0N EDP_PAD_TX1N EDP_PAD_TX1P EDP_PAD_TX2N EDP_PAD_TX2P EDP_PAD_TX3N EDP_PAD_TX3P DP_PAD_AVDDP0 DP_PAD_AVDD DAC_COMP EDP_PAD_AVDDX EDP_PAD_AVDDP0 EDP_PAD_AVDD EDP_PAD_AVDD_AUX DP_PAD_DVDD EDP_PAD_AVSS_AUX DP_PAD_AVSSP0 DP_PAD_AVSSX DP_PAD_DVSS DP_PAD_AVSS DP_PAD_TX0N DAC_OUT2 EDP_PAD_DC_TP DAC_AVDD30D DAC_AVDD30A DP_PAD_AVDD_AUX MIPI_VDD11 MIPI1D_VREG_0P4V MIPI0D_VREG_0P4V ISP0_FLASH SENSOR1_RST SENSOR1_CLK SENSOR0_RST SENSOR0_CLK MIPI1C_DNDATA0 MIPI_VSYNC ISP1_SCL ISP1_PRE_FLASH ISP1_FLASH ISP0_SDA ISP0_SCL ISP0_PRE_FLASH MIPI1C_DPDATA0 MIPI1D_VDD18 MIPI0D_VDD18 MIPI0C_DNDATA3 MIPI1C_DNCLK MIPI1C_DPCLK MIPI1C_DNDATA1 MIPI1C_DPDATA1 MIPI0C_DPDATA0 MIPI0C_DNDATA0 MIPI0C_DPDATA1 MIPI0C_DPDATA2 MIPI0C_DNDATA2 MIPI0C_DPDATA3 MIPI0C_DPCLK MIPI0C_DNCLK MIPI0C_DNDATA1 ISP1_SDA (6 OF 12) PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_ALT_ITEM Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT 1.2MA 5MA 2MA 332MA 21MA 4MA DP LANES 2/3 ARE FOR STEVE-NOTE ONLY NOTE: 0.6V ANALOG REF NOTE: 0.6V ANALOG REF 6MA 5MA 2MA 5MA 1.2MA 5MA 172MA 14MA 6.3V 0.22UF 20% X5R 402 1/20W 1% 201 6.34K MF 10% 6.3V 201 X5R 0.1UF X5R 6.3V 10% 01005 0.01UF 6.3V 01005 NP0-C0G 56PF 5% 1UF 402 6.3V 10% CERM 6.3V 10% 0.01UF X5R 01005 0.22UF 20% 402 X5R 6.3V 402 X5R 6.3V 20% 0.22UF MF 1/20W 201 0 5% 6.3V NP0-C0G 01005 56PF 5% 0.1UF 10% 201 X5R 6.3V 1% 201 200 1/20W MF MF 201 1/20W 1% 200 201 MF 1% 200 1/20W 4.99K 1/32W 1% MF 01005 0.01UF 01005 X5R 6.3V 10% NOSTUFF NP0-C0G 01005 6.3V 56PF 5% 0 201 MF 1/20W 5% 01005 56PF NP0-C0G 6.3V 5% 6.3V 20% X5R 402 0.22UF 402 0.22UF X5R 20% 6.3V 402 0.22UF 20% X5R 6.3V 10% 6.3V 0.1UF X5R 201 MF 1/32W 01005 1% 4.99K 01005 X5R 6.3V 10% 0.01UF NOSTUFF 402 1UF 10% CERM 6.3V 201 6.3V X5R 10% 0.1UF 6.3V X5R 201 10% 0.1UF 0.1UF X5R 10% 201 6.3V 0.00 MF 01005 0% 1/32W MF 0.00 01005 0% 1/32W 0201 240-OHM-0.2A-0.8-OHM 201 X5R 10% 10V 2.2NF 10V X5R 201 10% 2.2NF 28 43 28 43 28 43 28 43 28 43 28 43 37 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 0.1UF 201 X5R 6.3V 10% 11 43 11 43 11 43 2543 2543 2543 2543 2543 2543 25 43 25 43 25 43 25 43 25 42 25 42 25 42 25 42 1/32W 01005 MF 1.00K 5% 1/32W MF 01005 1.00K 5% 1/32W MF 01005 1.00K 5% 1/32W MF 01005 1.00K 5% 28 43 28 43 28 43 28 43 H4G OMIT FCBGA OMIT H4G FCBGA SYNC_MASTER=JOE SYNC_DATE=01/13/2011 AP: TV,DP,MIPI 132S0279 132S0154 RADAR:9624625C0960,C0961 NET_SPACING_TYPE=PWR PP0V4_MIPI1D VOLTAGE=0.4V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM MAX_NECK_LENGTH=3MM =PP1V8_H4 ISP_AP_1_SDA TP_CAM0_1V2_VDDCORE_EN ISP_AP_0_SCL CAM0_RESET_L ISP_AP_0_SDA ISP_AP_1_SCL CLK_CAM_RF PM_FRONT_CAM_SHUTDOWN CLK_CAM_FF_R PM_REAR_CAM_SHUTDOWN CLK_CAM_RF_R NC_ISP_AP_1_PRE_FLASH NC_ISP_AP_1_FLASH =PP1V8_MIPI_H4 NC_MIPI0C_AP_DATA_N<3> MIPI1C_AP_CLK_N MIPI1C_AP_CLK_P NC_MIPI1C_AP_DATA_N<1> NC_MIPI1C_AP_DATA_P<1> MIPI0C_AP_DATA_P<0> MIPI0C_AP_DATA_N<0> MIPI0C_AP_DATA_P<1> NC_MIPI0C_AP_DATA_P<2> NC_MIPI0C_AP_DATA_N<2> NC_MIPI0C_AP_DATA_P<3> MIPI0C_AP_CLK_N MIPI0C_AP_DATA_N<1> DAC_AP_VREF DP_AP_TX_P<0> DP_AP_AUX_N DP_AP_AUX_P EDP_AP_TX_P<0> DP_AP_TX_P<2> DP_AP_TX_N<1> DP_AP_TX_P<1> DAC_AP_OUT1 DP_AP_HPD TP_DP_AP_ANALOG_TEST AP_DP_R_BIAS DP_AP_TX_N<2> DP_AP_TX_N<3> DP_AP_TX_P<3> EDP_AP_AUX_N EDP_AP_AUX_P =PP1V1_EDP_PAD_DVDD_H4 AP_EDP_R_BIAS EDP_AP_TX_N<0> EDP_AP_TX_N<1> EDP_AP_TX_P<2> EDP_AP_TX_N<3> EDP_AP_TX_P<3> DAC_AP_COMP DP_AP_TX_N<0> DAC_AP_OUT2 =PP1V8_EDP_H4 DAC_AP_COMP_FTR=PP3V0_VIDEO_H4 CLK_CAM_FF EDP_AP_HPD EDP_AP_TX_P<1> EDP_AP_TX_N<2> TP_EDP_AP_ANALOG_TEST MAX_NECK_LENGTH=3MM MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=PWR VOLTAGE=1.8V PP1V8_EDP_AVDD_AUX MIN_NECK_WIDTH=0.1MM MAX_NECK_LENGTH=3MM NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.2MM VOLTAGE=0.4V PP0V4_MIPI0D DAC_AP_IREF MIPI1C_AP_DATA_N<0> MIPI0C_AP_CLK_P DAC_AP_OUT3 =PP3V0_VIDEO_H4 NC_MIPI_VSYNC_H4 =PP1V1_DP_PAD_DVDD_H4 MIPI1C_AP_DATA_P<0> =PP3V0_IO_H4 =PP1V8_DP_H4 VOLTAGE=1.8V MIN_LINE_WIDTH=0.2MM PP1V8_DP_AVDD_AUX MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM =PP1V1_MIPI_H4 C09271 2 R09501 2 C09551 2 C09521 2 C09241 2 C09511 2 C09531 2 C09261 2 C09251 2 R0910 1 2 C09231 2 C09091 2 R09551 2 R09561 2 R09571 2 R09201 2 C09501 2 C09301 2 R0911 1 2 C09311 2 C09321 2 C09331 2 C09341 2 C09101 2 R09211 2 C09571 2 C09351 2 C09031 2 C09081 2 C09071 2 R09001 2 R09401 2 FL0910 1 2 C09601 2 C09611 2 C09561 2 R09301 2 R09311 2 R09321 2 R09331 2 U0600 G31 D32 G32 F32 D31 E32 F31 G35 G34 G33E31 AL15 C27 C28 C26 C25 D24 D23 D28 D27 B29 A26 A25 B24 B23 B28 B27 D29 F23 A29C29 E23 A27 A28 D25 D26 B25 B26 C23 C24 AJ15 A23 A24 B18 A18 E19 E18 D20 D19 C21 D18 C18 F19 F18 B20 B19 A21 F20 C22A22 E20 D21 D22 B21 B22 C19 C20 A19 A20 U0600 AD17 AF13 AK22 AF22 AF14 AE17 AP24 AN23 A32 C35 B32 B30 A30 A33 D35 B33 B31 A31 F25 F26 E35 E34 C34 F35 F34 D34 F28 F29 G24 G25 G26 G27 G28 G29 AD15 AJ24 AK24 AH24 AL24 051-8773 10.0.0 9 OF 157 7 OF 48 45 4 10 35 26 25 42 25 42 25 42 46 46 35 4346 43 46 43 46 4346 4346 4346 45 35 35 735 25 42 45 45 735 46 35 935 3545 35
BI BI BI BI BI BI BI OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT BI BI BI BI BI BI BI BI OUT OUT OUT OUT BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT BI BI BI BI BI BI BI BI OUT OUT OUT OUT BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI OUT BI BI BI BI OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT BI BI BI BI BI BI BI BI OUT BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI OUT OUT OUT OUT BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT (7 OF 12) DDR0_CA0 DDR0_CA1 DDR0_CA2 DDR0_CA3 DDR0_CA4 DDR0_CA5 DDR0_CA6 DDR0_CA7 DDR0_CA8 DDR0_CA9 DDR0_CK DDR0_CKB DDR0_CKE0 DDR0_CKE1 DDR0_CSN0 DDR0_CSN1 DDR0_DM0 DDR0_DM1 DDR0_DM2 DDR0_DM3 DDR0_DQ0 DDR0_DQ1 DDR0_DQ10 DDR0_DQ11 DDR0_DQ12 DDR0_DQ13 DDR0_DQ14 DDR0_DQ15 DDR0_DQ16 DDR0_DQ17 DDR0_DQ18 DDR0_DQ19 DDR0_DQ2 DDR0_DQ20 DDR0_DQ21 DDR0_DQ22 DDR0_DQ23 DDR0_DQ24 DDR0_DQ25 DDR0_DQ26 DDR0_DQ27 DDR0_DQ28 DDR0_DQ29 DDR0_DQ3 DDR0_DQ30 DDR0_DQ31 DDR0_DQ4 DDR0_DQ5 DDR0_DQ6 DDR0_DQ7 DDR0_NDQS0 DDR0_NDQS1 DDR0_NDQS2 DDR0_NDQS3 DDR0_PDQS0 DDR0_PDQS1 DDR0_PDQS2 DDR0_PDQS3 DDR0_VDDQ_CKE DDR0_VREF_DQ DDR0_ZQ DDR1_CA0 DDR1_CA1 DDR1_CA2 DDR1_CA3 DDR1_CA4 DDR1_CA6 DDR1_CA7 DDR1_CA8 DDR1_CA9 DDR1_CK DDR1_CKB DDR1_CKE0 DDR1_CSN0 DDR1_CSN1 DDR1_DM0 DDR1_DM1 DDR1_DM2 DDR1_DM3 DDR1_DQ0 DDR1_DQ1 DDR1_DQ10 DDR1_DQ11 DDR1_DQ12 DDR1_DQ13 DDR1_DQ14 DDR1_DQ15 DDR1_DQ16 DDR1_DQ17 DDR1_DQ18 DDR1_DQ19 DDR1_DQ2 DDR1_DQ20 DDR1_DQ21 DDR1_DQ22 DDR1_DQ23 DDR1_DQ24 DDR1_DQ25 DDR1_DQ26 DDR1_DQ27 DDR1_DQ28 DDR1_DQ29 DDR1_DQ3 DDR1_DQ30 DDR1_DQ31 DDR1_DQ4 DDR1_DQ5 DDR1_DQ6 DDR1_DQ7 DDR1_DQ8 DDR1_DQ9 DDR1_NDQS0 DDR1_NDQS1 DDR1_NDQS2 DDR1_NDQS3 DDR1_PDQS0 DDR1_PDQS1 DDR1_PDQS2 DDR1_PDQS3 DDR0_DQ8 DDR0_DQ9 DDR1_CA5 DDR1_VREF_DQ DDR1_CKE1 DDR1_VDDQ_CKE DDR1_ZQ (8 OF 12) DDR2_DQ0 DDR2_DQ1 DDR2_DQ2 DDR2_DQ3 DDR2_DQ4 DDR2_DQ5 DDR2_DQ6 DDR2_DQ7 DDR2_DQ8 DDR2_DQ9 DDR2_DQ10 DDR2_DQ11 DDR2_DQ12 DDR2_DQ13 DDR2_DQ14 DDR2_DQ15 DDR2_DQ16 DDR2_DQ17 DDR2_DQ18 DDR2_DQ19 DDR2_DQ20 DDR2_DQ21 DDR2_DQ22 DDR2_DQ23 DDR2_DQ24 DDR2_DQ25 DDR2_DQ26 DDR2_DQ27 DDR2_DQ28 DDR2_DQ29 DDR2_DQ30 DDR2_DQ31 DDR2_CA0 DDR2_CA1 DDR2_CA2 DDR2_CA3 DDR2_CA4 DDR2_CA5 DDR2_CA6 DDR2_CA7 DDR2_CA8 DDR2_CA9 DDR2_DM0 DDR2_DM1 DDR2_DM2 DDR2_DM3 DDR2_PDQS0 DDR2_NDQS0 DDR2_PDQS1 DDR2_NDQS1 DDR2_PDQS2 DDR2_NDQS2 DDR2_PDQS3 DDR2_NDQS3 DDR2_VDDQ_CKE DDR2_VREF_DQ DDR2_ZQ DDR2_CK DDR2_CKB DDR2_CKE0 DDR2_CKE1 DDR2_CSN0 DDR2_CSN1 DDR3_DQ0 DDR3_DQ1 DDR3_DQ2 DDR3_DQ3 DDR3_DQ4 DDR3_DQ5 DDR3_DQ6 DDR3_DQ7 DDR3_DQ8 DDR3_DQ9 DDR3_DQ10 DDR3_DQ11 DDR3_DQ12 DDR3_DQ13 DDR3_DQ14 DDR3_DQ15 DDR3_DQ16 DDR3_DQ17 DDR3_DQ18 DDR3_DQ19 DDR3_DQ20 DDR3_DQ21 DDR3_DQ22 DDR3_DQ23 DDR3_DQ24 DDR3_DQ25 DDR3_DQ26 DDR3_DQ27 DDR3_DQ28 DDR3_DQ29 DDR3_DQ30 DDR3_DQ31 DDR3_CA0 DDR3_CA1 DDR3_CA2 DDR3_CA3 DDR3_CA4 DDR3_CA5 DDR3_CA6 DDR3_CA7 DDR3_CA8 DDR3_CA9 DDR3_DM0 DDR3_DM1 DDR3_DM2 DDR3_DM3 DDR3_PDQS0 DDR3_NDQS0 DDR3_PDQS1 DDR3_NDQS1 DDR3_PDQS2 DDR3_NDQS2 DDR3_PDQS3 DDR3_NDQS3 DDR3_VDDQ_CKE DDR3_VREF_DQ DDR3_ZQ DDR3_CK DDR3_CKB DDR3_CKE0 DDR3_CKE1 DDR3_CSN0 DDR3_CSN1 BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT 998-3125 0.5MM PT 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 134044 134044 1344 1344 134044 1344 1344 1344 1344 1344 1344 1344 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 13 44 13 44 13 44 13 44 13 44 01005 10% 0.01UF NOSTUFF 6.3V X5R 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 1.00K 1% MF 1/32W 01005 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 1/32W 1% MF 01005 1.00K 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 10% 01005 0.01UF NOSTUFF 6.3V X5R 13 44 13 44 13 44 13 44 13 44 13 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 1.00K 1% 1/32W MF 01005 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 MF 1.00K 1/32W 1% 01005 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 H4G FCBGA OMIT H4G FCBGA OMIT 0.01UF 01005 10% NOSTUFF 6.3V X5R 1/32W 1.00K 1% MF 01005 MF 1.00K 1/32W 1% 01005 10% 01005 0.01UF NOSTUFF 6.3V X5R 01005 1/32W MF 1% 1.00K 01005 1.00K MF 1% 1/32W 0201 6.3V X5R 0.22UF 20% 0201 6.3V X5R 0.22UF 20% 0201 6.3V X5R 0.22UF 20% 0201 6.3V X5R 0.22UF 20% MF 1% 1/20W 240 201 1/20W 240 MF 1% 201 240 1% 1/20W MF 201 240 1% 1/20W MF 201 10% 01005 0.01UF 6.3V X5R NOSTUFF NOSTUFF 10% 01005 0.01UF 6.3V X5R NOSTUFF 0.01UF 10% 01005 6.3V X5R 10% 01005 0.01UF NOSTUFF 6.3V X5R 134044 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 134044 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 SYNC_MASTER=MIKE AP: DDR SYNC_DATE=N/A DDR1_DM<2> DDR1_DM<0> H4G_DDR0_ZQ MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.3MM PPVREF_DDR1_DQ_H4 MIN_NECK_WIDTH=0.2MM VOLTAGE=0.6V NET_SPACING_TYPE=PWR PPVREF_DDR1_DQ_H4 PPVREF_DDR0_DQ_H4 MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM MAX_NECK_LENGTH=3 MM VOLTAGE=0.6V NET_SPACING_TYPE=PWR PPVREF_DDR0_DQ_H4 MAX_NECK_LENGTH=3 MM VOLTAGE=0.6V MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM PPVREF_DDR2_DQ_H4 NET_SPACING_TYPE=PWR PPVREF_DDR2_DQ_H4 PPVREF_DDR3_DQ_H4 MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0.6V MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR PPVREF_DDR3_DQ_H4 DDR1_DQ<27> DDR1_DQ<23> =PP1V2_VDDIOD_H4 =PP1V2_VDDIOD_H4 =PP1V2_VDDIOD_H4 =PP1V2_VDDIOD_H4 H4G_DDR1_ZQ =PP1V2_S2R_H4 NC_DDR1_CKE<1> DDR1_CA<5> DDR0_DQ<9> DDR0_DQ<8> DDR1_DQS_P<3> DDR1_DQS_P<2> DDR1_DQS_P<1> DDR1_DQS_P<0> DDR1_DQS_N<3> DDR1_DQS_N<2> DDR1_DQS_N<1> DDR1_DQS_N<0> DDR1_DQ<9> DDR1_DQ<8> DDR1_DQ<7> DDR1_DQ<6> DDR1_DQ<5> DDR1_DQ<4> DDR1_DQ<31> DDR1_DQ<30> DDR1_DQ<3> DDR1_DQ<29> DDR1_DQ<28> DDR1_DQ<26> DDR1_DQ<25> DDR1_DQ<24> DDR1_DQ<22> DDR1_DQ<21> DDR1_DQ<20> DDR1_DQ<2> DDR1_DQ<19> DDR1_DQ<18> DDR1_DQ<17> DDR1_DQ<16> DDR1_DQ<15> DDR1_DQ<14> DDR1_DQ<13> DDR1_DQ<12> DDR1_DQ<11> DDR1_DQ<10> DDR1_DQ<1> DDR1_DQ<0> DDR1_DM<3> DDR1_DM<1> NC_DDR1_CSN<1> DDR1_CSN<0> DDR1_CKE<0> DDR1_CK_N DDR1_CK_P DDR1_CA<9> DDR1_CA<8> DDR1_CA<7> DDR1_CA<6> DDR1_CA<4> DDR1_CA<3> DDR1_CA<2> DDR1_CA<1> DDR1_CA<0> =PP1V2_S2R_H4 DDR0_DQS_P<3> DDR0_DQS_P<2> DDR0_DQS_P<1> DDR0_DQS_P<0> DDR0_DQS_N<3> DDR0_DQS_N<2> DDR0_DQS_N<1> DDR0_DQS_N<0> DDR0_DQ<7> DDR0_DQ<6> DDR0_DQ<5> DDR0_DQ<4> DDR0_DQ<31> DDR0_DQ<30> DDR0_DQ<3> DDR0_DQ<29> DDR0_DQ<28> DDR0_DQ<27> DDR0_DQ<26> DDR0_DQ<25> DDR0_DQ<24> DDR0_DQ<23> DDR0_DQ<22> DDR0_DQ<21> DDR0_DQ<20> DDR0_DQ<2> DDR0_DQ<19> DDR0_DQ<18> DDR0_DQ<17> DDR0_DQ<16> DDR0_DQ<15> DDR0_DQ<14> DDR0_DQ<13> DDR0_DQ<12> DDR0_DQ<11> DDR0_DQ<10> DDR0_DQ<1> DDR0_DQ<0> DDR0_DM<3> DDR0_DM<2> DDR0_DM<1> DDR0_DM<0> NC_DDR0_CSN<1> DDR0_CSN<0> NC_DDR0_CKE<1> DDR0_CKE<0> DDR0_CK_N DDR0_CK_P DDR0_CA<9> DDR0_CA<8> DDR0_CA<7> DDR0_CA<6> DDR0_CA<5> DDR0_CA<4> DDR0_CA<3> DDR0_CA<2> DDR0_CA<1> DDR0_CA<0> NC_DDR3_CSN<1> DDR3_CSN<0> NC_DDR3_CKE<1> DDR3_CKE<0> DDR3_CK_N DDR3_CK_P H4G_DDR3_ZQ =PP1V2_S2R_H4 DDR3_DQS_N<3> DDR3_DQS_P<3> DDR3_DQS_N<2> DDR3_DQS_P<2> DDR3_DQS_N<1> DDR3_DQS_P<1> DDR3_DQS_N<0> DDR3_DQS_P<0> DDR3_DM<3> DDR3_DM<2> DDR3_DM<1> DDR3_DM<0> DDR3_CA<9> DDR3_CA<8> DDR3_CA<7> DDR3_CA<6> DDR3_CA<5> DDR3_CA<4> DDR3_CA<3> DDR3_CA<2> DDR3_CA<1> DDR3_CA<0> DDR3_DQ<31> DDR3_DQ<30> DDR3_DQ<29> DDR3_DQ<28> DDR3_DQ<27> DDR3_DQ<26> DDR3_DQ<25> DDR3_DQ<24> DDR3_DQ<23> DDR3_DQ<22> DDR3_DQ<21> DDR3_DQ<20> DDR3_DQ<19> DDR3_DQ<18> DDR3_DQ<17> DDR3_DQ<16> DDR3_DQ<15> DDR3_DQ<14> DDR3_DQ<13> DDR3_DQ<12> DDR3_DQ<11> DDR3_DQ<10> DDR3_DQ<9> DDR3_DQ<8> DDR3_DQ<7> DDR3_DQ<6> DDR3_DQ<5> DDR3_DQ<4> DDR3_DQ<3> DDR3_DQ<2> DDR3_DQ<1> DDR3_DQ<0> NC_DDR2_CSN<1> DDR2_CSN<0> NC_DDR2_CKE<1> DDR2_CKE<0> DDR2_CK_N DDR2_CK_P H4G_DDR2_ZQ =PP1V2_S2R_H4 DDR2_DQS_N<3> DDR2_DQS_P<3> DDR2_DQS_N<2> DDR2_DQS_P<2> DDR2_DQS_N<1> DDR2_DQS_P<1> DDR2_DQS_N<0> DDR2_DQS_P<0> DDR2_DM<3> DDR2_DM<2> DDR2_DM<1> DDR2_DM<0> DDR2_CA<9> DDR2_CA<8> DDR2_CA<7> DDR2_CA<6> DDR2_CA<5> DDR2_CA<4> DDR2_CA<3> DDR2_CA<2> DDR2_CA<1> DDR2_CA<0> DDR2_DQ<31> DDR2_DQ<30> DDR2_DQ<29> DDR2_DQ<28> DDR2_DQ<27> DDR2_DQ<26> DDR2_DQ<25> DDR2_DQ<24> DDR2_DQ<23> DDR2_DQ<22> DDR2_DQ<21> DDR2_DQ<20> DDR2_DQ<19> DDR2_DQ<18> DDR2_DQ<17> DDR2_DQ<16> DDR2_DQ<15> DDR2_DQ<14> DDR2_DQ<13> DDR2_DQ<12> DDR2_DQ<11> DDR2_DQ<10> DDR2_DQ<9> DDR2_DQ<8> DDR2_DQ<7> DDR2_DQ<6> DDR2_DQ<5> DDR2_DQ<4> DDR2_DQ<3> DDR2_DQ<2> DDR2_DQ<1> DDR2_DQ<0> C10561 2 R10551 2 R10561 2 C10541 2 R10531 2 R10541 2 C10841 2 R10831 2 R10841 2 C10961 2 R10951 2 R10961 2 C10201 2 C10211 2 C10221 2 C10231 2 R10201 2 R10211 2 R10221 2 R102341 2 C10571 2 C10581 2 C10951 2 C10851 2 U0600 G5 G6 H5 H6 J5 M5 M6 N6 P5 P6 P4 N4 J1 K1 K6 J6 E12 E9 C14 D6 B14 B13 B8 C8 B7 B6 C6 D7 B17 C17 B16 E17 D13 D16 E16 C15 D15 E6 B5 C5 E5 C4 D4 C12 B3 C3 D12 B11 C11 B10 C9 D9 A12 A7 A15 A4 A13 A6 A16 A3 G11 D10 M4 E15 F15 F14 E14 F13 E8 F8 F7 E7 F6 F11 F12 A10 A9 F10 E13 L5 N5 G4 R5 H2 H3 P3 R3 U3 T2 U2 R4 C2 D2 E2 E4 J3 E3 F3 F4 G2 R6 T4 U4 V1 V2 V3 J4 V4 V5 K2 L2 K4 K5 N2 P2 G1 M1 D1 R1 F1 N1 C1 T1 N7 L3 E11 U0600 AL6 AK6 AL7 AK7 AL8 AL11 AK11 AK12 AL12 AK13 AM13 AM12 AR10 AR9 AK9 AK8 AD4 AG4 AA6 AK4 AB2 AB3 AH3 AF4 AJ3 AJ2 AK3 AF5 Y2 W2 Y3 W4 AC2 Y4 AA3 AA5 AA4 AL2 AL3 AL4 AM2 AN2 AN3 AC4 AL5 AK5 AE2 AD3 AF2 AE3 AG3 AH2 AD1 AJ1 AA1 AM1 AC1 AK1 Y1 AN1 AE7 AE4 AL9 AB5 AB6 AC5 AC6 AD5 AG5 AG6 AH6 AH5 AJ6 AH4 AJ4 AF1 AG1 AE6 AD6 AM11 AL13 AM6 AK14 AP7 AM7 AL10 AP13 AP14 AM14 AL14 AN14 AP4 AP3 AN4 AM4 AP8 AP5 AN5 AN6 AM5 AN15 AM15 AP16 AM16 AR18 AP17 AN8 AN17 AM17 AN9 AP10 AP11 AN11 AN12 AM10 AR7 AR12 AR4 AR15 AR6 AR13 AR3 AR16 AJ12 AM9 AE5 051-8773 10.0.0 10 OF 157 8 OF 48 8 45 8 45 8 45 845 8 45 845 8 45 8 45 8935 8935 8935 8935 8 35 46 46 835 46 46 46 46 8 35 46 46 835
(9 OF 12) VDD VDD VDDIO18_GPIO VDDIO18_UART1_TXD0 VDD_CPU VDDIOD VDDIOD7 VDDIOD6 VDDIOD5 VDDIOD4 VDDIOD3 VDDIOD2 VDDIOD1 VDDIOD0 VDDIO18_XO0 VDDIO18_FUSE0_FSRC VDDIO18_UART2_TXD VDDIO30_USB11 VDDIO30_GPIO_3V0 VDDIO30_DP_HPD VDDIO30_CFSB (10 OF 12) Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_ALT_ITEM FMI0-1 88MA FMI2-3 88MA 1000MA 160MA 44MA FMI2-3_CEN 2MA ISP FLASH, SPI3 3MA UART4 ?MA GPIO30-39 4MA 2300MA 3800MA SPI1 1MA I2C2 1MA C1100, C1102, C1103, C1117, C1121, C1122, C1124, C1153, C1154, C1155, C1156, C1158, C1191, C1615, C1621, C1715, C1721 10% 1UF 402 CERM 6.3V 10% 1UF 402 CERM 6.3V 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 402 10% 1UF CERM 6.3V 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 603 10UF X5R 6.3V 20% 0610 20% 4V X5R-CERM 4.3UF 603 10UF X5R 6.3V 20% 0610 20% 4V X5R-CERM 4.3UF 01005 10% 6.3V X5R 0.01UF 01005 10% 6.3V X5R 0.01UF 01005 10% 6.3V X5R 0.01UF 01005 10% 6.3V X5R 0.01UF 01005 0.01UF X5R 6.3V 10% 0201 0.22UF X5R 6.3V 20% 0201 20% 6.3V X5R 0.22UF 0201 20% 6.3V X5R 0.22UF 0201 20% 6.3V X5R 0.22UF 0201 0.22UF X5R 6.3V 20% 0201 0.22UF X5R 6.3V 20% 01005 10% 0.01UF 6.3V X5R 4.3UF 0610 4V X5R-CERM 20% 10UF 603 6.3V X5R 20% X5R-CERM 0610 4.3UF 4V 20% 0201 20% 6.3V X5R 0.22UF 0402-1 CERM-X5R 10UF 6.3V 20% 0201 0.22UF X5R 6.3V 20% 6.3V X5R 0201 0.22UF 20% 56PF 5% NP0-C0G 01005 6.3V 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 0 5% NAND_IO_1V8 MF 1/20W 201 NAND_IO_3V3 MF 1/20W 0 5% 201 H4G FCBGA OMIT FCBGA H4G OMIT 01005 5% 6.3V NP0-C0G 56PF 01005 56PF NP0-C0G 6.3V 5% 01005 NP0-C0G 5% 56PF 6.3V 01005 NP0-C0G 5% 56PF 6.3V 01005 NP0-C0G 5% 56PF 6.3V 01005 NP0-C0G 5% 56PF 6.3V 56PF 5% NP0-C0G 01005 6.3V 6.3V X5R 0201 0.22UF 20% 0610 20% 4V X5R-CERM 4.3UF 0610 20% 4V X5R-CERM 4.3UF 0201 0.22UF X5R 6.3V 20% 6.3V X5R 0201 0.22UF 20% 0201 0.22UF X5R 6.3V 20% 4V X5R-CERM 0610 4.3UF 20% 6.3V X5R 0201 0.22UF 20% 0610 20% 4V X5R-CERM 4.3UF 603 10UF 6.3V X5R 20% 0610 4.3UF X5R-CERM 4V 20% 0201 0.22UF X5R 6.3V 20% 0201 20% 6.3V X5R 0.22UF 0201 20% 6.3V X5R 0.22UF 01005 10% 6.3V X5R 0.01UF 6.3V X5R 0201 0.22UF 20% 0201 0.22UF X5R 6.3V 20% 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 0610 4.3UF X5R-CERM 4V 20% 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% X5R-CERM 4V 0610 4.3UF 20% 0610 4V 4.3UF X5R-CERM 20% 4.3UF X5R-CERM 4V 0610 20% 6.3V 56PF 5% NP0-C0G 0100501005 NP0-C0G 5% 56PF 6.3V 6.3V X5R 0201 0.22UF 20% 138S0657138S0702 QTY 17 RADAR:8837828C1100,C1102 SYNC_MASTER=MIKE SYNC_DATE=N/A AP: POWER =PPVDD_SOC_H4 =PPVDD_CPU_H4 =PPVDD_SOC_H4 =PP1V2_VDDIOD_H4 =PP3V0_VDDIOD_H4 MAX_NECK_LENGTH=3 MM VOLTAGE=1.8V NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.2MM PPIO_NAND_H4 =PP1V8_VDDIOD_H4 =PP1V8_VDDIO18_H4 =PP3V0_IO_H4 =PP1V8_NAND_H4 =PP3V3_NAND_H4 C11971 2 C1196 1 2 C1192 1 2 C11951 2 C1124 1 2 C1132 1 2 C1131 1 2 C1122 1 2 C1121 1 2 C1130 1 2 C1129 1 2 C1191 1 2 C1194 1 2 C1103 1 2 C1102 1 2 C1111 1 2 C1110 1 2 C1109 1 2 C1104 1 2 C1108 1 2 C11591 2 C11601 2 C11611 2 C11621 2 C11631 2 C11641 2 C11651 2 C11661 2 C1154 1 2 C1155 1 2 C1156 1 2 C1152 1 2 C1151 1 2 C11841 2 C11701 2 C11711 2 C11741 2 C11731 2 C11721 2 C11831 2 C11811 2 C11821 2 C1101 1 2 C1100 1 2 C1123 1 2 C1117 1 2 C1105 1 2 C1107 1 2 C1106 1 2 C1126 1 2 C1125 1 2 C1135 1 2 C1134 1 2 C1133 1 2 C1138 1 2 C1137 1 2 C1136 1 2 C1150 1 2 C1153 1 2 C1157 1 2 C1158 1 2 C11751 2 C1190 1 2 C1193 1 2 C11771 2 C11761 2 C11991 2 C11981 2 R1100 1 2 R1101 1 2 U0600 AA9 AA11 AC11 U25 U27 V10 V12 V14 V16 W9 W11 W13 W15 AD10 W17 Y10 Y12 Y14 Y16 AE11 AF10 AF11 AF12 AG10 AG11 AG12 AG13 AA13 J13 J15 J17 J19 J21 J23 J25 J27 K12 K14 AA15 K16 K18 K20 K22 K24 K26 L9 L11 L13 L15 AA17 L17 L19 L21 L23 L25 L27 M10 M12 M14 M16 AB10 M18 M20 M22 M24 M26 N9 N11 N13 N15 N17 AB12 N19 N21 N23 N25 N27 P10 P12 P14 P16 P18AB14 P20 P22 P24 P26 R9 R11 R13 R15 R17 R19 AB16 R21 R23 R25 R27 T10 T12 T14 T16 T18 T20 AC9 T22 T24 T26 U11 U13 U15 U17 U19 U21 U23 U0600 AA19 AA21 AC19 AC21 AC23 AC25 AC26 AC27 AD18 AD20 AD22 AD24 AA23 AD26 AE19 AE21 AE23 AE25 AE27 V18 V20 V22 V24 AA25 V26 W19 W21 W23 W25 W27 Y18 Y20 Y22 Y24 AA27 Y26 AB18 AB20 AB22 AB24 AB26 N29 AJ17 AJ22 AJ25 AJ26 T8 V28 V8 AF15 AJ28 M29 N28 Y8 AH20 AK20 AL19 AK30 AH29 AE29 AF29 AB29 AC29 AA7 AB7 AJ10 AJ11 G7 G8 G9 G10 G12 G13 G14 G15 AC7 G16 H7 J7 K7 L7 M7 P7 R7 AD7 AF7 AG7 AH7 AJ7 AJ8 AJ9 C1140 1 2 C1141 1 2 C11421 2 C11441 2 C11431 2 C11451 2 C11461 2 051-8773 10.0.0 11 OF 157 9 OF 48 935 35 935 8 35 35 645 5 35 35 735 35 35
IN OUT OUT OUT IN IN OUT OUT Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT 0101 0100 J2A DEV J2A AP 1111 RESERVED 1101 FMI0/1 4/4 CS 010 CURRENT SETTING -> 001 011 EVT PROTO 2 100 0100 FMI0 2CS 0010 SPI0 W/TEST 0011 SPI1 W/TEST 0000 SPI0 0101 FMI0 4CS 0111 RESERVED 1000 FMI1 2 CS BOOT_CONFIG[3:0] 0110 FMI0 4CS W/TEST 1010 FMI1 4CS W/TEST 1001 FMI1 4 CS 1100 FMI0/1 2/2 CS FOR REFERENCE 0001 SPI1 PROTO 1 CHINA PROTO 1 LOCAL 3. READ BOARD REVISION PROTO 0000 BRD_REV[2-0] 1110 FMI0/1 4/4 CS W/TEST 2. ENABLE PU AND DISABLE PD 1. SET GPIO AS INPUT S/W READ FLOW 0001 J2 DEV J2 AP J1 AP0000 BOARD_ID[2] BOARD_ID[1] BOARD_ID[0] BOARD_ID[3-0] J1 DEV BOARD_ID_3 BOARD ID DEVELOPMENT_JTAG 2-WIRE DAP SCAN DUMP JTAG_DAP PRODUCTION 3. READ 3. READ JTAG_DAP DEVELOPMENT_JTAG S/W READ FLOW JTAG I2C PULL-UPS 0010 0011 1. SET GPIO AS INPUT 1110 1101 1100 FMI0/1 4/4 CS BOOT_CONFIG[3-0] BOOT_CONFIG[3] (GPIO29) BOOT_CONFIG[0] (GPIO18) BOARD_ID[3] 2. DISABLE PU AND ENABLE PD FMI0/1 4/4 CS WITH TEST FMI0/1 2/2 CS BOOT_CONFIG[1] (GPIO25) BOOT_CONFIG[2] (GPIO28) S/W READ FLOW BOOT CONFIG ID 2. DISABLE PU AND ENABLE PD DEVELOPMENT_JTAG_TAP 1. SET GPIO AS INPUT MF 5% 01005 1/32W 10K J2 442 442 4104245 11 27 43 11 27 43 11 27 43 4 4 10 42 45 201 5% 1/20W 10K MF 5% 1/20W 10K 201 MF 1/32W MF 5% 01005 10K NOSTUFF 5% 01005 1/32W MF DEV 10K J2A 1/32W 10K MF 5% 01005 SHORT-01005NOSTUFF SHORT-01005NOSTUFF NOSTUFF SHORT-01005 100K MF 1/32W 01005 5% 01005 5% MF 1/32W 10K 1.00K 5% 1/32W MF 01005 1.00K 5% 1/32W MF 01005 1.00K 1/32W MF 01005 5%5% 01005 MF 1/32W 1.00K 5% 1/32W MF 01005 1.00K 5% 1/32W MF 1.00K 01005 NOSTUFF 201 5% MF 1/20W 10K JTAG_DAP 100 DEVELOPMENT_JTAG_TAP 1/32W 0.00 0% MF 01005 1/32W 0.00 0% MF DEVELOPMENT_JTAG_TAP 01005 100 JTAG_DAP 1/32W 0.00 0% MF DEVELOPMENT_JTAG_TAP 01005 1/20W 10K MF 201 5% 201 MF 1/20W 5% 10K NOSTUFF MF 10K 201 5% 1/20W SYNC_DATE=N/A AP: MISC & ALIASES SYNC_MASTER=ALEX =PP1V8_H4 PP3V0_SENSOR_FLT I2C0_SCL_1V8 I2C1_SDA_1V8 I2C2_SDA_3V0_ALS I2C1_SCL_1V8 AP_TESTMODE BOARD_ID_1 BOOT_CONFIG_1 BOOT_CONFIG_2 =PP1V8_H4 =PP1V8_H4 BOOT_CONFIG_0 BOOT_CONFIG_3 JTAG_AP_TRST_L AP_FAST_SCAN_CLK VIDEO_EMI_C_Y VIDEO_EMI_Y_PR VIDEO_EMI_CVBS_PB JTAG_AP_TDO JTAG_AP_TDI JTAG_AP_TRST_L AP_TST_STPCLK JTAG_AP_SEL AP_HOLD_RESET USB_AP_VBUS1 BOARD_ID_2 I2C2_SCL_3V0_ALS I2C0_SDA_1V8 BOARD_ID_0 GPIO42_BRD_REV2 GPIO41_BRD_REV1 GPIO40_BRD_REV0 R12051 2 R12021 2 R1210 1 2 R1212 1 2 R1213 1 2 R1211 1 2 R1214 1 2 R12071 2 R12081 2 R12091 2 R12011 2 R12001 2 R12031 2 R12061 2 R12041 2 XW1201 1 2 XW1200 1 2 XW1202 1 2 R1260 1 2 R1261 1 2 R07061 2 R07051 2 R07041 2 R07031 2 R07021 2 R07011 2 051-8773 10.0.0 12 OF 157 10 OF 48 471035 242645 519223742 52542 242542 52542 4 5 5 5 471035 471035 5 5 4 4 4 4 5 242542 519223742 5 5 5 5
RX_VHIGH/USB_2D+ TX_VHIGH/USB_2D- CH.3_OUT CH.2_OUT CH.1_OUT VID_EN USB_1D- USB_1D+ SEL DGNDAGND CH.1_IN CH.2_IN CH.3_IN USB_D- USB_D+ RX_VLOW TX_VLOW VA_1 VDH VA_0 VDL OUT OUT OUT OUT INOUT IN BI BI BI BI IN IN IN IN IN Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_ALT_ITEM CVBSIN BB USB <-> H4P FS USBDOCK_BB_EN = 0: DOCK_BB_EN = 1: BB USB <-> DOCK SERIAL NOTE: H4P UART0 <-> DOCK SERIAL NOTE: PLACE R0960-62 NEAR U0900 CIN YIN ~15MA THS7380IZSYR UCSP CRITICAL 10 27 43 10 27 43 75 1/20W MF 1% 201 JTAG_DAP 201 MF 1% 75 JTAG_DAP 1/20W 201 1% MF 75 JTAG_DAP 1/20W 10 27 43 6.3V 0.1UF 10% X5R 201 MF 100K 5% 1/32W 01005 27 42 27 421542 1542 3042 3042 4 42 4 42 743 743 743 01005 6.3V 5% NP0-C0G 56PF 6.3V 0.1UF 10% X5R 201 100K 5% MF 01005 1/32W 5 37 1/32W 01005 5% 1.00M MF RADAR:9009078U1300343S0539 343S0520 AP: VIDEO BUFFER,BB USB MUXES SYNC_DATE=12/10/2010SYNC_MASTER=CHOPIN =PP3V0_VIDEO_BUF BUF_C_Y USB11_ACC_RX_P =PP3V2_S2R_USBMUX BUF_Y_PR PORT_DOCK_VIDEO_AMP_EN DAC_AP_OUT1 DAC_AP_OUT3 DAC_AP_OUT2 VIDEO_EMI_CVBS_PB VIDEO_EMI_Y_PR VIDEO_EMI_C_Y USB11_MUX_D0_N DOCK_BB_EN BUF_CVBS_PB USB11_MUX_D0_P USB11_ACC_TX_N USB_BB_D_N USB_BB_D_P UART0_MUX_RXD UART0_MUX_TXD U1300 B2 B3 A3 A2 A4 A1 B4 B1 D3 E3 E1 E4 C2 D1 D4 F1 F2 F4 F3 C1 C4 E2 D2 C3 R1360 1 2 R1361 1 2 R1362 1 2 C13701 2 R13721 2 C1301 1 2 C1300 1 2 R13201 2 R13151 2 051-8773 10.0.0 13 OF 157 11 OF 48 35 43 35 43 43
TP TP TP TP TP TP TP TP TP TP IN IN IN IN IN IN IN IN IN IN IN IN IO0-1 IO7-1 IO6-1 IO3-1 IO4-1 IO5-1 IO1-1 IO2-1 IO7-0 IO5-0 IO6-0 IO4-0 IO2-0 IO3-0 IO1-0 IO0-0 VCC CLE1 CE1* CLE0 CE0* WE0* ALE0 RE0 RE0* DQS0* R/B0* DQS0 ALE1 WE1* RE1 RE1* DQS1 DQS1* R/B1* ZQ VREF VSSQVSS VCCQ VDDI TMSC TCKC BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI IN IN IN IN IN IN IN IN IN IN IN IN IO0-1 IO7-1 IO6-1 IO3-1 IO4-1 IO5-1 IO1-1 IO2-1 IO7-0 IO5-0 IO6-0 IO4-0 IO2-0 IO3-0 IO1-0 IO0-0 VCC CLE1 CE1* CLE0 CE0* WE0* ALE0 RE0 RE0* DQS0* R/B0* DQS0 ALE1 WE1* RE1 RE1* DQS1 DQS1* R/B1* ZQ VREF VSSQVSS VCCQ VDDI TMSC TCKC BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI NC NC NC NC NC NC NC NC Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT LEAVE VREF AS TP FOR MLB DO NOT PLACE IN NAND SINGLE PCS SHIELD CAN AREA TEST POINTS LEAVE VREF AS TP FOR MLB 10UF CERM-X5R 0402-1 6.3V 20% CERM 402-LF 2.2UF 6.3V 20% 0.1UF 10% 201 6.3V X5R 6 12 44 6 44 6 12 44 6 12 44 6 12 44 6 12 44 6 12 44 6 44 6 12 44 6 12 44 6 12 44 6 12 44 MF 1/20W 1% 243 201 0.1UF 10% 201 6.3V X5RCERM-X5R 0402-1 10UF 6.3V 20% 0402-1 CERM-X5R 10UF 6.3V 20% 0402-1 CERM-X5R 6.3V 20% 10UF LGA OMIT XXNM-XGBX8-MLC-PPN1.5-ODP 6.3V X5R 0201-MUR 1.0UF 20% 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 MF 1/20W 5% 1K NOSTUFF 201 1K 5% 1/20W MF NOSTUFF 201 0402-1 CERM-X5R 10UF 6.3V 20% 402-LF CERM 2.2UF 6.3V 20% 0.1UF 10% 201 6.3V X5R 0.1UF 10% 201 6.3V X5RCERM-X5R 0402-1 10UF 6.3V 20% CERM-X5R 0402-1 10UF 6.3V 20% 0402-1 CERM-X5R 10UF 6.3V 20% 6 44 6 12 44 6 12 44 6 12 44 6 12 44 6 12 44 6 44 6 12 44 6 12 44 6 12 44 6 12 44 6 12 44 OMIT XXNM-XGBX8-MLC-PPN1.5-ODP LGA MF 1/20W 1% 243 201 6.3V X5R 1.0UF 20% 0201-MUR 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 MF 1/20W 5% 1K NOSTUFF 201 1K MF 5% 1/20W NOSTUFF 201 0.22UF 6.3V X5R 0201 20% 0.22UF 6.3V X5R 0201 20% 0.22UF 6.3V X5R 0201 20% 0.22UF 6.3V X5R 20% 0201 0.22UF 6.3V X5R 0201 20% 0.22UF 6.3V X5R 0201 20% 0.22UF 6.3V X5R 0201 20% 0.22UF 6.3V X5R 0201 20% 5% 1/32W MF 01005 100K 01005 MF 1/32W 5% 100K NAND_IO_3V3 MF 1/20W 0 5% 201 MF 0 5% NAND_IO_1V8 201 1/20W 6.3V X5R 0201-MUR 20% 1.0UF 6.3V X5R 0201-MUR 1.0UF 20% SYNC_DATE=N/A NAND SYNC_MASTER=MIKE FMI0_AD<0> MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.2MM VOLTAGE=1.8V PPVCCQ_NAND =PP3V3_NAND MIN_NECK_WIDTH=0.1MM VOLTAGE=3.3V MAX_NECK_LENGTH=3MM PPVDDI_NAND_U1400 NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.2MM FMI1_AD<0> FMI0_ALE FMI0_WE_L =PP3V3_NAND VOLTAGE=3.3V MIN_LINE_WIDTH=0.2MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM MIN_NECK_WIDTH=0.1MM PPVDDI_NAND_U1410 PPVCCQ_NAND VOLTAGE=1.8V NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.2MM MAX_NECK_LENGTH=3 MM FMI1_RE_N FMI0_RE_N FMI0_AD<1> =PP1V8_NAND FMI0_AD<7> FMI1_CLE FMI0_RE_N FMI0_AD<2> FMI0_AD<1> FMI1_AD<2> FMI1_AD<1> FMI1_AD<0> FMI0_AD<7> FMI0_AD<6> FMI0_AD<5> FMI0_AD<4> FMI0_AD<0> FMI0_ALE FMI0_CLE FMI0_WE_L FMI0_CE1_L FMI0_CLE FMI0_ALE FMI0_WE_L FMI0_RE_N FMI1_CLE FMI1_ALE FMI1_WE_L FMI1_RE_N FMI1_DQS_P TP_VREF_SLOT1 FMI_ZQ_U1410 FMI_TCKC_U1400 FMI1_DQS_P FMI1_ALE FMI0_DQS_P FMI0_CE0_L FMI1_CE0_L FMI0_AD<0> FMI0_AD<3> FMI0_AD<2> FMI0_AD<4> FMI1_AD<5> FMI1_AD<4> FMI1_AD<3> FMI1_AD<6> FMI1_AD<7> FMI1_AD<1> FMI1_AD<0> FMI0_AD<5> FMI0_CLE FMI1_AD<2> FMI1_RE_N FMI1_ALE FMI1_WE_L FMI1_CLE FMI_TMSC_U1400 FMI0_AD<6> FMI1_AD<5> FMI_ZQ_U1400 TP_VREF_SLOT0 FMI1_WE_L FMI_TMSC_U1410 FMI_TCKC_U1410 FMI1_AD<7> FMI1_AD<6> FMI1_CE1_L FMI0_DQS_P NAND_SLOT1_RDYBSY_L FMI1_AD<4> FMI1_AD<3> FMI0_AD<3> NAND_SLOT0_RDYBSY_L =PP3V3_NAND TP14001 TP14011 TP14021 TP14031 TP14041 TP14051 TP14061 TP14071 TP14081 TP14091 C14321 2 C14311 2 C14301 2 R14741 2 C14241 2 C14221 2 C14211 2 C14201 2 U1410 C1 D2 A5 C5 A3 C3 H4 F4 M4 K4 G3 G1 H2 J1 J3 L1 K2 N3 L5 N5 K6 L7 J5 J7 H6 G7 E5 E7 B4 C7 D4 D6 OA0 OB0 B6 F2 M6 N1 N7 OC8 OD8 OE0 OF8 G0 OA8 OB8 G5 B2 F6 L3 A7 M2 OC0 OD0 OE8 OF0 G8 E3 E1 A1 C14701 2 R14731 2 R14721 2 C14121 2 C14111 2 C14101 2 C14041 2 C14021 2 C14011 2 C14001 2 U1400 C1 D2 A5 C5 A3 C3 H4 F4 M4 K4 G3 G1 H2 J1 J3 L1 K2 N3 L5 N5 K6 L7 J5 J7 H6 G7 E5 E7 B4 C7 D4 D6 OA0 OB0 B6 F2 M6 N1 N7 OC8 OD8 OE0 OF8 G0 OA8 OB8 G5 B2 F6 L3 A7 M2 OC0 OD0 OE8 OF0 G8 E3 E1 A1 R14541 2 C14501 2 R14531 2 R14521 2 C14131 2 C14141 2 C14341 2 C14331 2 C14061 2 C14051 2 C14261 2 C14251 2 R1455 1 2 R1475 1 2 R1401 1 2 R1400 1 2 C14511 2 C14711 2 051-8773 10.0.0 14 OF 157 12 OF 48 12 45 1235 45 61244 12 35 12 45 61244 35 61244 61244 61244 61244 61244 61244 61244 61244 1235
CK_1 DQ13_2 DQ14_2 DQ2_2 DQ1_2 DQ0_2 CKB_2 CKE_2 DQ21_1 DQ12_1 DQ11_1 DQ10_1 DQ0_1 DQ1_1 DQ2_1 DQ3_1 DQ4_1 DQ5_1 CSB_1 CKE_1 CKB_1 CA9_1 CA8_1 CA7_1 CA6_1 CA5_1 CA4_1 CA3_1 CA2_1 CA1_1 CA0_1 DQSB2_1 DQS2_1 DQ20_1 DQ19_1 DQ22_1 DQ23_1 DQ18_1 DQ16_1 DQ17_1 DQ15_1 DQ14_1 DQ13_1 DQ9_1 DQ7_1 DQ8_1 DQ6_1 DQ24_1 DQ31_1 DQ30_1 DQ31_2 DQ29_2 DQ30_2 DQ28_2 DQ26_2 DQ27_2 DQ25_2 DQ24_2 DQ23_2 DQ21_2 DQ22_2 DQ20_2 DQ19_2 DQ18_2 DQ17_2 DQ16_2 DQ15_2 DQ12_2 DQ11_2 DQ10_2 DQ8_2 DQ9_2 DQ6_2 DQ7_2 DQ5_2 DQ4_2 DQ3_2 DQSB3_2 DQS3_2 CA7_2 CA8_2 CA9_2 CK_2 DQS1_2 VREFCA_1 VREFCA_2 VREFDQ_1 VREFDQ_2 ZQ_1 ZQ_2 DQSB3_1 DQSB2_2 DQSB1_2DQSB1_1 DQSB0_2DQSB0_1 DQS3_1 DQS2_2 DQS1_1 DQS0_2DQS0_1 DQ29_1 DQ28_1 DQ27_1 DQ26_1 DQ25_1 CA6_2 CA5_2 CA4_2 CA3_2 CA2_2 CA1_2 CA0_2 DM0_1 DM1_1 DM2_1 DM3_1 CSB_2 DM0_2 DM1_2 DM2_2 DM3_2 DDR_1 DDR_2 SYM 1 OF 2 VDD1_3 VDD1_1 VSS55 VSS51 VSS6 VSS49 VSS4 VSS3 VDDQ33 VDDCA1 VDDCA2 VSS46 VDD1_0 VDD1_8 VDD1_5 VDD1_6 VDD1_7 VSS52 VSS0 VSS2 VSS7 VSS9 VSS10 VSS13 VSS18 VSS20 VSS32 VSS33 VSS34 VSS42 VSS43 VSS44 VSS29 VSS28 VSS27 VSS26 VSS25 VSS23 VSS22 VSS47 VSS53 VSS48 VSS50 VSS1 VSS12 VDD1_11 VDD2_3 VDD2_2 VDD1_2 VDD2_6 VDD2_7 VDD2_13 VDD2_14 VDD2_16 VDDQ27 VDDQ32 VDDQ31 VDDQ VDDQ6 VDDQ23 VDDQ30 VDDQ22 VDDQ16 VDDQ34 VDDQ17 VDDQ21 VDDQ19 VDDQ24 VDDQ20 VDDQ28 VDDCA3 VDDCA4 VDDCA5 VDDCA6 VDDCA7 VDDCA8 VDD2_1 VDDQ26 VDDQ25 VSS24 VDD2_9 VDD2_8 VDDQ1 VDD1_9 VDD1_10 VDDCA9 VDDCA10 VDDQ29 VDDQ3 VDD1_4 VDD2_5 VDD2_4 VDD2_15 VSS41 VSS40 VSS39 VSS54 VSS36 VSS35 VDD2_10 VDD2_11 VDD2_12 VSS45 VDD2VDDQVDDCAVDD1 VSS SYM 2 OF 2 Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% XXXMB BGA H4G-DRAM OMIT XXXMB H4G-DRAM BGA OMIT 4.3UF 4V X5R-CERM 0610 20% 603 10UF 6.3V X5R 20% 56PF NP0-C0G 01005 5% 6.3V 6.3V X5R 0201 0.22UF 20% 56PF NP0-C0G 01005 5% 6.3V 0.01UF 10% 01005 6.3V X5R 6.3V X5R 0201 0.22UF 20% 10V 10% 0.01UF X5R 201 01005 0.01UF 10% 6.3V X5R 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 1UF 10% CERM 402 6.3V 10% CERM 1UF 402 6.3V CERM 10% 1UF 402 6.3V 402 10% CERM 1UF 6.3V X5R-CERM 4V 0610 4.3UF 20% 10UF 603 6.3V X5R 20% 603 10UF 6.3V X5R 20% NP0-C0G 01005 56PF 5% 6.3V6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20%6.3V X5R 0201 0.22UF 20% 10% 01005 0.01UF 6.3V X5R 5% 56PF 01005 NP0-C0G 6.3V 0.01UF 01005 10% 6.3V X5R 6.3V X5R 0201 0.22UF 20% 10% 402 CERM 1UF 6.3V 6.3V X5R 0201 0.22UF 20% 10% 402 CERM 1UF 6.3V 6.3V X5R 0201 0.22UF 20% 603 10UF 6.3V X5R 20% MF 1/20W 1% 240 201 MF 1/20W 1% 240 201 2.21K 1% 1/32W MF 01005 NOSTUFF 10% 01005 0.01UF 6.3V X5R 01005 MF 2.21K 1% 1/32W 01005 MF 1% 1/32W 2.21K NOSTUFF 10% 01005 0.01UF 6.3V X5R 01005 2.21K 1% MF 1/32W 01005 MF 1% 1.00K 1/32W NOSTUFF 10% 01005 0.01UF 6.3V X5R 01005 1% 1/32W 1.00K MF 01005 1/32W MF 1% 1.00K NOSTUFF 0.01UF 10% 01005 6.3V X5R 0.01UF 10% 01005 6.3V X5R 01005 1.00K MF 1% 1/32W NOSTUFF 0.01UF 01005 10% 6.3V X5R 0.01UF 01005 10% NOSTUFF 6.3V X5R 0.01UF 01005 10% NOSTUFF 6.3V X5R 0.01UF 01005 10% NOSTUFF 6.3V X5R 6.3V X5R 0201 0.22UF 20% SYNC_MASTER=MIKE DDR 0 AND 1 SYNC_DATE=06/21/2010 PPVREF_DDR0_CA NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM PPVREF_DDR0_CA MAX_NECK_LENGTH=3 MM VOLTAGE=0.6V PPVREF_DDR0_DQ NET_SPACING_TYPE=PWR PPVREF_DDR0_DQ VOLTAGE=0.6V MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM MAX_NECK_LENGTH=3 MM PPVREF_DDR1_CA NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.3MM VOLTAGE=0.6V MIN_NECK_WIDTH=0.2MM PPVREF_DDR1_CA PPVREF_DDR1_DQ NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0.6V PPVREF_DDR1_DQ DDR1_DM<3> DDR1_DM<1> DDR0_DQ<8> =PP1V2_VDDQ_DDR DDR0_DQ<30> DDR0_DQ<27> DDR1_DQ<5> DDR0_DQ<1> DDR0_DQ<2> DDR0_DQ<3> DDR0_DQ<4> DDR0_DQ<5> DDR0_DQ<6> DDR0_DQ<10> DDR0_DQ<13> DDR0_DQ<24> DDR0_DQ<25> DDR0_DQ<26> DDR0_DQ<28> DDR0_DQ<12> DDR0_DQ<11> DDR0_DQ<0> DDR0_DM<2> DDR0_DM<3> DDR0_DM<0> DDR0_DQ<7> DDR0_DQS_N<2> =PP1V2_S2R_DDR DDR1_DQ<30> DDR1_DQ<26> DDR0_DQ<18> DDR1_DQ<25> DDR0_DQ<14> DDR0_DQ<9> DDR0_DQ<15> DDR1_DQ<7> DDR1_DQ<6> DDR1_DQ<4> DDR1_DQ<3> DDR1_DQ<2> DDR1_DQ<1> DDR1_DQ<0> DDR1_DQ<8> DDR1_DQ<9> DDR1_DQ<10> DDR1_DQ<11> DDR1_DQ<12> DDR1_DQ<14> DDR1_DQ<15> DDR1_DQ<13> DDR0_DQS_P<3> =PP1V2_S2R_DDR =PP1V8_S2R_DDR DDR1_DQS_P<0> DDR1_DQS_N<1> =PP1V2_VDDQ_DDR =PP1V2_VDDQ_DDR =PP1V2_S2R_DDR =PP1V2_S2R_DDR DDR0_CSN<0> DDR1_DM<2> DDR1_DM<0> DDR0_CA<0> DDR0_CA<1> DDR0_CA<2> DDR0_CA<3> DDR0_CA<4> DDR0_CA<5> DDR0_CA<6> DDR1_DQ<17> DDR1_DQ<18> DDR1_DQ<19> DDR1_DQ<20> DDR1_DQ<21> DDR1_DQS_P<1> DDR1_DQS_P<2> DDR1_DQS_N<0> DDR0_DQS_N<1> DDR0_DQS_N<3> DDR1_DQS_N<2> DDR0_ZQDDR1_ZQ DDR0_CK_P DDR0_CA<9> DDR0_CA<8> DDR0_CA<7> DDR0_DQS_P<2> DDR0_DQ<29> DDR0_DQ<31> DDR0_DQ<23> DDR1_DQ<22> DDR1_DQ<23> DDR1_DQ<16> DDR1_DQ<24> DDR1_DQ<31> DDR1_DQ<27> DDR1_DQ<28> DDR1_DQS_P<3> DDR1_DQS_N<3> DDR1_CA<0> DDR1_CA<1> DDR1_CA<4> DDR1_CA<5> DDR1_CA<6> DDR1_CA<7> DDR1_CA<8> DDR1_CA<9> DDR1_CK_N DDR1_CKE<0> DDR1_CSN<0> DDR1_DQ<29> DDR0_CKE<0> DDR0_CK_N DDR1_CK_P DDR0_DM<1> DDR1_CA<3> DDR1_CA<2> DDR0_DQ<16> DDR0_DQ<22> DDR0_DQ<19> DDR0_DQ<20> DDR0_DQ<17> DDR0_DQS_P<1> DDR0_DQS_N<0> DDR0_DQS_P<0> DDR0_DQ<21> C1622 1 2 C1621 1 2 C1620 1 2 C16231 2 C16131 2 C1619 1 2 C1605 1 2 C1612 1 2 C1618 1 2 C1604 1 2 C1611 1 2 C1610 1 2 C16171 2 C1603 1 2 C1616 1 2 C1602 1 2 C1615 1 2 C1601 1 2 C1614 1 2 C1609 1 2 C16081 2 C16071 2 C1606 1 2 C1631 1 2 C1635 1 2 C1630 1 2 C16341 2 C1629 1 2 C16331 2 C1628 1 2 C1632 1 2 C1627 1 2 R16201 2 R16211 2 R16051 2 C16501 2 R16061 2 R16511 2 C16521 2 R16521 2 R16531 2 C16541 2 R16541 2 R16551 2 C16561 2 R16561 2 C16601 2 C16621 2 C16631 2 C16611 2 C1626 1 2 C1625 1 2 C16241 2 U1600 T15 G16 U15 G17 U14 H17 V14 H18 T13 J16 T9 N16 U9 N17 U8 P17 V8 P18 T7 R16 U12 K17 U11 L17 V13 J18 U13 J17 C12 K3 B10 M2 B16 G4 D7 T2 C15 G3 B8 P5 C8 P4 D8 P3 E8 P2 B7 R4 C7 R3 B18 B2 C18 C2 D18 D3 E18 D2 D15 G2 B17 E4 D17 E3 E17 E2 E16 F2 B6 T5 B5 U5 C5 U4 D5 U2 B4 V5 C4 V4 B14 H5 B3 V3 C3 V2 C14 H4 D14 H3 E14 H2 B13 J3 C13 J2 C9 N4 D9 N3 D13 J4 D10 M4 C16 F4 D6 T3 D12 K4 C10 M3 D16 F3 C6 T4 U10 M17 D11 L4 U7 R17 U1600 A2 B1 W17 U19 B11 F17 L2 M16 T10 U18 V17 V6 E11 W5 W16 W19 W18 V19 A3 T19 E19 L5 M18 U17 T18 V10 V16 V18 F18 T8 H16 K16 L16 P16 T11 T12 T14 V7 E1 U1 J5 K2 N2 R5 A8 A10 A14 A13 C17 C19 H1 E10 E15 B12 U3 W3 M1 P1 A17 D4 A16 A1 D19 E12 E13 F16 A4 G18 J1 K18 K5 L18 L3 M5 N18 N5 A6 R18 R2 T1 T17 U16 U6 B15 V11 V12 V15 T6 V9 W1 W4 A18 B19 C1 E7 G5 T16 V1 W2 A19 B9 C11 D1 051-8773 10.0.0 16 OF 157 13 OF 48 13 44 45 13 44 45 13 44 45 13 44 45 134445 13 44 45 134445 13 44 45 844 844 8 44 131435 8 44 8 44 844 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 40 44 8 44 8 44 8 44 8 44 8 44 131435 844 844 8 44 844 8 40 44 8 44 8 44 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 8 44 131435 1435 844 844 131435 131435 131435 131435 8 44 844 844 8 44 8 44 8 44 8 44 8 44 8 44 8 44 844 844 844 844 844 844 844 844 8 40 44 8 44 844 4444 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 8 44 8 44 844 8 44 844 844 8 44 8 44 8 44 8 44 8 44 8 44 8 40 44 8 40 44 8 44
CK_1 DQ13_2 DQ14_2 DQ2_2 DQ1_2 DQ0_2 CKB_2 CKE_2 DQ21_1 DQ12_1 DQ11_1 DQ10_1 DQ0_1 DQ1_1 DQ2_1 DQ3_1 DQ4_1 DQ5_1 CSB_1 CKE_1 CKB_1 CA9_1 CA8_1 CA7_1 CA6_1 CA5_1 CA4_1 CA3_1 CA2_1 CA1_1 CA0_1 DQSB2_1 DQS2_1 DQ20_1 DQ19_1 DQ22_1 DQ23_1 DQ18_1 DQ16_1 DQ17_1 DQ15_1 DQ14_1 DQ13_1 DQ9_1 DQ7_1 DQ8_1 DQ6_1 DQ24_1 DQ31_1 DQ30_1 DQ31_2 DQ29_2 DQ30_2 DQ28_2 DQ26_2 DQ27_2 DQ25_2 DQ24_2 DQ23_2 DQ21_2 DQ22_2 DQ20_2 DQ19_2 DQ18_2 DQ17_2 DQ16_2 DQ15_2 DQ12_2 DQ11_2 DQ10_2 DQ8_2 DQ9_2 DQ6_2 DQ7_2 DQ5_2 DQ4_2 DQ3_2 DQSB3_2 DQS3_2 CA7_2 CA8_2 CA9_2 CK_2 DQS1_2 VREFCA_1 VREFCA_2 VREFDQ_1 VREFDQ_2 ZQ_1 ZQ_2 DQSB3_1 DQSB2_2 DQSB1_2DQSB1_1 DQSB0_2DQSB0_1 DQS3_1 DQS2_2 DQS1_1 DQS0_2DQS0_1 DQ29_1 DQ28_1 DQ27_1 DQ26_1 DQ25_1 CA6_2 CA5_2 CA4_2 CA3_2 CA2_2 CA1_2 CA0_2 DM0_1 DM1_1 DM2_1 DM3_1 CSB_2 DM0_2 DM1_2 DM2_2 DM3_2 DDR_1 DDR_2 SYM 1 OF 2 VDD1_3 VDD1_1 VSS55 VSS51 VSS6 VSS49 VSS4 VSS3 VDDQ33 VDDCA1 VDDCA2 VSS46 VDD1_0 VDD1_8 VDD1_5 VDD1_6 VDD1_7 VSS52 VSS0 VSS2 VSS7 VSS9 VSS10 VSS13 VSS18 VSS20 VSS32 VSS33 VSS34 VSS42 VSS43 VSS44 VSS29 VSS28 VSS27 VSS26 VSS25 VSS23 VSS22 VSS47 VSS53 VSS48 VSS50 VSS1 VSS12 VDD1_11 VDD2_3 VDD2_2 VDD1_2 VDD2_6 VDD2_7 VDD2_13 VDD2_14 VDD2_16 VDDQ27 VDDQ32 VDDQ31 VDDQ VDDQ6 VDDQ23 VDDQ30 VDDQ22 VDDQ16 VDDQ34 VDDQ17 VDDQ21 VDDQ19 VDDQ24 VDDQ20 VDDQ28 VDDCA3 VDDCA4 VDDCA5 VDDCA6 VDDCA7 VDDCA8 VDD2_1 VDDQ26 VDDQ25 VSS24 VDD2_9 VDD2_8 VDDQ1 VDD1_9 VDD1_10 VDDCA9 VDDCA10 VDDQ29 VDDQ3 VDD1_4 VDD2_5 VDD2_4 VDD2_15 VSS41 VSS40 VSS39 VSS54 VSS36 VSS35 VDD2_10 VDD2_11 VDD2_12 VSS45 VDD2VDDQVDDCAVDD1 VSS SYM 2 OF 2 Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT 20% 0.22UF 0201 X5R 6.3V 20% X5R 6.3V 603 10UF 20% 0.22UF 0201 X5R 6.3V 6.3V NP0-C0G 56PF 5% 01005 X5R 6.3V 0.01UF 01005 10% 6.3V NP0-C0G 5% 56PF 01005 X5R 6.3V 01005 10% 0.01UF 6.3V 01005 5% NP0-C0G 56PF 20% 0.22UF 0201 X5R 6.3V 201 X5R 0.01UF 10% 10V 20% 0.22UF 0201 X5R 6.3V X5R 6.3V 01005 10% 0.01UF 6.3V CERM 1UF 10% 402 20% 0.22UF 0201 X5R 6.3V 20% 0610 4V 4.3UF X5R-CERM 6.3V 1UF 10% CERM 402 20% X5R-CERM 4.3UF 4V 0610 6.3V 01005 5% 56PF NP0-C0G X5R 6.3V 0.01UF 01005 10% 6.3V 1UF 10% 402 CERM 6.3V 1UF CERM 10% 402 20% X5R 6.3V 10UF 603 20% X5R 6.3V 10UF 603 X5R 6.3V 01005 10% 0.01UF 20% X5R 6.3V 10UF 603 20% 0.22UF 0201 X5R 6.3V20% 0.22UF 0201 X5R 6.3V 20% 0.22UF 0201 X5R 6.3V 201 240 1% 1/20W MF 201 MF 1/20W 1% 240 20% 0.22UF 0201 X5R 6.3V X5R 6.3V NOSTUFF 0.01UF 01005 10% 2.21K 01005 1/32W MF 1% 01005 MF 2.21K 1% 1/32W X5R 6.3V NOSTUFF 10% 01005 0.01UF 01005 MF 2.21K 1% 1/32W 2.21K 01005 1% 1/32W MF 1.00K 01005 MF 1% 1/32W 6.3V 10% 402 CERM 1UF X5R 6.3V NOSTUFF 10% 01005 0.01UF1.00K 01005 1% 1/32W MF 01005 1/32W MF 1% 1.00K X5R 6.3V NOSTUFF 0.01UF 10% 0100501005 1.00K MF 1% 1/32W 20% 0.22UF 0201 X5R 6.3V X5R 6.3V NOSTUFF 0.01UF 01005 10% X5R 6.3V NOSTUFF 0.01UF 01005 10% X5R 6.3V 0.01UF 01005 10% NOSTUFF X5R 6.3V NOSTUFF 10% 01005 0.01UF 20% 0.22UF 0201 X5R 6.3V 20% 0.22UF 0201 X5R 6.3V 20% 0.22UF 0201 X5R 6.3V 6.3V 1UF CERM 10% 402 BGA XXXMB H4G-DRAM OMIT BGA H4G-DRAM XXXMB OMIT DDR 2 AND 3 SYNC_DATE=06/21/2010SYNC_MASTER=MIKE NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.3MM PPVREF_DDR2_CA MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0.6V PPVREF_DDR2_CA PPVREF_DDR2_DQ NET_SPACING_TYPE=PWR PPVREF_DDR2_DQ MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0.6V MAX_NECK_LENGTH=3 MM PPVREF_DDR3_CA NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM PPVREF_DDR3_CA VOLTAGE=0.6V PPVREF_DDR3_DQ NET_SPACING_TYPE=PWR PPVREF_DDR3_DQ MIN_LINE_WIDTH=0.3MM VOLTAGE=0.6V MIN_NECK_WIDTH=0.2MM MAX_NECK_LENGTH=3 MM DDR3_DM<2> DDR3_DM<3> DDR3_DM<1> DDR3_DM<0> =PP1V2_S2R_DDR DDR2_DQS_P<1> DDR3_DQ<14> DDR3_DQ<11> DDR3_CSN<0> DDR2_DQ<7> DDR2_DQ<6> DDR2_DQ<4> DDR2_DQ<2> DDR2_DQ<0> DDR2_DQ<1> DDR2_DQ<10> DDR2_DQ<15> DDR2_DQ<8> DDR2_DQ<14> DDR2_DQ<9> DDR2_DQ<13> DDR2_DQ<12> DDR2_DQ<11> DDR3_DQ<4> DDR3_DQ<3> DDR3_DQ<2> DDR3_DQ<7> DDR3_DQ<6> DDR3_DQ<5> DDR3_DQ<1> DDR3_DQ<0> DDR3_DQ<8> DDR3_DQ<9> DDR3_DQ<10> DDR3_DQ<12> DDR3_DQ<13> DDR3_DQ<15> =PP1V2_VDDQ_DDR =PP1V2_VDDQ_DDR =PP1V2_S2R_DDR DDR2_DM<2> DDR2_DM<1> DDR2_DM<0> DDR2_CSN<0> DDR2_CA<0> DDR2_CA<1> DDR2_CA<2> DDR2_CA<3> DDR2_CA<4> DDR2_CA<5> DDR2_CA<6> DDR3_DQ<17> DDR3_DQ<18> DDR3_DQ<19> DDR3_DQ<20> DDR3_DQ<21> DDR3_DQS_P<0> DDR2_DQS_P<0> DDR3_DQS_P<1> DDR2_DQS_P<3> DDR3_DQS_P<2> DDR3_DQS_N<0> DDR2_DQS_N<0> DDR3_DQS_N<1> DDR2_DQS_N<1> DDR2_DQS_N<3> DDR3_DQS_N<2> DDR2_ZQDDR3_ZQ DDR2_CK_P DDR2_CA<9> DDR2_CA<8> DDR2_CA<7> DDR2_DQS_P<2> DDR2_DQS_N<2> DDR2_DQ<24> DDR2_DQ<25> DDR2_DQ<26> DDR2_DQ<27> DDR2_DQ<30> DDR2_DQ<28> DDR2_DQ<29> DDR2_DQ<31> DDR2_DQ<16> DDR2_DQ<20> DDR2_DQ<19> DDR2_DQ<18> DDR2_DQ<23> DDR2_DQ<22> DDR2_DQ<21> DDR2_DQ<17> DDR3_DQ<22> DDR3_DQ<23> DDR3_DQ<16> DDR3_DQ<25> DDR3_DQ<24> DDR3_DQ<26> DDR3_DQ<31> DDR3_DQ<30> DDR3_DQ<27> DDR3_DQ<28> DDR3_DQS_P<3> DDR3_DQS_N<3> DDR3_CA<0> DDR3_CA<1> DDR3_CA<2> DDR3_CA<3> DDR3_CA<4> DDR3_CA<5> DDR3_CA<6> DDR3_CA<7> DDR3_CA<9> DDR3_CK_N DDR3_CKE<0> DDR3_DQ<29> DDR2_CKE<0> DDR2_CK_N DDR3_CK_P =PP1V2_S2R_DDR =PP1V2_S2R_DDR =PP1V8_S2R_DDR DDR2_DM<3> DDR3_CA<8> DDR2_DQ<3> DDR2_DQ<5> =PP1V2_VDDQ_DDR C17231 2 C1705 1 2 C1709 1 2 C1704 1 2 C17081 2 C1703 1 2 C17071 2 C1702 1 2 C1706 1 2 C1701 1 2 C17131 2 C1719 1 2 C1722 1 2 C1731 1 2 C1735 1 2 C1712 1 2 C1718 1 2 C1711 1 2 C17171 2 C1710 1 2 C1715 1 2 C1716 1 2 C1721 1 2 C1730 1 2 C1729 1 2 C1728 1 2 C1714 1 2 C1720 1 2 C1727 1 2 C17341 2 C17331 2 C1732 1 2 R17201 2 R17211 2 C17501 2 R17051 2 R17061 2 C17521 2 R17511 2 R17521 2 R17531 2 C17541 2 R17541 2 R17551 2 C17561 2 R17561 2 C17601 2 C17611 2 C17621 2 C17631 2 C1726 1 2 C1725 1 2 C17241 2 U1700 T15 G16 U15 G17 U14 H17 V14 H18 T13 J16 T9 N16 U9 N17 U8 P17 V8 P18 T7 R16 U12 K17 U11 L17 V13 J18 U13 J17 C12 K3 B10 M2 B16 G4 D7 T2 C15 G3 B8 P5 C8 P4 D8 P3 E8 P2 B7 R4 C7 R3 B18 B2 C18 C2 D18 D3 E18 D2 D15 G2 B17 E4 D17 E3 E17 E2 E16 F2 B6 T5 B5 U5 C5 U4 D5 U2 B4 V5 C4 V4 B14 H5 B3 V3 C3 V2 C14 H4 D14 H3 E14 H2 B13 J3 C13 J2 C9 N4 D9 N3 D13 J4 D10 M4 C16 F4 D6 T3 D12 K4 C10 M3 D16 F3 C6 T4 U10 M17 D11 L4 U7 R17 U1700 A2 B1 W17 U19 B11 F17 L2 M16 T10 U18 V17 V6 E11 W5 W16 W19 W18 V19 A3 T19 E19 L5 M18 U17 T18 V10 V16 V18 F18 T8 H16 K16 L16 P16 T11 T12 T14 V7 E1 U1 J5 K2 N2 R5 A8 A10 A14 A13 C17 C19 H1 E10 E15 B12 U3 W3 M1 P1 A17 D4 A16 A1 D19 E12 E13 F16 A4 G18 J1 K18 K5 L18 L3 M5 N18 N5 A6 R18 R2 T1 T17 U16 U6 B15 V11 V12 V15 T6 V9 W1 W4 A18 B19 C1 E7 G5 T16 V1 W2 A19 B9 C11 D1 051-8773 10.0.0 17 OF 157 14 OF 48 14 45 14 45 14 45 14 45 1445 14 45 1445 14 45 844 844 844 844 131435 8 44 844 844 844 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 844 844 844 844 844 844 844 844 844 844 844 844 844 844 131435 131435 131435 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 844 844 844 844 844 844 8 44 844 8 44 844 844 8 44 844 8 44 8 44 844 4444 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 8 44 8 44 844 131435 131435 1335 8 44 844 8 44 8 44 131435
Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT NEED TO DOUBLE CHECK IF WE NEED THIS IN IPAD, OR IF THIS MIGHT BE A PHONE SPECIFIC ISSUE WIFI ALIASES UART ALIASES OBSOLETE ALIASES SYNC_MASTER=ALEX SYNC_DATE=09/30/2010 MLB ALIASES/CONNECTIONS EXT_PWM_REQ UART0_MUX_TXD UART0_MUX_RXDUART0_AP_RXD MAKE_BASE=TRUE UART0_AP_TXD MAKE_BASE=TRUE WLAN_GPIO4MAKE_BASE=TRUEUART6_WLAN_RXD MAKE_BASE=TRUEUART6_WLAN_TXD HSIC_STROBE_4330 WLAN_ENABLE WLAN_GPIO0 I2S2_VSP_LRCK MAKE_BASE=TRUE BT_PCM_SYNC WLAN_GPIO3 I2S2_VSP_DIN MAKE_BASE=TRUE BT_PCM_DOUT I2S2_VSP_DOUT MAKE_BASE=TRUE BT_PCM_DIN UART3_BT_CTS_L MAKE_BASE=TRUE BT_UART_RTS_N CLK_32K_WLAN MAKE_BASE=TRUE CLK32K I2S2_VSP_BCLK MAKE_BASE=TRUE BT_PCM_CLK UART3_BT_RTS_L MAKE_BASE=TRUE BT_UART_CTS_N UART3_BT_TXD MAKE_BASE=TRUE BT_UART_RXD PM_BT_HOST_WAKE MAKE_BASE=TRUE BT_HOST_WAKE MAKE_BASE=TRUEPM_BT_WAKE BT_WAKE UART3_BT_RXD MAKE_BASE=TRUE BT_UART_TXD MAKE_BASE=TRUERST_BT_L BT_RESET_N RST_WLAN_L MAKE_BASE=TRUE MAKE_BASE=TRUEPM_WLAN_HOST_WAKE MAKE_BASE=TRUEHSIC_HOST_READY_WLAN WLAN_GPIO1 MAKE_BASE=TRUEHSIC1_WLAN_DATA1 HSIC_DATA_4330 MAKE_BASE=TRUEHSIC1_WLAN_STB1 MAKE_BASE=TRUEHSIC_WLAN_RDY HSIC_DEVICE_READY MAKE_BASE=TRUENC_EXT_SMPS_REQ MAKE_BASE=TRUENC_EXT_PWM_REQ MAKE_BASE=TRUENC_BT_GPIO5 EXT_SMPS_REQ BT_GPIO5 MAKE_BASE=TRUETP_WLAN_GPIO5 MAKE_BASE=TRUEGSM_TXBURST_IND LED_DRIVE_GSMB WLAN_GPIO5 051-8773 10.0.0 21 OF 157 15 OF 48 11 42 11 42542 542 31 33542 542 31 33 31 33 31 33 51942 31 31 33 51942 31 51942 31 542 31 33 3742 32 33 51942 31 542 31 33 542 31 33 37 31 33 5 31 33 542 31 33 3745 31 33 3745 37 542 31 33 44042 31 33 44042 542 31 31 53045 31
S D G D S G IN IN IN SYM_VER-2 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN SYM_VER-2 SYM_VER-2 SYM_VER-2 SYM_VER-2 OUT NC NC NC NC NC NC NC NC NC TABLE_ALT_ITEM TABLE_ALT_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT EDP CONNECTORIMAX CHANNEL VGS MAX +/- 8V MOSFET RDS(ON) 3 A SIA413DJ P-TYPE SIA413DJ 518S0827 100MOHM @-1.5V CRITICAL FERR-120-OHM-1.5A 0402B 6.3V X5R 0.1UF 201 10% 1/20W 100K MF 1% 201 2N7002TXG SOT-523-3 SIA413DJ SC70-6L CRITICAL 10% X5R 0201 0.015UF 6.3V 39K MF 1% 1/20W 201 NOSTUFF 201 MF 1/20W 1% 10K 201 10K MF 1% 1/20W NOSTUFF 201 MF 1/20W 1% 21.5K 10% 50V 402 CERM 820PF CERM 100PF 5% 402 50V 0201 82PF 25V CERM 5% CERM 5% 82PF 0201 25V 25V CERM 5% 0201 82PF FERR-240-OHM-25%-300MA 0402 CRITICAL 6 743 743 TCM0605-1 90-OHM-50MA 1/20W MF 5% 201 0 0201 82PF 25V 5% CERM 201 1000PF 16V 10% X7R 10%6.3V X5R201 0.1UF 0.1UF 201 6.3V 10% X5R 201 X5R10%6.3V 0.1UF 743 201 X5R6.3V 0.1UF 10% 743 201 6.3V X5R10% 0.1UF 743 X5R10%6.3V 0.1UF 201 743 6.3V 10% X5R 0.1UF 201 743 0.1UF 10%201 X5R6.3V 743 MF 01005 1% 100K 1/32W 1% 1/32W 100K MF 01005 0.1UF X5R201 10%6.3V 6.3V 0.1UF 201 10% X5R 743 743 10% 50V 402 CERM 820PF 5% CERM 100PF 402 50V 0402 CRITICAL FERR-240-OHM-25%-300MA 3743 3743 3743 3743 3743 3743 37 43 37 43 37 43 37 43 37 43 37 43 TCM0806-4SM 12-OHM-100MA-8.5GHZ 12-OHM-100MA-8.5GHZ TCM0806-4SM 12-OHM-100MA-8.5GHZ TCM0806-4SM 12-OHM-100MA-8.5GHZ TCM0806-4SM 402 6.3V CERM 1UF 10% 1% 100K MF 01005 1/32W 502250-8051 F-RT-SM CRITICAL 7 43 01005 1.00M 01005 1.00M 01005 1.00M 01005 1.00M 01005 1.00M 01005 1.00M 1.00M 01005 1.00M 01005 47K MF 1/20W 5% 201 L2242,L5500,L5501,L5600,L5601,L5620 155S0667 VIDEO: EDP CONNECTOR SYNC_DATE=01/19/2011SYNC_MASTER=JOE 376S0903 376S0796 PP3V3_LCDVDD_SW_FMIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.30 MM VOLTAGE=3.3V PP3V3_S0_LCD_FERR VOLTAGE=3.3V MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM =PP3V3_LCD =PP3V3_LCD EDP_AUX_CONN_N EDP_DATA_CONN_N<2> EDP_DATA_CONN_P<3> LED_IO_6_B EDP_AUX_CONN_P EDP_DATA_CONN_P<0> PPLED_BACK_REG_B NET_SPACING_TYPE=PWR VOLTAGE=20.4V MIN_LINE_WIDTH=0.6 MM MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.2 MM EDP_DATA_CONN_N<3> LED_IO_2_B LED_IO_5_A LED_IO_3_A EDP_DATA_CONN_P<3> EDP_DATA_CONN_N<3> EDP_DATA_CONN_P<2> EDP_DATA_CONN_N<2> EDP_DATA_CONN_P<1> EDP_DATA_CONN_N<1> EDP_DATA_CONN_N<0> EDP_DATA_CONN_P<0> EDP_DATA_CONN_P<3> EDP_DATA_CONN_P<1> EDP_DATA_CONN_N<1> EDP_DATA_CONN_P<2> EDP_DATA_CONN_N<3> EDP_DATA_CONN_N<0> EDP_DATA_CONN_P<0> EDP_DATA_CONN_N<2> =PPLED_REG_A =PPLED_REG_B PPLED_BACK_REG_A MIN_LINE_WIDTH=0.6 MM VOLTAGE=20.4V MIN_NECK_WIDTH=0.2 MM MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR EDP_DATA_CONN_P<1> EDP_DATA_CONN_N<1> EDP_EMI_TX_N<1> EDP_EMI_TX_P<1> EDP_AUX_CONN_N EDP_EMI_AUX_P EDP_AP_HPD EDP_AUX_CONN_PEDP_AP_AUX_P EDP_AP_AUX_N EDP_EMI_AUX_N EDP_AP_TX_P<3> EDP_AP_TX_N<3> EDP_AP_TX_P<2> EDP_AP_TX_N<2> EDP_AP_TX_P<1> EDP_AP_TX_N<1> EDP_AP_TX_N<0> EDP_AP_TX_P<0> PP3V3_S0_LCD_FERR LCDVDD_PWREN_L_R LED_IO_4_B LED_IO_3_B EDP_DATA_CONN_P<2> LED_IO_1_B LED_IO_6_A LED_IO_5_B LED_IO_1_A EDP_DATA_CONN_N<0> LED_IO_4_A LED_IO_2_A PM_LCDVDD_PWREN LCDVDD_PWREN_L EDP_EMI_TX_N<0> EDP_EMI_TX_N<2> EDP_EMI_TX_N<3> EDP_EMI_TX_P<3> EDP_EMI_TX_P<2> EDP_EMI_TX_P<0> R2250_1 Q2200 155S0583 RADAR:8616060, RADAR: 9015335 RADAR:8379470 L2201 1 2 C22031 2 R22051 2 Q2201 3 1 2 Q2200 1 3 47 C2204 1 2 R22031 2 R22101 2 R22111 2 R2204 1 2 C22201 2 C22331 2 C22411 2 C22401 2 C22301 2 L2200 1 2 L2242 1 2 3 4 R2250 1 2 C22321 2 C22061 2 C22501 2 C22511 2 C22421 2 C22431 2 C22441 2 C22451 2 C22461 2 C22471 2 R22401 2 R22411 2 C22481 2 C22491 2 C22701 2 C22531 2 L2210 1 2 L2202 1 2 3 4 L2232 1 2 3 4 L2222 1 2 3 4 L2212 1 2 3 4 C22021 2 R22421 2 J2200 1 10 11 12 13 14 15 16 17 18 19 2 20 21 22 23 24 25 26 27 28 29 3 30 31 32 33 34 35 36 37 38 39 4 40 41 42 43 44 45 46 47 48 49 5 50 51 52 53 54 55 6 7 8 9 R2280 1 2 R2281 1 2 R2282 1 2 R2283 1 2 R2284 1 2 R2285 1 2 R2286 1 2 R2287 1 2 R22901 2 051-8773 10.0.0 22 OF 157 16 OF 48 45 1645 1635 1635 16 43 16 43 16 43 1643 16 43 45 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 35 35 45 16 43 16 43 43 43 16 43 43 16 43 43 1645 16 43 16 43 43 43 43 43 43 43
CTRL PGND THRML L VIN DO FB SW PAD GND VCCA 1B1 1B2 2A2 1A1 2A1 1A2 2DIR 2OE* 1DIR 1OE* 2B2 2B1 GND VCCB VSTM26 VSTM25 VSTM24 VSTM23 MUX19 MUX17 BON_L0 BON_L1 BON_L2 BON_L3 BON_L4 BON_L5 MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 MUX8 MUX9 MUX10 MUX11 MUX12 MUX13 MUX16 MUX15 MUX18 MUX20 MUX21 MUX22 MUX23 NC VSTM1 VSTM0 VSTM6 VSTM5 VSTM4 VSTM3 VSTM2 VSTM8 VSTM11 VSTM10 VSTM7 VSTM16 VSTM15 VSTM14 VSTM13 VSTM12 VSTM21 VSTM20 VSTM19 VSTM18 VSTM17 VSTM22 VSTM27 VSTM31 VSTM30 VSTM29 VSTM28 VSTM32 VSTM36 VSTM35 VSTM34 VSTM33 VSTM37 VSTM42 VSTM41 VSTM40 VSTM39 VSTM38 VSTM47 VSTM45 VSTM44 VSTM43 A_AD_R2 A_AD_R1 A_AD_R0 MUX14 VSTM46 GND VSTM9 VDDH VCC_DIG VCC OE A NC Y GND NC OE* IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT IN IN IN IN OUT OUT IN OUT OUT OUT OUT OUT NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT TABLE_5_ITEM CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD P/N 518S0828 (A -> B) LOAD CURRENT ~ 153UA MATES WITH RIGHTMOST GRAPE FLEX TAIL APN:311S0485 TO Z2 TO Z1/Z2 MATES WITH LEFTMOST GRAPE FLEX TAIL MIN_NECK_MIDTH SHOULD BE 0.4MMBOOST CONVERTOR CONNECTORS TO GRAPE FLEX 10% X5R 25V 603-1 1UF VLF 4.7UH-700MA-280MOHM CRITICAL TPS61045 QFN-1 CRITICAL SM 10% X5R 201 6.3V 0.1UF0.1UF 6.3V X5R 10% 201 10K MF 1/20W 5% 201 1/20W 5% MF 201 10K 3.3K 5% 201 1/20W MF MF 1/20W 201 10K 5% 0.1UF 10% X5R 201 6.3V 0.1UF 6.3V X5R 201 10% 201 10K MF 1/20W 5% CRITICAL SN74AVCH4T245RSV PQFP1 10% 25V X5R 402 0.1UF 10% 0.1UF 25V X5R 402 0.1UF 10% 25V X5R 402 201 10% 0.1UF X5R 6.3V GROUNDHOG OMIT CRITICAL BGA CRITICAL SN74LVC1G126DRYR-M LLP CRITICAL SN74LVC1G125DRYR-M LLP 51742 51742 51742 645 51742 51742 51742 6 18 17 18 18 40 17 18 51742 18 1718 1718 1718 18 51742 18 18 18 18 18 18 X5R-X7R 201 470PF 16V 10% 10% 0.1UF X5R 25V 402 1/20W 201 0 5% MF 5% 1/20W MF 0 NOSTUFF 201 502250-8037 F-RT-SM CRITICAL 502250-8037 F-RT-SM CRITICAL MF-LF 1/16W 1M 1% 402 MF 71.5K 201 1/20W 1% 603 10% 6.3V X5R 2.2UF NP0-C0G 5% 33PF 25V 201 SOD-323 B0520WSXG CRITICAL 16V 402 X5R 10% 0.1UF 1/20W 0.1 MF 201 1% U3007311S0485311S0523 311S0532311S0525 U3010 311S0524 311S0533 U3009 U30031343S0525 IC,ASIC,GROUNDHOG B0,120B BGA CRITICAL GRAPE: GROUNDHOG,CONN,BOOST SYNC_DATE=12/17/2010SYNC_MASTER=RAMSIN MT_PANEL_IN<27> MT_PANEL_OUT<34> MT_PANEL_OUT<32> MT_PANEL_OUT<30> MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.2MM VR_BOOST_L PM_BOOST_EN VR_BOOST_FBK MT_PANEL_OUT<22> MT_PANEL_OUT<24> =PP3V0_GRAPE MT_PANEL_IN<0> AGND_U3000 MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.2MM VR_BOOST_SW AG_SHLD_TST_FLEX GRAPE_MISOSPI1_GRAPE_MISO MAKE_BASE=TRUE SPI1_GRAPE_MOSI MAKE_BASE=TRUE RST_GRAPE_Z1_L =PP3V0_GRAPE GRAPE_CS_L SPI1_GRAPE_SCLK MAKE_BASE=TRUE GRAPE_SCLK GRAPE_MOSI DIR_U3007 Z1_CS_L Z1_CS_OE Z1_CS_OE Z2_H_CS_L Z1_MISO Z2_H_CS_L Z1_SCLK NET_SPACING_TYPE=PWR VOLTAGE=18V MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM PP18V_GRAPE MIN_NECK_WIDTH=0.25MM MIN_LINE_WIDTH=0.6MM VOLTAGE=18V PP18V_R_GRAPE NET_SPACING_TYPE=PWR SPI1_GRAPE_MISO Z1_CS_OE SPI1_GRAPE_MOSI RST_GRAPE_Z2_L MAKE_BASE=TRUE RST_GRAPE_L SPI1_GRAPE_CS_L MAKE_BASE=TRUE AG_SHLD_TST =PP3V0_GRAPE MT_PANEL_IN<10> MT_PANEL_IN<8> MT_PANEL_IN<1> MT_PANEL_IN<2> MT_PANEL_IN<3> MT_PANEL_IN<4> MT_PANEL_IN<5> MT_PANEL_IN<6> MT_PANEL_IN<7> MT_PANEL_IN<9> MT_PANEL_IN<11> MT_PANEL_IN<12> MT_PANEL_IN<13> MT_PANEL_IN<14> MT_PANEL_IN<15> MT_PANEL_IN<16> MT_PANEL_IN<17> MT_PANEL_IN<18> MT_PANEL_IN<19> MT_PANEL_IN<20> MT_PANEL_IN<21> MT_PANEL_IN<22> MT_PANEL_IN<23> MT_PANEL_IN<24> MT_PANEL_IN<25> MT_PANEL_IN<26> MT_PANEL_IN<28> MT_PANEL_IN<29> MT_PANEL_OUT<39> MT_PANEL_OUT<38> MT_PANEL_OUT<37> MT_PANEL_OUT<36> AG_SHLD_TST_FLEX MT_PANEL_OUT<26> MT_PANEL_OUT<33> MT_PANEL_OUT<31> MT_PANEL_OUT<29> MT_PANEL_OUT<28> MT_PANEL_OUT<27> MT_PANEL_OUT<25> MT_PANEL_OUT<23> MT_PANEL_OUT<20> MT_PANEL_OUT<19> MT_PANEL_OUT<18> MT_PANEL_OUT<17> MT_PANEL_OUT<16> MT_PANEL_OUT<15> MT_PANEL_OUT<14> MT_PANEL_OUT<13> MT_PANEL_OUT<12> MT_PANEL_OUT<11> MT_PANEL_OUT<10> MT_PANEL_OUT<9> MT_PANEL_OUT<8> MT_PANEL_OUT<7> MT_PANEL_OUT<6> MT_PANEL_OUT<5> MT_PANEL_OUT<4> MT_PANEL_OUT<3> MT_PANEL_OUT<2> MT_PANEL_OUT<1> MT_PANEL_OUT<0> MT_PANEL_OUT<35> SPI1_GRAPE_SCLK SPI1_GRAPE_CS_L MT_PANEL_OUT<21> Z1_MOSI =PP3V0_GRAPE GRAPE_FW_DNLD_EN_L =PP3V0_GRAPE MT_PANEL_OUT<26> MT_PANEL_OUT<25> MT_PANEL_OUT<24> MT_PANEL_OUT<23> MUX_IN<19> MUX_IN<17> Z1_BON_L<0> Z1_BON_L<1> Z1_BON_L<2> Z1_BON_L<3> Z1_BON_L<4> Z1_BON_L<5> MUX_IN<0> MUX_IN<1> MUX_IN<2> MUX_IN<3> MUX_IN<4> MUX_IN<5> MUX_IN<6> MUX_IN<7> MUX_IN<8> MUX_IN<9> MUX_IN<10> MUX_IN<11> MUX_IN<12> MUX_IN<13> MUX_IN<16> MUX_IN<15> MUX_IN<18> MT_PANEL_OUT<1> MT_PANEL_OUT<0> MT_PANEL_OUT<6> MT_PANEL_OUT<5> MT_PANEL_OUT<4> MT_PANEL_OUT<3> MT_PANEL_OUT<2> MT_PANEL_OUT<8> MT_PANEL_OUT<11> MT_PANEL_OUT<10> MT_PANEL_OUT<7> MT_PANEL_OUT<16> MT_PANEL_OUT<15> MT_PANEL_OUT<14> MT_PANEL_OUT<13> MT_PANEL_OUT<12> MT_PANEL_OUT<21> MT_PANEL_OUT<20> MT_PANEL_OUT<19> MT_PANEL_OUT<18> MT_PANEL_OUT<17> MT_PANEL_OUT<22> MT_PANEL_OUT<27> MT_PANEL_OUT<31> MT_PANEL_OUT<30> MT_PANEL_OUT<29> MT_PANEL_OUT<28> MT_PANEL_OUT<32> MT_PANEL_OUT<36> MT_PANEL_OUT<35> MT_PANEL_OUT<34> MT_PANEL_OUT<33> MT_PANEL_OUT<37> MT_PANEL_OUT<39> MT_PANEL_OUT<38> Z1_B_ADR<2> Z1_B_ADR<1> Z1_B_ADR<0> MUX_IN<14> MT_PANEL_OUT<9> PP18V_GRAPE =PP3V0_GRAPE_MARIO1 C30001 2 R3009 1 2 R30121 2 C3008 1 2 D3000 1 2 C3009 1 2 L3000 1 2 U3000 53 4 6 1 7 8 9 2 XW3000 1 2 C30011 2 R3066 1 2 C30311 2 C30301 2 R30311 2 R30301 2 R30321 2 R30251 2 C30411 2 C30501 2 R30331 2 U3007 6 7 15 14 4 1 8 9 13 12 5 16 10 11 3 2 C3005 1 2 C3007 1 2 C3053 1 2 C30061 2 U3003 A10 B9 A9 C7 A7 B7 B8 A8 C8 C9 D7 G7 G8 E3 E5 E6 E7 F6 F7 G5 G6 B1 C1 I5 J8 J9 K8 J10 I10 H10 F11 C11 E10 E1 A11 B4 A5 A2 F2 H1 J1 J2 J3 K4 H5 C6 D3 F5 F8 F9 G3 G4 G9 H3 H4 H7 H8 D4 H9 J6 K7 D5 D6 D8 D9 E4 E8 F4 A6 B6 E9 F3 A1 B2 H2 I2 K1 K2 I3 K3 J4 I4 K6 H6 C2 K5 J5 I7 K9 I8 K10 I6 J7 K11 I9 D1 J11 I11 H11 G11 G10 F10 C10 D10 E11 D11 D2 B11 B10 C4 A4 B5 C5 A3 B3 E2 F1 G1 G2 I1 U3010 2 3 1 6 4 U3009 2 3 1 6 4 C30021 2 C30701 2 R3070 1 2 R3071 12 J3010 1 10 11 12 13 14 15 16 17 18 19 2 20 21 22 23 24 25 26 27 28 29 3 30 31 32 33 34 35 36 37 38 39 4 40 41 5 6 7 8 9 J3011 1 10 11 12 13 14 15 16 17 18 19 2 20 21 22 23 24 25 26 27 28 29 3 30 31 32 33 34 35 36 37 38 39 4 40 41 5 6 7 8 9 051-8773 10.0.0 30 OF 157 17 OF 48 5 5 18 17 17 17 45 18 17 17 171835 18 45 45 17 17 18 35 17 45 45 18 17 18 35 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 18 35 17 18 35 17 17 17 17 18 18 18 18 18 18 1840 1840 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 18 40 18 40 18 40 18 17 1745 35
OUT OUT IN IN IN OUT IN IN IN IN OUT IN IN OUT IN IN IN IN51 RESET* VDDDIG VDDIO V18 MOSI VDDANA IN25 BON_L0 BON_L1 BON_L2 BON_L3 BON_L4 BON_L5 B_ADR0 B_ADR1 B_ADR2 CS* DONE GNDANA GNDDIG GNDIO GO IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12 IN13 IN14 IN15 IN16 IN17 IN18 IN19 IN20 IN21 IN22 IN23 IN24 IN27 IN28 IN29 IN30 IN31 IN32 IN33 IN34 IN35 IN36 IN37 IN38 IN39 IN40 IN41 IN42 IN43 IN44 IN45 IN46 IN47 IN48 IN49 IN50 IN52 IN53 IN54 IN55 IN56 IN57 IN58 IN59 IN60 IN61 MISO PCLK SCLK STMIN STMOUT TM IN26 IN62 IN63 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VDDANA VDDCORE TM0 TM1 RESET* LFOO A_CS* A_SDI IN7_0 H_SCLK VDDLDO JTAG_TDI JTAG_TCK IN9_1 IN9_0 IN8_1 IN8_0 IN7_1 IN6_1 IN6_0 IN5_1 IN4_1 IN4_0 IN3_1 IN3_0 IN2_1 IN2_0 IN11_1 IN11_0 IN10_1 IN10_0 IN1_1 IN1_0 IN0_1 IN0_0 H_SDO H_SDI H_CS* GPIO7 GPIO6 FLOO BOOT_CFG1 BOOT_CFG0 BON_L5 BON_L4 BON_L3 BON_L2 BON_L1 BON_L0 B_ADR1 ARMTAPMD* A_SDO A_SCLK GPIO1 GPIO0 GPIO2 GPIO3 VDDIO GPIO5 CLKIN CLKOUT EXTFLLIN JTAG_TDO JTAG_TMS GPIO4 IN5_0 B_ADR2 B_ADR0 GND Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT K94FLOATFLOAT MIN_NECK_MIDTH SHOULD BE 0.4MM INTERNAL PU MODECFG0 AUTONOMOUS DEPENDENT 1 DEPENDENT 2 SLAVE K48 USES DEPENDENT 2 MODE 1 0 1 0 1 1 0 0 CRITICAL ERROR MODE K48X J2FLOAT BON_L3BON_L4 X LOW DEFAULT ALL OTHER STRAPS LOW FLOAT BON_L5 FLOAT J2 Z2 AND BYPASSED OUTSIDE ARE EACH GENERATED WITHIN VDDANA AND VDDCORE ARM9 MCU (Z2 BASED) ZEPHYR 1+ ASIC CFG1 Z2 - PRODUCT STRAP OPTIONS 0 1/20W 201 5% MF 0 0 201 5% 1/20W MF CERM-X5R 10UF 0402-1 6.3V 20% 6.3V X5R-CERM1 402 4.7UF 20% 17 5 17 17 17 17 17 17 17 18 17 18 40 17 18 17 37 42 5% 1/32W 01005 MF 100 01005 5% 100 1/32W MF 17 18 17 18 40 17 17 18 100K 201 1/20W 5% MF 2.2UF 4V X5R 402 20% 0.1UF 10% 201 6.3V X5R 201 0.1UF 10% 6.3V X5R 4V 2.2UF X5R 402 20% 4.7 201 5% 1/20W MF CERM-X5R 10UF 0402-1 6.3V 20% BCM5973 CRITICAL BGA 10% 0.1UF 201 6.3V X5R 201 10% 0.1UF 6.3V X5R 0.1UF 10% 201 6.3V X5R 100K 1/20W 5% 201 MF 0.1UF 10% 201 6.3V X5R 201 10% 0.1UF 6.3V X5R 10UF CERM-X5R 0402-1 6.3V 20% 4V 2.2UF X5R 402 20% CRITICAL Z1_GO FBGA BCM5974CKFBGH 201 MF 1/20W 100K 5% 1.00 201 MF 1% 1/20W GRAPE: Z1, Z2 SYNC_DATE=12/17/2010SYNC_MASTER=RAMSIN =PP3V0_GRAPE_Z1 MT_PANEL_IN<0> MT_PANEL_IN<1> Z1_SCLK TP_Z2_A_SDI Z1_MISO Z2_A_CS_L TP_Z2_A_SDO U3101_TM1 MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM Z2_3V3_1V8_IN VOLTAGE=1.8V NET_SPACING_TYPE=PWR NC_BON_L1 GRAPE_CS_L Z1_CS_OE_R IRQ_GRAPE_HOST_INT_L PM_BOOST_EN NC_BON_L5 TP_U3101_TMS TP_U3101_TDO HOST_REFCLK GRAPE_MOSI Z1_DONE TP_Z2_A_SCLK NC_BON_L3 GRAPE_SCLK Z2_H_CS_L Z1_MOSI TP_U3101_TCK TP_U3101_TDI Z1_SCLK TP_U3101_TM0 BOOT_CFG0_R MAKE_BASE=TRUE CLK_32K_PMU =PP3V0_GRAPE BOOT_CFG1_R =PP3V0_GRAPE =PP3V0_GRAPE AG_SHLD_TST Z1_CS_OE Z1_PCLK MIN_NECK_WIDTH=0.1MM VOLTAGE=1.8V MIN_LINE_WIDTH=0.5MM Z2_VDDANA NET_SPACING_TYPE=PWR Z2_VDDCORE VOLTAGE=1.8V MIN_LINE_WIDTH=0.5MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.1MM =PP3V0_GRAPE_Z2 GRAPE_MISO RST_GRAPE_Z2_L MT_PANEL_IN<26> U3100_TM Z1_STMIN Z1_PCLK Z1_MISO MUX_IN<19> MUX_IN<18> MUX_IN<17> MUX_IN<16> MUX_IN<15> MUX_IN<14> MUX_IN<13> MUX_IN<12> MUX_IN<11> MUX_IN<10> MUX_IN<9> MUX_IN<8> MUX_IN<7> MUX_IN<6> MUX_IN<5> MUX_IN<4> MUX_IN<3> MUX_IN<2> MUX_IN<1> MUX_IN<0> MT_PANEL_IN<29> MT_PANEL_IN<28> MT_PANEL_IN<27> MT_PANEL_IN<24> MT_PANEL_IN<23> MT_PANEL_IN<22> MT_PANEL_IN<21> MT_PANEL_IN<20> MT_PANEL_IN<19> MT_PANEL_IN<18> MT_PANEL_IN<17> MT_PANEL_IN<16> MT_PANEL_IN<15> MT_PANEL_IN<14> MT_PANEL_IN<13> MT_PANEL_IN<12> MT_PANEL_IN<11> MT_PANEL_IN<10> MT_PANEL_IN<9> MT_PANEL_IN<8> MT_PANEL_IN<7> MT_PANEL_IN<6> MT_PANEL_IN<5> MT_PANEL_IN<4> MT_PANEL_IN<3> MT_PANEL_IN<2> Z1_GO Z1_DONE Z1_CS_L Z1_B_ADR<2> Z1_B_ADR<1> Z1_B_ADR<0> Z1_BON_L<5> Z1_BON_L<4> Z1_BON_L<3> Z1_BON_L<2> Z1_BON_L<1> Z1_BON_L<0> MT_PANEL_IN<25> MIN_NECK_WIDTH=0.2MM VOLTAGE=3.0V MIN_LINE_WIDTH=0.2MM NET_SPACING_TYPE=PWR MT_3V3_INT Z1_MOSI RST_GRAPE_Z1_L Z1_1V8_OUT Z1_1V8_OUT MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.8V NET_SPACING_TYPE=PWRC31061 2 C31051 2 C31081 2 R31071 2 C31091 2 C31101 2 C31111 2 C31121 2 U3101 F1 G1 F2 G4 E6 F9 F8 G9 J8 H9 J9 H7 J7 H5 F6 D3 E5 E4 G7 G5 C3 H8 C4 D6 D7 D8 C9 D9 G2 D1 J2 J3 H4 J6 G3 F3 F4 H6 H1 J1 H3 J4 A9 B9 B2 C1 B1 A1 A7 A8 B8 C8 B7 C7 A6 B6 C6 C5 B5 A5 A4 B4 A3 B3 C2 A2 G6 E8 E9 F7 F5 D5 E7 D4 D2 E1 G8 H2 J5 E2 E3 R31601 2 R3190 1 2 R3171 1 2 R31731 2 R3120 1 2 C31911 2 C31071 2 R3180 1 2 R3181 1 2 R31551 2 C31011 2 C31021 2 C31031 2 C31041 2 R3101 1 2 C31921 2 U3100 A5 B5 A6 A2 A1 A3 A4 B4 B3 B10 B7 B1 B2 C12 D3 D11 F7 H7 L3 L4 L5 L6 L7 B12 L8 L9 L10 L11 B13 C2 C3 C6 C7 C8 C11 C4 B11 A8 H2 G2 E1 E2 J2 G1 F2 J7 K2 N4 M5 N5 D7 M6 N3 M3 L1 K1 L2 N6 M2 M4 M1 C1 N2 N1 N13 N12 M10 M13 N8 M12 K13 L13 F1 L12 M11 N11 M8 N9 M9 N10 K12 J13 F12 J1 G13 J12 E12 E13 H13 N7 D13 D12 H12 F13 D2 C13 E7 M7 G12 D1 K7 H1 B9 B8 A12 A7 A11 A13 A10 A9 B6 G6 G7 G8 K4 K10 C10 C5 C9 051-8773 10.0.0 31 OF 157 18 OF 48 18 35 17 17 45 46 46 18 46 171835 17 18 35 17 18 35 17 18 45 45 35 17 18 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 18 18 17 40 17 40 17 40 17 40 17 40 17 17 17 17 17 45 17 1845 18 45
IN OUT IN OUT IN IN BI OUT OUT OUT IN IN IN OUT IN IN IN SCL SDA INT* SPEAKEROUTB+ SPEAKEROUTB- SPEAKEROUTA+ SPEAKEROUTA- EAROUT+ EAROUT- LINEOUT2B LINEOUT2B_REF LINEOUT2A LINEOUT2A_REF LINEOUT1_REF LINEOUT1A LINEOUT1B HPOUT_REF HPOUTB HPOUTA HP_DETECT VL VA VCP VP VD RESET* MCLK WAKE* ASP_LRCLK ASP_SCLK ASP_SDIN ASP_SDOUT VSP_LRCLK VSP_SLCLK VSP_SDIN VSP_SDOUT XSP_LRCLK XSP_SCLK XSP_SDIN/DAC2B_MUTE DMIC_SCLK LINEINA_REF MIC1 MIC2_REF MIC2_DETECT_REF MIC2_BIAS_FILT MIC3A_BIAS MIC3A_REF MIC3B FLYP -VCP_FILT +VCP_FILT FLYC FLYN SPEAKER_VQ FILT+ GND GNDP GNDA GNDCP GNDD MIC2 MIC2_DETECT MIC2_BIAS MIC1_BIAS_FILT MIC1_REF LINEINB_REF XSP_SDOUT MIC3B_BIAS_FILT MIC3B_REF MIC3B_BIAS MIC3A_BIAS_FILT MIC3A MIC1_BIAS DMIC_SD LINEINA LINEINB OUT IN IN OUT IN OUT OUT IN IN IN OUT IN IN IN OUT IN IN OUT IN NC NC NC NC NC NC NC NC NC NC NC NC Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT I2C ADDRESS: 1001010X?? L63B AUDIO CODEC 2.2UF NOT USING SPEAKER AMPLIFIER WITH SPEAKER LOAD. APN:338S0940 RECOMMENDED 20% X5R 0.1UF 4V 01005 X5R-CERM 6.3V 10% 01005 1000PF 5% NP0-C0G 16V 01005 27PF 20% 402 4V X5R 10UF SM SM SM 20% 6.3V 10UF CERM-X5R 0402-1 6.3V 0.1UF X5R 10% 201 542 21 43 51542 5 3745 510223742 510223742 21 43 21 40 21 40 21 22 21 40 20 43 20 43 20 43 542 542 WLCSP-1 CS42L63B CRITICAL 20% 4.7UF 402-3 TANT 4V 20% 6.3V 10UF CERM-X5R 0402-1 20% 6.3V 0402-1 CERM-X5R 10UF 20 43 20% 4.7UF 402 X5R-CERM1 6.3V 1.00K MF 1/32W 1% 01005 X5R-CERM1 6.3V 402 4.7UF 20% 2243 2243 22 01005 MF1% 1/32W 1.00K 2243 37 542 22 MF5% 010051/32W 542 51542 51542 51542 010051/32W 5% 22 MF 22 01005 MF5% 1/32W 542 542 542 542 20% 01005 0.1UF 4V X5R 23 2243 20% 4.7UF 402 X5R-CERM1 6.3V CRITICAL 5% 01005 MF 22 1/32W 5% MF 22 1/32W 01005 26 26 20% 4.7UF 402 X5R-CERM1 6.3V CRITICAL 20% 402 X5R-CERM 2.2UF 10V 20% 402 X5R-CERM 2.2UF 10V 20% X5R 4V 0.1UF 01005 SYNC_DATE=02/03/2011 AUDIO: L63B CODEC SYNC_MASTER=KAVITHA NC_LINE_IN2_CODEC NC_LINE_IN1_CODEC DMIC_SD_CODEC NC_MIC1_BIAS_CODEC I2S_L63_XSP_SDOUT NC_LINE_IN2_REF_CODEC NC_MIC1N_CODEC NC_MIC1_FILT_CODEC EXT_MIC_BIAS MIC2_DET EXT_MIC_P GND_AUDIO_CODEC MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM MAX_NECK_LENGTH=75 MM FILT_POS SPKR_VQ VHP_FLYN VHP_FLYC VHPPFILT VHPNFILT VHP_FLYP MIC2_BIAS_FILT MIC2_DET_REF EXT_MIC_REF NC_MIC1P_CODEC NC_LINE_IN1_REF_CODEC DMIC_SCLK_CODEC I2S3_XSP_DOUT I2S3_XSP_BCLK I2S3_XSP_LRCK I2S_L63_VSP_SDOUT I2S2_VSP_DOUT I2S2_VSP_BCLK I2S2_VSP_LRCK I2S_L63_ASP_SDOUT I2S0_ASP_DOUT I2S0_ASP_BCLK I2S0_ASP_LRCK AUD_MIK_HS1_INT_L I2S0_ASP_MCK_R RST_L63_L =PPVCC_MAIN_AUDIO =PP1V7_VA_VCP =PP1V8_AUDIO HP_DET HP_L HP_R HP_REF CODEC_LINE_OUT_R CODEC_LINE_OUT_L CODEC_LINE_OUT_REF LEFT_CH_OUT_REF LEFT_CH_OUT_P RIGHT_CH_OUT_REF RIGHT_CH_OUT_P NC_EAROUT_AN NC_EAROUT_AP IRQ_CODEC_L I2C0_SDA_1V8 I2C0_SCL_1V8 I2S0_ASP_DIN I2S2_VSP_DIN I2S3_XSP_DIN GND_AUDIO_HP_AMP MIN_LINE_WIDTH=1.0MM MIN_NECK_WIDTH=0.2MM GND_AUDIO_CODEC DMIC_SCLK_SENSOR DMIC_SD_SENSOR HSMIC_C_N HSMIC_C_P C36171 2 C36181 2 C3602 1 2 C3601 1 2 C3600 1 2 C36051 2 C36061 2 XW3600 1 2 XW3601 1 2 XW3602 1 2 C3603 1 2 C36041 2 U3600 C8 B7 B8 A9 B5 A5 F3 G3 G1 F11 G11 E11 D8 D9 F2 E10 B10 G5 E9 F9 G10 G9 E4 C5 C4 D6 D5 E8 F8 G8 D7 E7 F7 G7 F10 B9 A3 D4 E2 B3 B1 C2 C1 D3 C3 B2 A1 D2 D1 A2 A4 F1 E1 B4 D10 E5 C6 C7 E6 G6 F6 G4 F4 G2 D11 B11 C11 F5 C9 C10 A11 A10 E3 B6 A6 A8 A7 C36081 2 C3614 1 2 C36131 2 C3611 1 2 R3605 1 2 C3609 1 2 R3604 1 2 R3601 1 2 R3602 1 2 R3603 1 2 C36071 2 C36161 2 R36081 2 R36211 2 C36151 2 051-8773 10.0.0 36 OF 157 19 OF 48 46 46 46 42 46 46 46 192145 46 46 42 42 202235 35 35 46 46 21 22 45 19 21 45
OUT IN IN OUT OUT OUT OUT IN- IN+ OUT+ OUT- GAINSHDN* PVDD NC PGND IN- IN+ OUT+ OUT- GAINSHDN* PVDD NC PGND OUT NC NC IN OUT Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT NC GAIN:6DB GAIN 100K GND APN:353S3317) TURN ON TIME: 3.5MS NC NC NC100K SHORT NC 12DB NC SHORT 0DB L63 LINEOUT2A IS CONNECTED TO U3700 L63 LINEOUT2B IS CONNECTED TO U3710 6DB GAIN:6DB VDD 9DB 3DB TURN ON DELAY: ?MS SPEAKER CONNECTOR APN 518S0672 MAY NEED TUNING FOR THESE FILTERS 75HZ +/- XXX% SPEAKER AMPLIFIER LEFT CHANNEL IS INVERTED TO FIX CODEC BUG ON LINEOUT2 1943 1943 1943 SM SM 20 43 20 43 20 43 20 43 0603-1 10V X5R 10UF 20% 0603-1 10V X5R 10UF 20% 5% NP0-C0G CRITICAL NOSTUFF 100PF 16V 01005 5% NP0-C0G NOSTUFF 100PF 16V 01005 CRITICAL 0% 1/32W 0.00 MF 01005 1/32W MF 1% 01005 100 01005 0.00 1/32W MF 0% CRITICAL 0.015UF 10% 0201 6.3V X5R MF 1% 100 01005 1/32W 1/32W MF 01005 0% 0.00 01005 0.00 MF 0% 1/32W 5% NP0-C0G 01005 16V 100PF NOSTUFF CRITICAL 5% NP0-C0G 01005 16V 100PF NOSTUFF CRITICAL MAX98304C WLPNDIFPR_BADTERM CRITICAL MAX98304C WLP CRITICAL CRITICAL 0.015UF 0201 X5R 6.3V 10% 0.015UF 0201 6.3V 10% X5R CRITICAL 0.015UF 0201 X5R 6.3V 10% CRITICAL 78171-6006 M-RT-SM CRITICAL 6 0201 240-OHM-0.2A-0.8-OHM 5% 27PF NP0-C0G 25V 0201 520 SM SM 201 X5R 10% 6.3V 0.1UF 1943 01005 5% 1/32W 100K MF 201 X5R 6.3V 10% 0.1UF AUDIO: SPEAKER AMP SYNC_MASTER=KAVITHA SYNC_DATE=02/03/2011 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM GND_SPKR_AMP2 AUD_SPKR_AMP2_PBUS MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.30MM GND_SPKR_AMP1 AUD_SPKR_AMP1_PBUSMIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.30MM MAX983X4_L_IN_P SPKRAMP_L_OUT_N SPKRAMP_L_OUT_P SPKRAMP_R_OUT_P SPKRAMP_R_OUT_N SPK_ID SPK_ID_FILT LEFT_CH_OUT_REF RIGHT_CH_OUT_P LEFT_CH_OUT_P =PPVCC_MAIN_AUDIO LEFT_CH_P RIGHT_CH_OUT_REF RIGHT_CH_P =PPVCC_MAIN_AUDIO AUD_SPKRAMP_MUTE_L MAX983X4_R_GAIN SPKRAMP_R_OUT_N MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MMSPKRAMP_R_OUT_PMAX983X4_R_IN_P MAX983X4_R_IN_N AUD_SPKRAMP_MUTE_L MAX983X4_L_GAIN MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.50MM SPKRAMP_L_OUT_N SPKRAMP_L_OUT_P MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.50MM MAX983X4_L_IN_N XW3700 1 2 XW3701 1 2 C3703 1 2 R37001 2 C3713 1 2 XW3710 1 2 XW3711 1 2 C37041 2 C37141 2 C3753 1 2 C37521 2 R37031 2 R3701 12 R37021 2 C3701 1 2 R3711 12 R37121 2 R37131 2 C3751 1 2 C37501 2 U3700 B3 C2 C3 A1 A2 B1A3 C1 U3710 B3 C2 C3 A1 A2 B1A3 C1 C3702 1 2 C3711 1 2 C3712 1 2 J3700 7 8 1 2 3 4 5 6 L3700 1 2 C37001 2 051-8773 10.0.0 37 OF 157 20 OF 48 B2 B2 45 40 45 40 43 2043 2043 2043 2043 19202235 43 43 19202235 520 43 43 43
OUT OUT IN IN OUT IN OUT OUT OUT IN IN IN IN Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT HEADPHONE OUTPUT ZOBEL NETWORK CODEC DOCK LINE OUTPUT DOCK 01005 MF 1% 100 1/32W 01005 1% MF 100 1/32W 10% 6.3V X5R 33000PF 201201 6.3V X5R 10% 33000PF 27PF 01005 5% NP0-C0G 16V 01005 16V NP0-C0G 27PF 5% 16V 01005 NP0-C0G-CERM 15PF 5% 15PF 16V 5% 01005 NP0-C0G-CERM 23 43 1922 1943 1943 23 43 1922 27 1940 27 1940 1940 27 45 27 SM SM NP0-C0G-CERM 01005 16V 15PF 5% 01005 5% 16V NP0-C0G 27PF SM SM 01005 1% 100 100 1% 01005 SYNC_DATE=02/03/2011 AUDIO: HEADPHONE OUT SYNC_MASTER=KAVITHA AUDIO_EMI_LO_L MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.07MM MIN_NECK_WIDTH=0.07MM AUDIO_EMI_LO_R MIN_LINE_WIDTH=0.1MM MIN_LINE_WIDTH=0.1MM CODEC_LINE_OUT_R MIN_NECK_WIDTH=0.07MM MIN_NECK_WIDTH=0.07MM MIN_LINE_WIDTH=0.1MM CODEC_LINE_OUT_L GND_AUDIO_PT_DK MAX_NECK_LENGTH=75 MM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MMGND_AUDIO_CODEC MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.07MM CODEC_LINE_OUT_REF HP_R AUD_HP1_MLBCON_L MIN_NECK_WIDTH=0.07MM MIN_LINE_WIDTH=0.1MM AV_EMI_DIFF_SENSE HP_REF HP_ZR AUD_HP1_MLBCON_R HP_L GND_AUDIO_HP_AMP HP_ZL R38511 2 R38501 2 C38511 2 C3850 1 2 C38531 2 C38521 2 C3802 1 2 C38011 2 XW3800 1 2 XW3803 1 2 C3803 1 2 C38541 2 XW3851 1 2 XW3850 1 2 R3800 12 R3801 12 051-8773 10.0.0 38 OF 157 21 OF 48 1945 192245
OUT OUT IN IN IN OUT OUT OUT ADDR SDA SCL REF MIC CLAMPO CLAMPI RAMPO RAMPI GND2 MIC2 GND MIC1 VDD GND1 IN IN Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT (HSMIC_C_N) (HSMIC_C_P) EXT MIC LPF FC = 677KHZ TO CODEC EXTERNAL (HEADSET) MIC INPUT CIRCUITRY FROM HEADSET 10% 6.3V 201 0.1UF X5R 19 43 19 43 2340 2340 5% 33PF NP0-C0G-CERM 16V 01005 X7R 1000PF 10% 201 16V MF 1/20W 1% 201 470 MF 1/20W 1% 470 201 1% 1/20W 201 MF 1K 19 6.3V 10% X5R 201 0.1UF 201 2.2K 1/20W MF 1% 1/20W 1% 2.2K 201 MF 20% 0402-1 CERM-X5R 10UF 6.3V 19 43 19 43 19 21 SM TS3A8235YFP CRITICAL WCSP NOSTUFF CERM-X5R 6.3V 20% 10UF 0402-1 201 MF 1/20W NOSTUFF 5% 0 MF 1/20W 5% 0 201 2340 2340 201 MF 1/20W 5% 0 NOSTUFF 201 5% 0 MF 1/20W 201 6.3V X5R 10% 0.1UF 5% 01005 NP0-C0G-CERM 16V 15PF SYNC_DATE=02/03/2011 AUDIO: DETECT/MIC BIAS SYNC_MASTER=KAVITHA AUD_HS_MIC2_HI AUD_HS_MIC1_HI GND_AUDIO_HP_AMP =PP3V0_S2R_HALL_CHSW PPVDD_CHSW MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.30MM MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR VOLTAGE=4.6V AUD_HS_MIC2_RET HSMIC_C_P CHS_CAP_REF CHS_CLAMPO HSMIC_R_P EXT_MIC_REFHSMIC_R_N EXT_MIC_P CHS_CLAMPI HP_REF EXT_MIC_BIAS I2C0_SDA_1V8 I2C0_SCL_1V8 HSMIC_C_N =PPVCC_MAIN_AUDIO AUD_HS_MIC1_RET C4211 1 2 C4212 1 2 C4213 1 2 C4216 1 2 C42171 2 R4212 1 2 R4213 1 2 R4201 1 2 C42001 2 R4202 1 2 R4203 1 2 C42011 2 XW4200 1 2 U4200 A2 C4 B4 C2 B2 B3 C3 D2B1 C1 D4 D3 D1 A3 A4 A1 C42021 2 R4204 1 2 R4205 1 2 R4210 1 2 R4211 1 2 051-8773 10.0.0 42 OF 157 22 OF 48 192145 35 43 43 5 10 19 37 42 5 10 19 37 42 192035
OUT OUT OUT OUT IN IN IN OUT OUT IN IN OUT IN IN IN OUT Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT HEADSET JACK INSERTION DETECT HEADPHONE JACK CONNECTION IS ON FRONT PANEL FLEX, CSA 55/PDF 29 PLACE ALL COMPONENTS NEAR J5401 22 40 0402 30-OHM-1.7A CRITICAL0402 30-OHM-1.7A CRITICAL 22 40 2443 2443 2440 24 24 0402 30-OHM-1.7A 0402 30-OHM-1.7A CRITICAL 22 40 22 40 0402 30-OHM-1.7A CRITICAL0402 30-OHM-1.7A 2440 2440 0201 240-OHM-0.2A-0.8-OHM 23 40 21 43 21 43 10V 10% 201 X7R 4700PF NOSTUFF1/32W 5% 01005 MF 3.3K 2340 19 SYNC_MASTER=KAVITHA SYNC_DATE=02/03/2011 AUDIO: HP/MIC FILTERS HP_DETAUD_HP1_DET_H MIN_NECK_WIDTH=0.05MM MIN_LINE_WIDTH=0.1MM AUD_HS_MIC2_HI MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM AUD_HS_MIC2_RET MIN_NECK_WIDTH=0.05MM MIN_LINE_WIDTH=0.1MM CONN_AUD_HEADSET_CHS_MIC2 MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM CONN_AUD_HEADSET_CHS_RET2 AUD_HP1_DET_H MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM AUD_HS_MIC1_RET MIN_NECK_WIDTH=0.05MM MIN_LINE_WIDTH=0.1MM AUD_HS_MIC1_HI MIN_NECK_WIDTH=0.05MM MIN_LINE_WIDTH=0.1MM CONN_AUD_HEADSET_CHS_MIC1 MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM CONN_AUD_HEADSET_CHS_RET1 MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.15MM AUD_HP1_MLBCON_R MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.15MM AUD_HP1_MLBCON_L MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.15MM CONN_AUD_HEADSET_LEFT MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.15MM CONN_AUD_HEADSET_RIGHT CONN_AUD_HEADSET_DET L4303 1 2 C43101 2 R4312 1 2 L4306 1 2 L4304 1 2 L4301 1 2 L4302 1 2 L4308 1 2 L4307 1 2 051-8773 10.0.0 43 OF 157 23 OF 48
NC NC NC NC NC NC NC NC NC NC NC NC Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT APN: 518S0828 APN: 518S0828 CAM CLOCK 0 CAM CLOCK 1 CRITICAL F-RT-SM 502250-8037 CRITICAL F-RT-SM 502250-8037 SYNC_MASTER=MARK CONNECTOR: SENSOR SYNC_DATE=01/11/2011 MIPI0C_CAM_CLK_P CLK_CAM_FF_CONN ISP_CAM_1_SDA MIPI1C_CAM_CLK_P CONN_IRQ_GYRO_INT2 SRL_L AUD_VOL_UP_L CONN_IRQ_ACCEL_INT2_L CONN_AUD_HEADSET_CHS_RET2 CONN_AUD_HEADSET_CHS_MIC2 CONN_AUD_HEADSET_CHS_MIC1 CONN_AUD_HEADSET_RIGHT CONN_AUD_HEADSET_CHS_RET1 ISP_CAM_0_SCL DMIC_DATA_CONN I2C1_SDA_1V8_CONN IRQ_ALS_INT_CONN_L I2C2_SCL_3V0_ALS PM_REAR_CAM_SHUTDOWN_FILT I2C1_SCL_1V8_CONN MIPI1C_CAM_CLK_N ISP_CAM_1_SCL CONN_IRQ_PROX_INT_L MIPI0C_CAM_CLK_N ONOFF_L MIPI1C_CAM_DATA_P<0> MIPI0C_CAM_DATA_P<1> ISP_CAM_0_SDA PP3V0_S2R_HALL_FLT MIPI0C_CAM_DATA_N<1> PP1V8_SENSOR_FLT CLK_CAM_RF_CONN CAM0_RESET_L_FLT PP3V0_SENSOR_FLT PP2V85_CAM_FLT MIPI0C_CAM_DATA_N<0> DMIC_CLK_CONN I2C2_SDA_3V0_ALS CONN_IRQ_GYRO_INT1 CONN_AUD_HEADSET_LEFT CONN_AUD_HEADSET_DET CONN_IRQ_ACCEL_INT1_L AUD_VOL_DOWN_L MIPI1C_CAM_DATA_N<0> CONN_IRQ_HALL MIPI0C_CAM_DATA_P<0> PM_FRONT_CAM_SHUTDOWN_FILT J5400 1 10 11 12 13 14 15 16 17 18 19 2 20 21 22 23 24 25 26 27 28 29 3 30 31 32 33 34 35 36 37 38 39 4 40 41 5 6 7 8 9 J5401 1 10 11 12 13 14 15 16 17 18 19 2 20 21 22 23 24 25 26 27 28 29 3 30 31 32 33 34 35 36 37 38 39 4 40 41 5 6 7 8 9 051-8773 10.0.0 54 OF 157 24 OF 48 25 43 25 42 25 42 25 43 26 5 37 5 26 23 40 2340 23 2343 23 2542 26 25 42 25 102542 25 2542 2543 2542 26 2543 537 25 43 25 43 25 42 26 45 2543 26 45 25 42 26 10 26 45 26 45 25 43 26 10 25 42 26 23 43 2340 26 5 2543 25 2543 25
IN IN IN1 IN2 IN4 IN3 OUT1 OUT2 OUT3 OUT4 GND IN1 IN2 IN4 IN3 OUT1 OUT2 OUT3 OUT4 GND IN BI BI OUT IN IN BI BI SYM_VER-1 SYM_VER-1 IN BI BI OUT OUT OUT OUT OUT BI BI OUT SYM_VER-1 SYM_VER-1 SYM_VER-1 IN BI IN1 IN2 IN4 IN3 OUT1 OUT2 OUT3 OUT4 GND OUT BI OUT IN1 IN2 IN4 IN3 OUT1 OUT2 OUT3 OUT4 GND BI IN IN IN OUT OUT IN BI OUT BI IN IN BI BI BI BI OUT OUT BI BI BI BI NC NC NC NC Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT TABLE_ALT_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD PLACE IT NEAR H4 22 OHM PLACE IT NEAR H4 22 OHM 7 742 0603 800MHZ-100MA-27PF 0603 800MHZ-100MA-27PF 742 742 542 5 743 743 743 743 90-OHM-50MA TCM0605-1 90-OHM-50MA TCM0605-1 5% 1/20W MF 201 0 NOSTUFF 1/20W 0 MF5% NOSTUFF201 1/20W 201 MF5% 0 NOSTUFF 201 MF 1/20W 5% 0 NOSTUFF 24 10 24 42 24 42 24 24 24 42 24 43 24 43 24 43 24 43 5% 201 MF 1/20W 100K NOSTUFF 24 42 1/20W 0 MF5% 201 NOSTUFF 1/20W 5% MF 201 NOSTUFF 0 90-OHM-50MA TCM0605-1 1/20W 0 MF5% 201 NOSTUFF 1/20W 5% MF 201 0 NOSTUFF MF 2011/20W 0 5% NOSTUFF 90-OHM-50MA TCM0605-1 90-OHM-50MA TCM0605-1 201 MF 0 5% 1/20W NOSTUFF 742 24 42 0603 800MHZ-100MA-27PF 24 24 42 24 42 800MHZ-100MA-27PF 0603 NOSTUFF 5% 201 MF 1/20W 100K 742 7 742 542 10 24 42 NOSTUFF 5% 100PF CERM 25V 201 25V CERM 100PF 5% NOSTUFF 201 MF-LF 22 1/16W 5% 402 402 MF-LF 1/16W 22 5% 37 51042 51042 24 42 24 42 743 743 743 743 743 743 24 43 24 43 24 43 24 43 24 43 24 43 22 5% 402 1/16W MF-LF 22 5% 402 1/16W MF-LF ?155S0643 155S0373 U5502,U5503,U5500,U5501,U5600,U5601 RADAR:8376668 SYNC_MASTER=MARK SENSOR PANEL FILTERS 1 SYNC_DATE=01/11/2011CLK_CAM_RF_C MIPI0C_CAM_DATA_P<0> MIPI0C_CAM_CLK_N MIPI0C_CAM_CLK_P CLK_CAM_FF_C CLK_CAM_FF_FILT MIPI1C_AP_CLK_N MIPI1C_AP_CLK_P I2C1_SCL_1V8_CONN I2C1_SDA_1V8_CONN MIPI0C_CAM_DATA_N<0> MIPI0C_CAM_DATA_P<1> MIPI0C_CAM_DATA_N<1> MIPI0C_AP_DATA_P<1> MIPI0C_AP_DATA_N<0> MIPI0C_AP_DATA_P<0> MIPI0C_AP_CLK_P MIPI0C_AP_CLK_N MIPI1C_CAM_DATA_N<0> MIPI1C_CAM_DATA_P<0> MIPI1C_CAM_CLK_N MIPI1C_CAM_CLK_P MIPI1C_AP_DATA_P<0> IRQ_HALL I2C1_SDA_1V8 I2C1_SCL_1V8 ISP_CAM_1_SCL IRQ_ALS_INT_CONN_L I2C2_SCL_3V0_ALS I2C2_SDA_3V0_ALS ISP_AP_1_SDA PM_FRONT_CAM_SHUTDOWN_FILT ISP_CAM_1_SDA I2C2_SCL_3V0 CLK_CAM_FF_CONN I2C2_SDA_3V0 IRQ_ALS_INT_L CONN_IRQ_HALL ISP_AP_1_SCL =PP1V8_CAM PM_FRONT_CAM_SHUTDOWN =PP1V8_CAM CLK_CAM_RF ISP_AP_0_SDA PM_REAR_CAM_SHUTDOWN ISP_AP_0_SCL ISP_CAM_0_SDA PM_REAR_CAM_SHUTDOWN_FILT ISP_CAM_0_SCL CLK_CAM_RF_CONN CLK_CAM_RF_FILT CLK_CAM_FF MIPI1C_AP_DATA_N<0> MIPI0C_AP_DATA_N<1> U5500 9 10 1 2 3 4 5 6 7 8 U5501 9 10 1 2 3 4 5 6 7 8 L5500 1 2 3 4 L5501 1 2 3 4 R55101 2 R55111 2 R55121 2 R55131 2 R55011 2 R56201 2 R56211 2 L5620 1 2 3 4 R56101 2 R56111 2 R56121 2 L5600 1 2 3 4 L5601 1 2 3 4 R56131 2 U5502 9 10 1 2 3 4 5 6 7 8 U5503 9 10 1 2 3 4 5 6 7 8 R55021 2 C55011 2 C55001 2 R5601 1 2 R5600 1 2 R5603 1 2 R5602 1 2 051-8773 10.0.0 55 OF 157 25 OF 48 42 42 42 2535 2535 42
IN1 IN2 IN4 IN3 OUT1 OUT2 OUT3 OUT4 GND OUT IN OUT OUT IN IN OUT OUT IN IN IN OUT IN OUT IN1 IN2 IN4 IN3 OUT1 OUT2 OUT3 OUT4 GND OUT IN Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT DCR 0.31 DCR 0.31 DCR 0.31 240-OHM-0.2A-0.8-OHM 0201 0603 800MHZ-100MA-27PF 5 24 5 5 24 24 5 5 24 24 0402 240-OHM-25%-400MA 240-OHM-25%-400MA 0402 240-OHM-25%-400MA 0402 7 24 19 19 10% 201 X7R 16V 1000PF 10% X5R 201 6.3V 0.1UF 10% 1UF 402-1 X5R 10V 82PF CERM 0201 5% 25V 10% 16V X7R 201 1000PF 10% 1UF 402-1 X5R 10V 10% 1000PF 201 16V X7R 10% 1UF 402-1 X5R 10V 25V 5% CERM 0201 82PF 0201 CERM 25V 5% 82PF 10% 1000PF 16V X7R 201 10% 1UF 402-1 X5R 10V25V 5% CERM 82PF 0201 800MHZ-100MA-27PF 0603 24 24 SYNC_MASTER=MARK SYNC_DATE=01/11/2011 SENSOR PANEL FILTERS 2 =PP3V0_OPTICAL PP3V0_SENSOR_FLT VOLTAGE=3.0V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR =PP2V85_CAM PP2V85_CAM_FLT NET_SPACING_TYPE=PWR VOLTAGE=2.85V MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm MAX_NECK_LENGTH=3 MM DMIC_SCLK_SENSOR DMIC_SD_SENSOR PP1V8_SENSOR_FLT MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.6 mm PP3V0_S2R_HALL_FLT MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.6 mm VOLTAGE=3.0V MIN_NECK_WIDTH=0.2 mm NET_SPACING_TYPE=PWR =PP1V8_SENSOR =PP3V0_S2R_HALL CAM0_RESET_L_FLT CONN_IRQ_PROX_INT_L CAM0_RESET_L IRQ_PROX_INT_L CONN_IRQ_GYRO_INT2 CONN_IRQ_GYRO_INT1 CONN_IRQ_ACCEL_INT1_L CONN_IRQ_ACCEL_INT2_L IRQ_GYRO_INT2 IRQ_GYRO_INT1 IRQ_ACCEL_INT1_L IRQ_ACCEL_INT2_L DMIC_CLK_CONN DMIC_DATA_CONN C56231 2 C56161 2 C56151 2 C56141 2 C56211 2 C56181 2 C56201 2 C56131 2 C56171 2 C56121 2 C5631 2 C56021 2 C56011 2 U5600 9 10 1 2 3 4 5 6 7 8 L5610 1 2 U5601 9 10 1 2 3 4 5 6 7 8 L5611 1 2 L5613 1 2 L5612 1 2 051-8773 10.0.0 56 OF 157 26 OF 48 35 10 24 45 35 24 45 24 45 24 45 35 35
GND VBUS IO NC IO NC GND VBUS IO NC IO NC GND VBUS IO NC IO NC REF GND IN OUTBI BI IN IN IN IN IN IN IN IN IN IN IN IN IN OUT IN IN IN OUT OUT OUT OUT SYM_VER-1 SYM_VER-1 SYM_VER-1 SYM_VER-1 GND VBUS IO NC IO NC Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_ALT_ITEM TABLE_ALT_ITEM ACCESSORY FIREWIRE DETECT/ DISPLAYPORT HPD USB LINEOUTVIDEO RETURN CURRENT DISPLAYPORT (JTAG_TCK) JTAG_AP_TMS = 1.8V: U5730’S IN = 1.16V NOTE: JTAG_AP_TMS = 3.3V: U5730’S IN = 2.13V JTAG PLACE BY PMU NOTE: 0.095 OHM DCR SEPARATION BETWEEN AUDIO AND NOTE: R5700 ADDED TO PROVIDE ANALOG VIDEO MAX CONTINUOUS VOLTAGE IS 19V - SPEC IS 16V (JTAG_TMS) 0201 25V NP0-C0G 27PF 5% 0201 25V NP0-C0G 27PF 5% 0201 25V NP0-C0G 27PF 5% 25V NP0-C0G 27PF 5% 0201 NOSTUFF 0201 25V NP0-C0G 27PF 5% NOSTUFF 0201 25V NP0-C0G 27PF 5% RCLAMP0502N SLP1210N6 RCLAMP0502N SLP1210N6 RCLAMP0502N SLP1210N6 5% 12PF NP0-C0G-CERM 25V 0201 5% 25V NP0-C0G 27PF 0201 0201 22-OHM-25%-900MA 0.01UF 10V 10% X5R 201 10% 402 X7R 0.01UF 25V FERR-120-OHM-1.5A 0402A FERR-120-OHM-1.5A 0402A 30-OHM-1.7A 0402 10% X7R 50V 402 0.01UF201 1/20W MF 47K 5% GDZT2R5.1B GDZ-0201 UCLAMP0511Z 0201 UCLAMP0511Z 0201 6.8V-100PF 0201 150 1/20W MF 201 5% DEVELOPMENT_JTAG 0 DEVELOPMENT_JTAG 0 DEVELOPMENT_JTAG UCSP MAX9061 0.1UF X5R 10% 6.3V DEVELOPMENT_JTAG 201 1/20W MF 220K 201 5% MF 1/20W 10K 201 5% 100K 1/20W MF 1% 201 442 442 2843 2843 2843 2843 2843 2843 101143 101143 101143 21 21 21 2145 1142 1142 1/20W 10K MF 201 5% 442 442 4 30 37 45 37 37 37 0201 0.01UF 16V 10% X5R-CERM DEVELOPMENT_JTAG 01005 MF 1/32W 1% 523K 1% 1/32W MF 01005 DEVELOPMENT_JTAG 1.00M 12-OHM-100MA-8.5GHZ TCM0806-4SM 12-OHM-100MA-8.5GHZ TCM0806-4SM TCM0605 35-OHM-50MA 0201-1 14.2V-6PF 0201 6.8V-100PF OMIT SM 0402 27V-100PF USBULC6-2F3 BGA MF 1/20W 0 201 5% 0 1/20W MF 201 5% 0.200 1% 1/20W MF 201 0201 25V NP0-C0G 27PF 5% 0201 25V NP0-C0G 27PF 5% 5% 27PF NP0-C0G 25V 0201 5% 27PF 0201 25V NP0-C0G NOSTUFF 0201 25V NP0-C0G 27PF 5% NOSTUFF 0201 25V NP0-C0G 27PF 5% NOSTUFF 0201 25V NP0-C0G 27PF 5% NOSTUFF 0201 25V NP0-C0G 27PF 5% NOSTUFF 0201 25V NP0-C0G 27PF 5% NP0-C0G NOSTUFF 0201 25V 27PF 5% 0201 NOSTUFF 25V NP0-C0G 27PF 5% FERR-120-OHM-1.5A 0402A 0603 FERR-70-OHM-4A SOT953 NUP412VP5XXG 0201 8V-100PF 0201 80-OHM-0.2A-0.4-OHM 0201 80-OHM-0.2A-0.4-OHM 0201 80-OHM-0.2A-0.4-OHM TCM0605 35-OHM-50MA 100K 5% 1/20W MF 201 RCLAMP0502N SLP1210N6 RADAR:8849707377S0111 DZ5710,DZ5711 377S0099 RADAR:8972666DZ5751377S0090 377S0081 D5700,D5701,D5702,D5703 377S0107 RADAR:8947642377S0066 RADAR:8423156155S0625 L5700,L5701155S0559 377S0116 377S0108 DZ5760 RADAR:8370432 155S0276155S0725 FL0600, FL5707, FL5708, FL5711 QTY 4 RADAR:9625553 RADAR:9625601L5762155S0513 155S0320 IO FLEX: DOCK COMPONENTS SYNC_DATE=01/19/2011SYNC_MASTER=JOE USB_DK_D0_P USB_DK_D0_N USB_PT_DK_CON_D_N USB_PT_DK_CON_D_P DP_PT_DK_CON_TX_N<1> DP_PT_DK_CON_TX_P<1> AV_PT_DK_CON_RET VIDEO_PT_DK_CON_C_Y MIN_LINE_WIDTH=4.1MM VOLTAGE=5.0V NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.2MM MAX_NECK_LENGTH=3 MM PPVBUS_USB_PT_DK_CON JTAG_AP_TMS =PP1V8_S2R_MISC AUDIO_PT_DK_RET MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VIDEO_PT_DK_CON_CVBS_PB VIDEO_PT_DK_CON_Y_PR ACC_PT_DK_CON_ID D5701_6 D5702_6 DP_PT_DK_CON_AUX_N DP_PT_DK_CON_TX_N<0> DP_PT_DK_CON_TX_P<0> D5703_6 ACC_PT_DK_CON_TX DP_EMI_AUX_N DP_EMI_AUX_P DP_EMI_TX_N<1> DP_EMI_TX_P<1> DP_EMI_TX_N<0> DP_EMI_TX_P<0> ACC_PT_DK_CON_RXUSB11_ACC_RX_P USB11_ACC_TX_N AUDIO_PT_DK_RET VIDEO_EMI_C_Y PORT_DOCK_ACCID PMU_ADC_REF GND_AUDIO_PT_DK AV_EMI_DIFF_SENSE PORT_DOCK_ACC_DET_L =PPVCC_MAIN_DOCK VIDEO_EMI_CVBS_PB VIDEO_EMI_Y_PR VIDEO_PT_DK_CON_Y_PR VIDEO_PT_DK_CON_C_Y VIDEO_PT_DK_CON_CVBS_PB RST_AP_L PT_DK_CON_P14 PT_DK_CON_P17 JTAG_AP_TCK U5730_IN DP_PT_DK_CON_AUX_P MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.07MM AV_PT_DK_CON_DIFF_SENSE ACC_PT_DK_CON_DET_L D5700_6 MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=4.1MM PPVBUS_USB_EMI FW_ZENER_PWR FW_PT_DK_CON_PWR =PP3V3_PORT_ACC MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.1MM VOLTAGE=3.3V NET_SPACING_TYPE=PWR ACC_PT_DK_CON_PP3V3 AUDIO_EMI_LO_L AUDIO_PT_DK_CON_LO_L MIN_NECK_WIDTH=0.07MM MIN_LINE_WIDTH=0.1MM AUDIO_EMI_LO_R AUDIO_PT_DK_CON_LO_R MIN_NECK_WIDTH=0.07MM MIN_LINE_WIDTH=0.1MM L5714 1 2 L5757 1 2 U5700 1 2 3 4 5 DZ5790 1 2 FL5711 1 2 FL5707 1 2 FL5708 1 2 L5716 1 2 3 4 R57901 2 D5703 1 5 4 6 C57501 2 C57511 2 C57521 2 C57531 2 C57541 2 C57551 2 D5702 1 5 4 6 D5701 1 5 4 6 D5700 1 5 4 6 C57221 2 C57211 2 L5762 1 2 C57821 2 C57831 2 L5761 1 2 L5760 1 2 L5763 1 2 C57801 2 R5710 1 2 DZ5720 1 2 DZ5710 1 2 DZ5711 1 2 DZ5712 1 2 R57401 2 R5730 1 2 R5731 1 2 U5730 B2 A2 A1 B1 C57301 2 R57501 2 R5751 1 2 R5752 1 2 R5753 1 2 C57601 2 R57951 2 R57961 2 L5700 1 2 3 4 L5701 1 2 3 4 L5702 1 2 3 4 DZ5752 A C DZ5753 1 2 XW5700 1 2 DZ5760 1 2 DZ5751 A1 A2 B1 B2 R5720 1 2 R5721 1 2 R57001 2 C57031 2 C57001 2 C57011 2 C57021 2 C57051 2 C57061 2 C57071 2 C57081 2 C57101 2 C57111 2 C57121 2 051-8773 10.0.0 57 OF 157 27 OF 48 2 3 2 3 2 3 2 3 29 42 29 42 29 43 29 43 29 27 28 43 29 45 53539 27 27 28 43 27 28 43 29 29 43 29 43 29 43 29 42 29 42 27 37 35 27 28 43 27 28 43 27 28 43 28 28 29 43 29 29 35 29 35 29 45 29 29
OUT OUT OUT OUT BI BI OUT OUT OUT OUT OUTIN OUTIN OUTIN OUTIN IN OUT IN IN IN IN BI BI Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT PLACE NEAR J5900. PLACE NEAR R5901 PLACE NEAR R5903 PLACE NEAR J5900. STUFF FOR STEVENOTE STUFFING OPTIONS FOR DP LANES 2, 3 FOR STEVENOTE. PLACE NEAR J5900. ALTERNATE PINOUT FOR JTAG FOR STEVENOTE ON MLB, STUFF ALL OF THE PLACE NEAR J5900. PLACE NEAR J5900. PLACE NEAR R5907 DISPLAYPORT AC COUPLING SUPPORT ON MLB ONLY ALTERNATE PINOUT FOR JTAG R5904, R5906, R5914, R5915, R5916, AND R5917. FOR DEV BOARD, STUFF R5918 AND NOSTUFF R5903. PLACE NEAR R5905 PLACE NEAR J5900. SNOTE BOM OPTIONS. NOSTUFF R5902, R5900,R5908 PLACEMENT NOTE: NEAR U0600 1/32W MF 100K 1% 01005 MF 1/32W 100K 1% 01005 27 43 27 43 27 43 27 43 27 28 43 27 28 43 7 28 43 7 28 43 7 28 43 7 28 43 NOSTUFF SIGNAL_MODEL=EMPTY 150 MF 201 1/20W 5% SIGNAL_MODEL=EMPTY NOSTUFF 150 1/20W MF 201 5% SIGNAL_MODEL=EMPTY 100PF 201 CERM NOSTUFF 25V 5% 201 MF 1/20W 150 NOSTUFF SIGNAL_MODEL=EMPTY 5% MF 201 150 NOSTUFF 1/20W SIGNAL_MODEL=EMPTY 5% NOSTUFF 201 100PF SIGNAL_MODEL=EMPTY CERM 25V 5% 28 43 2016.3V 0.1UF X5R10% 743 28 43 X5R6.3V 201 0.1UF 10% 743 28 43 10% X5R 0.1UF 2016.3V 743 28 43 10% 201 0.1UF 6.3V X5R 743 29 6.8V-100PF 0201 201MF 0 1/20W DEVELOPMENT_JTAG 5% 1/20W SNOTE NO_XNET_CONNECTION=TRUE 201MF 0 SIGNAL_MODEL=EMPTY 5% 201MF 0 1/20W DEVELOPMENT_JTAG 5% 0 1/20W MF 201 SNOTE SIGNAL_MODEL=EMPTY NO_XNET_CONNECTION=TRUE 5% MF1/20W 0 2015% 0 SNOTE 1/20W MF 201 NO_XNET_CONNECTION=TRUE SIGNAL_MODEL=EMPTY 5% 201 0 1/20W MF5% SNOTE 201MF 0 1/20W NO_XNET_CONNECTION=TRUE SIGNAL_MODEL=EMPTY 5% 201MF1/20W 0 5% SNOTE 201 MF 1/20W 0 5% MF 0 201 1/20W 5% 0 1/20W MF 201 SNOTE 5% 0 2011/20W MF SNOTE 5% MF 0 201 1/20W 5% 1% 1/20W MF 45.3 201 1/20W 1% 45.3 MF 201 201 MF 1/20W 1% 45.3 201 MF 1/20W 1% 45.3 5 37 25V NP0-C0G 0201 27PF 5% 25V NP0-C0G 0201 27PF 5% 120-OHM-200MA 0201 72843 72843 72843 72843 743 743 6.3V 201X5R10% 0.1UF 10% 201X5R6.3V 0.1UF 10% 0.1UF 6.3V 201X5R 6.3V 0.1UF X5R10% 201 6.3V 201X5R10% 0.1UF X5R10% 2016.3V 0.1UF SYNC_DATE=01/19/2011 DISPLAY PORT MISC SYNC_MASTER=JOE DP_PT_DK_CON_TX_P<2> DP_PT_DK_CON_TX_P<3> VIDEO_PT_DK_CON_C_Y_R VIDEO_PT_DK_CON_CVBS_PB_R VIDEO_PT_DK_CON_CVBS_PB PT_DK_CON_P15_R PT_DK_CON_P14PT_DK_CON_P14_R DP_AP_TX_N<1> DP_AP_TX_P<1> DP_TERM_C1251 DP_EMI_AUX_N DP_EMI_AUX_P =PP3V0_IO_MISC DP_EMI_TX_P<0> DP_EMI_TX_N<0> DP_EMI_TX_P<1> DP_EMI_TX_N<1> DP_PT_DK_CON_TX_P<2> DP_PT_DK_CON_TX_N<2> DP_PT_DK_CON_TX_P<3> DP_PT_DK_CON_TX_N<3> DP_AP_TX_P<0> DP_AP_TX_N<0> DP_AP_TX_P<1> DP_AP_TX_N<1> DP_AP_TX_N<2> DP_AP_TX_P<2> DP_AP_TX_N<3> DP_AP_TX_P<3> DP_EMI_AUX_P DP_EMI_AUX_N DP_AP_AUX_P VIDEO_PT_DK_CON_C_Y DP_PT_DK_CON_TX_N<3> DP_TERM_C1250 VIDEO_PT_DK_CON_Y_PR_R VIDEO_PT_DK_CON_Y_PR PT_DK_CON_P17_R PT_DK_CON_P16_R PT_DK_CON_P17 DP_PT_DK_CON_TX_N<2> DP_AP_AUX_N DP_AP_TX_N<0> DP_AP_TX_P<0> HOME_L HOME_EMI_L C5802 1 2 C5803 1 2 C5804 1 2 C5805 1 2 C5806 1 2 C5807 1 2 R58201 2 R58231 2 R12531 2 R12521 2 C12511 2 R12511 2 R12501 2 C12501 2 C5808 1 2 C5809 1 2 C5810 1 2 C5811 1 2 DZ5750 1 2 R5900 12 R5901 12 R5902 12 R5903 12 R5904 12 R5905 12 R5906 12 R5907 12 R5908 12 R59091 2 R59121 2 R5913 12 R5911 12 R59101 2 R59141 2 R59151 2 R59161 2 R59171 2 C57661 2 C57651 2 FL5750 1 2 051-8773 10.0.0 58 OF 157 28 OF 48 28 43 28 43 2943 2943 27 43 29 2729 272843 272843 635 27 43 28 43 2943 27 43 29 29 27 28 43
IN IN IN OUT BI BI IN IN IN IN BI BI IN IN OUT OUT OUT OUT OUT OUT IN IN IN IN IN Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT (JTAG_TMS_BACKUP) (JTAG_TCK_BACKUP) PN 516S0542 (PLUG - MALE) (JTAG_TMS) (JTAG_TCK) (DP_HPD) 28 28 2742 2742 27 42 27 42 27 43 27 43 27 43 27 43 27 43 27 43 27 27 27 27 27 28 27 27 2843 2843 2843 M-ST-SM CPB6450-0101F CRITICAL 28 28 SYNC_MASTER=JOE IO FLEX: B2B CONNECTOR SYNC_DATE=01/19/2011 PPVBUS_USB_PT_DK_CON PT_DK_CON_P15_R PT_DK_CON_P16_R VIDEO_PT_DK_CON_CVBS_PB_R VIDEO_PT_DK_CON_C_Y_R VIDEO_PT_DK_CON_Y_PR_R AUDIO_PT_DK_CON_LO_R PT_DK_CON_P17_R PT_DK_CON_P14_R ACC_PT_DK_CON_TX ACC_PT_DK_CON_RX ACC_PT_DK_CON_PP3V3 FW_PT_DK_CON_PWR ACC_PT_DK_CON_DET_L HOME_L DP_PT_DK_CON_AUX_N DP_PT_DK_CON_AUX_P USB_PT_DK_CON_D_P USB_PT_DK_CON_D_N ACC_PT_DK_CON_ID AV_PT_DK_CON_RET AUDIO_PT_DK_CON_LO_L AV_PT_DK_CON_DIFF_SENSE DP_PT_DK_CON_TX_N<1> DP_PT_DK_CON_TX_P<1> DP_PT_DK_CON_TX_N<0> DP_PT_DK_CON_TX_P<0> J5900 51 52 53 54 1 10 1112 1314 1516 1718 19 2 20 2122 2324 2526 2728 29 3 30 3132 3334 3536 3738 39 4 40 4142 4344 4546 4748 49 5 50 6 78 9 051-8773 10.0.0 59 OF 157 29 OF 48 2745 2745
BI BI BI BI BI OUT IN OUT IN OUT IN OUT IN OUT IN IN OUT OUT OUT IN OUT IN OUT IN IN NC NC NC NC Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT X26 CELLULAR/GPS CONNECTOR 998-3732 - AP_MODEM_WAKE (RADAR #9179861) - H4G -> BB NOTE FOR IPC_GPIO_X26 (GPIO24): NOTE FOR SPI2_IPC_SRDY (GPIO12): - BB_DIAGS_READY (RADAR #9179861) - BB -> H4G 1142 1142 5 442 442 MF 1/32W 1% 255K 01005 255K 1% 1/32W MF 01005 10% 6.3V 01005 X5R 0.01UF NOSTUFF 37 5 4273745 3745 51545 545 545 542 542 542 542 542 5 37 37 542 542 542 542 542 OMIT HB-SM HOT-BAR-PADS SYNC_DATE=01/19/2011 CONNECTOR: X26 SYNC_MASTER=JOE ADC_IN7 SPI2_IPC_SRDY HSIC_HOST_RDY HSIC0_BB_DATA1 SNSV_BATT_POS_ACF =BATT_POS_F_3G RST_AP_L PM_RADIO_ON RST_BB_PMU_L GSM_TXBURST_IND RST_BB_L RST_DET_L SPI2_IPC_SCLK SPI2_IPC_MOSI SPI2_IPC_MISO BB_EMERGENCY_DWLD PM_BB_HOST_WAKE USB_BB_D_N BB_VBUS_DET USB_BB_D_P UART1_BB_RXD UART1_BB_TXD UART1_BB_CTS_L UART1_BB_RTS_L IPC_GPIO_X26 HSIC_BB_RDY HSIC0_BB_STB1 R61011 2 R61001 2 C61001 2 J6000 1 10 11 12 13 14 15 16 17 18 19 2 20 21 22 23 24 25 26 27 28 29 3 30 31 32 33 34 35 36 37 38 39 4 40 41 42 5 6 7 8 9 051-8773 10.0.0 60 OF 157 30 OF 48 35
SYM 1 OF 3 MISCSR MISC JTAG FM BT WLAN GND LDO WRF_VCO_GND WRF_PA_GND0 WRF_PA_GND1 WRF_PA_GND2 WRF_PADRV_GND WRF_GNDLNA_2G WRF_XTAL_GND WRF_LOGEN_A_GND WRF_AFE_GND WRF_ANA_GND WL_VSS_0 WL_VSS_1 WL_VSS_2 WRF_GND FM_RXVSS VOUT_LNLDO1 VOUT_CLDO VIN_LDO VOUT_3P1 VOUT_3P3 WRF_VCOLDO_OUT_1P2 SR_VLX BT_RFVSS BT_FEVSS BT_VSS SR_PVSS WRF_TCXO_VDD WL_VDDC1 WL_VDDC2 WRF_VDDANA_1P2 WL_VDDC0 WRF_VDDAFE_1P2 WRF_LOGEN_A_VDD1P2 BT_VDDIO WL_VDDIO VDDIO_RF HSIC_AVDD12 BT_PAVDD3P3 BT_VCOVDD1P2 BT_VDDC1 BT_VDDC0 BT_RFVDD1P2 BT_IFVDD1P2 BT_PLLVDD1P2 FM_VDDAUDIO FM_VDD2P5 FM_VDDPLL1P2 FM_RFVDD1P2 PMU_AVSS HSIC_AVSS BT_VSSC BT_IFVSS BT_PLLVSS FM_VSSAUDIO FM_VSSVCO FM_PLLVSS WRF_XTAL_VDD1P2 WRF_VDDLNA_1P2_2G WRF_PADRV_VDD WRF_VDDPA WRF_VDD_VCOLDO_IN_1P8 SR_VDDBAT2 BT_REG_ON WL_REG_ON BT_RST* EXT_SMPS_REQ EXT_PWM_REQ JTAG_SEL SR_VDDBAT1_1 SR_VDDBAT1_0 WLANGPIOHSIC SYM 3 OF 3 BT/FMLOGIC WLANLOGIC GPIOPCMFMI2S TEST UART WLANSDIO SDIO_DATA_0 SDIO_DATA_1 SDIO_DATA_2 SDIO_DATA_3 SDIO_CLK WRF_GPIO_OUT BT_I2S_CLK BT_GPIO_3 BT_GPIO_4 BT_GPIO_5 BT_GPIO_1 BT_GPIO_2 BT_PCM_SYNC BT_GPIO_0 BT_PCM_CLK BT_PCM_IN BT_PCM_OUT BT_UART_TXD BT_UART_RXD BT_UART_RTS* BT_UART_CTS* BT_TM0 BT_I2S_DI HSIC_DATA HSIC_RREF WL_GPIO_1 WL_GPIO_6 WL_GPIO_5 WL_GPIO_3 WL_GPIO_4 WL_GPIO_2 WL_GPIO_0 HSIC_STROBE SDIO_CMD BT_I2S_DO BT_I2S_WS BT_CLK_REQ_IN BT_CLK_REQ_MODE IN OUT OUT IN IN IN OUT OUT IN IN OUT IN IN IN OUT IN OUT IN BI IN IN IN BI IN IN YA B NC GND VCC IN OUT BI NC NC NC NC NC NC NC NC NC NC NC NC Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT TABLE_ALT_ITEM TABLE_ALT_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_ALT_ITEM (NEARM9) ALTERNATE PARTS AVAILABLE: USED FOR BOOTSTRAPPING OPTIONS WE HAVE 500MILIAMP BURST RETURN CURRENTS TO BATTERY PULL-UP/DOWN RESISTORS BOOTSTRAP RESISTORS SDIO_DATA2 PULL DOWN FOR GPIO SET TAU = 200MILISEC WLAN RESET FALLS DEVICE READY DE-ASSERTS WHEN: SW-DEFINED GPIO2 FALLS 1 0 1 1 X 0 1 SDIO_DATA1 GSPI SDIO 1 0 MODE DEF.ARM STATE RESET RESET RUNNING RUNNING HOST WAKE FM I2S NOT WIRED UP GET RFDESIGN OK FOR ANY SEPARATION HSIC DEV RDY / JTAG TCK RF GUYS HATE MULTIPLE GROUND PLANES JTAG TRST_N (UNUSED) UART TX / JTAG TDO UART RX / JTAG TDI HSIC BOOTLOADERLESS HSIC SUPPLY FILTERING GPIO6 WLAN/BT POWER HSIC HOST RDY / JTAG TMS 1 X X BOOTSTRAPPING OPTIONS SDIO NOT WIRED UP WLAN/BT BASEBAND HSIC READY KLUDGE (NEARE1) MF 201 5% 1/20W 10K SHORT-0402 NOSTUFF X5R 20% 6.3V 0201 0.22UF MF 5% 1/20W 10K 201 120-OHM-200MA 0201 0201 120-OHM-200MA 4.7UF X5R 603 20% 6.3V 20% X5R 603 6.3V 4.7UF 0201 600-OHM-150MA WLBGA BCM4330XKUBG CRITICAL CKPLUS_WAIVE=PWRTERM2GND BCM4330XKUBG WLBGA CRITICAL 15 33 15 33 15 33 15 33 15 15 31 33 15 33 15 15 15 1533 1533 3133 1533 1533 15 31 201 1/20W MF 1% 49.9 1533 1533 32 15 31 33 15 33 201 X7R 16V 10% 1000PF 603 X5R 20% 6.3V 4.7UF 603 X5R 20% 6.3V 4.7UF 1UF 402 6.3V 10% CERM CRITICAL 2.2UH-1.3A-0.1OHM 1008 603 4.7UF 20% X5R 6.3V 10% 6.3V X5R 201 0.1UF X7R-CERM 10% 220PF 201 25V 5% 10PF NPO 201 25V 0.1UF 10% 201 6.3V X5R 201 X5R 10% 0.1UF 6.3V 6.3V 0.1UF 10% X5R 201 MF 201 5% 1/20W 10K 31 1/20W 201 0 5% MF NOSTUFF 3133 313335 MF 201 5% 1/20W 100K 20% X5R 6.3V 4.7UF 603 10K 5% 201 1/20W MF 5% 201 CERM 25V 100PF 0201 600-OHM-150MA 201 25V NPO 10PF 5% 74AUP1G08GF SOT891 10% 0.1UF 6.3V X5R 201 2.2M 1/20W MF 201 5% 10% 0.1UF 6.3V X5R 201 153133 10% 6.3V X5R 0.1UF 201 0.1UF 10% 6.3V X5R 201 201 0 5% MF 1/20W 15 31 15 0 5% 1/20W 201 MF 1UF 10% 6.3V 402 CERM 25V 201 NPO 10PF 5% 10% 201 X5R 0.1UF 6.3V MF 100K 1/20W 5% 201100K 201 MF 1/20W 5% MF 201 5% 1/20W 100K MF 201 5% 1/20W 100K MF 201 5% 1/20W 100K NOSTUFF ANDGATE_TI TIU8311S0548 311S0398 155S0657 FERRITE_TY TAIYO YUDENFL2,FL4155S0537 155S0337 155S0444 FERRITE_TDK TDKFL6,FL9 WLAN BB & POWER PWR100VDD_LNLDO_1V2 SR_VLX PWR1000 PWR100VDD_CORE_1V2 PWR1000 VDD_CBUCK_1V5 PWR1000 BATT_VDD_4330 PWR100VDD_LDO_2V5 SDIO_DATA1_4330 VDD_VCO_1V2 VDD_IO_1V8 BT_WAKE VDD_IO_1V8 SDIO_DATA3_4330 SDIO_CLK_4330 SDIO_DATA3_4330 SDIO_DATA2_4330 SDIO_CMD_4330 SDIO_CLK_4330 HSIC_STROBE_4330 HSIC_RREF WLAN_GPIO6 2G_TSSI WLAN_GPIO1 VDD_IO_1V8 WLAN_GPIO2 WLAN_GPIO2_R VDD_IO_1V8 WLAN_ENABLE_RC HSIC_DEVICE_READY_R HSIC_DEVICE_READY WLAN_ENABLE WLAN_GPIO2 HSIC_DEVICE_READY SDIO_DATA2_4330 WLAN_GPIO6 WLAN_GPIO0 WLAN_GPIO2 WLAN_GPIO4 WLAN_GPIO3 WLAN_GPIO5 HSIC_DATA_4330 BT_UART_CTS_N BT_UART_RTS_N BT_UART_RXD BT_UART_TXD BT_PCM_DOUT BT_PCM_DIN BT_PCM_CLK BT_WAKE BT_PCM_SYNC BT_HOST_WAKE BT_GPIO5 SDIO_DATA0_4330 SDIO_CMD_4330 SDIO_DATA0_4330 SDIO_DATA1_4330 VDD_CORE_1V2 VDD_LNLDO_1V2 VDD_IO_1V8 VDD_LDO_3V3 VDD_CORE_1V2 VDD_LDO_3V3 VDD_BTCORE_1V2 VDD_BT_1V2 VDD_LDO_2V5 VDD_BT_1V2 VDD_XTAL_1V2 VDD_WRF_1V2 BATT_VDD_4330 BATT_VDD_4330 BT_RESET_N WLAN_ENABLE JTAG_SEL VDD_LDO_3V3 PWR100 PWR100 VDD_BT_1V2 PWR100 VDD_BTCORE_1V2 BATT_VCC PWR500 PWR100 VDD_WRF_1V2 PWR100 PWR100 VDD_LNLDO_1V2 PWR100 VDD_WRF_1V2 PWR100 VDD_XTAL_1V2 PWR100 VDD_CORE_1V2 R5 1 2 XW1 1 2 C291 2 R4 1 2 FL2 1 2 FL4 1 2 C21 2 C11 2 FL6 1 2 U4 A10 B8 C8 A8 B11 C10 K10 B9 B10 G10 A11 K8 E8 F7 C9 F8 J10 K9 F10 E12 E11 F12 D10 E10 C11 F11 L1 M1 F5 L11 M11 K12 L12 K11 M12 L3 M10 J11 J12 M9 L10 L9 K1 K7 E7 M3 K2 L5 E5 F4 C1 C5 C7 D3D2 B2 B4 B6 C4C3 F3 F1F2 E1 G4 D1 B7 A4 H2H3 U4 D7 E9 F9 D9 H10 H9 H12 J9 H8 G7 H7 G8 H6 J6 J5 K6 G11 G6 F6 E6 D6 L2 J1 M2 M7 L7 M6 M8 M5 L8 H4 G5 H5 D5 J8 L6 D8 E4 R10 1 2 C31 2 C481 2 C491 2 C501 2 L1 1 2 C58 1 2 C561 2 C541 2 C531 2 C551 2 C571 2 C591 2 R11 1 2 R76 1 2 R12 1 2 C701 2 R16 1 2 C791 2 FL9 1 2 C781 2 U8 2 1 36 4 C801 2 R27 1 2 C811 2 C821 2 C521 2 R28 1 2 R26 1 2 C171 2 C851 2 C861 2 R31 1 2 R34 1 2 R33 1 2 R32 1 2 R35 1 2 051-8773 10.0.0 61 OF 157 31 OF 48 5 31 31 313233 31 31 313335 153133 31 31 31 31 31 31 313335 313335 3133 15 31 3131 31 31 31 31 31 313335 313233 31 313233 31 31 31 31 31 31 313233 313233 313233 31 31 3335 31 31 31 31 31
OUT VDD RX BT TX SW_OUT/NC GND ANT VC3 VC2 VC1 LNA_IN/NC BI BI OUT GND IN BI IN IN RF / CLOCKS BT RFFM CLOCKSWLANRF SYM 2 OF 3 FM_RXN FM_TX FM_RXP WRF_XTAL_OP WRF_XTAL_ON WRF_RFOUT_5G WRF_RFIN_5G WRF_RES_EXT RF_SW_CTRL_6 WRF_RFOUT_2G WRF_RFIN_2G WRF_A_TSSI_IN WRF_TCXO_IN LPO BT_RF BT_CLK_REQ_OUT RF_SW_CTRL_2 RF_SW_CTRL_1 RF_SW_CTRL_0 RF_SW_CTRL_5 RF_SW_CTRL_4 RF_SW_CTRL_3 FM_AOUT2 FM_AOUT1 RF_SW_CTRL_7 OUT OUT OUT OUT OUT OUT OUT OUT OUT IN OUT IN IN OUT IN RFIN RFOUT THRM_PAD VDET VCTRL VCC1 VCC2 IN OUT IN IN IN ANT(COMMON) LOW(2.4GHZ) HIGH(5.0GHZ) GND NC NC NC NC NC NC Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT WLAN TRANSCEIVER 2.4GHZ RX + T/R SWITCH 2.4GHZ BPF 0 0 1 WLAN TX RF_SW_CTRL_5: 5G_CTRL_TX RF_SW_CTRL_4: 5G_CTRL_RX 1 0 0 BT TX/RX 0 1 0 WLAN RX RF_SW_CTRL_1: 2G_CTRL_RX RF_SW_CTRL_7: 5G_CTRL_PA_EN RF_SW_CTRL_2: 2G_CTRL_TX 0 0 0 LNA BYPASS VCTL1 VCTL2 VCTL3 MODE . RF_SW_CTRL_3: 2G_CTRL_PA_EN RF I/O PLAN FORM GROUND ISLAND FOR XTAL CKT BACK TO BUMP H4 2.4GHZ/5GHZ DIPLEXER RF_SW_CTRL_6: 5G_CTRL_LNA_EN RF_SW_CTRL_0: 2G_CTRL_BT ANTENNA CONNECTOR SP3T+LNA 2.4GHZ TX CONDUCTED TEST PORT 1% MF 201 1/20W 15K 32 CRITICAL SKY65513-11 QFN 0201 CRITICAL 3.3NH+/-0.1NH-0.45A 201 6.3V X5R 0.1UF 10% CER 8.2PF 25V 0201 +/-0.1PF% 5.6NH 0201 NOSTUFF 33 32 4.7PF 0201 COG-CERM 25V +/-0.1PF NOSTUFF 0201 5.6NH CRITICAL F-ST-SM MM8030-2600RK0 32 1.0PF +/-0.1PF C0G NOSTUFF 25V 201 5.6NH NOSTUFF 0201 MM4829-2702 F-ST-SM CRITICAL 32 32 201 25V CERM 5% 100PF100PF 5% CERM 25V 201 CRITICAL 0805 2.45GHZ-2.4DB 3.3NH+/-0.1NH-0.45A NOSTUFF 0201 +/-0.1PF% 0201 CER 25V 8.2PF 3.3NH+/-0.1NH-0.45A 0201 NOSTUFF 1% 201 1/20W MF 47 WLBGA BCM4330XKUBG CRITICAL +/-0.1PF C0G 25V 1.8PF NOSTUFF 201 10% 6.3V 201 X5R 0.1UF 33PF NP0-C0G 5% 201 25V 10PF 5% NPO 25V 201 1.2NH+/-0.1NH-0.75A NOSTUFF 0201 0201 1.2NH+/-0.1NH-0.75A CRITICAL 0201 25V CER 8.2PF +/-0.1PF% 32 32 32 32 33 33 33 33 33 33 32 32 33 32 SM-2 CRITICAL 37.4MHZ-18PF-10PPM 1% MF 220 1/20W 201 32 LLP MF2425PL-DL0767 CRITICAL 32 31 32 4.7UF 603 20% 6.3V X5R 15 33 CRITICAL 2450MHZ-3.50DB LFB182G45CG3C179 32 0201 25V 8.2PF +/-0.1PF% CER NOSTUFF +/-0.1PF 201 1.8PF 25V C0G 1.8PF C0G 25V 201 +/-0.1PF NOSTUFF NOSTUFF 201 25V 1.8PF C0G +/-0.1PF+/-0.1PF 1.8PF C0G 25V 201 NOSTUFF 8.2PF +/-0.1PF% CER 25V 0201 10K 1% 1/20W MF 201 1% 201 MF 1/20W 2.2K 5% 25V 201 100PF CERM 201 C0G 25V NOSTUFF +/-0.1PF 1.8PF 0201 4.7NH-3%-0.35A CRITICAL CRITICAL 0805 2.4-5.0GHZ 4.7NH-3%-0.35A 0201CRITICAL CRITICAL 0201 4.3NH-3%-0.35A 0.1UF 201 X5R 10% 6.3V 0201 CRITICAL 1/20W MF 0.00 1% 0201 6.8NH-5%-0.3A NOSTUFF 25V NP0-C0G 33PF 5% 201 25V 33PF 5% 201 NP0-C0G 0201 1.2NH+/-0.1NH-0.75A CRITICAL 201 25V NPO 10PF 5% WLAN 2.4GHZ AND ANT50_OHM 50_OHM RF_ANT_MATCH1 RF_ANT 50_OHM 50_OHM 5G_CTRL_RX 2G_CTRL_RX CLK32K 2G_PA_VCRL WLAN_RBIAS_4330 WLAN_XTAL_N_XTAL WLAN_XTAL_P_4330 2G_PA_VDET 2G_CTRL_PA_EN 2G_RF_SP3T_LNA1 2G_RF_SP3T_LNA2 2G_CTRL_BT 2G_RF 5G_RF 2G_PA_VCC2 2G_TSSI BATT_VDD_4330 5G_CTRL_PA_EN 2G_CTRL_PA_EN 5G_CTRL_TX 2G_CTRL_BT 2G_CTRL_RX 2G_CTRL_TX 5G_TSSI 5G_CTRL_LNA_EN WLAN_XTAL_N_4330 2G_CTRL_TX 50_OHM 2G_RF_BPF1_OUT 50_OHM 2G_RF_BPF1_IN 50_OHM 50_OHM 50_OHM 50_OHM 2G_RF_OUT_4330 50_OHM 2G_RF_BT_433050_OHM 50_OHM 50_OHM 2G_RF_IN_4330 2G_RF_TX_SP3T 50_OHM 50_OHM 2G_RF_PA_OUT 50_OHM 50_OHM 50_OHM 50_OHM RF_CAL_MATCH RF_CAL 50_OHM 50_OHM 2G_RF 50_OHM 50_OHM 50_OHM 50_OHM 2G_RF_BPF2_OUT 2G_RF_OUT_4330 50_OHM50_OHM 50_OHM 50_OHM 2G_RF_BT_4330 2G_RF_SP3T_ANT 50_OHM 50_OHM 50_OHM 5G_RF_IN_433050_OHM 50_OHM 2G_RF_IN_433050_OHM 50_OHM 5G_RF_OUT_433050_OHM 50_OHM 50_OHM 2G_RF_RX_SP3T 50_OHM 50_OHM 2G_RF_BPF2_IN PWR100 2G_SP3T_VDD 50_OHM 50_OHM 2G_RF_BT_SP3T PWR100 VDD_LDO_3V3 50_OHM 50_OHM 2G_RF_PA_IN R1 1 2 U3 2 12 7 9 6 8 5 4 1 11 3 10 L2 1 2 C891 2 C18 1 2 L6 1 2 C21 1 2 L7 1 2 J1 3 4 1 2 C111 2 L9 1 2 J2 2 3 4 1 C51 2 C41 2 FL1 2 1 3 L43 1 2 C20 1 2 L5 12 R2 12 U4 G12 A9 A12 B12 D12 D11 C12 J7 K5 J2 L4 M4 K3 J4 J3 K4 D4 E3 A7 B1 A6 A2 G3 H1 G1 C44 1 2 C411 2 C42 1 2 C431 2 L15 1 2 L16 12 C37 12 Y1 24 13 R9 1 2 U6 4 1 7 3 2 5 6 C38 1 2 FL8 2 1 3 C65 1 2 C63 1 2 C67 1 2 C68 1 2 C64 1 2 C66 1 2 R15 12 R14 1 2 C691 2 C45 1 2 L20 1 2 FL10 2 1 3 5 4 6 L14 1 2 L17 1 2 C391 2 R3 1 2 L23 12 C46 1 2 C47 1 2 L24 1 2 C61 2 051-8773 10.0.0 62 OF 157 32 OF 48 3133 31 33
A A A A A A GND OUTPUT2 OUTPUT1 VCONT2 VCONT1 INPUT A BI VCTL RFIN NC/GND THRM NC/GND VDET RFOUT VCC12 VCC3 PAD A PP PP A A A A A A OUT A THRM GND VCC V_ENABLE RF_INRF_OUT PAD IN A A IN OUT A IN IN AIN Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT VCRL1 VCTL2 PA_EN LNA_EN MODE 0 1 0 1 RX TEST AND PROBE POINTS TEST POINTS 1 0 1 0 TX 5GHZ PA NEED DC BLOCKING ON ALL PORTS 1 0 0 1 RX SUPERBYPASS MODE -- 26DB GAIN STEP 5GHZ FRONT-END CONTROL 5GHZ BPF 5GHZ LNA 5GHZ T/R SWITCH TP-P6 NOSTUFF TP-P6 NOSTUFF +/-0.05PF 0201 NOSTUFF 0.6PF 25V CERM 2.0PF +/-0.1PF 25V C0G-CERM 0201 CRITICAL TP-P6 NOSTUFF NOSTUFF TP-P6 NOSTUFF TP-P6 NOSTUFF TP-P6 CRITICAL UPG2185T6R TSSON TP-P6 NOSTUFF 201 5% MF 1/20W 62 25V +/-0.1PF C0G-CERM 0201 2.0PF CRITICAL 32 NOSTUFF 1.0NH+/-0.1NH-0.75A 0201 +/-0.1PF C0G-CERM 2.0PF 25V 0201 CRITICAL MF5060PK-DL0967 LGA CRITICAL NOSTUFF TP-P6 0201 1.0NH+/-0.1NH-0.75A NOSTUFF P4MM SM P4MM SM +/-0.1PF 0201 COG-CERM 25V 4.7PF TP-P6 NOSTUFF TP-1P0-TOP NOSTUFF TP-1P0-TOP NOSTUFF NOSTUFF TP-1P0-TOP NOSTUFF TP-1P0-TOP NOSTUFF TP-1P0-TOP 32 TP-P6 NOSTUFF SKY65404-31 QFN 5G_RF_LNA_OUT CRITICAL 100PF CERM 201 25V 5% +/-0.10PF CERM 25V 201 NOSTUFF 0.6PF 32 201 10V 10% 0.01UF X5R NOSTUFF TP-P6 0201 CRITICAL 1.0NH+/-0.1NH-0.75A NOSTUFF TP-P6 C0G-CERM 2.0PF 0201 +/-0.1PF 25V CRITICAL 0201 NOSTUFF 1.0NH+/-0.1NH-0.75A +/-0.1PF C0G-CERM 0201 25V 2.0PF CRITICAL 32 6.3V 20% X5R 603 4.7UF 1.0NH+/-0.1NH-0.75A NOSTUFF 0201 1.0NH+/-0.1NH-0.75A NOSTUFF 0201 10PF NPO 201 25V 5% 32 NP0-C0G 25V 27PF 5% 0201 10K 1% 201 1/20W MF CRITICAL 5.0GHZ-1.7DB DEA165375BT +/-0.10PF CERM 25V 201 0.6PF NOSTUFF 201 NOSTUFF 0.6PF 25V +/-0.10PF CERM C0G-CERM 2.0PF 0201 +/-0.1PF 25V CRITICAL 1/20W MF 201 1% 2.2K NOSTUFF TP-P6 32 32 TP-P6 NOSTUFF 100PF 201 25V CERM 5% 25V 201 CERM 5% 100PF 32 100PF 201 25V CERM 5% 0201 C0G-CERM +/-0.1PF 25V 2.0PF CRITICAL 0.6PF 25V CERM 0201 +/-0.05PF WLAN 5GHZ AND TEST POINTS 5G_PA_VDET VDD_LDO_3V3 50_OHM 50_OHM 5G_RF_RX 50_OHM 50_OHM 5G_RF_TRSW 5G_CTRL_TX 5G_CTRL_LNA_EN WLAN_GPIO2 BATT_VDD_4330 HSIC_STROBE_4330 HSIC_DATA_4330 CLK32K WLAN_GPIO3 WLAN_ENABLE5G_CTRL_PA_EN 5G_TSSI 5G_LNA_CHOKE BATT_VCC VDD_IO_1V8 BATT_VDD_4330 WLAN_GPIO0 WLAN_GPIO1 WLAN_GPIO4 BT_UART_CTS_N BT_HOST_WAKE BT_WAKE BT_UART_RTS_N BT_UART_RXD BT_UART_TXD BT_RESET_N5G_PA_VCTL 50_OHM 50_OHM 5G_RF 50_OHM 5G_RF_RX_BPF_IN 50_OHM 5G_RF_TX_MATCH 50_OHM 50_OHM 5G_RF_PA_OUT 50_OHM 50_OHM 50_OHM 50_OHM 5G_RF_RX_BPF_OUT 5G_RF_LNA_IN 50_OHM 50_OHM50_OHM 50_OHM 5G_RF_IN_4330 5G_RF_OUT_4330 50_OHM 50_OHM 50_OHM 50_OHM 5G_RF_PA_IN 50_OHM 50_OHM 50_OHM 50_OHM 5G_RF_TX 5G_CTRL_RX TP91 TP81 TP71 TP61 TP21TP11 TP291 TP271 TP281 TP261 TP181 TP191 TP161 TP171 TP151 U1 2 5 34 7 1 6 C81 2 C101 2 C71 2 L46 12 C33 1 2 L10 12 C35 1 2 C321 2 L11 12 L12 12 C341 2 C361 2 R7 1 2 FL7 2 4 1 3 C621 2 C60 1 2 C61 1 2 R13 1 2 C76 1 2 C751 2 C741 2 C72 1 2 C731 2 C71 1 2 C77 1 2 TP31 TP41 TP51 TP101 U9 2 51 3 6 4 R29 1 2 C84 1 2 L21 12 C83 1 2 U10 2 3 5 1 9 6 7 4 8 L22 12 PP29 1 PP30 1 C871 2 051-8773 10.0.0 63 OF 157 33 OF 48 31 32 31 313233 15 31 15 31 15 32 15 31 15 31 31 35 31 35 31 32 33 15 31 15 31 15 31 15 31 15 31 15 31 15 31 15 31 15 31 15 31
BI BI A A A A HDQ THERM PACK_NEG PACK_POS SENSE Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT NOTE: GET RID OF THE MIN_NECK_MIDTH SHOULD BE 0.2MM RES AFTER BRINGUP APN:516S0926 NP0-C0G 5% 25V 201 33PF 1000PF 10% 201 16V X7R 33PF 5% 25V NP0-C0G 201 0201 240-OHM-0.2A-0.8-OHM 0 1/20W 5% MF 201 537 0201 82PF 5% CERM 25V 37 NOSTUFF TP-P55 TP-P55 NOSTUFF NOSTUFF TP-P55 TP-P55 NOSTUFF CRITICAL BATT-J2 F-RT-SMTH SYNC_DATE=01/13/2011 POWER: BATTERY CONNECTOR SYNC_MASTER=MADHAVI MIN_NECK_WIDT=0.15MM MIN_LINE_WIDT=0.25MM BATT_SNS NET_SPACING_TYPE=ANLG =BATT_POS_CONN BATT_NTC_CONN NET_SPACING_TYPE=ANLG BATT_SWI_CONNBATTERY_SWI BATTERY_NTC NET_SPACING_TYPE=ANLG C7522 1 2 C7524 1 2 C7523 1 2 FL7500 1 2 R7541 1 2 C7525 1 2 TP75001 TP75011 TP75021 TP75031 J7500 1 2 3 4 5 6 7 8 051-8773 10.0.0 75 OF 157 34 OF 48 36 35
Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT VOUT_LED_A (BUCK3) VOUT_LED_B (BUCK3) BUCK4 LDO2 LDO7 LCM_BOOST LDO11 LDO10 LDO9 LDO12 LDO6 LDO5 LDO8 CHARGER MAIN LDO4 LDO3 BATTERY BUCK5 LDO RAILS BUCK3 CPU1V8_SW BUCK2 PROGRAMMABLE ON/OFF BUCK RAILS BUCK0 BUCK4_SW USED BY WIFI_BT LDO1 POWER CONN / ALIAS USB POWER INPUT WDIG_SW POWER ALIASES SYNC_DATE=01/13/2011SYNC_MASTER=MADHAVI =PP3V0_VIDEO_BUF =PP3V3_PORT_ACC =PP3V0_S2R_HALL_CHSW =PP2V85_CAM =PP1V1_PLL_H4 MIN_LINE_WIDTH=0.6 MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE VOLTAGE=1.1V PP1V1 MAX_NECK_LENGTH=3 MM =PP1V1_MIPI_PLL_H4 =PP1V1_USB_H4 =PP1V1_DP_PAD_DVDD_H4 =PP1V1_MIPI_H4 =PP3V0_VDDIOD_H4 =PP3V2_LDO5 =PP3V0_S2R_HALL =PP1V1_HSIC_H4 MIN_LINE_WIDTH=0.6 mm MAKE_BASE=TRUE VOLTAGE=3.0V MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.2 mm PP3V0_VIDEO =PP3V0_VIDEO_H4 =PP1V7_VA_VCP =PP3V0_GRAPE_Z2 =PP3V0_GRAPE_MARIO1 =PP3V0_GRAPE_Z1 =PP3V0_OPTICAL MIN_LINE_WIDTH=0.6MM MAX_NECK_LENGTH=3 MM PPVCC_MAIN VOLTAGE=4.7V MAKE_BASE=TRUE NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.1MM =PPVCC_MAIN_DOCK =PP1V2_HSIC_H4 NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.2MM MAKE_BASE=TRUE PP3V3_OUT VOLTAGE=3.3V MAX_NECK_LENGTH=3MM =PP1V8_AUDIO =PP1V8_CAM =PP1V8_DP_H4 =PP1V8_EDP_H4 =PP1V8_H4 =PP1V8_MIPI_H4 =PP1V8_NAND =PP1V8_NAND_H4 =PP1V8_SENSOR =PP1V8_VDDA18_TS =PP1V8_VDDIO18_H4 =PP1V8_VDDIOD_H4 VOLTAGE=1.1V PP1V8 MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM MAKE_BASE=TRUE =PPVDD_CPU_H4 VOLTAGE=1.2V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 MM MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.25 MM PP1V2_SOC =BATT_POS_CONN =BATT_POS_F_3G BATT_VCC MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR PPBATT_VCC MAKE_BASE=TRUE VOLTAGE=4.2V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.20 MM =PP1V1_EDP_PAD_DVDD_H4 =PP1V2_VDDIOD_H4 =PP1V2_S2R_DDR =PP1V2_S2R_H4 =PPVDD_SOC_H4 =PP1V8_ALWAYS =PP1V8_S2R_DDR VDD_IO_1V8 =PP3V0_GRAPE =PP3V0_IO_H4 =PP3V0_IO_MISC =PP3V2_S2R_USBMUX =PP3V3_LCD =PP3V3_NAND =PP3V3_NAND_H4 =PP3V3_USB_H4 =PP5V25_GRAPE_VDDH =PPLED_REG_A =PPLED_REG_B =PPVCC_MAIN_AUDIO =PPVCC_MAIN_LED NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 MM MAKE_BASE=TRUE VOLTAGE=1.2V PP1V2 MIN_NECK_WIDTH=0.25 MM MIN_LINE_WIDTH=0.6 MM MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR VOLTAGE=1.2V MAKE_BASE=TRUE PP1V2_S2R MIN_LINE_WIDTH=0.6MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.2MM PP1V7_VA_VCP VOLTAGE=1.7V MAKE_BASE=TRUE PP1V8_ALWAYS MIN_NECK_WIDTH=0.1 MM VOLTAGE=1.8V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.8V MAKE_BASE=TRUE PP1V8_GRAPE MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V MIN_LINE_WIDTH=0.6 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MAKE_BASE=TRUE PP1V25_CPU MIN_LINE_WIDTH=0.6MM VOLTAGE=2.85V PP2V85_CAM MAKE_BASE=TRUE MIN_NECK_WIDTH=0.2MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.2MM MAKE_BASE=TRUE VOLTAGE=3.0V PP3V0_GRAPE MIN_LINE_WIDTH=0.6MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM MAKE_BASE=TRUE VOLTAGE=3.0V NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM PP3V0_IO MIN_NECK_WIDTH=0.2 mm NET_SPACING_TYPE=PWR VOLTAGE=3.0V MAKE_BASE=TRUE MAX_NECK_LENGTH=3 MM PP3V0_OPTICAL MIN_LINE_WIDTH=0.6 MM MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM PP3V0_S2R_HALL VOLTAGE=3.0V NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM PP3V0_VIDEO_BUF MAKE_BASE=TRUE MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR VOLTAGE=3.0V MIN_NECK_WIDTH=0.2MM PP3V2_LDO5 MAKE_BASE=TRUE MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR VOLTAGE=3.2V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.6 MM MAX_NECK_LENGTH=3 MM PP3V2_S2R_USBMUX VOLTAGE=3.2V MAKE_BASE=TRUE MAX_NECK_LENGTH=3 MM PP3V3_ACC NET_SPACING_TYPE=PWR VOLTAGE=3.3V MAKE_BASE=TRUE MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM VOLTAGE=5.25V MIN_LINE_WIDTH=0.6 MM NET_SPACING_TYPE=PWR MAKE_BASE=TRUE MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.25 MM PP5V25_VLCM2 MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.6 MM VOLTAGE=20.4V MAKE_BASE=TRUE MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR PPLED_OUT_B =PP1V8_S2R_MISC MIN_NECK_WIDTH=0.15 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.8V MAKE_BASE=TRUE PP1V8_S2R =PP1V8_GRAPE =PP1V2_VDDQ_DDR MAX_NECK_LENGTH=3 MM MAKE_BASE=TRUE NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.6 MM VOLTAGE=20.4V PPLED_OUT_A PPVBUS_USB_DCIN MAKE_BASE=TRUE PPVBUS_USB_EMI MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.3MM GND MAKE_BASE=TRUE NET_SPACING_TYPE=GND MAX_NECK_LENGTH=5 MM VOLTAGE=0V 051-8773 10.0.0 80 OF 157 35 OF 48 11 27 22 26 43645 4 4 7 7 9 26 4 3645 7 19 18 17 18 26 363745 27 4 3645 19 25 7 7 4 7 10 7 12 9 26 5 9 5 9 36 45 9 3645 34 30 31 33 363945 7 8 9 13 14 8 9 5 13 14 31 33 17 18 7 9 6 28 11 16 12 9 4 16 16 19 20 22 37 3645 3645 364045 3645 3645 3645 3645 3645 3645 3645 3645 3645 3645 3645 3645 3745 3745 5 27 393645 13 14 3745 36 4527
S D G S G D TP TP BUCK5_LX VBUCK5_BYP BUCK0_LXL BUCK0_LXM BUCK4_LXL VBUCK4 VLDO10 CPU1V2_SW DSP_SW BUCK2_LXR BUCK2_LXM VBAT CHG_LX BUCK2_FB VLDO4 ACT_DIO VLDO11 VLDO12 ON_BUF VBUS_OV_N BUCK2_LXL XTAL2 XTAL1 WDIG_SW VPUMP VLDO8 VLDO6 VLDO5 VLDO3 VLDO2 VDD_LDO9 VDD_LDO4_7 VDD_LDO3_5_8 VDD_LDO2 VDD_LDO12 VDD_LDO11 VDD_LDO10 VDD_LDO1_6 VDD_BUCK0 VCC_MAIN VCC_MAIN_SENSE VBUS VBUCK3 VBUCK0_SW0_S VBUCK0_SW0_G IBAT CPU1V8_SW BUCK4_LXM BUCK4_FB BUCK3_LXM BUCK3_LXL BUCK3_FB BUCK0_FB IBAT_SENSE VLDO7 VLDO9 VDD_BUCK5 VDD_BUCK3 VDD_BUCK2 VDD_BUCK5_BYP VDD_BUCK4 VLDO1 BUCK5_FB VCENTER LDO LDOINPUTXTALVCC-MAIN SWITCHPOWER SYM 2 OF 4 BUCK USB/BAT Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT TABLE_ALT_ITEM TABLE_ALT_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD C8172- PLACE NEAR PMU 6.9 A 27 MOHM @-4.5V P-TYPE FDMC6676BZ (150MA; 2.5-3.6V) USB REVERSE VOLTAGE PROTECTION RDSON=0.0136@VGS=-2.5V R8173- PLACE NEAR PMU R8172- PLACE NEAR BMU (50MA; 2.5-3.3V) (100MA; 1.8-3.3V) (50MA; 1.5-3.3V) (200MA; 2.5-3.55V) RIGHT AT THE PIN (300MA; 2.5-3.6V) ID=12.0A NOTE: FOR NO BATTERY SITUATION ALTERNATE FOUNDRY (BYPASS RON=0.14 OHM MAX) (10MA; 2.0-3.55V) LAYOUT NOTE: PLACE RIGHT AT THE PIN (RON=0.5 OHM MAX) (RON=0.2 OHM MAX) (100MA; 1.65-1.805V; BUCK3) REVIEW THESE ESR MAX=70MOHM NOTE: CONCERNED ABOUT ESR > 20MOHM NOTE: CHANGE SOME 1UF TO 4.7UF ESR MAX=70MOHM +/- 25V LDO BYPASS 25UF (N0 DE-RATING) ADDITIONAL DISTRIBUTED VGS MAX (RON=1 OHM MAX) (300MA; 1.2-3.0V) (150MA; 2.5-3.55V) DCR=64MOHM MAX (DISTRIBUTED AND NO DE-RATING) TOTAL CAPS = ~400UF VCC_MAIN BYPASS (PLACE ONE 10UF CAP AT EACH VDD INPUT) IMAX MOSFET CHANNEL RDS(ON) LAYOUT NOTE: PLACE 14UF (N0 DE-RATING) ADDITIONAL DISTRIBUTED ADDITIONAL DISTRIBUTED 20UF (N0 DE-RATING) (200MA; 1.7-3.0V) (150MA; 0.6-1.3V) ADDITIONAL DISTRIBUTED 30UF (N0 DE-RATING) ADDITIONAL DISTRIBUTED LAYOUT NOTE - DCR=32MOHM MAX NOTE: 10V ZENER (RON=0.1 OHM MAX) 47UF (N0 DE-RATING) 10UF 20% 6.3V CRITICAL 603 X5R 201 5% 25V 18PF NP0-C0G 0201 CERM 5% 82PF 25V 20% 6.3V CRITICAL TANT-1 B15G 150UF X5R-CERM-1 6.3V 20% 22UF 603 CRITICAL NOSTUFF SM SM NOSTUFF NOSTUFF SM NOSTUFF SM SHORT-0201 NOSTUFF 201 MF 470K 1/20W 1% NOSTUFF CRITICAL LLP BZT52C10LP CRITICAL MLP3.3X3.3 FDMC6676BZ 201 1% 1/20W MF 220K 10% CRITICAL X5R-CERM 805 2.2UF 25V 25V CRITICAL X5R 805 10% 10UF 6.3V 402 CERM 10% 1UF 201 5% 18PF 25V NP0-C0G 201 NP0-C0G 25V 18PF 5% CRITICAL 2012 32.768K-20PPM-12.5PF NOSTUFF SM CRITICAL 2.2UH-20%-3.3A-0.064OHM PIME051E-SM CRITICAL SOD-123W PMEG4030ER 402 0.5 MF 1% 1/16W 20% 6.3V CRITICAL 4.7UF 402 X5R-CERM1 6.3V CRITICAL X5R 10% 2.2UF 402 6.3V CRITICAL X5R 10% 2.2UF 402 20% 6.3V CRITICAL CERM-X5R 10UF 0402 6.3V CRITICAL X5R 10% 402 2.2UF 20% 6.3V 0.22UF 0201 X5R 6.3V CRITICAL X5R 402 2.2UF 10% 20% 6.3V CRITICAL X5R-CERM1 402 4.7UF 6.3V CRITICAL 1UF 10% CERM 402 6.3V CRITICAL X5R 402 2.2UF 10% 6.3V CRITICAL X5R 2.2UF 402 10% 6.3V CRITICAL X5R 402 2.2UF 10% 402 CERM 6.3V 10% 1UF X5R-CERM-1 6.3V 20% 22UF 603 CRITICAL X5R-CERM-1 6.3V 20% 22UF 603 CRITICAL X5R-CERM-1 6.3V 20% 22UF 603 CRITICAL X5R-CERM-1 6.3V 20% 22UF 603 CRITICAL X5R-CERM-1 6.3V 20% 22UF 603 CRITICAL X5R-CERM-1 6.3V 20% 22UF 603 CRITICAL X5R-CERM-1 6.3V 20% 22UF 603 CRITICAL X5R-CERM-1 6.3V 20% 22UF 603 CRITICAL 6.3V CERM 1UF 10% 402 6.3V CERM 1UF 10% 402 20% 6.3V X5R 0201 1UF 6.3V CERM 1UF 10% 402 6.3V X5R 0.01UF 01005 10% CRITICAL FDMC6683 MLP3.3X3.3 20% 6.3V CRITICAL 0201 X5R 1UF 6.3V CRITICAL X5R 2.2UF 10% 402 NOSTUFF TP-P55 TP-P55 NOSTUFF 20% 6.3V CRITICAL PLACEMENT_NOTE=PLACE NEAR L8225.1 TANT-1 150UF B15G 20% 6.3V CRITICAL 0402 CERM-X5R 10UF 20% 6.3V CRITICAL 10UF 0402 CERM-X5R 20% 6.3V CRITICAL 0402 CERM-X5R 10UF 20% 6.3V CRITICAL 0402 CERM-X5R 10UF 20% 6.3V CRITICAL 0402 CERM-X5R 10UF 20% 6.3V CRITICAL CERM-X5R 0402 10UF 20% 6.3V CRITICAL 0402 CERM-X5R 10UF 20% 6.3V CRITICAL CERM-X5R 0402 10UF X5R-CERM-1 6.3V 20% 22UF 603 CRITICAL 20% 6.3V CRITICAL 10UF NOSTUFF 0402-1 CERM-X5R 20% 6.3V CRITICAL CERM-X5R 0402-1 10UF NOSTUFF 20% 6.3V CRITICAL 10UF CERM-X5R 0402-1 20% 6.3V CRITICAL CERM-X5R 10UF 0402-1 201 1/20W 0 MF 5% 0402 25V X7R 0.022UF 10% NOSTUFF 201 1/20W MF 499 1% CRITICAL 2.2UH-20%-1.85A-80MOHM PST25201B-SM CRITICAL PST25201B-SM 2.2UH-20%-1.85A-80MOHM CRITICAL 2.2UH-20%-1.85A-80MOHM PST25201B-SM CRITICAL 2.2UH-20%-1.85A-80MOHM PST25201B-SM CRITICAL PST25201B-SM 2.2UH-20%-1.85A-80MOHM CRITICAL 2.2UH-20%-1.85A-80MOHM PST25201B-SM PST25201B-SM 2.2UH-20%-1.85A-80MOHM CRITICAL CRITICAL 2.2UH-20%-1.85A-80MOHM PST25201B-SM CRITICAL 2.2UH-20%-1.85A-80MOHM PST25201B-SM CRITICAL PIME101E-SM 2.2UH-20%-4A-32MOHM OMIT D1974AB TFBGA 20% 6.3V CRITICAL 603 X5R 10UF 197S0299197S0392 Y8138 RADAR:8788152? L8128 RADAR:8376462152S1452 152S1292 ? SYNC_DATE=01/13/2011 POWER: AMELIA PMU SYNC_MASTER=MADHAVI PP1V2_S2R MIN_LINE_WIDTH=0.25 MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.20 MM BUCK5_FB PP3V3_OUT MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM BUCK3_FB NET_SPACING_TYPE=PWR PP3V0_IO PP1V2_SOC PP2V85_CAM PP1V2_S2R PP1V8_S2R VOLTAGE=6.0V MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR PPVBUS_USB_DCIN PPVCC_MAIN PPBATT_VCC VOLTAGE=4.6V MIN_NECK_WIDTH=0.20MM MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.30MM PMU_VPUMP PP3V3_ACC PP1V1 PP1V8_ALWAYS PP3V0_S2R_HALL PP3V0_VIDEO_BUF PP3V0_VIDEO PP3V2_LDO5 PP3V2_S2R_USBMUX PP1V7_VA_VCP PP3V0_GRAPE BATT_POS_RC VOLTAGE=4.6V MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.30MM PPVBUS_USB PP1V25_CPU PP3V0_OPTICAL BATT_SNS MIN_NECK_WIDTH=0.25 MM NET_SPACING_TYPE=PWR BUCK5_LX MIN_LINE_WIDTH=0.6 MM DIDT=TRUE NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.25 MM MIN_LINE_WIDTH=0.6 MM BUCK0_LXL DIDT=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6 MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.25 MM BUCK0_LXM MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM DIDT=TRUE BUCK4_LXL NET_SPACING_TYPE=PWR PP3V0_S2R_HALL PP1V2 DSP_SW DIDT=TRUE MIN_NECK_WIDTH=0.25 MM MIN_LINE_WIDTH=0.6 MM BUCK2_LXR NET_SPACING_TYPE=PWR BUCK2_LXM DIDT=TRUE MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.20 MM NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.25 MM BUCK2_FB PP3V0_OPTICAL PP2V85_CAM PP1V1 PP1V8_ALWAYS MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM DIDT=TRUE NET_SPACING_TYPE=PWR BUCK2_LXL NET_SPACING_TYPE=CRYSTAL PMU_EXTAL PP1V8_GRAPE PMU_VPUMP PP3V2_S2R_USBMUX PP3V3_ACC PP3V2_LDO5 PP3V0_VIDEO PP1V7_VA_VCP PP1V8_S2R NC_PMU_VBUCK0_SW0_S NC_PMU_VBUCK0_SW0_G PP1V8 NET_SPACING_TYPE=SWITCHNODE MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM SW_CHGA DIDT=TRUE DIDT=TRUE MIN_NECK_WIDTH=0.25 MM MIN_LINE_WIDTH=0.6 MM BUCK4_LXM NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.25 MM BUCK0_FB PP3V0_VIDEO_BUF PP3V0_IO PP3V0_GRAPE PPVCC_MAIN MIN_NECK_WIDTH=0.20 MM NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.25 MM BUCK4_FB MIN_NECK_WIDTH=0.25 MM DIDT=TRUE MIN_LINE_WIDTH=0.6 MM NET_SPACING_TYPE=PWR BUCK3_LXM MIN_LINE_WIDTH=0.6 MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.25 MM DIDT=TRUE BUCK3_LXL PPBATT_VCC PMU_VCENTER MIN_LINE_WIDTH=0.60MM NET_SPACING_TYPE=PWR VOLTAGE=6V MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.25MM DIDT=TRUE NC_VBUS_A_OV_L MAX_NECK_LENGTH=3 MM VOLTAGE=6.0V NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.25MM MIN_LINE_WIDTH=0.60MM PPVBUS_PROT DIDT=TRUE MIN_LINE_WIDTH=0.20MM VBUS_PROT_G NET_SPACING_TYPE=ANLG MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=ANLG MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM ACT_DIO BATT_SNS_R PMU_XTAL NET_SPACING_TYPE=CRYSTAL PP1V8_S2R PPVCC_MAIN DIDT=TRUE PP1V8_S2R C81551 2 C81541 2 C81641 2 C81631 2 C8165 1 2 C81021 2 XW8126 1 2 XW8103 1 2 XW8117 1 2 XW8113 1 2 XW8114 12 R81161 2 DZ8120 12 Q8123 5 4 1 2 3 R81301 2 C8124 1 2 C81251 2 C81351 2 C81431 2 C8142 1 2 Y8138 1 2 XW8132 1 2 L8128 1 2 D8100 1 2 R8100 12 C8148 1 2 C8146 1 2 C8145 1 2 C8144 1 2 C8149 1 2 C8169 1 2 C8153 1 2 C8152 1 2 C8151 1 2 C8150 1 2 C8167 1 2 C8168 1 2 C81361 2 C81031 2 C81081 2 C81071 2 C81181 2 C81171 2 C81211 2 C81191 2 C81201 2 C81401 2 C81391 2 C81381 2 C81411 2 C8137 1 2 Q8104 5 4 1 2 3 C81311 2 C8147 1 2 TP81331 TP81011 C8166 1 2 C81561 2 C81571 2 C81581 2 C81591 2 C81601 2 C81611 2 C81621 2 C81301 2 C81221 2 C81001 2 C81011 2 C81701 2 C81711 2 R8172 1 2 C81721 2 R8173 12 L8100 1 2 L8101 1 2 L8105 1 2 L8107 1 2 L8110 1 2 L8115 1 2 L8116 1 2 L8119 1 2 L8121 1 2 L8112 1 2 U8100 B25 D7 A11 A9 D5 A7 A6 A4 D16 A18 A16 D13 A14 A12 G3 E1 E2 F30 G30 H30 A20 A19 B21 A22 A23 A27 L2 K10 B16 B14 B18 A21 H1 H2 E29 F29 G29 H29 J29 A30 A24 A25 A26 E30 J30 A10 B10 A5 B5 A17 A13 B13 F1 F2 G1 G2 M7 M4 M6 M8 K2 M11 M5 M12 N8 N7 N3 N6 K1 N10 N4 N11 N9 N5 M10 N12 B20 B19 N1 N2 81 OF 157 10.0.0 051-8773 36 OF 48 35 36 45 45 35 45 45 353645 35 45 353645 35 36 45 35 36 45 3545 35 36 37 45 35363945 36 353645 353645 353645 353645 353645 353645 353645 353645 35364045 353645 45 445 35 45 353645 34 45 45 45 45 35 36 45 35 45 45 45 45 35 36 45 35 36 45 35 36 45 35 36 45 45 42 3545 36 35 36 45 35 36 45 35 36 45 35 36 45 35 36 40 45 35 36 45 46 46 35 45 45 45 35 36 45 35 36 45 35 36 45 35363745 45 45 45 35363945 46 45 42 353645 35363745 353645
IN IN OUT IN BI IN OUT IN IN OUT OUT OUT OUT OUT IN OUT OUT OUT OUT OUT IN IN IN IN IN IN OUT OUT IN OUT OUT OUT OUT OUT OUT OUT IN IN IN IN IN IN OUT OUT SYM 1 OF 4 I2C&DWI ANALOGMUXLCM/GRAPE LED RESETWDOG ANALOG BACKLIGHTTEMPERATURE REFERENCES DIGITALINPUT GPIO INPUT GPIO9 TDEV7 TDEV1 AMUX_A0 AMUX_A1 AMUX_A2 AMUX_A3 AMUX_AY AMUX_B2 AMUX_B0 WLED_LXB GPIO6 GPIO7 GPIO4 WLED5_A GPIO12 VREF VDD_RTC VDD_REF TDEV8 TDEV5 TCAL TBAT SHDN SDA SCL RESET* IRQ* KEEPACT IREF GPIO8 GPIO3 GPIO2 GPIO16 GPIO15 GPIO14 GPIO13 GPIO11 GPIO1 ADC_REF WLED6_B WLED6_A WLED5_B WLED4_B WLED4_A WLED3_B WLED3_A WLED1_B GPIO5 GPIO10 GPIO17 WLED2_B RESET_IN WLED2_A WLED1_A DWI_DO DWI_DI DWI_CK WLED_LXA LCM2_EN VLCM2 VLCM1 VLCM3 LX_BOOST_LCM LCM_FB VDD_LCM VDD_BOOST_LCM VDD_LCM_SW AMUX_B1 AMUX_BY AMUX_B3 TDEV6 TDEV4 TDEV2 TDEV3 VDD_REF_ABUTTON2 ACC_DET BUTTON1 FW_DPHP_DET DPHP BUTTON3 ACC_ID ADC_IN7 BRICK_ID ADC_IN31 VOUT_WLED_A VOUT_WLED_B OUT Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT (NOTE: 2MHZ) (TEMP1 - BOTTOM SIDE NEAR I/O FLEX CONN) DCR=106MOHM MAX CLOSE TO PMU PLACE XW AND CAP CLOSE TO PMUPLACE XW AND CAP CLOSE TO PMU PLACE XW AND CAP CLOSE TO PMU PLACE XW AND CAP CLOSE TO PMUPLACE XW AND CAP CLOSE TO PMU PLACE XW AND CAP (TEMP5 - TOP SIDE NEAR NAND) RESISTOR FOR TEMP CALIBRATION (INTERNAL PULL-DOWN) PLACEMENT NOTE: PLACE NEAR PIN K4 (PULLUP INSIDE H4P) (INTERNAL PULL-DOWN) (INTERNAL PULL-DOWN) (INTERNAL PULL-DOWN) PLACEMENT NOTE: PLACE NEAR PIN K24 (TEMP2 - BOTTOM SIDE NEAR PMU) (TEMP3 - BOTTOM SIDE NEAR H4G) DWI NAMING RELATIVE TO AP (TEMP4 - BOTTOM SIDE NEAR WIFI) DCR=106MOHM MAX (PPLED_OUT_B) (PPLED_OUT_A) (INTERNAL PULL-DOWN) USED BY ZEPHYR2. WHICH IS NOW POR(CPU1V8; PUSH-PULL) (1.8_S2R; PUSH-PULL; NO PD REQ’D PER BB TEAM) (1.8_S2R; PUSH-PULL; NO PD REQ’D PER BB TEAM) (1.8_S2R; PUSH-PULL) (INTERNAL PD; RISING EDGE SENSITIVE) (INTERNAL PD; RISING EDGE SENSITIVE) CAN’T BE USED FOR 32K CLK OUTPUT (FALLING EDGE SENSITIVE) 2.5V ALWAYS ON PU IN BMU (1.8_S2R; PUSH-PULL) EXT PD BY BB MUXES (1.8_S2R; PUSH-PULL) (INTERNAL PU TO 1.8_S2R) (TEMP6 BOTTOM SIDE NEAR BRIDGE FLEX) (INTERNAL PD; RISING EDGE SENSITIVE) (INTERNAL PU TO PP1V8_S2R; RISING EDGE SENSITIVE) NEED RADAR TO STOP GENERATING 32K CLOCK (BOTH EDGES SENSITIVE) EXT PU (WHAT SIGNALS DO YOU WANT MEASURED?) (INTERNAL PULLDOWN; TE ENABLE) I2C ADDRESS: 0111100X (0X78) X5R 10% 6.3V 0.01UF 01005 X5R 10% 6.3V 0.01UF 01005 0.1% 3.92K 402 MF 1/16W CRITICAL 6.3V 100PF CERM 5% 01005 201 1.00 MF 1% 1/20W 201 1% MF 1/20W 1.00 201 1% 1.00 1/20W MF 201 1.00 1% 1/20W MF 201 1% MF 1.00 1/20W 201 1% MF 1/20W 1.00 201 1/20W 200K 1% MF 402 CERM 1UF 10% 6.3V X5R 10% 201 6.3V 0.1UF 10% 6.3V 1000PF 01005 X5R-CERM X5R 10% 201 6.3V 0.1UF SOD882 PMEG2005AEL CRICITAL 542 542 542 510192242 510192242 5 4273045 445 27 1643 1643 1643 1643 1643 19 11 30 45 15 45 15 45 15 42 30 15 15 5 34 34 0603-1 10V X5R 10UF 20%20% 402 10V X5R-CERM 2.2UF CRITICAL 4.7UH-3.2A PIME051E-SM CRITICAL SOD-323 PMEG4010BEA CRITICAL X5R 603 20% 10V 10UF 10KOHM-1% 0201 CRITICAL 0201 10KOHM-1% CRITICAL 0201 10KOHM-1% CRITICAL 6.3V CERM 5% 100PF 01005 6.3V 5% 100PF CERM 01005 6.3V 01005 CERM 5% 100PF 6.3V 01005 5% 100PF CERM 39 5 10% 50V PLACEMENT_NOTE=PLACE NEAR U8100.K22 X7R 0.01UF 402 X5R 20% 0.22UF 0201 6.3V VLS201612E-SM 2.2UH-1.05A-0.195OHM CRICITAL 19 45 SM NOSTUFF SM NOSTUFF SM NOSTUFF SM NOSTUFF 25 201 MF 1/20W 1.00 1% 201 MF 1.00 1% 1/20W 201 1.00 MF 1/20W 1% 201 1% MF 1/20W 1.00201 1% MF 1/20W 1.00 201 1% MF 1/20W 1.00 1643 1643 1643 1643 1643 1643 CRITICAL PMEG4010BEA SOD-323 CRITICAL 4.7UH-3.2A PIME051E-SMCRITICAL X5R 603 20% 10UF 10V 1643 10% PLACEMENT_NOTE=PLACE NEAR U8100.K23 50V X7R 0.01UF 402 0201 10KOHM-1% 01005 5% 100PF CERM 6.3V 10KOHM-1% 0201 SM NOSTUFF SM NOSTUFF 6.3V 5% 100PF CERM 01005 10KOHM-1% 0201 CRITICAL X5R-CERM 35V 10% 4.7UF 0603 CRITICAL X5R-CERM 35V 10% 4.7UF 0603 CRITICAL X5R-CERM 35V 10% 4.7UF 0603 CRITICAL X5R-CERM 35V 10% 4.7UF 0603 CRITICAL X5R-CERM 35V 10% 4.7UF 0603 CRITICAL X5R-CERM 35V 10% 4.7UF 0603 CRITICAL X5R-CERM 35V 10% 4.7UF 0603 CRITICAL X5R-CERM 35V 10% 4.7UF 0603 CRITICAL 528 524 524 27 27 4 743 220K MF 01005 1/32W 5% NOSTUFF 30 1UF 10% 6.3V CERM 402 X5R 10% 6.3V 2.2UF 402 10% PLACEMENT_NOTE=PLACE NEAR U8100.K220.01UF 402 X7R 50V 10% 0.01UF 50V X7R 402 PLACEMENT_NOTE=PLACE NEAR U8100.K23 TFBGA D1974AB OMIT 18 42 SYNC_MASTER=MLB POWER: AMELIA PMU SYNC_DATE=01/14/2011 MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=6.0V PP6V0_LCM_VBOOST NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.4MM MAX_NECK_LENGTH=3 MM VOLTAGE=6.0V MAKE_BASE=TRUE PP6V0_LCM_HI LCM_LX DIDT=TRUE MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=SWITCHNODE NC_PMU_AMUX_B3 NC_PMU_AMUX_A3 NC_PMU_AMUX_A2 NC_PMU_AMUX_A1 HOME_EMI_L DP_AP_HPD ONOFF_L FW_ZENER_PWR RST_BB_PMU_L PM_BT_HOST_WAKE BATTERY_SWI RST_WLAN_L RST_BT_L PMU_ADC_REFNET_SPACING_TYPE=ANLG MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM CLK_32K_PMU PM_BB_HOST_WAKE PMU_IREFNET_SPACING_TYPE=ANLG PMU_VREF NET_SPACING_TYPE=ANLG CLK_32K_WLAN PMU_VDD_REF NET_SPACING_TYPE=ANLG BOARD_TEMP2_P NET_SPACING_TYPE=ANLG BOARD_TEMP5_PNET_SPACING_TYPE=ANLG NET_SPACING_TYPE=ANLGNC_BOARD_TEMP7 NC_PMU_AMUX_AY NC_PMU_AMUX_B2 NC_PMU_AMUX_B0 PMU_VDD_RTCNET_SPACING_TYPE=ANLG NET_SPACING_TYPE=ANLGNC_BOARD_TEMP8 PMU_TCAL NET_SPACING_TYPE=ANLG BATTERY_NTC PMU_SHDWN NET_SPACING_TYPE=ANLG I2C0_SDA_1V8 I2C0_SCL_1V8 RST_AP_L IRQ_PMU_L PM_KEEPACT PM_WLAN_HOST_WAKE NC_PMU_GPIO16 IRQ_HALL RST_L63_L NC_PMU_GPIO13 DOCK_BB_EN LED_IO6_B_R MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.2 MM LED_IO4_B_R MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM LED_IO4_A_R MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.2 MM LED_IO3_B_R MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.2 MM LED_IO3_A_R MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM LED_IO1_B_R MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM AUD_MIK_HS1_INT_L LED_IO2_B_R MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.2 MM RST_PMU_IN LED_IO2_A_R MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.2 MM LED_IO1_A_R MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.2 MM DWI_AP_DI DWI_AP_DO DWI_AP_CLK NC_LCM2_EN PP5V25_VLCM2 NC_VLCM1 PPVCC_MAIN NC_PMU_AMUX_B1 NC_PMU_AMUX_BY NET_SPACING_TYPE=ANLGBOARD_TEMP6_P BOARD_TEMP4_P NET_SPACING_TYPE=ANLG PORT_DOCK_ACC_DET_L SRL_L PORT_DOCK_ACCID ADC_IN7 USB_BRICKID PPLED_OUT_B BOARD_TEMP5_N BOARD_TEMP6_N PPLED_OUT_B PPLED_OUT_A BOARD_TEMP3_N =PPVCC_MAIN_LED =PPVCC_MAIN_LED BOARD_TEMP4_N MIN_NECK_WIDTH=0.1 MM LED_IO_2_A MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM LED_IO_3_A MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM LED_IO_4_A MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM LED_IO_6_A MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM LED_IO_6_B MIN_LINE_WIDTH=0.1 MM LED_IO_3_B MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM LED_IO_1_B MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM LED_IO_2_B MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM LED_IO_1_A MIN_LINE_WIDTH=0.1 MM LED_IO_4_B MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM LED_IO_5_B MIN_LINE_WIDTH=0.1 MM NET_SPACING_TYPE=ANLG BOARD_TEMP6_P BOARD_TEMP2_N BOARD_TEMP1_N MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.2 MM LED_IO5_B_R DIDT=TRUE NET_SPACING_TYPE=SWITCHNODE MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM WLED_LX_B MIN_LINE_WIDTH=0.1 MM LED_IO_5_A MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM LED_IO6_A_R MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.2 MM LED_IO5_A_R NC_PMU_GPIO12 BOARD_TEMP5_P NET_SPACING_TYPE=ANLG BOARD_TEMP1_P NET_SPACING_TYPE=ANLG BOARD_TEMP3_P NET_SPACING_TYPE=ANLG NC_PMU_GPIO17 NC_PMU_AMUX_A0 BB_VBUS_DET MIN_NECK_WIDTH=0.25 MM DIDT=TRUE NET_SPACING_TYPE=SWITCHNODEMIN_LINE_WIDTH=0.6 MM WLED_LX_A PPLED_OUT_A C82071 2 C82061 2 R8219 1 2 C8220 1 2 R8227 1 2 R8231 1 2 R8235 1 2 R8232 1 2 R8239 1 2 R8240 1 2 R82031 2 C82091 2 C82041 2 C82141 2 C82121 2 D8230 1 2 C82371 2 C8236 1 2 L8225 1 2 D8228 1 2 C8226 1 2 R8218 1 2 R8222 1 2 R8216 1 2C8215 1 2 C8221 1 2 C8217 1 2 C8223 1 2 C8201 1 2 C82101 2 L8229 1 2 XW8203 1 2 XW8202 1 2 XW8201 1 2 XW8200 1 2 R8257 1 2 R8261 1 2 R8262 1 2 R8269 1 2 R8265 1 2 R8270 1 2 D8258 1 2 L8255 1 2 C8256 1 2 C8251 1 2 R8282 1 2C8282 1 2 R8281 1 2 XW8282 1 2 XW8281 1 2 C8281 1 2 R8280 1 2 C82631 2 C82621 2 C82641 2 C82651 2 C82321 2 C82331 2 C82341 2 C82351 2 R82601 2 C82381 2 C8240 1 2 C8266 1 2 C8267 1 2 U8100 A1 M2 M26 N27 K9 J28 H28 K26 K27 K29 G28 F28 E28 D27 D29 N28 K16 K17 J17 K18 N29 M27 M28 L29 B22 D18 D15 K21 J20 K20 J19 K19 J18 B23 B24 D21 D20 D14 D19 E16 D17 M1 B27 B28 K30 N25 M24 B29 B30 C29 D30 A2 C30 D26 N30 M30 M29 L30 A29 A28 B26 D25 N26 M14 M25 K24 K4 M9 N14 M13 N13 K22 K23 L1 N15 N18 M15 N19 N16 M18 M16 N20 N17 M19 M17 M20 M21 N21 M23 N23 051-8773 10.0.0 82 OF 157 37 OF 48 45 45 46 46 46 46 27 37 46 46 46 46 46 46 46 43 43 43 43 43 43 43 43 43 46 35 45 46 35 36 45 46 46 37 30 353745 35 37 45 35 37 45 3537 3537 37 43 43 43 46 37 46 46 353745
SYM 3 OF 4 VSS_BUCK3 VSS_BUCK5 VSS_BUCK04 VSS_BUCK2 VSS_BUCK02 VSSA_BUCK2 VSS VSSA_BUCK5 VSSA_BUCK4 VSSA_BUCK3 VSSA_BUCK0 VSS VSS_WLED VSS_LCM VSS_BUCK34 VSS VSS SYM 4 OF 4 Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT TFBGA OMIT D1974AB TFBGA D1974AB OMIT SYNC_DATE=01/13/2011SYNC_MASTER=MADHAVI POWER: AMELIA VSS U8100 A3 B1 D23 D24 D4 D9 E10 E11 E12 E13 E14 E17 B2 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 B3 E3 E4 E5 E6 E7 E8 E9 F10 F11 F12 B4 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 B9 F23 F24 F25 F26 F27 C2 D10 D11 D22 A8 B8 B11 B12 B6 B7 B17 A15 B15 D1 D2 N24 M22 N22 D8 D6 E15 D12 C1 U8100 H24 H25 H26 H27 H3 H4 H5 H6 H7 H8 H9 J1 J10 J11 J12 J13 J14 J15 J16 J2 J21 J22 J23 J24 J25 J26 J27 J3 J4 J5 J6 J7 J8 J9 K11 K12 K13 K14 K15 K25 K5 K6 K7 K8 M3 F3 F4 F5 F6 F7 F8 F9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G4 G5 G6 G7 G8 G9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 051-8773 10.0.0 83 OF 157 38 OF 48
OUT OUT Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT PLACE OUTSIDE OF CAN DEBUG RESET ACCESS 300 5% 1/20W MF 201 NOSTUFF 0603 RED-50MCD-20MA NOSTUFF 1% 1/20W MF 201 1.5K NOSTUFF 37 5 5% 1/20W MF 201 300 NOSTUFF DEBUG AND MISC SYNC_DATE=10/04/2010SYNC_MASTER=ALEX =PP1V8_S2R_MISC FORCE_DFU PMU_SHDWN PPBATT_VCC PWR_ON_LED R90011 2 LED9000 A K R90021 2 R90001 2 051-8773 10.0.0 90 OF 157 39 OF 48 52735 353645
PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT PLATING SIZE: 1.4MM X 0.7MM DRILL SIZE: 1.1MM X 0.4MM PLATED THROUGH HOLES PROBE POINTS SL-1.1X0.4-1.4X0.7 TH-NSP SL-1.1X0.4-1.4X0.7 TH-NSP SL-1.1X0.4-1.4X0.7 TH-NSP SL-1.1X0.4-1.4X0.7 TH-NSP TH-NSP SL-1.1X0.4-1.4X0.7 TH-NSP SL-1.1X0.4-1.4X0.7 TH-NSP SL-1.1X0.4-1.4X0.7 TH-NSP SL-1.1X0.4-1.4X0.7 SL-1.1X0.4-1.4X0.7 TH-NSP FID 0P5SM1P0SQ-NSP FID 0P5SM1P0SQ-NSP FID 0P5SM1P0SQ-NSP FID 0P5SM1P0SQ-NSP FID 0P5SM1P0SQ-NSP FID 0P5SM1P0SQ-NSP TH-NSP SL-1.1X0.4-1.4X0.7 SL-1.1X0.4-1.4X0.7 TH-NSP P4MM SM P4MM SM SM P4MM P4MM SM P4MM SM P4MM SM P4MM SM P4MM SM P4MM SM SM P4MM P4MM SM P4MM SM P4MM SM P4MM SM P4MM SM P4MM SM P4MM SM P4MM SM P4MM SM SM P4MM SM P4MM P4MM SM P4MM SM P4MM SM P4MM SM P4MM SM SM P4MM SL-1.1X0.4-1.4X0.7 TH-NSP SYNC_DATE=10/04/2010 FCT/ICT TEST/BRACKETS SYNC_MASTER=ALEX Z1_BON_L<4> HSIC1_WLAN_DATA1 DDR0_DQ<14> DDR0_DQS_N<1> DDR0_DQS_P<0> AUD_SPKR_AMP1_PBUS CODEC_LINE_OUT_R AUD_SPKR_AMP2_PBUS CODEC_LINE_OUT_L DDR0_DQ<0> DDR0_DQS_N<0> HSIC1_WLAN_STB1 Z1_BON_L<5> Z1_B_ADR<2> Z1_B_ADR<1> Z1_B_ADR<0> Z1_MISO PP1V7_VA_VCP CONN_AUD_HEADSET_CHS_RET2 CONN_AUD_HEADSET_CHS_MIC2 CONN_AUD_HEADSET_DET AUD_HP1_DET_H AUD_HS_MIC2_RET AUD_HS_MIC1_HI AUD_HS_MIC1_RET AUD_HS_MIC2_HI CODEC_LINE_OUT_REF SL9306 1 SL9305 1 SL9304 1 SL9302 1 SL9310 1 SL9312 1 SL9313 1 SL9314 1 SL9315 1 SL9316 1 FID9300 1 FID9305 1 FID9304 1 FID9303 1 FID9302 1 FID9301 1 SL9300 1 SL9301 1 PP0 1 PP26 1 PP25 1 PP24 1 PP23 1 PP22 1 PP21 1 PP20 1 PP19 1 PP18 1 PP17 1 PP16 1 PP15 1 PP14 1 PP13 1 PP12 1 PP11 1 PP10 1 PP9 1 PP8 1 PP7 1 PP6 1 PP5 1 PP4 1 PP3 1 PP2 1 PP1 1 051-8773 10.0.0 93 OF 157 40 OF 48 17 18 4 15 42 8 13 44 8 13 44 8 13 44 20 19 21 20 19 21 8 13 44 8 13 44 4 15 42 17 18 17 18 17 18 17 18 17 18 35 36 45 23 24 23 24 23 24 23 22 23 22 23 22 23 22 23 19 21
TABLE_BOARD_INFO VERSION ALLEGRO (MIL or MM) BOARD UNITSBOARD LAYERS BOARD AREAS TABLE_SPACING_RULE_ITEM LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM MINIMUM LINE WIDTHALLOW ROUTE ON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM MINIMUM LINE WIDTHALLOW ROUTE ON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT TABLE_SPACING_RULE_HEAD MINIMUM LINE WIDTHALLOW ROUTE ON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM MINIMUM LINE WIDTHALLOW ROUTE ON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM MINIMUM LINE WIDTHALLOW ROUTE ON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MINIMUM LINE WIDTHALLOW ROUTE ON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM MINIMUM LINE WIDTHALLOW ROUTE ON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET TABLE_PHYSICAL_RULE_HEAD Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT 0.18 MM ~ 7 MIL 0.3 MM ~ 12 MIL SPACING CONSTRAINTS REGULAR SPACING RULES 0.125 MM ~ 5 MIL 0.140 MM ~ 5.5 MIL 0.075 MM ~ 3 MIL 0.089 MM ~ 3.5 MIL 0.102 MM ~ 4 MIL 0.114 MM ~ 4.5 MIL NOTES: 0.2 MM ~ 8 MIL 0.33 MM ~ 13 MIL 0.4 MM ~ 16 MIL 1.0 MM = 39.37 MIL 0.25 MM ~ 10 MIL 90 OHMS 50 OHMS DIFFERENTIAL PAIR PHYSICAL RULES BGA AREA PHYSICAL RULES SINGLE-ENDED PHYSICAL RULES 45 OHMS PHYSICAL CONSTRAINTS DEFAULT/BGA SPACING RULES 0.15 MM ~ 6 MIL*NOTE: ASSUMING 0.060MM DIELECTRIC THICKNESS POWER/GND SPACING RULES MISC PHYSICAL RULES POWER MISC MLB CONSTRAINTS SYNC_MASTER=MIKE CONSTRAINTS: MLB RULES SYNC_DATE=01/21/2011 0.050 MM 3.0 MM50_OHM_SE 0.050 MMISL3 Y Y 3.0 MM50_OHM_SE 0.088 MM 0.050 MMISL1,ISL12 LED 3:1_SPACING* * ANLG ** 3:1_SPACING SWITCHNODE ** SWITCHNODE GND_P1SPACINGGND ** * PWR_P1SPACING*PWR BGA_SPA* BGACLK BGA* BGA_SPA* 0.10MM0.2 MMLED 0.08 MM0.08 MM10 MMY* SPEAKER * 0.19MMY 10 MM 0.08 MM 0.08 MM0.3 MM 0.08 MM=STANDARD=STANDARD* 0.08 MMY =STANDARD1:1_DIFFPAIR Y 0.060 MMBGA_PHY * 0.060 MM =STANDARD 0.076 MM 0.075 MM 0.120 MM90_OHM_DIFF Y =STANDARD0.075 MM 0.120 MM0.072 MMISL5,ISL8 90_OHM_DIFF =STANDARDYISL3 0.051 MM 0.051 MM 0.120 MM 0.120 MM DEFAULT ?* 0.100 MM 3.0 MM45_OHM_SE * N 0.050 MM0.055 MM 45_OHM_SE 3.0 MMISL3 Y 0.055 MM 0.050 MM 3.0 MMY 0.060 MM45_OHM_SE 0.077 MMISL5,ISL8 3.0 MMY45_OHM_SE 0.060 MM0.110 MMISL1,ISL12 0.050 MM50_OHM_SE * N 3.0 MM0.050 MM 3.0 MMY50_OHM_SE 0.050 MMISL5,ISL8 0.062 MM 10.0 MM0.6MM* YGND_PH 0.075 MM YPWR * 0.6MM 0.25 MM 10.0 MM ?2:1_SPACING 0.114 MM* *3:1_SPACING ?0.171 MM * ?4:1_SPACING 0.228 MM 5:1_SPACING * ?0.285 MM ?STANDARD =DEFAULT* ?BGA_SPA * =DEFAULT 0.1 MMPWR_P1SPACING 900* SWITCHNODE 0.5 MM* 1000 1000SWITCHNODE 0.2 MMTOP,BOTTOM * 0.1 MM 950GND_P1SPACING DEFAULT =45_OHM_SE 30 MM 0 MM0 MMY* =45_OHM_SE 12.7 MM=DEFAULT* =DEFAULTY =DEFAULT =DEFAULTSTANDARD BGA BGA_PHY* 0.110 MMTOP,BOTTOM90_OHM_DIFF Y 0.085 MM 0.110 MM0.085 MM 0P5MM_SPACING * ?0.5 MM * ?2.5:1_SPACING 0.143 MM * ?1.5:1_SPACING 0.086 MM 0.080 MM ?*0P08_SPACING ?* 0.057 MM1:1_SPACING 0P64MM_SPACING 0.64 MM ?* MMNO_TYPE,BGA,BGA06-06 16.2TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM 051-8773 10.0.0 150 OF 157 41 OF 48
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM ELECTRICAL_CONSTRAINT_SET ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING SPACING NET_TYPE HSIC UART PHYSICAL NET_TYPE SPACING Clock Signal Constraints NET_TYPE USB ELECTRICAL_CONSTRAINT_SET PHYSICAL NET_TYPE SPACING I2S XTAL I2C JTAG ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING PHYSICAL NET_TYPE SPACING PHYSICAL DWI PHYSICAL NET_TYPE SPACING NET_TYPE SPACINGPHYSICALELECTRICAL_CONSTRAINT_SET SPACING NET_TYPE PHYSICALELECTRICAL_CONSTRAINT_SET ELECTRICAL_CONSTRAINT_SET ELECTRICAL_CONSTRAINT_SET SPACING NET_TYPE SPI PHYSICALELECTRICAL_CONSTRAINT_SET ELECTRICAL_CONSTRAINT_SET I1 I100 I101 I102 I103 I124 I125 I128 I129 I13 I130 I131 I14 I140 I141 I142 I143 I144 I145 I146 I147 I148 I149 I15 I150 I151 I152 I153 I156 I157 I158 I159 I16 I160 I161 I162 I171 I172 I173 I174 I175 I176 I177 I178 I179 I180 I181 I182 I183 I184 I185 I186 I187 I188 I189 I190 I191 I192 I193 I194 I195 I196 I197 I198 I199 I2 I20 I200 I201 I202 I203 I204 I205 I206 I207 I208 I209 I210 I211 I212 I213 I214 I215 I216 I217 I218 I219 I221 I222 I223 I224 I225 I226 I227 I228 I229 I230 I231 I232 I233 I234 I235 I236 I237 I3 I4 I5 I6 I61 I62 I63 I7 I8 I81 I82 I83 I84 I85 I88 I89 I90 I92 I93 I94 I95 I96 I98 I99 5:1_SPACING*HSIC * SPI * 2:1_SPACING* *SPI_50S 45_OHM_SE SYNC_MASTER=MIKE SYNC_DATE=01/21/2011 CONSTRAINTS: LOW SPEED BUS 1.5:1_SPACINGI2C ** 5:1_SPACING*CLK * 2:1_SPACINGDWI ** 90_OHM_DIFF*USB_90D CLK_50S * 50_OHM_SE UART_50S 50_OHM_SE* 5:1_SPACING* *CRYSTAL * 5:1_SPACING*USB JTAG * * 2:1_SPACING * 50_OHM_SEHSIC 3:1_SPACINGUART ** I2S *I2S 2:1_SPACING I2S * 3:1_SPACING* I2S_90S 45_OHM_SE* 2:1_SPACINGUARTUART * I2C_50S 50_OHM_SE* UART3_BT_RXDUART_50S UART UART_50S UART UART3_BT_RTS_L UARTUART_50S UART3_BT_CTS_L UART1_BB_RXDUART_50S UART UART0_MUX_TXDUARTUART_50S UART0_MUX_RXDUARTUART_50S UART0_AP_RXDUARTUART_50S UART0_AP_TXDUARTUART_50S UART1_BB_CTS_LUART_50S UART UART1_BB_RTS_LUART_50S UART UART3_BT_TXDUARTUART_50S UART1_BB_TXDUARTUART_50S UART6_WLAN_TXDUARTUART_50S UART6_WLAN_RXDUART_50S UART SPISPI_50S SPI2_IPC_SRDY SPI_50S SPI SPI2_IPC_SCLK SPI2_IPC_MOSISPI_50S SPI SPI_50S SPI SPI2_IPC_MISO SPI1_GRAPE_CS_LSPI_50S SPI SPI1_GRAPE_SCLKSPI_50S SPI SPI1_GRAPE_MOSISPI_50S SPI SPI1_GRAPE_MISOSPI_50S SPI ISP_CAM_0_SDAI2CI2C_50S HSIC1_WLAN_DATA1HSIC HSIC_WLAN CLK_CAM_RF_CCLKCLK_50S CLK_CAM_FF_CCLKCLK_50S CLK_CAM_RF_RCLKCLK_50S CLK_CAM_FF_RCLKCLK_50S I2S0_ASP_MCK_RCLKCLK_50S 0P2MM_SPACINGSE_50S CLK_CAM_FF_CONN CLKCLK_50S CLK_32K_GPS CLK_32K_WLANCLK_50S CLK I2CI2C_50S ISP_CAM_0_SCL I2C1_SDA_1V8_CONNI2CI2C_50S I2C_50S I2C I2C0_SCL_1V8 I2C_50S I2C I2C2_SDA_3V0 I2C_50S I2C I2C1_SCL_1V8_CONN ISP_CAM_1_SCLI2CI2C_50S DWI_AP_CLKDWI CLK_50S CLK CLK_CAM_FF I2S_50S I2S I2S2_VSP_DIN I2S I2S2_VSP_DOUTI2S_50S I2S_50S I2S I2S3_XSP_BCLK I2S_50S I2S3_XSP_DINI2S I2S_50S I2S3_XSP_LRCKI2S I2S_50S I2S I2S3_XSP_DOUT I2SI2S_50S I2S_L63_XSP_SDOUT USB USB_DK_CON_D0_PUSB_90D USB_90D USB USB_DK_CON_D0_NCLKCLK_50S CLK_32K_PMU NC_HSIC1_STB2HSIC HSIC CLK_CAM_FF_FILTCLK_50S CLK I2S0_ASP_LRCKI2S_50S I2S I2S_50S I2S I2S0_ASP_DIN I2SI2S_50S I2S0_ASP_DOUT I2SI2S_50S I2S_L63_ASP_SDOUT I2S_50S I2S2_VSP_BCLKI2S ACC_PT_DK_CON_TXUSB_90D USB ACC_PT_DK_CON_RXUSB_90D USB USB_90D USB USB11_ACC_RX_P USB_90D USB USB_BB_D_N USBUSB_90D USB11_MUX_D0_P USBUSB_90D USB11_MUX_D0_N USBUSB_90D USB11_ACC_TX_N USBUSB_90D USB_BB_D_P NC_USB_D1_NUSB_90D USB NC_USB11_D1_PUSB_90D USB NC_USB11_D1_NUSBUSB_90D TP_WLAN_USB_DPUSBUSB_90D TP_WLAN_USB_DNUSBUSB_90D USB_GPIO_DMUSBUSB_90D USB_GPIO_DP_CONNUSB_90D USB USB_GPIO_DPUSB_90D USB USB_GPIO_DM_CONNUSBUSB_90D USB USB_UART_DM_CONNUSB_90D USB_PT_DK_CON_D_PUSBUSB_90D USB_PT_DK_CON_D_NUSBUSB_90D HSIC HSIC NC_HSIC1_DATA2 HSIC_HOST_READY_WLHSIC HSIC HSIC_HOST_RDYHSICHSIC CLK_50S CLK_CAM_RFCLK CLK_CAM_RF_FILTCLK_50S CLK JTAG_AP_TDOJTAG USBUSB_90D EXTRA_USB_D1_N USB EXTRA_USB_D1_PUSB_90D NC_USB_D1_PUSBUSB_90D HSIC0_BB_DATA1HSIC HSIC_BB NC_HSIC0_STB2HSIC HSIC USB_90D USB USB_DK_D0_P USB_90D USB USB_DK_D0_N JTAG_AP_TRST_LRST I2C_50S I2C ISP_AP_1_SDA I2C1_SDA_1V8I2C_50S I2C I2C_50S I2C I2C1_SCL_1V8 I2C_50S I2C I2C0_SDA_1V8 I2CI2C_50S I2C2_SCL_3V0 I2CI2C_50S ISP_AP_0_SCL I2C_50S I2C ISP_AP_0_SDA I2C_50S I2C ISP_AP_1_SCL I2C_50S I2C I2C2_SCL_3V0_ALS I2C_50S I2C I2C2_SDA_3V0_ALS USB_90D USB EXTRA_USB11_D1_N USB_UART_DMUSBUSB_90D ISP_CAM_1_SDAI2CI2C_50S CRYSTAL XTAL_24M_I CRYSTAL XTAL_24M_O 24M_OCRYSTAL PMU_XTALCRYSTAL PMU_EXTALCRYSTAL HSIC_WLAN_RDYHSIC HSIC HSIC0_BB_STB1HSIC HSIC_BB HSIC_WLAN HSIC1_WLAN_STB1HSIC HSIC_BB_RDYHSIC HSIC HSIC HSIC_HOST_READY_WLANHSIC NC_HSIC0_DATA2HSIC HSIC USB_90D USB EXTRA_USB11_D1_P USBUSB_90D USB_UART_DP_CONN USB USB_UART_DPUSB_90D I2S0_ASP_BCLKI2S_50S I2S I2SI2S_50S I2S2_VSP_LRCK I2SI2S_50S I2S_L63_VSP_SDOUT DWI_AP_DIDWI DWI_AP_DODWI CLK_CAM_RF_CONNCLK_50S CLK I2S0_ASP_MCKCLK_50S CLK JTAG JTAG_AP_TCK JTAG_AP_TMSJTAG JTAG JTAG_AP_TDI 051-8773 10.0.0 151 OF 157 42 OF 48 5 15 5 15 5 15 5 30 11 15 11 15 5 15 5 15 5 30 5 30 5 15 5 30 5 15 5 15 5 30 5 30 5 30 5 30 5 17 5 17 5 17 5 17 24 25 4 15 40 25 25 7 7 5 19 24 25 15 37 24 25 24 25 5 10 19 22 37 5 25 24 25 24 25 5 37 7 25 5 15 19 5 15 19 5 19 5 19 5 19 5 19 19 18 37 4 46 25 5 19 5 19 5 19 19 5 15 19 27 29 27 29 11 27 11 30 4 11 4 11 11 27 11 30 4 46 4 46 4 46 27 29 27 29 4 46 5 5 30 7 25 25 4 10 4 46 4 30 4 46 4 27 4 27 4 10 45 7 25 5 10 25 5 10 25 5 10 19 22 37 5 25 7 25 7 25 7 25 10 24 25 10 24 25 24 25 4 4 4 36 36 5 15 4 30 4 15 40 5 30 5 15 4 46 5 19 5 15 19 19 5 37 5 37 24 25 5 4 27 4 27 4 10
PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD MINIMUM LINE WIDTHALLOW ROUTE ON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT MIPI NET_TYPE SPACING ANALOG VIDEO CONSTRAINTS NET_TYPE PHYSICAL PHYSICAL NET_TYPE SPACING ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACINGPHYSICAL ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING ELECTRICAL_CONSTRAINT_SET DISPLAYPORT NET_TYPE BACKLIGHT NET_TYPE ELECTRICAL_CONSTRAINT_SET SPACING NET_TYPE PHYSICAL EMBEDDED DISPLAYPORT ELECTRICAL_CONSTRAINT_SET AUDIO/SPEAKER SPACINGELECTRICAL_CONSTRAINT_SET I213 I214 I215 I219 I220 I221 I222 I223 I224 I231 I232 I233 I311 I312 I315 I316 I342 I343 I345 I346 I347 I348 I353 I354 I355 I356 I384 I385 I386 I387 I388 I389 I390 I391 I392 I393 I394 I395 I396 I397 I398 I399 I412 I413 I414 I415 I416 I417 I418 I419 I420 I421 I422 I423 I424 I425 I426 I427 I428 I429 I430 I431 I432 I433 I434 I435 I436 I437 I438 I439 I440 I441 I442 I443 I444 I445 I446 I447 I448 I449 I450 I451 I452 I453 I454 I455 I456 I457 I458 I459 I460 I461 I462 I463 I464 I465 I466 I467 I468 I469 I470 I471 I472 I473 I474 I475 I476 I477 I478 I479 I480 I481 I482 I483 I484 I485 I486 I487 I488 I489 I490 I491 I492 I493 I494 I495 I496 I497 I498 I499 I500 I501 I502 I503 I504 I505 I506 I507 I508 I510 I511 I512 I513 I514 I515 I516 I517 I518 I519 I520 I521 I522 I523 I524 I525 I526 I527 I528 I529 I530 I531 I532 I533 I534 I535 I536 I537 I538 I539 I540 I541 I542 I543 I544 I545 SYNC_DATE=01/21/2011 CONSTRAINTS: DISPLAY/AUDIO SYNC_MASTER=MIKE 1:1_DIFFPAIR*AUDIO SPEAKER*SPEAKER 5:1_SPACING* *EDP *EDP_90D 90_OHM_DIFF 50_OHM_SE*EDP_50S 3:1_SPACINGLED ** ANALOG_VIDEO 3:1_SPACING*ANALOG_VIDEO *ANALOG_VIDEO 5:1_SPACING* 4:1_SPACINGMIPI * * * 90_OHM_DIFFDP_90D **DP 5:1_SPACING =50_OHM_SE =50_OHM_SE =STANDARDVID_50S =50_OHM_SE =STANDARDY* MIPI_90D * 90_OHM_DIFF DP_50S * 50_OHM_SE ** 3:1_SPACINGAUDIO LEDLED * AUDIOAUDIO LEFT_CH_OUT_REF AUDIOAUDIO LEFT_CH_P AUDIOAUDIO MAX983X4_L_IN_P AUDIO AUDIO AUD_HP1_MLBCON_L LED LED_IO2_A_RLEDA AUDIO AUDIO HP_L AUDIOAUDIO HP_R AUDIOAUDIO CONN_AUD_HEADSET_RIGHT AUDIOAUDIO CONN_AUD_HEADSET_LEFT AUDIO AUDIO AUD_HP1_MLBCON_R AUDIOAUDIO HSMIC_R_P AUDIOAUDIO HSMIC_R_N AUDIOAUDIO HSMIC_C_P AUDIOAUDIO HSMIC_C_N AUDIO EXT_MIC_PAUDIO AUDIOAUDIO EXT_MIC_REF AUDIOAUDIO SPKRAMP_R_OUT_P AUDIO AUDIO MAX983X4_R_IN_N SPKRAMP_R_OUT_NAUDIOAUDIO RIGHT_CH_PAUDIO AUDIO AUDIOAUDIO MAX983X4_R_IN_P RIGHT_CH_OUT_PAUDIOAUDIO RIGHT_CH_OUT_REFAUDIO AUDIO SPKRAMP_L_OUT_PAUDIOAUDIO AUDIOAUDIO SPKRAMP_L_OUT_N AUDIOAUDIO MAX983X4_L_IN_N AUDIO AUDIO LEFT_CH_OUT_P EDPEDP_90D EDP_EMI_TX_P<2> EDPEDP_90D EDP_EMI_TX_P<3> EDPEDP_90D EDP_EMI_TX_P<1> EDPEDP_90D EDP_EMI_TX_P<0> EDP_EMI_TX_N<3>EDPEDP_90D EDPEDP_90D EDP_EMI_TX_N<1> EDPEDP_90D EDP_EMI_TX_N<2> EDPEDP_90D EDP_EMI_TX_N<0> EDP EDP_EMI_AUX_PEDP_90D EDP_EMI_AUX_NEDPEDP_90D EDP_90D EDP EDP_DATA_CONN_P<0> EDPEDP_90D EDP_DATA_CONN_P<2> EDP EDP_DATA_CONN_P<1>EDP_90D EDPEDP_90D EDP_DATA_CONN_P<3> EDP_90D EDP EDP_DATA_CONN_N<3> EDP_90D EDP EDP_DATA_CONN_N<2> EDP_90D EDP EDP_DATA_CONN_N<0> EDP_90D EDP EDP_DATA_CONN_N<1> EDP_90D EDP EDP_AUX_CONN_P EDP_90D EDP EDP_AUX_CONN_N EDP_90D EDP EDP_AP_TX_P<3> EDP_90D EDP EDP_AP_TX_P<2> EDP_90D EDP EDP_AP_TX_P<1> EDP_90D EDP EDP_AP_TX_N<3> EDP_90D EDP EDP_AP_TX_P<0> EDP_90D EDP EDP_AP_TX_N<2> EDP_90D EDP_AP_TX_N<1>EDP EDP_90D EDP EDP_AP_TX_N<0> EDP_AP_HPDEDP_50S EDP EDP_90D EDP EDP_AP_AUX_P EDP EDP_AP_AUX_NEDP_90D LED_IO3_A_RLED LEDA LED_IO1_B_RLED LEDB DPDP_90D DP_PT_DK_CON_AUX_P DP_EMI_TX_P<3>DP_90D DP MIPI_90D MIPI0C_AP_DATA_P<0>MIPI0C MIPI0C MIPI0C_AP_DATA_N<1>MIPI_90D MIPI0C_CAM_DATA_P<0>CAM_100DVA3 CAM MIPI_90D MIPI1C_CAM_CLK_DEBUG_PMIPI1C MIPI_90D MIPI1C_CAM_CLK_DEBUG_NMIPI1C MIPI1C_CAM_CLK_NMIPI1CMIPI_90D MIPI0C_CAM_D0_DEBUG_PMIPI_90D MIPI0C MIPI0C_CAM_DATA_P<3>MIPI_90D MIPI0C LED_IO_6_BLED LEDB LED_IO4_B_RLED LEDB LED_IO5_A_RLED LEDA DP_90D DP DP_PT_DK_CON_TX_P<3> ANALOG_VIDEO VIDEO_EMI_Y_PRVID_50S ANALOG_VIDEOVID_50S VIDEO_PT_DK_CON_CVBS_PB ANALOG_VIDEOVID_50S VIDEO_PT_DK_CON_C_Y DP_AP_TX_N<3>DPDP_90D DP_AP_TX_P<2>DPDP_90D DP_PT_DK_CON_TX_N<1>DPDP_90D VIDEO_PT_DK_CON_CVBS_PB_RVID_50S ANALOG_VIDEO VIDEO_PT_DK_CON_C_Y_RANALOG_VIDEOVID_50S ANALOG_VIDEO VIDEO_PT_DK_CON_Y_PR_RVID_50S ANALOG_VIDEO VIDEO_PT_DK_CON_Y_PRVID_50S BUF_C_YVID_50S ANALOG_VIDEO DP_PT_DK_CON_AUX_PDP_90D DP DP_PT_DK_CON_AUX_NDP_90D DP DP_EMI_TX_N<0>DP_90D DP NC_MIPI0C_AP_DATA_N<2>MIPI_90D MIPI0C NC_MIPI0C_AP_DATA_P<2>MIPI_90D MIPI0C MIPI0CMIPI_90D MIPI0C_CAM_DATA_N<3> MIPI_90D MIPI0C_CAM_D2_DEBUG_PMIPI0C MIPI0C_CAM_D3_DEBUG_PMIPI_90D MIPI0C LED LEDB LED_IO2_B_R LEDB LED_IO3_B_RLED LED_IO5_B_RLED LEDB LED_IO6_A_RLED LEDA LED_IO4_A_RLED LEDA LEDB LED_IO_2_BLED LED_IO_3_ALED LEDA LED_IO_3_BLED LEDB LED_IO_4_BLED LEDB LED_IO_5_BLED LEDB DPDP_90D DP_PT_DK_CON_TX_N<3> DP_EMI_TX_P<1>DPDP_90D DPDP_90D DP_PT_DK_CON_TX_N<2> LED_IO1_A_RLED LEDA DAC_AP_OUT2ANALOG_VIDEOVID_50S MIPI0C_AP_CLK_NMIPI_90D MIPI0C DP_AP_TX_N<0>DP_90D DP MIPI_90D MIPI0C_AP_DATA_N<0>MIPI0C MIPI0C_CAM_DATA_N<2>MIPI0CMIPI_90D MIPI0C_CAM_D1_DEBUG_NMIPI_90D MIPI0C MIPI0C_CAM_D0_DEBUG_NMIPI0CMIPI_90D DPDP_90D DP_AP_AUX_N DP_90D DP DP_AP_AUX_P VIDEO_EMI_C_YVID_50S ANALOG_VIDEO ANALOG_VIDEOVID_50S VIDEO_EMI_CVBS_PB VID_50S ANALOG_VIDEO BUF_Y_PR ANALOG_VIDEO DAC_AP_OUT3VID_50S DP_50S DP DP_AP_HPD DAC_AP_OUT1VID_50S ANALOG_VIDEO DP_AP_TX_N<1>DP_90D DP DP_AP_TX_P<1>DP_90D DP DP_PT_DK_CON_TX_N<0>DP_90D DP DP_90D DP DP_EMI_TX_P<0> DP_EMI_AUX_NDP_90D DP DP_AP_TX_P<0>DP_90D DP DP_EMI_AUX_PDP_90D DP DP_90D DP_EMI_TX_N<2>DP DP_EMI_TX_N<3>DPDP_90D DP_EMI_AUX_PDPDP_90D DP_EMI_TX_P<2>DPDP_90D DP_90D DP DP_PT_DK_CON_TX_P<2> LEDB LED_IO6_B_RLED LEDB LED_IO_1_BLED LEDA LED_IO_1_ALED LEDA LED_IO_2_ALED LED_IO_4_ALED LEDA LED_IO_5_ALED LEDA LED_IO_6_ALED LEDA DP_EMI_AUX_NDPDP_90D DP_PT_DK_CON_TX_P<1>DPDP_90D DP_90D DP_PT_DK_CON_TX_P<0>DP DP_90D DP_EMI_TX_N<1>DP DP_AP_TX_N<2>DPDP_90D DP_90D DP_AP_TX_P<3>DP MIPI0CMIPI_90D MIPI0C_CAM_DATA_N<1> MIPI0C_CAM_DATA_P<2>MIPI_90D MIPI0C MIPI0C_CAM_DATA_P<1>MIPI0CMIPI_90D MIPI0C_AP_CLK_PMIPI_90D MIPI0C MIPI_90D MIPI1C_CAM_D0_DEBUG_NMIPI1C MIPI_90D MIPI1C_CAM_D0_DEBUG_PMIPI1C MIPI1C_CAM_CLK_PMIPI1CMIPI_90D MIPI0C_CAM_CLK_DEBUG_NMIPI_90D MIPI0C MIPI0C_CAM_CLK_DEBUG_PMIPI0CMIPI_90D MIPI0C_CAM_D1_DEBUG_PMIPI_90D MIPI0C MIPI0C_CAM_D2_DEBUG_NMIPI_90D MIPI0C MIPI0C_CAM_D3_DEBUG_NMIPI_90D MIPI0C MIPI1C MIPI1C_AP_CLK_PMIPI_90D MIPI1CMIPI_90D MIPI1C_AP_CLK_N MIPI1C_CAM_DATA_P<0>CAM_100DVGA CAM MIPI1C_CAM_DATA_N<0>CAM_100DVGA CAM DPDP_90D DP_PT_DK_CON_AUX_N BUF_CVBS_PBVID_50S ANALOG_VIDEO CAM_100DVA3 CAM MIPI0C_CAM_DATA_N<0> NC_MIPI0C_AP_DATA_P<3>MIPI0CMIPI_90D MIPI0C_AP_DATA_P<1>MIPI_90D MIPI0C NC_MIPI0C_AP_DATA_N<3>MIPI_90D MIPI0C MIPI0C_CAM_CLK_NMIPI_90D MIPI0C MIPI0C_CAM_CLK_PMIPI_90D MIPI0C NC_MIPI1C_AP_DATA_N<1>MIPI_90D MIPI1C NC_MIPI1C_AP_DATA_P<1>MIPI_90D MIPI1C MIPI1C MIPI1C_AP_DATA_N<0>MIPI_90D MIPI1C MIPI1C_AP_DATA_P<0>MIPI_90D 051-8773 10.0.0 152 OF 157 43 OF 48 19 20 20 20 21 23 37 19 21 19 21 23 24 23 24 21 23 22 22 19 22 19 22 19 22 19 22 20 20 20 20 20 19 20 19 20 20 20 20 19 20 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 7 16 7 16 7 16 7 16 7 16 7 16 7 16 7 16 7 16 7 16 7 16 37 37 27 29 43 7 25 7 25 24 25 24 25 16 37 37 37 28 10 11 27 27 28 27 28 7 28 7 28 27 29 28 29 28 29 28 29 27 28 11 27 29 43 27 29 43 27 28 7 46 7 46 37 37 37 37 37 16 37 16 37 16 37 16 37 16 37 28 27 28 28 37 7 11 7 25 7 28 7 25 7 28 7 28 10 11 27 10 11 27 11 7 11 7 37 7 11 7 28 7 28 27 29 27 28 27 28 43 7 28 27 28 43 27 28 43 28 37 16 37 16 37 16 37 16 37 16 37 16 37 27 28 43 27 29 27 29 27 28 7 28 7 28 24 25 24 25 7 25 24 25 7 25 7 25 24 25 24 25 27 29 43 11 24 25 7 46 7 25 7 46 24 25 24 25 7 46 7 46 7 25 7 25
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT NAND DEV NAND PHYSICALELECTRICAL_CONSTRAINT_SET NET_TYPE SPACING DDR DDR VREF PHYSICAL SPACING NET_TYPE ELECTRICAL_CONSTRAINT_SET ELECTRICAL_CONSTRAINT_SET PHYSICAL NET_TYPE SPACING NET_TYPE PHYSICAL SPACING ELECTRICAL_CONSTRAINT_SET I100 I101 I102 I103 I104 I105 I106 I107 I108 I109 I110 I111 I112 I113 I114 I115 I116 I117 I118 I119 I120 I121 I122 I123 I124 I125 I126 I127 I128 I129 I130 I131 I132 I133 I134 I135 I136 I137 I138 I139 I140 I141 I142 I143 I144 I145 I146 I147 I148 I149 I150 I151 I152 I153 I154 I155 I156 I157 I158 I159 I160 I161 I162 I163 I164 I165 I166 I167 I168 I169 I170 I171 I172 I173 I174 I175 I176 I177 I178 I179 I180 I181 I182 I183 I184 I185 I186 I188 I189 I190 I191 I192 I193 I194 I195 I196 I197 I198 I199 I200 I201 I202 I203 I204 I205 I206 I208 I209 I210 I211 I212 I213 I214 I215 I216 I217 I218 I219 I220 I221 I222 I223 I224 I225 I226 I228 I229 I230 I231 I232 I233 I234 I235 I236 I237 I238 I239 I240 I37 I38 I39 I41 I43 I44 I47 I48 I49 I50 I51 I52 I53 I54 I55 I56 I57 I58 I59 I60 I61 I62 I63 I64 I65 I66 I67 I68 I69 I70 I71 I72 I73 I74 I75 I76 I77 I78 I79 I80 I81 I82 I83 I84 I85 I86 I87 I88 I89 I90 I91 I92 I93 I94 I95 I96 I97 I98 I99 SYNC_MASTER=MIKE SYNC_DATE=01/21/2011 CONSTRAINTS: DDR/FMI DDR_50S * 50_OHM_SE 50_OHM_SE*NAND_50S 2:1_SPACING**NAND **VREF 5:1_SPACING 3:1_SPACING**DDR * 90_OHM_DIFFDDR_90D FMI0_RE_PNAND_50S NAND0 FMI1_RE_PNAND_50S NAND1 NAND_50S FMI0_RB0_LNAND0 FMI0_RB1_LNAND_50S NAND0 FMI0_WE_LNAND_50S NAND0 FMI0_WP_LNAND_50S NAND0 NAND1 FMI1_AD<2>NAND_50S FMI1_AD<3>NAND_50S NAND1 NAND_50S FMI1_AD<1>NAND1 DDR_50S DDR DDR1_ZQ DDRDDR_50S DDR1_CSN<2..0> DDR_50S DDR DDR1_CKE<1..0> DDR_90D DDR DDR1_CK_P DDR_50S DDR0_DQ<31..24>DDR3 DDRDDR_50S DDR1_DM<3..0> DDR_50S DDR1_DQ<7..0>DDR0 FMI0_AD<0>NAND_50S NAND0 FMI0_AD<2>NAND_50S NAND0 FMI0_AD<1>NAND_50S NAND0 FMI0_ALENAND_50S NAND0 NAND_50S FMI0_AD<7>NAND0 FMI0_AD<6>NAND_50S NAND0 FMI0_CE1_LNAND_50S NAND0 FMI1_WE_LNAND_50S NAND1 FMI1_ALENAND_50S NAND1 FMI1_WP_LNAND_50S NAND1 FMI1_AD<4>NAND_50S NAND1 FMI1_AD<5>NAND_50S NAND1 FMI1_AD<7>NAND_50S NAND1 FMI1_CE0_LNAND_50S NAND1 FMI1_ALENAND_50S NAND1 FMI1_CE2_LNAND_50S NAND1 FMI1_CE3_LNAND_50S NAND1 FMI1_CE5_LNAND_50S NAND1 NAND_50S FMI1_CE6_LNAND1 FMI1_DQS_NNAND_50S NAND1 NAND_50S FMI1_AD<0>NAND1 FMI0_CE3_LNAND_50S NAND0 FMI0_CE2_LNAND_50S NAND0 FMI0_CE5_LNAND_50S NAND0 FMI0_CE4_LNAND_50S NAND0 FMI0_CE6_LNAND_50S NAND0 FMI1_CE1_LNAND_50S NAND1 FMI1_CLENAND_50S NAND1 NAND_50S SLOT0_FMI0_AD<0>NAND0 NAND_50S SLOT0_FMI0_AD<1>NAND0 NAND_50S SLOT0_FMI0_AD<2>NAND0 NAND_50S SLOT0_FMI0_AD<3>NAND0 NAND_50S SLOT0_FMI0_AD<4>NAND0 NAND_50S SLOT0_FMI0_AD<5>NAND0 NAND_50S SLOT0_FMI0_ALENAND0 NAND_50S SLOT0_FMI0_CE1_LNAND0 NAND_50S SLOT0_FMI0_CE0_LNAND0 NAND_50S SLOT0_FMI0_DQS_PNAND0 NAND_50S SLOT0_FMI0_RE_NNAND0 NAND0NAND_50S SLOT0_FMI0_WE_L NAND_50S SLOT0_FMI1_AD<0>NAND1 NAND_50S SLOT0_FMI1_AD<1>NAND1 NAND_50S SLOT0_FMI1_AD<2>NAND1 NAND_50S SLOT0_FMI1_AD<3>NAND1 NAND_50S SLOT0_FMI1_AD<5>NAND1 SLOT0_FMI1_CE1_LNAND_50S NAND1 SLOT0_FMI1_CLENAND_50S NAND1 SLOT0_FMI1_RE_NNAND_50S NAND1 SLOT1_FMI0_AD<0>NAND_50S NAND0 NAND_50S SLOT1_FMI0_AD<1>NAND0 NAND_50S SLOT1_FMI0_AD<2>NAND0 NAND_50S SLOT1_FMI0_AD<3>NAND0 NAND0NAND_50S SLOT1_FMI0_AD<4> NAND_50S SLOT1_FMI0_ALENAND0 NAND_50S SLOT1_FMI0_AD<7>NAND0 NAND_50S SLOT1_FMI0_CE0_LNAND0 NAND_50S SLOT1_FMI0_CLENAND0 NAND_50S SLOT1_FMI0_WE_LNAND0 NAND_50S SLOT1_FMI1_AD<2>NAND1 NAND1NAND_50S SLOT1_FMI1_AD<1> NAND_50S SLOT1_FMI1_AD<0>NAND1 SLOT1_FMI1_AD<6>NAND_50S NAND1 NAND_50S SLOT1_FMI1_AD<5>NAND1 NAND_50S SLOT1_FMI1_ALENAND1 NAND_50S SLOT1_FMI1_AD<7>NAND1 NAND_50S SLOT1_FMI1_CE0_LNAND1 NAND_50S SLOT1_FMI1_CE1_LNAND1 NAND_50S SLOT1_FMI1_CLENAND1 NAND_50S SLOT1_FMI1_DQS_PNAND1 NAND_50S SLOT1_FMI1_WE_LNAND1 NAND_50S SLOT1_FMI1_AD<4>NAND1 SLOT1_FMI1_AD<3>NAND_50S NAND1FMI1_RE_NNAND_50S NAND1 FMI1_CLENAND_50S NAND1 FMI1_WP_LNAND_50S NAND1 FMI0_AD<5>NAND_50S NAND0 FMI0_AD<3>NAND_50S NAND0 FMI0_AD<4>NAND_50S NAND0 FMI0_RE_NNAND_50S NAND0 NAND_50S FMI0_CE7_LNAND0 NAND_50S FMI0_CLENAND0 NAND_50S FMI0_DQS_NNAND0 NAND_50S FMI0_DQS_PNAND0 FMI1_AD<6>NAND_50S NAND1 FMI1_CE4_LNAND_50S NAND1 PWR PPVREF_DDR0_CA PWR PPVREF_DDR0_DQ PWR PPVREF_DDR1_CA PWR PPVREF_DDR1_DQ DDR3_DQS_N<3>DDR_50S DDR3 DDR3_DQS_P<3>DDR_50S DDR3 DDR3_DQS_N<2>DDR_50S DDR2 DDR3_DQ<31..24>DDR_50S DDR3 DDR3_DQ<23..16>DDR_50S DDR2 DDR3_DQS_P<2>DDR_50S DDR2 DDR3_DQS_N<1>DDR_50S DDR1 DDR3_DQ<15..8>DDR_50S DDR1 DDR3_DQS_P<1>DDR_50S DDR1 DDR3_DQS_P<0>DDR_50S DDR0 DDR3_DQS_N<0>DDR_50S DDR0 DDR3_DQ<7..0>DDR_50S DDR0 DDR_50S DDR DDR3_ZQ DDR3_CSN<2..0>DDR_50S DDR DDRDDR_50S DDR3_CKE<1..0> DDR DDR3_DM<3..0>DDR_50S DDRDDR_90D DDR3_CK_N DDRDDR_90D DDR3_CK_P DDR DDR3_CA<9..0>DDR_50S DDR_50S DDR DDR2_CA<9..0> DDR_90D DDR DDR2_CK_P DDR_50S DDR DDR2_DM<3..0> DDR_50S DDR DDR2_CKE<1..0> DDRDDR_50S DDR2_ZQ DDR_50S DDR2_DQ<7..0>DDR0 DDR_50S DDR2_DQS_N<0>DDR0 DDR_50S DDR2_DQS_P<0>DDR0 DDR_50S DDR2_DQS_P<1>DDR1 DDR_50S DDR2_DQ<15..8>DDR1 DDR_50S DDR2_DQS_P<2>DDR2 DDR_50S DDR2_DQ<23..16>DDR2 DDR_50S DDR2_DQ<31..24>DDR3 DDR_50S DDR2_DQS_P<3>DDR3 DDR_50S DDR2_DQS_N<3>DDR3 DDRDDR_50S DDR1_CA<9..0> DDR_50S DDR1_DQS_N<0>DDR0 DDR_50S DDR1_DQ<15..8>DDR1 DDR_50S DDR1_DQS_N<1>DDR1 DDR_50S DDR1_DQS_P<2>DDR2 DDR_50S DDR1_DQ<23..16>DDR2 DDR_50S DDR1_DQ<31..24>DDR3 DDR_50S DDR1_DQS_P<3>DDR3 DDR_50S DDR1_DQS_N<3>DDR3 DDR_90D DDR DDR1_CK_N DDR_50S DDR1_DQS_N<2>DDR2 DDRDDR_50S DDR2_CSN<2..0> DDR_50S DDR2_DQS_N<1>DDR1 DDR_50S DDR2_DQS_N<2>DDR2 DDR_50S DDR DDR0_CSN<2..0> DDR_50S DDR0_DQS_N<0>DDR0 DDR_50S DDR0_DQS_P<1>DDR1 DDR_50S DDR0_DQ<15..8>DDR1 DDR_50S DDR0_DQS_N<1>DDR1 DDR_50S DDR0_DQS_P<3>DDR3 DDR_50S DDR0_DQS_N<3>DDR3 DDR_50S DDR0_DQS_P<0>DDR0 DDR_50S DDR0_DQ<7..0>DDR0 DDR_50S DDR DDR0_ZQ DDRDDR_50S DDR0_DM<3..0> DDRDDR_90D DDR0_CK_P DDR_50S DDR DDR0_CKE<1..0> DDRDDR_90D DDR0_CK_N DDRDDR_50S DDR0_CA<9..0> DDR_50S DDR0_DQ<23..16>DDR2 DDR_50S DDR0_DQS_P<2>DDR2 DDR_50S DDR0_DQS_N<2>DDR2 DDR_50S DDR1_DQS_P<0>DDR0 DDR_50S DDR1_DQS_P<1>DDR1 DDR_90D DDR DDR2_CK_N SLOT0_FMI1_WE_LNAND_50S NAND1 SLOT0_FMI1_ALENAND_50S NAND1 NAND1NAND_50S SLOT0_FMI1_AD<7> NAND_50S SLOT0_FMI1_AD<4>NAND1 FMI0_CE0_LNAND_50S NAND0 NAND_50S SLOT0_FMI0_AD<6>NAND0 NAND_50S SLOT0_FMI0_AD<7>NAND0 NAND_50S SLOT0_FMI0_CLENAND0 NAND1NAND_50S SLOT0_FMI1_AD<6> NAND_50S SLOT0_FMI1_CE0_LNAND1 NAND_50S SLOT0_FMI1_DQS_PNAND1 NAND_50S SLOT1_FMI0_AD<5>NAND0 NAND_50S SLOT1_FMI0_AD<6>NAND0 NAND_50S SLOT1_FMI0_CE1_LNAND0 NAND_50S SLOT1_FMI0_DQS_PNAND0FMI1_CE7_LNAND_50S NAND1 FMI1_DQS_PNAND_50S NAND1 FMI1_RB0_LNAND_50S NAND1 NAND1 FMI1_RB1_LNAND_50S FMI1_WE_LNAND_50S NAND1 FMI1_RE_LNAND_50S NAND1 NAND_50S SLOT1_FMI1_RE_NNAND1 NAND_50S SLOT1_FMI0_RE_NNAND0 051-8773 10.0.0 153 OF 157 44 OF 48 6 12 6 12 6 12 6 12 13 8 13 8 13 8 13 8 13 8 13 8 13 6 12 6 12 6 12 6 12 6 12 6 12 6 12 6 12 44 6 12 44 44 6 12 6 12 6 12 6 12 6 12 44 6 12 6 12 6 12 44 6 12 6 12 44 44 6 12 6 12 6 12 6 12 6 12 6 12 6 12 13 45 13 45 13 45 13 45 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 13 8 13 8 13 8 13 8 13 8 13 8 13 8 13 8 13 8 13 8 13 8 14 8 14 8 14 8 13 8 13 40 8 13 8 13 40 8 13 40 8 13 8 13 8 13 40 8 13 40 13 8 13 8 13 8 13 8 13 8 13 8 13 8 13 8 13 8 13 8 13 8 14 6 12 6 12 6 12 44
Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM SPACING NET_TYPE PWR PHYSICALVOLTAGE SPACINGPHYSICAL NET_TYPE ELECTRICAL_CONSTRAINT_SET RST SPACING NET_TYPE PHYSICALELECTRICAL_CONSTRAINT_SET SPACING NET_TYPE PHYSICALELECTRICAL_CONSTRAINT_SET GND I1 I10 I11 I12 I13 I14 I15 I16 I165 I166 I167 I168 I169 I17 I170 I171 I172 I173 I174 I175 I176 I177 I178 I179 I18 I180 I181 I182 I183 I19 I199 I2 I20 I200 I201 I202 I203 I205 I206 I207 I21 I217 I219 I22 I220 I221 I223 I224 I225 I226 I23 I24 I25 I255 I256 I257 I258 I259 I26 I27 I28 I29 I3 I30 I31 I32 I33 I34 I35 I36 I37 I38 I39 I4 I40 I41 I42 I43 I44 I45 I46 I47 I49 I5 I50 I51 I52 I53 I54 I55 I56 I57 I58 I59 I6 I60 I61 I62 I63 I64 I65 I66 I67 I68 I69 I7 I70 I71 I72 I73 I74 I75 I76 I77 I78 I79 I8 I80 I81 I82 I83 I84 I85 I9 GNDGND_PH * PWR * PWR_PMU **PWR 3:1_SPACING * 4:1_SPACING*RST CONSTRAINTS: POWER / GND SYNC_MASTER=MIKE SYNC_DATE=01/21/2011 AGNDGND GND AGND_U3000GNDGND VOLTAGE=0V GND_PMUGNDGND VOLTAGE=0V GND_SPKR_AMP1GND GND VOLTAGE=0V GND_SPKR_AMP2GND GND VOLTAGE=0V GND_AUDIO_PT_DKGND GND GNDGNDGND VOLTAGE=0V GND_AUDIO_CODECGNDGND VOLTAGE=0V GND_AUDIO_HP_AMPGNDGND PPVREF_DDR0_DQ0.6V PP_PWR PWR 3.3V PWRPP_PWR PP3V3_S0_LCD_FERR BUCK0_LXLPWRPP_PWR PWR BUCK2_LXMPP_PWR PWRPP_PWR ACC_PT_DK_CON_PP3V33.3V VR_BOOST_SWPP_PWR PWR VR_BOOST_LPWRPP_PWR 6.0V PPVBUS_USB_DCINPWRPP_PWR 1.8V Z2_VDDCOREPP_PWR PWR 1.8V Z2_VDDANAPP_PWR PWR 1.8V Z1_1V8_OUTPWRPP_PWR 3.0V PP_PWR PWR MT_3V3_INT PP_PWR PWR MT_3V3_INT3.0V UD882_RSTRST UD881_RSTRST RST TP_WLAN_TRST_L SIMCRD_RSTRST RST_PMU_INRST RST RST_DET_L RST RST_BB_PMU_L RST_BB_LRST RST_AP_LRST RST_AP_1V8_LRST GSM_TXBURST_INDRST RST JTAG_AP_TRST_L DEBUG_RST_LRST DBG_RSTRST PPVREF_DDR0_CAPP_PWR PWR0.6V PPLED_BACK_REG_B20.4V PP_PWR PWR 4.2V PWRPWR500 PPBATT_VCC 6.0V PWRPP_PWR PP6V0_LCM_HI 6.0V PWRPP_PWR PPVBUS_USB PPLED_OUT_BPWRPP_PWR20.4V PP_PWR PWR BUCK4_FB 3.0V PWRPP_PWR PP3V0_S2R_HALL BUCK0_LXMPP_PWR PWR 1.1V PWRPP_PWR PP1V1_PL2_F PP_PWR PWR BUCK3_FB PP_PWR PWR BUCK3_LXL PP_PWR1.1V PWR PP1V1_PL4_F PP_PWR1.7V PWR PP1V7_VA_VCP 1.1V PWRPP_PWR PP1V1_PL3_F 1.1V PWRPP_PWR PP1V1_PL5_F 1.8V PP_PWR PWR PP1V8_GRAPE 1.8V PP_PWR PWR PP1V8_ALWAYS PP_PWR PWR1.2V PP1V2_S2R PWR1.25V PP_PWR PP1V25_CPU 1.1V PP_PWR PWR PP1V1_PLL_USB_F PP1V2_SOC1.2V PP_PWR PWR 3.0V PWR PP3V0_SENSOR_FLTPP_PWR 1.8V PP_PWR PWR PP1V8_SENSOR_FLT 2.85V PP_PWR PWR PP2V85_CAM 3.2V PP_PWR PP3V2_S2R_USBMUXPWR 3.2V PP_PWR PWR PP3V2_LDO5 PWR1.8V PP_PWR PP1V8_S2R PP_PWR1.8V PWR PP1V8_EDP_AVDD_AUX 3.3V PWR PP3V3_LCDVDD_SW_FPP_PWR 3.0V PP_PWR PWR PP3V0_VIDEO_BUF PPIO_NAND_H41.8V PWRPP_PWR 3.3V PP_PWR PWR PP3V3_ACC 20.4V PPLED_BACK_REG_APP_PWR PWR PWRPP_PWR3.0V PP3V0_S2R_HALL_FLT 3.0V PWR PP3V0_GRAPEPP_PWR 1.8V PWRPP_PWR PP1V8_DP_AVDD_AUX 1.1V PP_PWR PWR PP1V1_PL0_F PWRPP_PWR BUCK5_LX PWRPP_PWR BUCK4_LXL PWR PP1V1PP_PWR1.1V PWR0.6V PP_PWR PPVREF_DDR3_DQ 0.6V PWRPP_PWR PPVREF_DDR3_CA PWRPP_PWR PPVREF_DDR2_DQ_H40.6V PPVDDI_NAND_U14003.3V PP_PWR PWR DAC_AP_VREFPWRPP_PWR PP18V_R_GRAPEPP_PWR PWR18V PP18V_GRAPEPWRPP_PWR18V BATT_POS_RCPP_PWR PWR4.6V PP_PWR PWR0.6V PPVREF_DDR3_DQ_H4 PPVREF_DDR1_DQ_H4PWR0.6V PP_PWR PPVREF_DDR0_DQ_H40.6V PP_PWR PWR PPVREF_DDR1_CAPWR0.6V PP_PWR PPVREF_DDR1_DQPWR0.6V PP_PWR 0.6V PPVREF_DDR2_CAPWRPP_PWR PWR PPVREF_DDR2_DQ0.6V PP_PWR 1.1V PWRPP_PWR PP1V1_MIPID_PLL_F 1.1V PP_PWR PP1V8PWR PP_PWR PWR1.2V PP1V2 PWRPP_PWR PP0V4_MIPI0D0.4V PWRPP_PWR BUCK5_FB PWRPP_PWR BUCK4_LXM PP_PWR PWR BUCK2_LXR PWR BUCK2_LXLPP_PWR PWR BUCK2_FBPP_PWR PWRPP_PWR BUCK0_FB 1.8V Z2_3V3_1V8_INPP_PWR PWR RST BB_TRST_L 2.85V PP_PWR PWR PP2V85_CAM_FLT 3.0V PP_PWR PWR PP3V0_IO 3.0V PP_PWR PWR PP3V0_OPTICAL PP_PWR PWR PP5V25_VLCM25.25V 3.3V PP_PWR PWR PP3V3_OUT 3.0V PP_PWR PWR PP3V0_VIDEO RST_WLAN_LRST RST_L63_LRST GRAPE RST_GRAPE_L RST_BT_LRST PP_PWR PWR BUCK3_LXM 0.4V PP_PWR PWR PP0V4_MIPI1D 1.1V PWRPP_PWR PP1V1_PL1_F 1.8V PP_PWR PWR PP1V8_VDDA18_TS 6.0V PP6V0_LCM_VBOOSTPP_PWR PWR PWRPP_PWR PPVBUS_USB_PT_DK_CON5.0V 4.7V PPVCC_MAINPWRPP_PWR PWR1.8V PP_PWR PPVCCQ_NAND PWR PPVBUS_PROT6.0V PP_PWR PPLED_OUT_APP_PWR20.4V PWR 051-8773 10.0.0 154 OF 157 45 OF 48 17 20 20 21 27 19 21 19 21 22 13 44 16 36 36 27 29 17 17 35 36 18 18 18 18 45 18 45 4 37 5 30 30 37 5 30 4 27 30 37 4 5 15 30 4 10 42 13 44 16 35 36 39 37 4 36 35 37 36 35 36 36 4 36 36 4 35 36 40 4 4 35 36 35 36 35 36 35 36 4 35 36 10 24 26 24 26 35 36 35 36 35 36 35 36 7 16 35 36 6 9 35 36 16 24 26 35 36 7 4 36 36 35 36 14 14 8 12 7 17 17 36 8 8 8 13 44 13 44 14 14 4 35 36 35 36 7 36 36 36 36 36 36 18 24 26 35 36 35 36 35 37 35 36 35 36 15 37 19 37 6 17 15 37 36 7 4 5 37 27 29 35 36 37 12 36 35 37
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD SNS I100 I101 I102 I104 I105 I106 I107 I108 I109 I110 I117 I118 I119 I120 I121 I122 I123 I124 I126 I127 I128 I130 I131 I132 I133 I134 I135 I136 I137 I138 I139 I140 I142 I143 I144 I145 I146 I147 I148 I150 I151 I152 I153 I154 I155 I156 I157 I159 I160 I161 I162 I163 I164 I165 I166 I168 I169 I170 I171 I173 I174 I176 I177 I179 I180 I181 I183 I184 I185 I189 I190 I191 I193 I195 I196 I198 I200 I204 I205 I207 I209 I210 I212 I213 I214 I216 I217 I218 I219 I220 I221 I222 I223 I224 I225 I226 I227 I228 I229 I230 I231 I232 I233 I234 I235 I236 I237 I238 I239 I240 I241 I242 I243 I244 I245 I48 I49 I50 I51 I52 I54 I55 I56 I57 I58 I59 I60 I61 I62 I63 I64 I65 I66 I67 I68 I69 I70 I71 I72 I73 I75 I76 I77 I79 I80 I81 I82 I83 I85 I90 I91 I92 I93 I94 I95 I96 I97 I98 I99 50_OHM_SESNS_50S * SNS_90D * 90_OHM_DIFF 3:1_SPACING**SNS SYNC_MASTER=MIKE SYNC_DATE=01/21/2011 CONSTRAINTS: DEBUG NC_MIC1_FILT_CODEC NO_TEST=TRUE NC_MIC1N_CODEC NO_TEST=TRUE NC_MIC1P_CODEC NO_TEST=TRUE NC_MIC1_BIAS_CODEC NO_TEST=TRUE NC_LINE_IN2_REF_CODEC NO_TEST=TRUE NC_LINE_IN2_CODEC NO_TEST=TRUE NC_LINE_IN1_REF_CODEC NO_TEST=TRUE NC_LINE_IN1_CODEC NO_TEST=TRUE NC_VLCM1 NO_TEST=TRUE NC_LCM2_EN NO_TEST=TRUE NC_D5702_6 NO_TEST=TRUE NC_D5701_6 NO_TEST=TRUE NC_D5700_6 NO_TEST=TRUE NC_D5703_6 NO_TEST=TRUE NC_EAROUT_AN NO_TEST=TRUE NC_EAROUT_AP NO_TEST=TRUE NC_BON_L5 NO_TEST=TRUE NC_BON_L3 NO_TEST=TRUE NC_BON_L1 NO_TEST=TRUE NC_VBUS_A_OV_L NO_TEST=TRUE NC_USB_D1_N NO_TEST=TRUE NC_PMU_AMUX_BY NO_TEST=TRUE NC_PMU_AMUX_B2 NO_TEST=TRUE NC_PMU_AMUX_B3 NO_TEST=TRUE NC_PMU_AMUX_B1 NO_TEST=TRUE NC_PMU_AMUX_B0 NO_TEST=TRUE NC_PMU_AMUX_AY NO_TEST=TRUE NC_PMU_AMUX_A3 NO_TEST=TRUE NC_PMU_AMUX_A2 NO_TEST=TRUE NC_PMU_AMUX_A1 NO_TEST=TRUE NC_PMU_AMUX_A0 NO_TEST=TRUE NC_PMU_GPIO17 NO_TEST=TRUE NC_PMU_GPIO16 NO_TEST=TRUE NC_PMU_GPIO13 NO_TEST=TRUE NC_PMU_GPIO12 NO_TEST=TRUE NET_SPACING_TYPE=ANLG NO_TEST=TRUENC_BOARD_TEMP8 NC_BOARD_TEMP7 NET_SPACING_TYPE=ANLG NO_TEST=TRUE NC_PMU_VBUCK0_SW0_S NO_TEST=TRUE NC_PMU_VBUCK0_SW0_G NO_TEST=TRUE NC_DDR3_CSN<1> NO_TEST=TRUE NC_DDR2_CSN<1> NO_TEST=TRUE NC_DDR0_CSN<1> NO_TEST=TRUE NC_DDR1_CSN<1> NO_TEST=TRUE NC_DDR3_CKE<1> NO_TEST=TRUE NC_DDR0_CKE<1> NO_TEST=TRUE NC_DDR2_CKE<1> NO_TEST=TRUE NC_DDR1_CKE<1> NO_TEST=TRUE NC_JTAG_AP_TRTCK NO_TEST=TRUE NC_USB_D1_P NO_TEST=TRUE NC_USB11_D1_P NO_TEST=TRUE NC_USB11_D1_N NO_TEST=TRUE NC_USB_ANALOGTEST0 NO_TEST=TRUE NC_USB_ANALOGTEST1 NO_TEST=TRUE NC_USB_ID0 NO_TEST=TRUE NC_USB_ID1 NO_TEST=TRUE NC_USB_BRICKID1 NO_TEST=TRUE NC_I2S1_MCK NO_TEST=TRUE NC_I2S1_BCLK NO_TEST=TRUE NC_I2S1_LRCK NO_TEST=TRUE NC_I2S1_DIN NO_TEST=TRUE NC_I2S1_DOUT NO_TEST=TRUE NC_I2S2_MCK NO_TEST=TRUE NC_I2S3_MCK NO_TEST=TRUE NC_AP_GPIO216 NO_TEST=TRUE NC_SPI_FLASH_CS_L NO_TEST=TRUE NC_SDIO0_WL_DATA<2> NO_TEST=TRUE NC_SDIO0_WL_DATA<3> NO_TEST=TRUE NC_SDIO0_WL_DATA<1> NO_TEST=TRUE NC_SDIO0_WL_CMD NO_TEST=TRUE NC_SDIO0_WL_DATA<0> NO_TEST=TRUE NC_SDIO0_WL_CLK NO_TEST=TRUE NC_SWI_AP NO_TEST=TRUE NC_SPI3_CS_L NO_TEST=TRUE NC_SPI3_MOSI NO_TEST=TRUE NC_SPI3_SCLK NO_TEST=TRUE NC_SPI3_MISO NO_TEST=TRUE NC_AP_GPIO19 NO_TEST=TRUE NC_AP_GPIO31 NO_TEST=TRUE NC_AP_GPIO35 NO_TEST=TRUE NC_BOARD_ID_3 NO_TEST=TRUE NC_AP_GPIO11 NO_TEST=TRUE NC_AP_GPIO13 NO_TEST=TRUE NC_AP_GPIO7 NO_TEST=TRUE NC_AP_GPIO8 NO_TEST=TRUE NC_AP_GPIO3 NO_TEST=TRUE NC_UART4_CTS_L NO_TEST=TRUE NC_UART4_RTS_L NO_TEST=TRUE NC_UART4_RXD NO_TEST=TRUE NC_UART2_TXD NO_TEST=TRUE NC_UART2_RXD NO_TEST=TRUE NC_AP_GPIO185 NO_TEST=TRUE NC_AP_GPIO186 NO_TEST=TRUE NC_AP_GPIO3V1 NO_TEST=TRUE NC_UART6_CTSN NO_TEST=TRUE NO_TEST=TRUENC_UART6_RTSN NC_UART4_TXD NO_TEST=TRUE NO_TEST=TRUENC_HSIC0_DATA2 NC_HSIC0_STB2 NO_TEST=TRUE NC_HSIC1_DATA2 NO_TEST=TRUE NC_HSIC1_STB2 NO_TEST=TRUE NC_ISP_AP_1_PRE_FLASH NO_TEST=TRUE NC_ISP_AP_1_FLASH NO_TEST=TRUE NC_MIPI1C_AP_DATA_N<1> NO_TEST=TRUE NC_MIPI1C_AP_DATA_P<1> NO_TEST=TRUE NC_MIPI0C_AP_DATA_N<3> NO_TEST=TRUE NC_MIPI0C_AP_DATA_P<3> NO_TEST=TRUE NC_MIPI0C_AP_DATA_N<2> NO_TEST=TRUE NC_MIPI0C_AP_DATA_P<2> NO_TEST=TRUE NC_MIPI_VSYNC_H4 NO_TEST=TRUE NC_FMI3_DQS NO_TEST=TRUE NC_FMI3_RE_L NO_TEST=TRUE NC_FMI3_CLE NO_TEST=TRUE NC_FMI3_WE_L NO_TEST=TRUE NC_FMI3_ALE NO_TEST=TRUE NC_FMI3_AD<7> NO_TEST=TRUE NC_FMI3_AD<5> NO_TEST=TRUE NC_FMI3_AD<6> NO_TEST=TRUE NC_FMI3_AD<3> NO_TEST=TRUE NC_FMI3_AD<4> NO_TEST=TRUE NC_FMI3_AD<2> NO_TEST=TRUE NC_FMI3_AD<1> NO_TEST=TRUE NC_FMI3_AD<0> NO_TEST=TRUE NC_FMI3_CE7_L NO_TEST=TRUE NC_FMI3_CE6_L NO_TEST=TRUE NC_FMI3_CE4_L NO_TEST=TRUE NC_FMI3_CE5_L NO_TEST=TRUE NC_FMI3_CE2_L NO_TEST=TRUE NC_FMI3_CE3_L NO_TEST=TRUE NC_FMI3_CE1_L NO_TEST=TRUE NC_FMI3_CE0_L NO_TEST=TRUE NC_FMI2_DQS NO_TEST=TRUE NC_FMI2_WE_L NO_TEST=TRUE NC_FMI2_RE_L NO_TEST=TRUE NC_FMI2_ALE NO_TEST=TRUE NC_FMI2_CLE NO_TEST=TRUE NC_FMI2_AD<7> NO_TEST=TRUE NC_FMI2_AD<6> NO_TEST=TRUE NC_FMI2_AD<4> NO_TEST=TRUE NC_FMI2_AD<5> NO_TEST=TRUE NC_FMI2_AD<3> NO_TEST=TRUE NC_FMI2_AD<2> NO_TEST=TRUE NC_FMI2_AD<1> NO_TEST=TRUE NC_FMI2_AD<0> NO_TEST=TRUE NC_FMI2_CE5_L NO_TEST=TRUE NC_FMI2_CE3_L NO_TEST=TRUE NC_FMI2_CE2_L NO_TEST=TRUE NC_FMI2_CE1_L NO_TEST=TRUE NC_FMI1_CE7_L NO_TEST=TRUE NC_FMI1_CE6_L NO_TEST=TRUE NC_FMI1_CE5_L NO_TEST=TRUE NO_TEST=TRUENC_FMI1_CE4_L NC_FMI1_CE2_L NO_TEST=TRUE NC_FMI0_CE6_L NO_TEST=TRUE NC_FMI0_CE2_L NO_TEST=TRUE NC_FMI1_CE3_L NO_TEST=TRUE NC_FMI0_CE3_L NO_TEST=TRUE NC_FMI0_CE4_L NO_TEST=TRUE NC_FMI0_CE5_L NO_TEST=TRUE NC_FMI0_CE7_L NO_TEST=TRUE 051-8773 10.0.0 155 OF 157 46 OF 48 19 19 19 19 19 19 19 19 37 37 19 19 18 18 18 36 4 42 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 36 36 8 8 8 8 8 8 8 8 4 4 42 4 42 4 42 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 42 4 42 4 42 4 42 7 7 7 43 7 43 7 43 7 43 7 43 7 43 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT SYNC_MASTER=MIKE SYNC_DATE=01/21/2011 FUNC TEST POINTS 051-8773 10.0.0 156 OF 157 47 OF 48
Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT FUNC TEST POINTS SYNC_DATE=01/21/2011SYNC_MASTER=MIKE 051-8773 10.0.0 157 OF 157 48 OF 48

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ipad 3 full Schematic Diagram

  • 1.
    Special thanks: all forummembers and users
  • 2.
    PROPRIETARY PROPERTY OFAPPLE INC. 2 1 1245678 B D 6 5 4 3 C A NOTICE OF PROPRIETARY PROPERTY: PAGE THE INFORMATION CONTAINED HEREIN IS THE C A D R SHEET Apple Inc. THE POSESSOR AGREES TO THE FOLLOWING: DRAWING TITLE D SIZE REVISION DRAWING NUMBER BRANCH 7 B 3 II NOT TO REPRODUCE OR COPY IT I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE IV ALL RIGHTS RESERVED III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 8 10.0.0 051-8773 R5750 R35 R34 R33 R32 R0714 R0715 R0885 R0713 R0720 R3160 R12 R3107 R5502 R5501 R31 R5753 R1209 R1207 R1202 R1201 R1200 R5751 R11 R4 R3031 R3030 R3033 R3025 FL5750 FL9 FL0910 L4303 FL7500 L5610 R8216 R8222 R8282 R8218 R10234 R1720 R1020 R1621 R1620 C1129 C1131 C1137 C1136 C1195 C1181 C1197 C1196 C1108 C1110 C1138 C1111 C1135 C1198 C1130 C1166 C1134 C1161 C1160 C1132 C1194 C1020 C1021 C1710 C1109 C1133 C1174 C1165 C1173 C1164 C1163 C1159 C1162 C1023 C1182 C1183 C1177 C8210 C8169 C1199 C1176 C1190 C1184C1022 C1406 C1414 C1425 C1405 C1413 C1433 C1426 C1434 C7 C5782 C89 C3703 C3713 C0907 C3006 C39 C5804 C5805 C41 C5802 C5803 C5810 C5811 C5806 C5807 C82 C5808 C5809 C80 C81 C8212 C8204 C0903 C0908 C0956 C0910 C0909 C3050 C1404 C1430 C3110 C3108 C3106 C3109 C3031 C3030 C3041 C1410 C1424 C4213 C4211 C3105 C3604 C2251 C2250C2203 C4200 C5616 C2249 C2247 C2248 C2245 C2246 C2243 C2244 C2242 C86 C42 C47 C46 C7523 C7522 C69 C5 C75 C76 C4 C8 C74 C1251 C1250 C5500 C5501 C6 C43 C34 C85 C5766 C5765 C5712 C5711 C5710 C5708 C5707 C5706 C5705 C5703 C5702 C5701C5700 C5753 C36 C5752C5754C5755 C5751 C8164 C32 C38 D5703 D5700 D5701 L5700 L5701 L5501 L5600L5620 L5702 R0801 R1475 R0803 R0812 R0800 R0802 R0811 R0813 R0810 R1455 R0609 R0622 R0608 R0620 R1260 R0621 R0836 R0712 R0834 R0831 R0832 R3700 R3180 R3604 R3605 R2280 R2282 R2281 R2284 R2283 R2286 R2285 R2287 R0652 R0730 R0731 R0940 R1180 R0900 R0602 R0605 R0601 R0603 R0604 R0606 R0607 R3712R3702 R3713 R3703 R3603 R3621 R3601 R3602 R3608 C6100 C1661 C0957 C1652 C0950 C0621 C0632 C0952 C0631 C8137 C8207 C8206 C1188 C1760 C1750 C1105 C1125 C1104 C0634 C0609 C0601 C0602 C0603 C0600 C0635 C0953 C1752C1761 C1107 C1150 C0607 C1126 C1106C0612 C0604 C0615 C0633 C0608 C0630 C1650 C1660 C0930 C0931 C0924 C0923 C1193 C0620 C1145 C1146 C1142 C1144 C1151 C1141 C1143 C1152 C1140 C1102 C1715 C1154C1153C1155C1158 C1191 C1124 C1122 C1156 C1100 C1103C1117C1121 C3112 C2202 C0951 C0935 C0622 C8136 C8209 C8135 C8141 C8140 C8139 C8151 C8238 C50 C1170 C1172 C1171 C0614 C3618 C3617 J6000 U3 Y1 U9 U3700U3710 DZ5752 R4211 R4210 R1101R1100 R5909 R5908 R5900 R5905 R5906 R5907 R5904 R5720 R5721 R76 R28 R26 R5912 R5910 R5913 R5731 R5911 R5730 R5902 R5903 R5901 R8172 R0910 R0911 R1400 R1401 R3070 R3071 R3171 R3120 R3173 R4204 R7541 R5620 R5621 R5611 R2250 R4205 R5610 R3 R5700 R9000 R9001 R29 R27 R5710 R2290 R1252 R1253 R1250 R1251 R5740 R1452 R1453 R1472 R1473 R3101 R3032 FL5708 FL5711 FL5707 FL0600 R14 R13 R4203 R4202 R0612 R0613 R0722 R5752 R2205 R2 R7R15 R2211 R2210 R5915 R5914 R5916 R5917 R10 R9 R8265 R8227 R8232 R8261 R8257 R8239 R3190 R8130 R8173 R8116 R8203 R0956 R0955 R0957 R1454 R1474 R3066 R4213 R4212 R2203 R2204 R4201 L24 L15 L16 L23 L2 L5 L43 L12 L21 L22 L46 L10 L11 L20 L14 L5762 L17 L9 L6 L7 C87 C21 C11 C5760 C3701 C3702 C3712 C3711 C2204 C0640 C3 C4217 C7524 C5621 C5620 C2206 C563 C5623 C73 C71 C35C83 C84 C61 C77C33 C72 C44 C45 C63 C64C67 C68 C20C18 C37 C65 C66 C62 C60 C10 C8163 C2241 C2230 C2240 C7525 C5617 C5612 C2232 C5601 C5614 C0961 C0960 C4310 C3851 C3850 C8131 C8138 C1450 C1451 C1470 C1471 U4200 L2212L2222L2232L2202 FL1 U3600 J1 R5603 R5602 R5600 R5601 L5611 L5612 L5613 U3100 U8 U4 U1 FL7 U10 FL8 U6 FL10 U3003 U3101 U3009U3010 U3007 DZ5751 U1600 U1700 R2242 R2240 R2241 R5820 R5823 R0641 R1030 R6101 R6100 R3850 R3851 R1211 R1210 R3711R3701 R3801 R3800 R4312 R0702 R0705R0933 R0932 R0704 R0703 R0706 R0931 R0701 R0930 R1652 R1651 R1705 R1706 R1751 R1752 R1605 R1606 R0921 R0920 R8260 R0700 R0643 R0642 R0640 R1203 R1204 R1205 R1261 R1206 C3107 C3615 C3609 C3611 C3616 C8148 C8152 C8157 C8159 C8160 C8161 C8144 C8158 C8162 C8130 C8156 C3608 D5702 Q2200 DZ5710 DZ5711 C4216 C4212 C3803 C3801 C3802 C3607 C3601 C3602 C3852 C3605 C3854C3853 C3600 C8214 C8281 C8223 C8215 C8221 C8282 C8220 C8217 C3751 C3750 C3753 C3752 DZ8120 C0934 C0932 C0927 C0933 C0926 C0925 C8172 Q8104 R8100 R8219 D8230 DZ5720 DZ0600 L2242 L5601L5500 L5716 C2220 C2270 C2253 C2233 L2201 L2210 L2200 L5714 L5760 L5761 DZ5750 DZ5753 DZ5712 DZ5790 U5700 U5500 U5502 U5601 U5501 U5503 U5600 L4308 L4306 L4302 L4304 L4307 L4301 L5763 C3192 C1175 C1400 C1420 C3111 C3191 C4202 C4201 C3603 C3613 C3614 C1421 C1402 C1412 C1422 C1432 C1401 C8170 C8101 C8171 C8100 C3606 C5602 C5613 C5615 C5618 C3070 C3053 C3005 C3007 C1431 C1411 C8153 C8147 C8149 C8146C8167 C8150 C8168 C8240 C8145 C8266 C5780 C8201 C8251C8267 R8270 R8262 R8269 R8240 R8231 R8235 R5512 R5513 R5510 R5511 R5613 R5612 820-2996-11-BOT MLB
  • 3.
    PROPRIETARY PROPERTY OFAPPLE INC. 2 1 1245678 B D 6 5 4 3 C A NOTICE OF PROPRIETARY PROPERTY: PAGE THE INFORMATION CONTAINED HEREIN IS THE C A D R SHEET Apple Inc. THE POSESSOR AGREES TO THE FOLLOWING: DRAWING TITLE D SIZE REVISION DRAWING NUMBER BRANCH 7 B 3 II NOT TO REPRODUCE OR COPY IT I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE IV ALL RIGHTS RESERVED III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 8 10.0.0 051-8773 C8236 C5783 C1628C1629C1717 C1716C1702 C1729C1728 C1703 C17 C1616C1617 C1602 C1603 C3101 C3104 LED9000 C1720 C1701 C1714 C1727 C8155 C1620 C1601 C1627 C8154 C1614 C1192 C1157 C1123 C1101 C3009 J5900 U5730 Q2201 DZ5760 L8229 C8125 D8100 R3009 Q8123 L5757 D8228 D8258 Y8138 C1721 C1621 C1615 Y0602 C8165 C8166 C0650 C0651 C1709 C1719 C1735 C1723 C1609 C1301 C1635 C1619 C1623 C1630 C1058 C1056 C1084 C1085 C1722 C1704 C1762 C1754 C1095 C1096 C1730 C1756 C1763 C1731 C1705 C1654 C1604 C1622 C1662 C1057 C1605 C1656 C1663 C1631 C1054 J5400 J5401 J3011J3010 R0651 R5795 R0650 R5796 R1212 R1213 R1214 R1315 R1055 R1056 R1083R1084 R1754 R1753 R1095 R1096 R1755 R1756 R1654 R1653 R1053 R1655 R1656 R1054 R3181 R1320 R1372 R0804 L3000 D3000 C3000 C3001 U3000 C8124 U1410 U1400 U8100J2200 C49 C48 C70C58 C2 C1 L1 J2J3700 J7500 C8256 C8226 C8237 C3714C3704 C8265 C8264 C8263 C8262 C8235 C8234 C8233 C8232 C8122 C8121 C8120 C8119 C8118 C8117 C8108 C8107 C8103 C8102 U0600 U1300 C8143 C8142 C5722 C3700 C5750 C5721 C54 C78C53 C79 C3002 C3008 C3102 C3103 C0955 C1370 C1300 C59 C52 C56 C57 C55 C5730 C1718 C1618 C1611 C1633 C1607 C1626 C1606 C1610 C1632 C1625 C1612 C1613 C29 C1707 C1733 C1708 C1724 C1734 C1706 C1726 C1711 C1713 C1712 C1725 C1732 C1634 C1608 C1624 R0950 R1362 R1360 R1361 R1 R9002 R1021 R1022 R1721 R3012 R8280 R8281 L3700 FL6 FL4 FL2 R16 R5 R1208 R5790 R3155 R0711 R0708 R0710 R0709 L8112 L8100 L8101 L8105 L8107 L8110 L8115 L8116 L8119 L8121 L8128 L8255 L8225 820-2996-11-TOP MLB
  • 4.
    2. ALL CAPACITANCEVALUES ARE IN MICROFARADS. PROPRIETARY PROPERTY OF APPLE INC. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. DESCRIPTION OF REVISION CK APPD 2 1 1245678 B D 6 5 4 3 C A NOTICE OF PROPRIETARY PROPERTY: PAGE THE INFORMATION CONTAINED HEREIN IS THE C A D DATE R SHEET Apple Inc. THE POSESSOR AGREES TO THE FOLLOWING: DRAWING TITLE D SIZE REVISION DRAWING NUMBER BRANCH REV ECN 7 B 3 II NOT TO REPRODUCE OR COPY IT I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE IV ALL RIGHTS RESERVED III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 8 TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM DRAWING TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM J2 MLB - DVT OK2FAB Schematic / PCB #’s 1 OF 48 2011-09-06ENGINEERING RELEASED 1 OF 157 10.0.0 051-8773 10 0001231154 LAST_MODIFIED=Tue Sep 6 17:35:11 2011 X26_WIFI_MIKE_BT 09/01/20116131 WLAN BB & POWER JOE 01/19/20116030 CONNECTOR: X26 JOE 01/19/20115929 IO FLEX: B2B CONNECTOR JOE 01/19/20115828 DISPLAY PORT MISC JOE 01/19/20115727 IO FLEX: DOCK COMPONENTS MARK 01/11/20115626 SENSOR PANEL FILTERS 2 MARK 01/11/20115525 SENSOR PANEL FILTERS 1 MARK 01/11/20115424 CONNECTOR: SENSOR KAVITHA 02/03/20114323 AUDIO: HP/MIC FILTERS KAVITHA 02/03/20114222 AUDIO: DETECT/MIC BIAS KAVITHA 02/03/20113821 AUDIO: HEADPHONE OUT KAVITHA 02/03/20113720 AUDIO: SPEAKER AMP KAVITHA 02/03/20113619 AUDIO: L63B CODEC RAMSIN 12/17/20103118 GRAPE: Z1, Z2 RAMSIN 12/17/20103017 GRAPE: GROUNDHOG,CONN,BOOST JOE 01/19/20112216 VIDEO: EDP CONNECTOR ALEX 09/30/20102115 MLB ALIASES/CONNECTIONS MIKE 06/21/20101714 DDR 2 AND 3 MIKE 06/21/20101613 DDR 0 AND 1 MIKE N/A1412 NAND CHOPIN 12/10/20101311 AP: VIDEO BUFFER,BB USB MUXES ALEX N/A1210 AP: MISC & ALIASES MIKE N/A119 AP: POWER MIKE N/A108 AP: DDR JOE 01/13/201197 AP: TV,DP,MIPI MIKE N/A86 AP: NAND JOE N/A75 AP: I/Os MIKE N/A64 AP: MAIN MIKE N/A43 BOM TABLES J2DEV N/A22 BLOCK DIAGRAM: SYSTEM 15748 01/21/2011FUNC TEST POINTS MIKE 15647 01/21/2011FUNC TEST POINTS MIKE 15546 01/21/2011CONSTRAINTS: DEBUG MIKE 15445 01/21/2011CONSTRAINTS: POWER / GND MIKE 15344 01/21/2011CONSTRAINTS: DDR/FMI MIKE 15243 01/21/2011CONSTRAINTS: DISPLAY/AUDIO MIKE 15142 01/21/2011CONSTRAINTS: LOW SPEED BUS MIKE 15041 01/21/2011CONSTRAINTS: MLB RULES MIKE 9340 10/04/2010FCT/ICT TEST/BRACKETS ALEX 9039 10/04/2010DEBUG AND MISC ALEX 8338 01/13/2011POWER: AMELIA VSS MADHAVI 8237 01/14/2011POWER: AMELIA PMU MLB 8136 01/13/2011POWER: AMELIA PMU MADHAVI 8035 01/13/2011POWER ALIASES MADHAVI 7534 01/13/2011POWER: BATTERY CONNECTOR MADHAVI 6333 09/01/2011WLAN 5GHZ AND TEST POINTS X26_WIFI_MIKE_BT SYNC MASTER DATECONTENTSCSAPDF DRAWING MLB MIKE NA11 Table of Contents 6232 09/01/2011WLAN 2.4GHZ AND ANT X26_WIFI_MIKE_BT PDF CONTENTSCSA DATESYNC MASTER SYNC_MASTER=MIKE SCH,J2,MLB SYNC_DATE=NA
  • 5.
    Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT FF CAMERA VGA FLEX REAR CAMERA AUDIO UART3 UART6 MIPI1C DUAL-CORE ARM CORTEX-A9 W/ SMP HSIC1_1 ISP_I2C1 LPDDR2 HSIC0_1 AMP AMP BT_I2S CSA 61-64 CSA 60 VA5/8 FLEX VGA FLEX BUTTON FLEX HALL EFF PROX SENSOR AE2 GPU ARM A5 CPU QUAD-CORE IMG SGX543-MP2400MHZ/800MB/S 4X32-BIT 1 GBYTE EDP MIMO WIFI/BT ANT 2 WIFI ANT 1 FMI2FMI1 HSIC1 CELLULAR/GPS X26 950 MHZ H4G DWI UART5 DISPLAYPORT CSA 31 CSA 31CSA 30 CSA 75 CSA 14CSA 14 I2S2 VIDEO DAC FMI0 USB2.0 I2C0 I2C2 DOCK 30-PIN GYRO ACCELEROMETER ALS ISP_I2C0 SPI1 WIFI/BT MIPI0C USART IPCSPI2 I2C1 UART1 AMP ASP LINEOUT I2S0 Z2 AUDIO CODEC L63B TOUCH PANEL RESOLUTION: 2048X1536 GROUNDHOG Z1 VSP FMI3 XSP CSA 36 I2S3 I2C 8’H94 I2C 8’H76 PPN1.0 PPN1.0 NAND FLASHNAND FLASH CSA 57 UART0 SPEAKER PRIMARY CELLULAR ANT DIVERSITY CELLULAR ANT GPS ANT PMU AMELIA BATTERY DISPLAY/ BACKLIGHT SENSOR PANELSENSOR PANEL SENSOR PANEL SENSOR PANEL COMPASS CSA 81,82 I2C 8’H1C I2C 8’H78 I2C 8’H58 I2C 8’H72I2C 8’H32I2C 8’HD0 MIC EXT MIC MUX US/CHINA SYNC_DATE=N/ASYNC_MASTER=J2DEV BLOCK DIAGRAM: SYSTEM 051-8773 10.0.0 2 OF 157 2 OF 48
  • 6.
    CRITICAL BOM OPTION TABLE_5_HEAD PART#DESCRIPTIONQTY REFERENCE DESIGNATOR(S) TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_5_ITEM TABLE_5_ITEM CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) TABLE_BOMGROUP_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD BOM OPTIONSBOM GROUP TABLE_BOMGROUP_HEAD TABLE_5_ITEM CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) TABLE_5_ITEM TABLE_5_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) TABLE_ALT_ITEM CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_ALT_ITEM CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_5_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_ALT_ITEM TABLE_5_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) TABLE_5_ITEM CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM NAND SDRAM SCH AND BOARD P/N DEVELOPMENT_JTAG_TAP Power aliases required by this page: INTERNAL_MIC DEVELOPMENT_JTAG 16GB_PROD (NONE) 32GB_PROD JTAG_DAP SPEAKER (NONE) ALTERNATE COMMON 64GB_PROD 128GB_PROD J2 MLB DEV NAND_IO_1V8 NAND_IO-3V3 SNOTE MECHANICAL PARTS BOM options provided by this page: BARCODE LABEL/EEEE CODES PMU 32GB FLASH CONFIGURATIONS 16GB FLASH CONFIGURATIONS 64GB FLASH CONFIGURATIONS 128GB FLASH CONFIGURATIONS Page Notes Signal aliases required by this page: ALL AVAIL BOM OPTIONS SOC DEV1DEV BOM,MLB,J2085-3058 ?1 PCB1PCBF,MLB,J2820-2996 ?1 CRITICAL SCH1SCH,MLB,J2051-8773 ?1 CRITICAL U0600IC,SOC,H4G,FCBGA1225343S0533 CRITICAL1 ? SYNC_MASTER=MIKE SYNC_DATE=N/A BOM TABLES 825-7691 CRITICAL1 EEEE_J2A_64GEEEE FOR 639-2827 (J2A 64G) EEEE_DRF5 1 CRITICALEEEE FOR 639-2826 (J2A 32G) EEEE_J2A_32G825-7691 EEEE_DRF6 EEEE FOR 639-2844 (J2A 16G) EEEE_DRJQ EEEE_J2A_16G825-7691 CRITICAL1 FENCE,LARGE,TOP,MLB,J2 PD_FENCE_LARGE806-1857 CRITICAL1 806-1860 PD_FENCE_BTM1FENCE,1,BTM,MLB,J21 CRITICAL 806-1865 FENCE,2,BTM,MLB,J2 CRITICALPD_FENCE_BTM21 FENCE,SMALLER,BTM,MLB,J2 CRITICALPD_FENCE_BTM31806-2352 AUDIO SPEAKER,INTERNAL_MIC U1400,U1410128GB_PROD335S0806 335S0814 TOSHIBA 24NM PPN1.0 128GB_PRODU1400,U14102 CRITICAL335S0814 HYNIX 26NM PPN1.0 64GB 64GB_PROD U1400,U1410335S0805 335S0782 TOSHIBA 24NM PPN1.0 CRITICAL 64GB_PROD2 U1400,U1410335S0782 HYNIX 26NM PPN1.0 32GB U1400,U141032GB_PROD335S0781335S0804 TOSHIBA 24NM PPN1.0 335S0804 335S0781 16GB_PROD U1400 TOSHIBA 24NM PPN1.0 16GB_PRODU1400HYNIX 26NM PPN1.0 16GB1335S0781 CRITICAL HYNIX 26NM PPN1.0 16GB335S0781 CRITICAL2 U1400,U1410 32GB_PROD U1600,U1700SDRAM,LPDDR2,512MB,SAMSUNG 46NM2333S0579 ?CRITICAL CRITICALU8100IC,PMU,AMELIA,D1974AB1343S0561 ? EEEE_J2_128GEEEE_DKQK1 CRITICALEEEE FOR 639-1870 (J2 128G)825-7691 825-7691 EEEE FOR 639-2352 (J1 16G)1 CRITICALEEEE_DNKT EEEE_J1_16G 825-7691 CRITICALEEEE_DM2N EEEE_J1_32G1 EEEE FOR 639-2058 (J1 32G) 825-7691 EEEE FOR 639-2059 (J1 64G)1 CRITICALEEEE_DM2P EEEE_J1_64G 825-7691 EEEE FOR 639-2353 (J2 16G)1 CRITICAL EEEE_J2_16GEEEE_DNKV 825-7691 EEEE FOR 639-1572 (J2 32G)1 CRITICAL EEEE_J2_32GEEEE_DHWV 825-7691 EEEE FOR 639-1871 (J2 64G)1 CRITICALEEEE_DKQL EEEE_J2_64G COMMON,ALTERNATEBASIC CRITICALFENCE,NAND,TOP,MLB,J2806-2105 1 PD_FENCE_NAND 806-2349 1 PD_FENCE_SMALL CRITICALFENCE,SMALLER,TOP,MLB,J2 LPDDR2,HYNIX 44NM333S0579 U1600,U1700333S0580 LPDDR2,ELPIDA 45NMU1600,U1700333S0579333S0581 051-8773 10.0.0 4 OF 157 3 OF 48
  • 7.
    BI BI BI BI (1 OF 12) JTAG_TRST* XO0 XI0 WDOG USB11_DP1 USB11_DP0 USB11_DM1 USB11_DM0 USB_VDD330 USB_VBUS1 USB_VBUS0 USB_ID1 USB_ID0 USB_DVDD USB_DP0 USB_DM0 USB_BRICKID1 USB_BRICKID0 USB_ANALOGTEST1 USB_ANALOGTEST0 TST_STPCLK TST_CLKOUT TESTMODE RESET* PLL5_AVDD11 PLL4_AVDD11 PLL3_AVDD11 PLL2_AVSS11 PLL2_AVDD11 PLL1_AVSS11 PLL1_AVDD11 PLL0_AVSS11 PLL0_AVDD11 PLL_USB_AVSS11 PLL_USB_AVDD11 MIPI1D_VDD11_PLL JTAG_TRTCK JTAG_TMS JTAG_TDO JTAG_TDI JTAG_TCK JTAG_SEL HSIC1_VSS122 HSIC1_VSS121 HSIC1_VDD122 HSIC1_VDD121 HSIC1_STB2 HSIC1_STB1 HSIC1_DVSS HSIC1_DVDD HSIC1_DATA2 HSIC1_DATA1 HSIC0_VSS122 HSIC0_VSS121 HSIC0_VDD122 HSIC0_VDD121 HSIC0_STB2 HSIC0_STB1 HSIC0_DVSS HSIC0_DVDD HSIC0_DATA2 HOLD_RESET FUSE1_FSRC FAST_SCAN_CLK DDR3_CKEIN DDR2_CKEIN DDR1_CKEIN DDR0_CKEIN CFSB1 HSIC0_DATA1 USB_DM1 USB_DP1 USB_DVSS USB_VSSA0 USB_VSSAC PLL5_AVSS11 MIPI_VSS USB_REXT1 USB_REXT0 PLL4_AVSS11 PLL3_AVSS11 CFSB0 MIPI0D_VDD11_PLL (11OF 12) VSS VSS IN IN IN OUT OUT IN OUT IN OUT OUT Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT 1 - DAISY CHAIN (FOR USE WITH 5-WIRE JTAG) 34MA 7MA 10MA 7MA 14MA 2.5MA EACH 2.5MA JTAGSEL 3.16V 1.75V 1.16V 28MA 34MA BB WLAN PER RADAR #6755237 0 - PARALLEL 01005 X5R 6.3V 0.01UF 10% 01005 0.01UF 10% X5R 6.3V 10% 01005 X5R 0.01UF 6.3V 0.01UF 01005 6.3V 10% X5R 3042 3042 1540 42 154042 5% 100K 1/32W 01005 5% 01005 100K 1/32W 01005 5% 100K 1/32W 01005 100K 1/32W MF 1% 1% 10K MF 01005 1/32W 1000PF 201 16V X7R 10% 01005 MF 1/32W 0.00 0% MLB 01005 0.01UF 10% X5R 6.3V H4G FCBGA OMIT H4G FCBGA OMIT 10 10 10 10 1042 104245 10 1% 44.2 201 MF 1/20W 201 MF 1/20W 1% 44.2 01005 0% 0.00 MF 1/32W 0% 0.00 MF 01005 1/32W 0.00 1/32W MF 0% 01005 0.00 0% 1/32W MF 01005 0.00 0% 1/32W 01005 MF 0% MF 01005 1/32W 0.00 1/32W 0% 01005 MF 0.00 0201 80-OHM-0.2A-0.4-OHM GDZ-0201 GDZT2R5.1B 100K 5% 1/32W MF 01005 DEVELOPMENT_JTAG_TAP 100K 5% 1/32W MF 01005 CRITICAL SM-2 24.000MHZ-16PF-60PPM 01005 1/32W 5% 22 MF 01005 22PF CERM 16V 5% 01005 5% 22PF CERM 16V 1.00M 010051/32W 1% MF 42.2K 1% MF 1/32W 01005 01005 1/32W MF 1% 82.5K 27303745 37 37 45 6.3V X5R 10% 01005 0.01UF 6.3V CERM 402 1UF 10% 6.3V X5R 10% 0.01UF 01005 0.01UF 6.3V X5R 10% 01005 01005 0.01UF 10% X5R 6.3V 6.3V 402 CERM 10% 1UF56PF NP0-C0G 01005 6.3V 5% 6.3V X5R 10% 0.01UF 01005 6.3V X5R 01005 10% 0.01UF 6.3V X5R 10% 0.01UF 01005 0.01UF 10% 6.3V X5R 01005 0.01UF 6.3V X5R 01005 10% 10% X5R 6.3V 0.01UF 01005 0.01UF 6.3V X5R 01005 10% 01005 0.01UF 6.3V X5R 10% SYNC_MASTER=MIKE AP: MAIN SYNC_DATE=N/A PP1V1_PL4_F VOLTAGE=1.1V MIN_LINE_WIDTH=0.2MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM MIN_NECK_WIDTH=0.1MM =PP1V1_PLL_H4 NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM PP1V1_MIPID_PLL_F VOLTAGE=1.1V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM MAX_NECK_LENGTH=3MM NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.2MM VOLTAGE=1.1V MIN_NECK_WIDTH=0.1MM PP1V1_PL1_F MIN_LINE_WIDTH=0.2MM VOLTAGE=1.1V MIN_NECK_WIDTH=0.1MM PP1V1_PL2_F NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM MIN_NECK_WIDTH=0.1MM PP1V1_PL3_F VOLTAGE=1.1V MIN_LINE_WIDTH=0.2MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM PP1V1_PL5_F MIN_LINE_WIDTH=0.2MM VOLTAGE=1.1V NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM MIN_NECK_WIDTH=0.1MM MAX_NECK_LENGTH=3MM NET_SPACING_TYPE=PWR PP1V1_PLL_USB_F VOLTAGE=1.1V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM RST_PMU_IN =PP1V8_H4 24M_O PPVBUS_USB =PP3V3_USB_H4 =PP1V1_PLL_H4 =PP1V1_USB_H4 =PP1V1_MIPI_PLL_H4 =PP1V8_H4 USB_REXT0 USB_REXT1 NC_USB_D1_P NC_USB_D1_N HSIC0_BB_DATA1 AP_DDR1_CKEIN_1V2 NC_HSIC0_DATA2 HSIC0_BB_STB1 NC_HSIC0_STB2 HSIC1_WLAN_DATA1 NC_HSIC1_DATA2 HSIC1_WLAN_STB1 NC_HSIC1_STB2 JTAG_AP_SEL JTAG_AP_TCK JTAG_AP_TDI JTAG_AP_TMS NC_JTAG_AP_TRTCK NC_USB_ANALOGTEST0 NC_USB_ANALOGTEST1 USB_BRICKID NC_USB_BRICKID1 USB_DK_D0_N USB_DK_D0_P NC_USB_ID0 NC_USB_ID1 USB_AP_VBUS0 USB11_MUX_D0_N NC_USB11_D1_N AP_WDOG XTAL_24M_I XTAL_24M_O =PP1V2_HSIC_H4 MIN_LINE_WIDTH=0.2MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.1MM PP1V1_PL0_F VOLTAGE=1.1V MAX_NECK_LENGTH=3MM =PP1V1_HSIC_H4 =PP1V1_USB_H4 =PP3V3_USB_H4 USB_AP_VBUS1 JTAG_AP_TDO JTAG_AP_TRST_L TP_AP_TST_CLKOUT AP_TST_STPCLK RST_AP_L AP_FAST_SCAN_CLK AP_HOLD_RESET AP_TESTMODE RST_AP_1V8_L USB11_MUX_D0_P NC_USB11_D1_P C06151 2 R06121 2 R06131 2 R0604 1 2 R0603 1 2 R0602 1 2 R0601 1 2 R0605 1 2 R0606 1 2 R0607 1 2 FL0600 1 2 DZ06001 2 R06091 2 R0608 1 2 Y0602 2 4 1 3 R0651 1 2 C06511 2 C06501 2 R0650 12 R06421 2 R06431 2 C06121 2 C06141 2 C06081 2 C06091 2 C06211 2 C06221 2 C06201 2 C06041 2 C06031 2 C06001 2 C06011 2 C06021 2 C06071 2 C06301 2 C06311 2 C06351 2 C06341 2 C06331 2 C06321 2 R0621 1 2 R0622 1 2 R0620 1 2 R06411 2 R06401 2 C06401 2 R0652 1 2 U0600 W6 AR32 L6 F9 AK10 AF6 AR33 M31 AN28 K35 K33 N31 N30 L35 L33 P29 P31 P28 P30 H35 H33 H32 H31 J35 J33 K30 J30 K29 J29 AK29 AN29 AN30 AP30 AJ27 AR27 AM27 F27 F30 H24 H25 H26 H27 H28 H29 V33 V32 U33 U32 T33 T32 R33 R32 P33 P32 N33 N32 M33 M32 AR30 AH27 AR29 AR28 R34 P35 T34 N35 R30 J28 T28 K31 T35 M34 U35 N34 U29 L30 U28 L31 T31 K32 R31 K28 T30 J32 R28 M28 T29 L28 R29 L29 AP29 W35 Y35 U0600 A1 A2 AA8 AN10 AN13 AN16 AP1 AP2 AP6 AP9 AP12 AP15 AP18 AA10 AP22 AP25 AP28 AP31 AP34 AP35 AR1 AR2 AR5 AR8 AA12 AR11 AR14 AR17 AR19 AR34 AR35 B1 B2 B4 B9 AA14 B12 B15 B34 B35 C7 C10 C13 C16 C30 C31 AA16 C32 C33 D3 D5 D8 D11 D14 D17 D30 D33 AA18 E1 E10 E21 E22 E24 E25 E26 E27 E28 E29 AA20 E30 E33 F2 F5 F16 F17 F21 F22 F24 F33 AA22 G3 G17 G18 G19 G20 G21 AA24 AA26 A5 AA35 AB1 AB4 AB8 AB9 AB11 AB13 AB15 AB17 AB19 A8 AB21 AB23 AB25 AB27 AC3 AC8 AC10 AC18 AC20 AC22 A11 AC24 AC28 AC32 AC34 AD2 AD8 AD9 AD11 AD19 AD21 A14 AD23 AD25 AD27 AD29 AE1 AE8 AE9 AE10 AE18 AE20 A17 AE22 AE24 AE26 AF3 AF8 AF9 AF27 AF30 AF32 AF34 A34 AG2 AG8 AG9 AH1 AH8 AH9 AH10 AH11 AH12 AH17 A35 AH22 AH25 AH26 AJ5 AJ13 AJ20 AJ29 AJ32 AJ34 AK2 AA2 AL1 AM3 AM8 AM19 AM22 AM25 AM28 AM32 AM34 AN7 051-8773 10.0.0 6 OF 157 4 OF 48 45435 4545 45 45 45 45 471035 42 36 45 435 4 35 4 35 35 471035 42 46 42 46 4246 4246 4246 42 46 10 2742 1042 2742 46 46 46 46 27 42 27 42 46 46 11 42 42 46 42 42 35 45 35 4 35 4 35 45 11 42 42 46
  • 8.
    IN OUT IN OUT OUT OUT OUT IN OUT OUT OUT OUT IN OUT OUT OUT OUT IN IN IN IN BI OUT BI OUT BI OUT IN OUT OUT OUT IN OUT OUT IN IN IN IN OUT IN OUT IN IN IN IN OUT OUT OUT OUT (2 OF 12) UART5_RTXD UART3_TXD UART3_RXD UART3_RTSN UART3_CTSN UART6_TXD UART6_RXD UART6_RTSN UART6_CTSN UART4_TXD UART4_RXD UART4_RTSN UART4_CTSN UART2_TXD UART2_RXD UART2_RTSN UART2_CTSN GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32 GPIO31 GPIO30 GPIO3 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO2 GPIO19 GPIO18 GPIO17 GPIO16 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO1 GPIO0 GPIO_3V1 GPIO_3V0 UART1_TXD UART1_RXD UART1_RTSN UART0_TXD UART0_RXD TMR32_PWM2 TMR32_PWM1 TMR32_PWM0 EHCI_PORT_PWR2 GPIO9 GPIO10 UART1_CTSN EHCI_PORT_PWR1 EHCI_PORT_PWR0 SPI0_SSIN SPI0_SCLK SPI0_MOSI SPI0_MISO SWI_DATA SPI3_SSIN SPI3_SCLK SPI3_MOSI SPI3_MISO SPI2_SCLK SPI2_MOSI SPI1_SSIN SPI1_SCLK SPI1_MOSI SPI1_MISO SPDIF SDIO0_DATA3 SDIO0_DATA2 SDIO0_DATA1 SDIO0_DATA0 SDIO0_CMD SDIO0_CLK I2S3_MCK I2S3_LRCK I2S3_DOUT I2S3_DIN I2S3_BCLK I2S2_MCK I2S2_BCLK I2S1_MCK I2S1_LRCK I2S1_DIN I2S1_BCLK I2S0_MCK I2S0_DOUT I2S0_BCLK I2C2_SDA I2C2_SCL I2C1_SDA I2C1_SCL I2C0_SDA I2C0_SCL DWI_DO DWI_DI DWI_CLK I2S2_DOUT I2S2_DIN I2S2_LRCK I2S1_DOUT I2S0_LRCK I2S0_DIN VSSA18_TS VDDA18_TS SPI2_SSIN SPI2_MISO THERM_RES_EXT THERM_TEST_OUT (3OF 12) IN OUT IN IN IN OUT IN OUT IN OUT OUT IN OUT IN IN IN OUT IN IN IN IN OUT OUT IN IN IN IN OUT IN OUT IN OUT IN OUT Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT CODEC ASP - BB -> H4G - BB_DIAGS_READY (RADAR #9179861) NOTE FOR GPIO12: - AP_MODEM_WAKE (RADAR #9179861) NOTE FOR GPIO24: - H4G -> BB BUT OPTION IS HERE IN CASE THEY NEED TO BE SEPARATE DEFAULT IS TO TIE HSIC_HOST_READY TO BOTH DEVICES TO BB NEW GPIO FOR J2. FILE A RADAR TO SENSOR BOARD (ALS) CODEC VSP & BT TO SENSOR BOARD TO CHARLESTON, CODEC AND PMU CODEC XSP NOT USED TO GRAPE 3.0V IO TO BT UART TO DOCK MUX TO BB USART 15 42 15 42 15 42 15 42 34 37 1% MF 01005 1/32W 33.2 1942 1942 1942 1942 1942 151942 151942 151942 151942 1942 1942 1942 1942 10 10 10 10 19 22 37 42 10 19 22 37 42 10 25 42 10 25 42 25 42 25 42 37 42 37 42 37 42 5% 201 220K 1/20W MF 5% MF 220K 1/20W 201 201 5% 220K 1/20W MF 201 MF 100K 1/20W 5% MF 100K 1/20W 5% 201 100K MF 1/20W 5% 201 MF 1/32W 01005 100K 5%5% 201 100K 1/20W MF 30 42 30 42 30 42 5 30 42 3042 24 24 30 537 3045 15 37 19 153045 201 100K 5% 1/20W MF NOSTUFF MF 100K 201 1% 1/20W 1742 1742 1742 1742 1/32W 0% 01005 MF 0.00 10% X5R 6.3V 0.01UF 01005 01005 MF 1/32W 1% 100K NOSTUFF 0% MF 01005 1/32W 0.00 MF 0% 1/32W 01005 0.00 MF 1/20W 5% 100K 201 542 OMIT H4G FCBGAOMIT H4G FCBGA 51542 15 42 15 42 52837 52437 530 3042 526 10 18 30 10 5 539 10 10 26 26 26 26 25 11 20 10 10 10 15 42 15 42 30 42 30 42 30 42 30 42 5 24 37 30 45 SYNC_MASTER=JOE SYNC_DATE=N/A AP: I/Os IRQ_CODEC_L NC_AP_GPIO7 NC_AP_GPIO8 PM_RADIO_ON RST_DET_L HSIC_BB_RDY ONOFF_L HOME_EMI_L GPIO42_BRD_REV2 IRQ_ALS_INT_L AUD_SPKRAMP_MUTE_L PORT_DOCK_VIDEO_AMP_EN RST_BB_L SRL_L NC_BOARD_ID_3 IRQ_ACCEL_INT1_L UART0_AP_TXD UART0_AP_RXD IRQ_PMU_L PM_BT_WAKE =PP1V8_VDDA18_TS HSIC_HOST_RDY =PP1V8_VDDIOD_H4 UART1_BB_RTS_L HSIC_HOST_READY_WLAN HSIC_HOST_RDY =PP1V8_S2R_MISC =PP1V8_ALWAYS =PP1V8_S2R_MISC SRL_L ONOFF_L HOME_EMI_L HSIC_WLAN_RDY HSIC_HOST_READY_WL GPIO40_BRD_REV0 GPIO41_BRD_REV1 UART1_BB_CTS_L NC_AP_GPIO185 NC_AP_GPIO186 TP_LED_STROBE_EN UART1_BB_RXD UART1_BB_TXD NC_AP_GPIO11 SPI2_IPC_SRDY NC_AP_GPIO13 AUD_VOL_DOWN_L GSM_TXBURST_IND IRQ_GYRO_INT2 BOOT_CONFIG_0 NC_AP_GPIO19 AUD_VOL_UP_L IRQ_GRAPE_HOST_INT_L PM_KEEPACT BB_EMERGENCY_DWLD IPC_GPIO_X26 BOOT_CONFIG_1 FORCE_DFU BOOT_CONFIG_2 BOOT_CONFIG_3 NC_AP_GPIO3 NC_UART2_RXD NC_UART2_TXD NC_UART4_CTS_L NC_UART4_RTS_L NC_UART4_RXD NC_UART4_TXD NC_UART6_CTSN NC_UART6_RTSN UART3_BT_CTS_L UART3_BT_RTS_L UART3_BT_RXD UART3_BT_TXD BATTERY_SWI TP_THERM_TEST_OUT THERM_RES_EXT SPI2_IPC_MISO PP1V8_VDDA18_TS NC_I2S1_DOUT I2S2_VSP_LRCK I2S2_VSP_DIN I2S2_VSP_DOUT DWI_AP_DI DWI_AP_DO I2C0_SCL_1V8 I2C0_SDA_1V8 I2C1_SCL_1V8 I2C2_SCL_3V0 I2C2_SDA_3V0NC_I2S1_BCLK NC_I2S1_DIN NC_I2S1_LRCK NC_I2S1_MCK I2S2_VSP_BCLK NC_I2S2_MCK I2S3_XSP_BCLK I2S3_XSP_DIN I2S3_XSP_DOUT I2S3_XSP_LRCK NC_I2S3_MCK NC_SDIO0_WL_CLK NC_SDIO0_WL_CMD NC_SDIO0_WL_DATA<0> NC_SDIO0_WL_DATA<1> NC_SDIO0_WL_DATA<2> NC_SDIO0_WL_DATA<3> NC_AP_GPIO216 SPI1_GRAPE_MISO SPI1_GRAPE_MOSI SPI1_GRAPE_SCLK SPI1_GRAPE_CS_L SPI2_IPC_MOSI SPI2_IPC_SCLK NC_SPI3_MISO NC_SPI3_MOSI NC_SPI3_SCLK NC_SPI3_CS_L NC_SWI_AP BOARD_ID_2 BOARD_ID_1 BOARD_ID_0 NC_SPI_FLASH_CS_L I2C1_SDA_1V8 DWI_AP_CLK IRQ_GYRO_INT1 IRQ_PROX_INT_L NC_AP_GPIO31 HSIC_HOST_READY_WL NC_AP_GPIO35 HSIC_WLAN_RDY NC_AP_GPIO3V1 DFU_STATUS IRQ_ACCEL_INT2_L UART6_WLAN_RXD UART6_WLAN_TXD PM_RADIO_ON DFU_STATUS FORCE_DFU IRQ_GYRO_INT2 PM_KEEPACT I2S0_ASP_MCK_R I2S0_ASP_BCLK I2S0_ASP_LRCK I2S0_ASP_DIN I2S0_ASP_DOUT I2S0_ASP_MCK R0700 1 2 R0708 1 2 R0709 1 2 R0710 1 2 R07151 2 R07141 2 R07131 2 R07121 2 R07111 2 R07201 2 R07221 2 R1180 1 2 C11881 2 R10301 2 R0730 1 2 R0731 1 2 R08851 2 U0600 AG26 AE15 AE16 AJ14 AK15 AG17 AD13 AK17 AE14 AL17 AF17 AL18 AK18 AJ18 AD12 AL16 AH18 AF18 AM18 AN18 AN19 AG18 AP20 AN20 AR20 AR21 AG14 AP21 AK19 AN21 AH19 AG19 AJ19 AR22 AL20 AM20 AN22 AP19 AH13 AH16 AE13 AE12 AH15 AN31 AP32 AD16 AD14 AC12 AH14 AG15 AP23 AL21 AG21 AF21 U5 T7 U8 T5 AG22 AJ21 AR24 AR23 Y6 Y7 W7 Y5 AL22 U9 V6 U7 V7 U0600 AN25 AM24 AG23 AJ23 AK23 AN24 AR25 AH21 AK21 AG24 AK25 AL25 AP26 AR26 AC17 AC16 AF26 AC14 AC15 AF24 AG25 AM26 AN26 AK27 AN27 AK26 AL26 AF25 AP27 AL27 AR31 AK28 AL28 AM29 AM30 AG27 U6 W5 T6 W8 AF20 AF19 AG20 AM21 AF23 AL23 AH23 AM23 AL30 AL29 AN32 AP33 AC13 AK16 AJ16 AF16 AG16 051-8773 10.0.0 7 OF 157 5 OF 48 46 46 46 35 935 15 42 53042 5273539 35 5273539 52437 52437 52837 51542 542 46 46 46 46 46 46 46 46 46 46 46 46 46 46 45 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 5 30 5 5 39 5 26 5 37 42
  • 9.
    BI BI BI BI OUT OUT OUT OUT OUT OUT BI BI BI BI BI BI BI BI OUT OUT OUT OUT OUT OUT FMI0_ALE FMI3_IO7 FMI3_IO6 FMI3_IO5 FMI3_IO4 FMI3_IO1 FMI3_IO0 FMI3_DQS FMI3_CLE FMI3_CEN7 FMI3_CEN6 FMI3_CEN5 FMI3_CEN4 FMI3_CEN3 FMI3_CEN2 FMI3_CEN1 FMI3_CEN0 FMI2_WEN FMI2_REN FMI2_IO7 FMI2_IO6 FMI2_IO5 FMI2_IO4 FMI2_IO3 FMI2_IO2 FMI2_DQS FMI2_CLE FMI2_CEN7 FMI2_CEN6 FMI2_CEN4 FMI2_CEN3 FMI2_CEN2 FMI2_CEN1 FMI2_CEN0 FMI2_ALE FMI1_IO7 FMI1_IO4 FMI1_IO3 FMI1_IO2 FMI1_IO1 FMI1_IO0 FMI1_DQS FMI1_CLE FMI1_CEN1 FMI1_CEN0 FMI1_ALE FMI0_WEN FMI0_IO7 FMI0_IO6 FMI0_IO5 FMI0_IO4 FMI0_IO3 FMI0_IO2 FMI0_IO1 FMI0_IO0 FMI0_DQS FMI0_CEN7 FMI0_CEN6 FMI0_CEN5 FMI0_CEN4 FMI0_CEN3 FMI0_CEN1 FMI0_CEN0 FMI1_CEN2 FMI1_CEN3 FMI1_CEN4 FMI1_CEN7 FMI1_CEN6 FMI1_CEN5 FMI2_IO1 FMI2_IO0 FMI0_CEN2 FMI2_CEN5 FMI0_CLE FMI0_REN FMI3_ALE FMI1_IO5 FMI1_IO6 FMI3_IO3 FMI3_IO2 FMI1_REN FMI1_WEN FMI3_REN FMI3_WEN (4 OF 12) (12OF 12) VSSVSS IN OUT OUT BI OUT OUT OUT BI BI BI Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT CHECK WITH GRAPE ON VOLTAGE FOR THESE TWO SIGNALS CHECK CONNECTION FOR VSSA18_TS FMI2-3_CEN IS 3.0V NEW GPIO FOR J2. FILE A RADAR 1244 1244 1244 1244 61244 61244 61244 61244 61244 61244 1244 1244 1244 1244 1244 1244 1244 1244 61244 61244 61244 61244 1244 1244 MF 1/32W 5% 100K 01005 NOSTUFF 01005 100K 5% 1/32W MF NOSTUFF MF 1/32W 5% 100K 01005 NOSTUFF MF 1/32W 5% 100K 01005 NOSTUFF 100K 5% 1/32W MF 01005 NOSTUFF 01005 100K 5% 1/32W MF NOSTUFF MF 1/32W 5% 100K 01005 NOSTUFF MF 1/32W 5% 100K 01005 NOSTUFF OMIT H4G FCBGA H4G FCBGA OMIT 100K 5% 1/32W MF 01005 20 01005 100K 5% 1/32W MF 01005 100K 5% 1/32W MF 01005 100K 5% 1/32W MF 100K 5% 1/32W MF 01005 17 45 16 1244 61244 17 61244 1244 1244 1244 SYNC_DATE=N/A AP: NAND SYNC_MASTER=MIKENC_FMI3_WE_LFMI1_WE_L FMI1_CLE FMI1_AD<7> FMI1_AD<6> FMI1_AD<5> FMI1_AD<4> NC_FMI2_CE1_L RST_GRAPE_L FMI0_ALE NC_FMI3_AD<7> NC_FMI3_AD<6> NC_FMI3_AD<5> NC_FMI3_AD<4> NC_FMI3_AD<1> NC_FMI3_AD<0> NC_FMI3_DQS NC_FMI3_CLE NC_FMI3_CE7_L NC_FMI3_CE6_L NC_FMI3_CE5_L NC_FMI3_CE4_L NC_FMI3_CE3_L NC_FMI3_CE2_L NC_FMI3_CE1_L NC_FMI3_CE0_L NC_FMI2_WE_L NC_FMI2_AD<7> NC_FMI2_AD<6> NC_FMI2_AD<5> NC_FMI2_AD<4> NC_FMI2_AD<3> NC_FMI2_AD<2> NC_FMI2_DQS NC_FMI2_CLE NC_FMI2_CE3_L NC_FMI2_CE2_L NC_FMI2_ALE FMI1_AD<3> FMI1_AD<2> FMI1_AD<1> FMI1_AD<0> FMI1_DQS_P FMI1_CE1_L FMI1_CE0_L FMI1_ALE FMI0_WE_L FMI0_AD<7> FMI0_AD<6> FMI0_AD<4> FMI0_AD<3> FMI0_AD<2> FMI0_AD<1> FMI0_AD<0> FMI0_DQS_P NC_FMI0_CE7_L NC_FMI0_CE6_L NC_FMI0_CE5_L NC_FMI0_CE4_L NC_FMI0_CE3_L FMI0_CE1_L FMI0_CE0_L NC_FMI1_CE2_L NC_FMI1_CE3_L NC_FMI1_CE4_L NC_FMI1_CE7_L NC_FMI1_CE6_L NC_FMI1_CE5_L NC_FMI2_AD<1> NC_FMI0_CE2_L NC_FMI2_CE5_L FMI0_CLE FMI0_RE_N NC_FMI3_ALE NC_FMI3_AD<3> NC_FMI3_AD<2> FMI1_RE_N NC_FMI3_RE_L NC_FMI2_RE_L GRAPE_FW_DNLD_EN_L NC_FMI2_AD<0> FMI0_AD<5> PM_LCDVDD_PWREN FMI1_CLE FMI0_CLE FMI1_ALE FMI1_RE_N FMI1_WE_L FMI0_RE_N PPIO_NAND_H4 FMI0_WE_L FMI0_ALE SPK_ID =PP3V0_IO_MISC FMI1_CE0_L FMI0_CE0_L FMI1_CE1_L PPIO_NAND_H4 FMI0_CE1_L R08341 2 R08311 2 R08361 2 R08321 2 R08031 2 R08021 2 R08011 2 R08001 2 R08131 2 R08121 2 R08111 2 R08101 2 U0600 AE32 AH31 AF31 AD28 AG29 Y29 AH28 AG28 AM31 AF33 AG33 AG35 AF35 AH35 AH33 AG31 AG32 AG34 AH32 AE33 AH34 AN34 AJ33 AN33 AD30 AE30 AJ31 AJ30 AL31 AK31 AK35 AL34 AL32 AN35 AK32 AK33 AL33 AK34 AM33 AJ35 AL35 AM35 AB34 AE35 AB28 AA28 AB30 AE28 AF28 AA29 AB31 AB32 AC33 AC31 AB33 AC35 AE34 AD34 AD32 AD35 AD31 AD33 AB35 Y33 W31 W28 W29 V30 AG30 AC30 AH30 AE31 W30 Y32 AA34 W33 AA33 V34 AA30 V31 W32 Y30 AA31 AA32 U0600 G22 G23 G30 H1 H4 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H30 H34 J2 J8 J9 J10 J11 J12 J14 J16 J18 J20 J22 J24 J26 J31 J34 K3 K8 K9 K10 K11 K13 K15 K17 K19 K21 K23 K25 K27 K34 L32 L1 L4 L8 L10 L12 L14 L16 L18 L20 L22 L24 L26 M2 M3 M8 M9 M11 M13 M15 M17 M19 M21 M23 M25 M27 M30 L34 N3 N8 N10 N12 N14 N16 N18 N20 N22 N24 N26 M35 P1 P8 P9 P11 P13 P15 P17 P19 P21 P23 P25 P27 R2 R8 R10 R12 R14 R16 R18 R20 R22 R24 R26 P34 T3 T9 T11 T13 T15 T17 T19 T21 T23 T25 T27 R35 U1 U10 U12 U14 U16 U18 U20 U22 U24 U26 U30 U31 V9 V11 V13 V15 V17 V19 V21 V23 V25 V27 V29 U34 V35 W1 W3 W10 W12 W14 W16 W18 W20 W22 W24 W26 W34 Y9 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y25 Y27 Y28 Y31 Y34 R08041 2 051-8773 10.0.0 8 OF 157 6 OF 48 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 61244 61244 61244 61244 61244 61244 6945 61244 61244 2835 61244 61244 61244 6945 61244
  • 10.
    OUT OUT OUT OUT OUT OUT IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT BI BI OUT OUT OUT OUT (5 OF 12) DAC_VREF DP_PAD_TX0P DP_PAD_AUXN DP_PAD_AUXP EDP_PAD_TX0P DP_PAD_AVSS_AUX EDP_PAD_AVSS DAC_AVSS30D DP_PAD_AVDDX DP_PAD_TX2P DP_PAD_TX1N DP_PAD_TX1P DAC_AVSS30A1 DAC_AVSS30A2 DAC_IREFDAC_OUT1 DAC_OUT3 DP_HPD DP_PAD_DC_TP DP_PAD_R_BIAS DP_PAD_TX2N DP_PAD_TX3N DP_PAD_TX3P EDP_HPD EDP_PAD_AUXN EDP_PAD_AUXP EDP_PAD_AVSSP0 EDP_PAD_AVSSX EDP_PAD_DVDDEDP_PAD_DVSS EDP_PAD_R_BIAS EDP_PAD_TX0N EDP_PAD_TX1N EDP_PAD_TX1P EDP_PAD_TX2N EDP_PAD_TX2P EDP_PAD_TX3N EDP_PAD_TX3P DP_PAD_AVDDP0 DP_PAD_AVDD DAC_COMP EDP_PAD_AVDDX EDP_PAD_AVDDP0 EDP_PAD_AVDD EDP_PAD_AVDD_AUX DP_PAD_DVDD EDP_PAD_AVSS_AUX DP_PAD_AVSSP0 DP_PAD_AVSSX DP_PAD_DVSS DP_PAD_AVSS DP_PAD_TX0N DAC_OUT2 EDP_PAD_DC_TP DAC_AVDD30D DAC_AVDD30A DP_PAD_AVDD_AUX MIPI_VDD11 MIPI1D_VREG_0P4V MIPI0D_VREG_0P4V ISP0_FLASH SENSOR1_RST SENSOR1_CLK SENSOR0_RST SENSOR0_CLK MIPI1C_DNDATA0 MIPI_VSYNC ISP1_SCL ISP1_PRE_FLASH ISP1_FLASH ISP0_SDA ISP0_SCL ISP0_PRE_FLASH MIPI1C_DPDATA0 MIPI1D_VDD18 MIPI0D_VDD18 MIPI0C_DNDATA3 MIPI1C_DNCLK MIPI1C_DPCLK MIPI1C_DNDATA1 MIPI1C_DPDATA1 MIPI0C_DPDATA0 MIPI0C_DNDATA0 MIPI0C_DPDATA1 MIPI0C_DPDATA2 MIPI0C_DNDATA2 MIPI0C_DPDATA3 MIPI0C_DPCLK MIPI0C_DNCLK MIPI0C_DNDATA1 ISP1_SDA (6 OF 12) PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_ALT_ITEM Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT 1.2MA 5MA 2MA 332MA 21MA 4MA DP LANES 2/3 ARE FOR STEVE-NOTE ONLY NOTE: 0.6V ANALOG REF NOTE: 0.6V ANALOG REF 6MA 5MA 2MA 5MA 1.2MA 5MA 172MA 14MA 6.3V 0.22UF 20% X5R 402 1/20W 1% 201 6.34K MF 10% 6.3V 201 X5R 0.1UF X5R 6.3V 10% 01005 0.01UF 6.3V 01005 NP0-C0G 56PF 5% 1UF 402 6.3V 10% CERM 6.3V 10% 0.01UF X5R 01005 0.22UF 20% 402 X5R 6.3V 402 X5R 6.3V 20% 0.22UF MF 1/20W 201 0 5% 6.3V NP0-C0G 01005 56PF 5% 0.1UF 10% 201 X5R 6.3V 1% 201 200 1/20W MF MF 201 1/20W 1% 200 201 MF 1% 200 1/20W 4.99K 1/32W 1% MF 01005 0.01UF 01005 X5R 6.3V 10% NOSTUFF NP0-C0G 01005 6.3V 56PF 5% 0 201 MF 1/20W 5% 01005 56PF NP0-C0G 6.3V 5% 6.3V 20% X5R 402 0.22UF 402 0.22UF X5R 20% 6.3V 402 0.22UF 20% X5R 6.3V 10% 6.3V 0.1UF X5R 201 MF 1/32W 01005 1% 4.99K 01005 X5R 6.3V 10% 0.01UF NOSTUFF 402 1UF 10% CERM 6.3V 201 6.3V X5R 10% 0.1UF 6.3V X5R 201 10% 0.1UF 0.1UF X5R 10% 201 6.3V 0.00 MF 01005 0% 1/32W MF 0.00 01005 0% 1/32W 0201 240-OHM-0.2A-0.8-OHM 201 X5R 10% 10V 2.2NF 10V X5R 201 10% 2.2NF 28 43 28 43 28 43 28 43 28 43 28 43 37 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 0.1UF 201 X5R 6.3V 10% 11 43 11 43 11 43 2543 2543 2543 2543 2543 2543 25 43 25 43 25 43 25 43 25 42 25 42 25 42 25 42 1/32W 01005 MF 1.00K 5% 1/32W MF 01005 1.00K 5% 1/32W MF 01005 1.00K 5% 1/32W MF 01005 1.00K 5% 28 43 28 43 28 43 28 43 H4G OMIT FCBGA OMIT H4G FCBGA SYNC_MASTER=JOE SYNC_DATE=01/13/2011 AP: TV,DP,MIPI 132S0279 132S0154 RADAR:9624625C0960,C0961 NET_SPACING_TYPE=PWR PP0V4_MIPI1D VOLTAGE=0.4V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM MAX_NECK_LENGTH=3MM =PP1V8_H4 ISP_AP_1_SDA TP_CAM0_1V2_VDDCORE_EN ISP_AP_0_SCL CAM0_RESET_L ISP_AP_0_SDA ISP_AP_1_SCL CLK_CAM_RF PM_FRONT_CAM_SHUTDOWN CLK_CAM_FF_R PM_REAR_CAM_SHUTDOWN CLK_CAM_RF_R NC_ISP_AP_1_PRE_FLASH NC_ISP_AP_1_FLASH =PP1V8_MIPI_H4 NC_MIPI0C_AP_DATA_N<3> MIPI1C_AP_CLK_N MIPI1C_AP_CLK_P NC_MIPI1C_AP_DATA_N<1> NC_MIPI1C_AP_DATA_P<1> MIPI0C_AP_DATA_P<0> MIPI0C_AP_DATA_N<0> MIPI0C_AP_DATA_P<1> NC_MIPI0C_AP_DATA_P<2> NC_MIPI0C_AP_DATA_N<2> NC_MIPI0C_AP_DATA_P<3> MIPI0C_AP_CLK_N MIPI0C_AP_DATA_N<1> DAC_AP_VREF DP_AP_TX_P<0> DP_AP_AUX_N DP_AP_AUX_P EDP_AP_TX_P<0> DP_AP_TX_P<2> DP_AP_TX_N<1> DP_AP_TX_P<1> DAC_AP_OUT1 DP_AP_HPD TP_DP_AP_ANALOG_TEST AP_DP_R_BIAS DP_AP_TX_N<2> DP_AP_TX_N<3> DP_AP_TX_P<3> EDP_AP_AUX_N EDP_AP_AUX_P =PP1V1_EDP_PAD_DVDD_H4 AP_EDP_R_BIAS EDP_AP_TX_N<0> EDP_AP_TX_N<1> EDP_AP_TX_P<2> EDP_AP_TX_N<3> EDP_AP_TX_P<3> DAC_AP_COMP DP_AP_TX_N<0> DAC_AP_OUT2 =PP1V8_EDP_H4 DAC_AP_COMP_FTR=PP3V0_VIDEO_H4 CLK_CAM_FF EDP_AP_HPD EDP_AP_TX_P<1> EDP_AP_TX_N<2> TP_EDP_AP_ANALOG_TEST MAX_NECK_LENGTH=3MM MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=PWR VOLTAGE=1.8V PP1V8_EDP_AVDD_AUX MIN_NECK_WIDTH=0.1MM MAX_NECK_LENGTH=3MM NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.2MM VOLTAGE=0.4V PP0V4_MIPI0D DAC_AP_IREF MIPI1C_AP_DATA_N<0> MIPI0C_AP_CLK_P DAC_AP_OUT3 =PP3V0_VIDEO_H4 NC_MIPI_VSYNC_H4 =PP1V1_DP_PAD_DVDD_H4 MIPI1C_AP_DATA_P<0> =PP3V0_IO_H4 =PP1V8_DP_H4 VOLTAGE=1.8V MIN_LINE_WIDTH=0.2MM PP1V8_DP_AVDD_AUX MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM =PP1V1_MIPI_H4 C09271 2 R09501 2 C09551 2 C09521 2 C09241 2 C09511 2 C09531 2 C09261 2 C09251 2 R0910 1 2 C09231 2 C09091 2 R09551 2 R09561 2 R09571 2 R09201 2 C09501 2 C09301 2 R0911 1 2 C09311 2 C09321 2 C09331 2 C09341 2 C09101 2 R09211 2 C09571 2 C09351 2 C09031 2 C09081 2 C09071 2 R09001 2 R09401 2 FL0910 1 2 C09601 2 C09611 2 C09561 2 R09301 2 R09311 2 R09321 2 R09331 2 U0600 G31 D32 G32 F32 D31 E32 F31 G35 G34 G33E31 AL15 C27 C28 C26 C25 D24 D23 D28 D27 B29 A26 A25 B24 B23 B28 B27 D29 F23 A29C29 E23 A27 A28 D25 D26 B25 B26 C23 C24 AJ15 A23 A24 B18 A18 E19 E18 D20 D19 C21 D18 C18 F19 F18 B20 B19 A21 F20 C22A22 E20 D21 D22 B21 B22 C19 C20 A19 A20 U0600 AD17 AF13 AK22 AF22 AF14 AE17 AP24 AN23 A32 C35 B32 B30 A30 A33 D35 B33 B31 A31 F25 F26 E35 E34 C34 F35 F34 D34 F28 F29 G24 G25 G26 G27 G28 G29 AD15 AJ24 AK24 AH24 AL24 051-8773 10.0.0 9 OF 157 7 OF 48 45 4 10 35 26 25 42 25 42 25 42 46 46 35 4346 43 46 43 46 4346 4346 4346 45 35 35 735 25 42 45 45 735 46 35 935 3545 35
  • 11.
    BI BI BI BI BI BI BI OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT BI BI BI BI BI BI BI BI OUT OUT OUT OUT BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT BI BI BI BI BI BI BI BI OUT OUT OUT OUT BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI OUT BI BI BI BI OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT BI BI BI BI BI BI BI BI OUT BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI OUT OUT OUT OUT BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT (7 OF 12) DDR0_CA0 DDR0_CA1 DDR0_CA2 DDR0_CA3 DDR0_CA4 DDR0_CA5 DDR0_CA6 DDR0_CA7 DDR0_CA8 DDR0_CA9 DDR0_CK DDR0_CKB DDR0_CKE0 DDR0_CKE1 DDR0_CSN0 DDR0_CSN1 DDR0_DM0 DDR0_DM1 DDR0_DM2 DDR0_DM3 DDR0_DQ0 DDR0_DQ1 DDR0_DQ10 DDR0_DQ11 DDR0_DQ12 DDR0_DQ13 DDR0_DQ14 DDR0_DQ15 DDR0_DQ16 DDR0_DQ17 DDR0_DQ18 DDR0_DQ19 DDR0_DQ2 DDR0_DQ20 DDR0_DQ21 DDR0_DQ22 DDR0_DQ23 DDR0_DQ24 DDR0_DQ25 DDR0_DQ26 DDR0_DQ27 DDR0_DQ28 DDR0_DQ29 DDR0_DQ3 DDR0_DQ30 DDR0_DQ31 DDR0_DQ4 DDR0_DQ5 DDR0_DQ6 DDR0_DQ7 DDR0_NDQS0 DDR0_NDQS1 DDR0_NDQS2 DDR0_NDQS3 DDR0_PDQS0 DDR0_PDQS1 DDR0_PDQS2 DDR0_PDQS3 DDR0_VDDQ_CKE DDR0_VREF_DQ DDR0_ZQ DDR1_CA0 DDR1_CA1 DDR1_CA2 DDR1_CA3 DDR1_CA4 DDR1_CA6 DDR1_CA7 DDR1_CA8 DDR1_CA9 DDR1_CK DDR1_CKB DDR1_CKE0 DDR1_CSN0 DDR1_CSN1 DDR1_DM0 DDR1_DM1 DDR1_DM2 DDR1_DM3 DDR1_DQ0 DDR1_DQ1 DDR1_DQ10 DDR1_DQ11 DDR1_DQ12 DDR1_DQ13 DDR1_DQ14 DDR1_DQ15 DDR1_DQ16 DDR1_DQ17 DDR1_DQ18 DDR1_DQ19 DDR1_DQ2 DDR1_DQ20 DDR1_DQ21 DDR1_DQ22 DDR1_DQ23 DDR1_DQ24 DDR1_DQ25 DDR1_DQ26 DDR1_DQ27 DDR1_DQ28 DDR1_DQ29 DDR1_DQ3 DDR1_DQ30 DDR1_DQ31 DDR1_DQ4 DDR1_DQ5 DDR1_DQ6 DDR1_DQ7 DDR1_DQ8 DDR1_DQ9 DDR1_NDQS0 DDR1_NDQS1 DDR1_NDQS2 DDR1_NDQS3 DDR1_PDQS0 DDR1_PDQS1 DDR1_PDQS2 DDR1_PDQS3 DDR0_DQ8 DDR0_DQ9 DDR1_CA5 DDR1_VREF_DQ DDR1_CKE1 DDR1_VDDQ_CKE DDR1_ZQ (8OF 12) DDR2_DQ0 DDR2_DQ1 DDR2_DQ2 DDR2_DQ3 DDR2_DQ4 DDR2_DQ5 DDR2_DQ6 DDR2_DQ7 DDR2_DQ8 DDR2_DQ9 DDR2_DQ10 DDR2_DQ11 DDR2_DQ12 DDR2_DQ13 DDR2_DQ14 DDR2_DQ15 DDR2_DQ16 DDR2_DQ17 DDR2_DQ18 DDR2_DQ19 DDR2_DQ20 DDR2_DQ21 DDR2_DQ22 DDR2_DQ23 DDR2_DQ24 DDR2_DQ25 DDR2_DQ26 DDR2_DQ27 DDR2_DQ28 DDR2_DQ29 DDR2_DQ30 DDR2_DQ31 DDR2_CA0 DDR2_CA1 DDR2_CA2 DDR2_CA3 DDR2_CA4 DDR2_CA5 DDR2_CA6 DDR2_CA7 DDR2_CA8 DDR2_CA9 DDR2_DM0 DDR2_DM1 DDR2_DM2 DDR2_DM3 DDR2_PDQS0 DDR2_NDQS0 DDR2_PDQS1 DDR2_NDQS1 DDR2_PDQS2 DDR2_NDQS2 DDR2_PDQS3 DDR2_NDQS3 DDR2_VDDQ_CKE DDR2_VREF_DQ DDR2_ZQ DDR2_CK DDR2_CKB DDR2_CKE0 DDR2_CKE1 DDR2_CSN0 DDR2_CSN1 DDR3_DQ0 DDR3_DQ1 DDR3_DQ2 DDR3_DQ3 DDR3_DQ4 DDR3_DQ5 DDR3_DQ6 DDR3_DQ7 DDR3_DQ8 DDR3_DQ9 DDR3_DQ10 DDR3_DQ11 DDR3_DQ12 DDR3_DQ13 DDR3_DQ14 DDR3_DQ15 DDR3_DQ16 DDR3_DQ17 DDR3_DQ18 DDR3_DQ19 DDR3_DQ20 DDR3_DQ21 DDR3_DQ22 DDR3_DQ23 DDR3_DQ24 DDR3_DQ25 DDR3_DQ26 DDR3_DQ27 DDR3_DQ28 DDR3_DQ29 DDR3_DQ30 DDR3_DQ31 DDR3_CA0 DDR3_CA1 DDR3_CA2 DDR3_CA3 DDR3_CA4 DDR3_CA5 DDR3_CA6 DDR3_CA7 DDR3_CA8 DDR3_CA9 DDR3_DM0 DDR3_DM1 DDR3_DM2 DDR3_DM3 DDR3_PDQS0 DDR3_NDQS0 DDR3_PDQS1 DDR3_NDQS1 DDR3_PDQS2 DDR3_NDQS2 DDR3_PDQS3 DDR3_NDQS3 DDR3_VDDQ_CKE DDR3_VREF_DQ DDR3_ZQ DDR3_CK DDR3_CKB DDR3_CKE0 DDR3_CKE1 DDR3_CSN0 DDR3_CSN1 BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT 998-3125 0.5MM PT 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 134044 134044 1344 1344 134044 1344 1344 1344 1344 1344 1344 1344 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 1444 13 44 13 44 13 44 13 44 13 44 01005 10% 0.01UF NOSTUFF 6.3V X5R 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 1.00K 1% MF 1/32W 01005 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 1/32W 1% MF 01005 1.00K 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 13 44 10% 01005 0.01UF NOSTUFF 6.3V X5R 13 44 13 44 13 44 13 44 13 44 13 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 1.00K 1% 1/32W MF 01005 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 MF 1.00K 1/32W 1% 01005 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 14 44 H4G FCBGA OMIT H4G FCBGA OMIT 0.01UF 01005 10% NOSTUFF 6.3V X5R 1/32W 1.00K 1% MF 01005 MF 1.00K 1/32W 1% 01005 10% 01005 0.01UF NOSTUFF 6.3V X5R 01005 1/32W MF 1% 1.00K 01005 1.00K MF 1% 1/32W 0201 6.3V X5R 0.22UF 20% 0201 6.3V X5R 0.22UF 20% 0201 6.3V X5R 0.22UF 20% 0201 6.3V X5R 0.22UF 20% MF 1% 1/20W 240 201 1/20W 240 MF 1% 201 240 1% 1/20W MF 201 240 1% 1/20W MF 201 10% 01005 0.01UF 6.3V X5R NOSTUFF NOSTUFF 10% 01005 0.01UF 6.3V X5R NOSTUFF 0.01UF 10% 01005 6.3V X5R 10% 01005 0.01UF NOSTUFF 6.3V X5R 134044 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 134044 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 SYNC_MASTER=MIKE AP: DDR SYNC_DATE=N/A DDR1_DM<2> DDR1_DM<0> H4G_DDR0_ZQ MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.3MM PPVREF_DDR1_DQ_H4 MIN_NECK_WIDTH=0.2MM VOLTAGE=0.6V NET_SPACING_TYPE=PWR PPVREF_DDR1_DQ_H4 PPVREF_DDR0_DQ_H4 MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM MAX_NECK_LENGTH=3 MM VOLTAGE=0.6V NET_SPACING_TYPE=PWR PPVREF_DDR0_DQ_H4 MAX_NECK_LENGTH=3 MM VOLTAGE=0.6V MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM PPVREF_DDR2_DQ_H4 NET_SPACING_TYPE=PWR PPVREF_DDR2_DQ_H4 PPVREF_DDR3_DQ_H4 MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0.6V MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR PPVREF_DDR3_DQ_H4 DDR1_DQ<27> DDR1_DQ<23> =PP1V2_VDDIOD_H4 =PP1V2_VDDIOD_H4 =PP1V2_VDDIOD_H4 =PP1V2_VDDIOD_H4 H4G_DDR1_ZQ =PP1V2_S2R_H4 NC_DDR1_CKE<1> DDR1_CA<5> DDR0_DQ<9> DDR0_DQ<8> DDR1_DQS_P<3> DDR1_DQS_P<2> DDR1_DQS_P<1> DDR1_DQS_P<0> DDR1_DQS_N<3> DDR1_DQS_N<2> DDR1_DQS_N<1> DDR1_DQS_N<0> DDR1_DQ<9> DDR1_DQ<8> DDR1_DQ<7> DDR1_DQ<6> DDR1_DQ<5> DDR1_DQ<4> DDR1_DQ<31> DDR1_DQ<30> DDR1_DQ<3> DDR1_DQ<29> DDR1_DQ<28> DDR1_DQ<26> DDR1_DQ<25> DDR1_DQ<24> DDR1_DQ<22> DDR1_DQ<21> DDR1_DQ<20> DDR1_DQ<2> DDR1_DQ<19> DDR1_DQ<18> DDR1_DQ<17> DDR1_DQ<16> DDR1_DQ<15> DDR1_DQ<14> DDR1_DQ<13> DDR1_DQ<12> DDR1_DQ<11> DDR1_DQ<10> DDR1_DQ<1> DDR1_DQ<0> DDR1_DM<3> DDR1_DM<1> NC_DDR1_CSN<1> DDR1_CSN<0> DDR1_CKE<0> DDR1_CK_N DDR1_CK_P DDR1_CA<9> DDR1_CA<8> DDR1_CA<7> DDR1_CA<6> DDR1_CA<4> DDR1_CA<3> DDR1_CA<2> DDR1_CA<1> DDR1_CA<0> =PP1V2_S2R_H4 DDR0_DQS_P<3> DDR0_DQS_P<2> DDR0_DQS_P<1> DDR0_DQS_P<0> DDR0_DQS_N<3> DDR0_DQS_N<2> DDR0_DQS_N<1> DDR0_DQS_N<0> DDR0_DQ<7> DDR0_DQ<6> DDR0_DQ<5> DDR0_DQ<4> DDR0_DQ<31> DDR0_DQ<30> DDR0_DQ<3> DDR0_DQ<29> DDR0_DQ<28> DDR0_DQ<27> DDR0_DQ<26> DDR0_DQ<25> DDR0_DQ<24> DDR0_DQ<23> DDR0_DQ<22> DDR0_DQ<21> DDR0_DQ<20> DDR0_DQ<2> DDR0_DQ<19> DDR0_DQ<18> DDR0_DQ<17> DDR0_DQ<16> DDR0_DQ<15> DDR0_DQ<14> DDR0_DQ<13> DDR0_DQ<12> DDR0_DQ<11> DDR0_DQ<10> DDR0_DQ<1> DDR0_DQ<0> DDR0_DM<3> DDR0_DM<2> DDR0_DM<1> DDR0_DM<0> NC_DDR0_CSN<1> DDR0_CSN<0> NC_DDR0_CKE<1> DDR0_CKE<0> DDR0_CK_N DDR0_CK_P DDR0_CA<9> DDR0_CA<8> DDR0_CA<7> DDR0_CA<6> DDR0_CA<5> DDR0_CA<4> DDR0_CA<3> DDR0_CA<2> DDR0_CA<1> DDR0_CA<0> NC_DDR3_CSN<1> DDR3_CSN<0> NC_DDR3_CKE<1> DDR3_CKE<0> DDR3_CK_N DDR3_CK_P H4G_DDR3_ZQ =PP1V2_S2R_H4 DDR3_DQS_N<3> DDR3_DQS_P<3> DDR3_DQS_N<2> DDR3_DQS_P<2> DDR3_DQS_N<1> DDR3_DQS_P<1> DDR3_DQS_N<0> DDR3_DQS_P<0> DDR3_DM<3> DDR3_DM<2> DDR3_DM<1> DDR3_DM<0> DDR3_CA<9> DDR3_CA<8> DDR3_CA<7> DDR3_CA<6> DDR3_CA<5> DDR3_CA<4> DDR3_CA<3> DDR3_CA<2> DDR3_CA<1> DDR3_CA<0> DDR3_DQ<31> DDR3_DQ<30> DDR3_DQ<29> DDR3_DQ<28> DDR3_DQ<27> DDR3_DQ<26> DDR3_DQ<25> DDR3_DQ<24> DDR3_DQ<23> DDR3_DQ<22> DDR3_DQ<21> DDR3_DQ<20> DDR3_DQ<19> DDR3_DQ<18> DDR3_DQ<17> DDR3_DQ<16> DDR3_DQ<15> DDR3_DQ<14> DDR3_DQ<13> DDR3_DQ<12> DDR3_DQ<11> DDR3_DQ<10> DDR3_DQ<9> DDR3_DQ<8> DDR3_DQ<7> DDR3_DQ<6> DDR3_DQ<5> DDR3_DQ<4> DDR3_DQ<3> DDR3_DQ<2> DDR3_DQ<1> DDR3_DQ<0> NC_DDR2_CSN<1> DDR2_CSN<0> NC_DDR2_CKE<1> DDR2_CKE<0> DDR2_CK_N DDR2_CK_P H4G_DDR2_ZQ =PP1V2_S2R_H4 DDR2_DQS_N<3> DDR2_DQS_P<3> DDR2_DQS_N<2> DDR2_DQS_P<2> DDR2_DQS_N<1> DDR2_DQS_P<1> DDR2_DQS_N<0> DDR2_DQS_P<0> DDR2_DM<3> DDR2_DM<2> DDR2_DM<1> DDR2_DM<0> DDR2_CA<9> DDR2_CA<8> DDR2_CA<7> DDR2_CA<6> DDR2_CA<5> DDR2_CA<4> DDR2_CA<3> DDR2_CA<2> DDR2_CA<1> DDR2_CA<0> DDR2_DQ<31> DDR2_DQ<30> DDR2_DQ<29> DDR2_DQ<28> DDR2_DQ<27> DDR2_DQ<26> DDR2_DQ<25> DDR2_DQ<24> DDR2_DQ<23> DDR2_DQ<22> DDR2_DQ<21> DDR2_DQ<20> DDR2_DQ<19> DDR2_DQ<18> DDR2_DQ<17> DDR2_DQ<16> DDR2_DQ<15> DDR2_DQ<14> DDR2_DQ<13> DDR2_DQ<12> DDR2_DQ<11> DDR2_DQ<10> DDR2_DQ<9> DDR2_DQ<8> DDR2_DQ<7> DDR2_DQ<6> DDR2_DQ<5> DDR2_DQ<4> DDR2_DQ<3> DDR2_DQ<2> DDR2_DQ<1> DDR2_DQ<0> C10561 2 R10551 2 R10561 2 C10541 2 R10531 2 R10541 2 C10841 2 R10831 2 R10841 2 C10961 2 R10951 2 R10961 2 C10201 2 C10211 2 C10221 2 C10231 2 R10201 2 R10211 2 R10221 2 R102341 2 C10571 2 C10581 2 C10951 2 C10851 2 U0600 G5 G6 H5 H6 J5 M5 M6 N6 P5 P6 P4 N4 J1 K1 K6 J6 E12 E9 C14 D6 B14 B13 B8 C8 B7 B6 C6 D7 B17 C17 B16 E17 D13 D16 E16 C15 D15 E6 B5 C5 E5 C4 D4 C12 B3 C3 D12 B11 C11 B10 C9 D9 A12 A7 A15 A4 A13 A6 A16 A3 G11 D10 M4 E15 F15 F14 E14 F13 E8 F8 F7 E7 F6 F11 F12 A10 A9 F10 E13 L5 N5 G4 R5 H2 H3 P3 R3 U3 T2 U2 R4 C2 D2 E2 E4 J3 E3 F3 F4 G2 R6 T4 U4 V1 V2 V3 J4 V4 V5 K2 L2 K4 K5 N2 P2 G1 M1 D1 R1 F1 N1 C1 T1 N7 L3 E11 U0600 AL6 AK6 AL7 AK7 AL8 AL11 AK11 AK12 AL12 AK13 AM13 AM12 AR10 AR9 AK9 AK8 AD4 AG4 AA6 AK4 AB2 AB3 AH3 AF4 AJ3 AJ2 AK3 AF5 Y2 W2 Y3 W4 AC2 Y4 AA3 AA5 AA4 AL2 AL3 AL4 AM2 AN2 AN3 AC4 AL5 AK5 AE2 AD3 AF2 AE3 AG3 AH2 AD1 AJ1 AA1 AM1 AC1 AK1 Y1 AN1 AE7 AE4 AL9 AB5 AB6 AC5 AC6 AD5 AG5 AG6 AH6 AH5 AJ6 AH4 AJ4 AF1 AG1 AE6 AD6 AM11 AL13 AM6 AK14 AP7 AM7 AL10 AP13 AP14 AM14 AL14 AN14 AP4 AP3 AN4 AM4 AP8 AP5 AN5 AN6 AM5 AN15 AM15 AP16 AM16 AR18 AP17 AN8 AN17 AM17 AN9 AP10 AP11 AN11 AN12 AM10 AR7 AR12 AR4 AR15 AR6 AR13 AR3 AR16 AJ12 AM9 AE5 051-8773 10.0.0 10 OF 157 8 OF 48 8 45 8 45 8 45 845 8 45 845 8 45 8 45 8935 8935 8935 8935 8 35 46 46 835 46 46 46 46 8 35 46 46 835
  • 12.
    (9 OF 12) VDD VDD VDDIO18_GPIO VDDIO18_UART1_TXD0 VDD_CPU VDDIOD VDDIOD7 VDDIOD6 VDDIOD5 VDDIOD4 VDDIOD3 VDDIOD2 VDDIOD1 VDDIOD0 VDDIO18_XO0 VDDIO18_FUSE0_FSRC VDDIO18_UART2_TXD VDDIO30_USB11 VDDIO30_GPIO_3V0 VDDIO30_DP_HPD VDDIO30_CFSB (10OF 12) Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_ALT_ITEM FMI0-1 88MA FMI2-3 88MA 1000MA 160MA 44MA FMI2-3_CEN 2MA ISP FLASH, SPI3 3MA UART4 ?MA GPIO30-39 4MA 2300MA 3800MA SPI1 1MA I2C2 1MA C1100, C1102, C1103, C1117, C1121, C1122, C1124, C1153, C1154, C1155, C1156, C1158, C1191, C1615, C1621, C1715, C1721 10% 1UF 402 CERM 6.3V 10% 1UF 402 CERM 6.3V 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 402 10% 1UF CERM 6.3V 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 603 10UF X5R 6.3V 20% 0610 20% 4V X5R-CERM 4.3UF 603 10UF X5R 6.3V 20% 0610 20% 4V X5R-CERM 4.3UF 01005 10% 6.3V X5R 0.01UF 01005 10% 6.3V X5R 0.01UF 01005 10% 6.3V X5R 0.01UF 01005 10% 6.3V X5R 0.01UF 01005 0.01UF X5R 6.3V 10% 0201 0.22UF X5R 6.3V 20% 0201 20% 6.3V X5R 0.22UF 0201 20% 6.3V X5R 0.22UF 0201 20% 6.3V X5R 0.22UF 0201 0.22UF X5R 6.3V 20% 0201 0.22UF X5R 6.3V 20% 01005 10% 0.01UF 6.3V X5R 4.3UF 0610 4V X5R-CERM 20% 10UF 603 6.3V X5R 20% X5R-CERM 0610 4.3UF 4V 20% 0201 20% 6.3V X5R 0.22UF 0402-1 CERM-X5R 10UF 6.3V 20% 0201 0.22UF X5R 6.3V 20% 6.3V X5R 0201 0.22UF 20% 56PF 5% NP0-C0G 01005 6.3V 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 0 5% NAND_IO_1V8 MF 1/20W 201 NAND_IO_3V3 MF 1/20W 0 5% 201 H4G FCBGA OMIT FCBGA H4G OMIT 01005 5% 6.3V NP0-C0G 56PF 01005 56PF NP0-C0G 6.3V 5% 01005 NP0-C0G 5% 56PF 6.3V 01005 NP0-C0G 5% 56PF 6.3V 01005 NP0-C0G 5% 56PF 6.3V 01005 NP0-C0G 5% 56PF 6.3V 56PF 5% NP0-C0G 01005 6.3V 6.3V X5R 0201 0.22UF 20% 0610 20% 4V X5R-CERM 4.3UF 0610 20% 4V X5R-CERM 4.3UF 0201 0.22UF X5R 6.3V 20% 6.3V X5R 0201 0.22UF 20% 0201 0.22UF X5R 6.3V 20% 4V X5R-CERM 0610 4.3UF 20% 6.3V X5R 0201 0.22UF 20% 0610 20% 4V X5R-CERM 4.3UF 603 10UF 6.3V X5R 20% 0610 4.3UF X5R-CERM 4V 20% 0201 0.22UF X5R 6.3V 20% 0201 20% 6.3V X5R 0.22UF 0201 20% 6.3V X5R 0.22UF 01005 10% 6.3V X5R 0.01UF 6.3V X5R 0201 0.22UF 20% 0201 0.22UF X5R 6.3V 20% 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 0610 4.3UF X5R-CERM 4V 20% 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% X5R-CERM 4V 0610 4.3UF 20% 0610 4V 4.3UF X5R-CERM 20% 4.3UF X5R-CERM 4V 0610 20% 6.3V 56PF 5% NP0-C0G 0100501005 NP0-C0G 5% 56PF 6.3V 6.3V X5R 0201 0.22UF 20% 138S0657138S0702 QTY 17 RADAR:8837828C1100,C1102 SYNC_MASTER=MIKE SYNC_DATE=N/A AP: POWER =PPVDD_SOC_H4 =PPVDD_CPU_H4 =PPVDD_SOC_H4 =PP1V2_VDDIOD_H4 =PP3V0_VDDIOD_H4 MAX_NECK_LENGTH=3 MM VOLTAGE=1.8V NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.2MM PPIO_NAND_H4 =PP1V8_VDDIOD_H4 =PP1V8_VDDIO18_H4 =PP3V0_IO_H4 =PP1V8_NAND_H4 =PP3V3_NAND_H4 C11971 2 C1196 1 2 C1192 1 2 C11951 2 C1124 1 2 C1132 1 2 C1131 1 2 C1122 1 2 C1121 1 2 C1130 1 2 C1129 1 2 C1191 1 2 C1194 1 2 C1103 1 2 C1102 1 2 C1111 1 2 C1110 1 2 C1109 1 2 C1104 1 2 C1108 1 2 C11591 2 C11601 2 C11611 2 C11621 2 C11631 2 C11641 2 C11651 2 C11661 2 C1154 1 2 C1155 1 2 C1156 1 2 C1152 1 2 C1151 1 2 C11841 2 C11701 2 C11711 2 C11741 2 C11731 2 C11721 2 C11831 2 C11811 2 C11821 2 C1101 1 2 C1100 1 2 C1123 1 2 C1117 1 2 C1105 1 2 C1107 1 2 C1106 1 2 C1126 1 2 C1125 1 2 C1135 1 2 C1134 1 2 C1133 1 2 C1138 1 2 C1137 1 2 C1136 1 2 C1150 1 2 C1153 1 2 C1157 1 2 C1158 1 2 C11751 2 C1190 1 2 C1193 1 2 C11771 2 C11761 2 C11991 2 C11981 2 R1100 1 2 R1101 1 2 U0600 AA9 AA11 AC11 U25 U27 V10 V12 V14 V16 W9 W11 W13 W15 AD10 W17 Y10 Y12 Y14 Y16 AE11 AF10 AF11 AF12 AG10 AG11 AG12 AG13 AA13 J13 J15 J17 J19 J21 J23 J25 J27 K12 K14 AA15 K16 K18 K20 K22 K24 K26 L9 L11 L13 L15 AA17 L17 L19 L21 L23 L25 L27 M10 M12 M14 M16 AB10 M18 M20 M22 M24 M26 N9 N11 N13 N15 N17 AB12 N19 N21 N23 N25 N27 P10 P12 P14 P16 P18AB14 P20 P22 P24 P26 R9 R11 R13 R15 R17 R19 AB16 R21 R23 R25 R27 T10 T12 T14 T16 T18 T20 AC9 T22 T24 T26 U11 U13 U15 U17 U19 U21 U23 U0600 AA19 AA21 AC19 AC21 AC23 AC25 AC26 AC27 AD18 AD20 AD22 AD24 AA23 AD26 AE19 AE21 AE23 AE25 AE27 V18 V20 V22 V24 AA25 V26 W19 W21 W23 W25 W27 Y18 Y20 Y22 Y24 AA27 Y26 AB18 AB20 AB22 AB24 AB26 N29 AJ17 AJ22 AJ25 AJ26 T8 V28 V8 AF15 AJ28 M29 N28 Y8 AH20 AK20 AL19 AK30 AH29 AE29 AF29 AB29 AC29 AA7 AB7 AJ10 AJ11 G7 G8 G9 G10 G12 G13 G14 G15 AC7 G16 H7 J7 K7 L7 M7 P7 R7 AD7 AF7 AG7 AH7 AJ7 AJ8 AJ9 C1140 1 2 C1141 1 2 C11421 2 C11441 2 C11431 2 C11451 2 C11461 2 051-8773 10.0.0 11 OF 157 9 OF 48 935 35 935 8 35 35 645 5 35 35 735 35 35
  • 13.
    IN OUT OUT OUT IN IN OUT OUT Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT 0101 0100 J2A DEV J2A AP 1111 RESERVED 1101 FMI0/1 4/4 CS 010 CURRENT SETTING -> 001 011 EVT PROTO 2 100 0100 FMI0 2CS 0010 SPI0 W/TEST 0011 SPI1 W/TEST 0000 SPI0 0101 FMI0 4CS 0111 RESERVED 1000 FMI1 2 CS BOOT_CONFIG[3:0] 0110 FMI0 4CS W/TEST 1010 FMI1 4CS W/TEST 1001 FMI1 4 CS 1100 FMI0/1 2/2 CS FOR REFERENCE 0001 SPI1 PROTO 1 CHINA PROTO 1 LOCAL 3. READ BOARD REVISION PROTO 0000 BRD_REV[2-0] 1110 FMI0/1 4/4 CS W/TEST 2. ENABLE PU AND DISABLE PD 1. SET GPIO AS INPUT S/W READ FLOW 0001 J2 DEV J2 AP J1 AP0000 BOARD_ID[2] BOARD_ID[1] BOARD_ID[0] BOARD_ID[3-0] J1 DEV BOARD_ID_3 BOARD ID DEVELOPMENT_JTAG 2-WIRE DAP SCAN DUMP JTAG_DAP PRODUCTION 3. READ 3. READ JTAG_DAP DEVELOPMENT_JTAG S/W READ FLOW JTAG I2C PULL-UPS 0010 0011 1. SET GPIO AS INPUT 1110 1101 1100 FMI0/1 4/4 CS BOOT_CONFIG[3-0] BOOT_CONFIG[3] (GPIO29) BOOT_CONFIG[0] (GPIO18) BOARD_ID[3] 2. DISABLE PU AND ENABLE PD FMI0/1 4/4 CS WITH TEST FMI0/1 2/2 CS BOOT_CONFIG[1] (GPIO25) BOOT_CONFIG[2] (GPIO28) S/W READ FLOW BOOT CONFIG ID 2. DISABLE PU AND ENABLE PD DEVELOPMENT_JTAG_TAP 1. SET GPIO AS INPUT MF 5% 01005 1/32W 10K J2 442 442 4104245 11 27 43 11 27 43 11 27 43 4 4 10 42 45 201 5% 1/20W 10K MF 5% 1/20W 10K 201 MF 1/32W MF 5% 01005 10K NOSTUFF 5% 01005 1/32W MF DEV 10K J2A 1/32W 10K MF 5% 01005 SHORT-01005NOSTUFF SHORT-01005NOSTUFF NOSTUFF SHORT-01005 100K MF 1/32W 01005 5% 01005 5% MF 1/32W 10K 1.00K 5% 1/32W MF 01005 1.00K 5% 1/32W MF 01005 1.00K 1/32W MF 01005 5%5% 01005 MF 1/32W 1.00K 5% 1/32W MF 01005 1.00K 5% 1/32W MF 1.00K 01005 NOSTUFF 201 5% MF 1/20W 10K JTAG_DAP 100 DEVELOPMENT_JTAG_TAP 1/32W 0.00 0% MF 01005 1/32W 0.00 0% MF DEVELOPMENT_JTAG_TAP 01005 100 JTAG_DAP 1/32W 0.00 0% MF DEVELOPMENT_JTAG_TAP 01005 1/20W 10K MF 201 5% 201 MF 1/20W 5% 10K NOSTUFF MF 10K 201 5% 1/20W SYNC_DATE=N/A AP: MISC & ALIASES SYNC_MASTER=ALEX =PP1V8_H4 PP3V0_SENSOR_FLT I2C0_SCL_1V8 I2C1_SDA_1V8 I2C2_SDA_3V0_ALS I2C1_SCL_1V8 AP_TESTMODE BOARD_ID_1 BOOT_CONFIG_1 BOOT_CONFIG_2 =PP1V8_H4 =PP1V8_H4 BOOT_CONFIG_0 BOOT_CONFIG_3 JTAG_AP_TRST_L AP_FAST_SCAN_CLK VIDEO_EMI_C_Y VIDEO_EMI_Y_PR VIDEO_EMI_CVBS_PB JTAG_AP_TDO JTAG_AP_TDI JTAG_AP_TRST_L AP_TST_STPCLK JTAG_AP_SEL AP_HOLD_RESET USB_AP_VBUS1 BOARD_ID_2 I2C2_SCL_3V0_ALS I2C0_SDA_1V8 BOARD_ID_0 GPIO42_BRD_REV2 GPIO41_BRD_REV1 GPIO40_BRD_REV0 R12051 2 R12021 2 R1210 1 2 R1212 1 2 R1213 1 2 R1211 1 2 R1214 1 2 R12071 2 R12081 2 R12091 2 R12011 2 R12001 2 R12031 2 R12061 2 R12041 2 XW1201 1 2 XW1200 1 2 XW1202 1 2 R1260 1 2 R1261 1 2 R07061 2 R07051 2 R07041 2 R07031 2 R07021 2 R07011 2 051-8773 10.0.0 12 OF 157 10 OF 48 471035 242645 519223742 52542 242542 52542 4 5 5 5 471035 471035 5 5 4 4 4 4 5 242542 519223742 5 5 5 5
  • 14.
    RX_VHIGH/USB_2D+ TX_VHIGH/USB_2D- CH.3_OUT CH.2_OUT CH.1_OUT VID_EN USB_1D- USB_1D+ SEL DGNDAGND CH.1_IN CH.2_IN CH.3_IN USB_D- USB_D+ RX_VLOW TX_VLOW VA_1 VDH VA_0 VDL OUT OUT OUT OUT INOUT IN BI BI BI BI IN IN IN IN IN Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_ALT_ITEM CVBSIN BB USB <-> H4P FS USBDOCK_BB_EN = 0: DOCK_BB_EN = 1: BB USB <-> DOCK SERIAL NOTE: H4P UART0 <-> DOCK SERIAL NOTE: PLACE R0960-62 NEAR U0900 CIN YIN ~15MA THS7380IZSYR UCSP CRITICAL 10 27 43 10 27 43 75 1/20W MF 1% 201 JTAG_DAP 201 MF 1% 75 JTAG_DAP 1/20W 201 1% MF 75 JTAG_DAP 1/20W 10 27 43 6.3V 0.1UF 10% X5R 201 MF 100K 5% 1/32W 01005 27 42 27 421542 1542 3042 3042 4 42 4 42 743 743 743 01005 6.3V 5% NP0-C0G 56PF 6.3V 0.1UF 10% X5R 201 100K 5% MF 01005 1/32W 5 37 1/32W 01005 5% 1.00M MF RADAR:9009078U1300343S0539 343S0520 AP: VIDEO BUFFER,BB USB MUXES SYNC_DATE=12/10/2010SYNC_MASTER=CHOPIN =PP3V0_VIDEO_BUF BUF_C_Y USB11_ACC_RX_P =PP3V2_S2R_USBMUX BUF_Y_PR PORT_DOCK_VIDEO_AMP_EN DAC_AP_OUT1 DAC_AP_OUT3 DAC_AP_OUT2 VIDEO_EMI_CVBS_PB VIDEO_EMI_Y_PR VIDEO_EMI_C_Y USB11_MUX_D0_N DOCK_BB_EN BUF_CVBS_PB USB11_MUX_D0_P USB11_ACC_TX_N USB_BB_D_N USB_BB_D_P UART0_MUX_RXD UART0_MUX_TXD U1300 B2 B3 A3 A2 A4 A1 B4 B1 D3 E3 E1 E4 C2 D1 D4 F1 F2 F4 F3 C1 C4 E2 D2 C3 R1360 1 2 R1361 1 2 R1362 1 2 C13701 2 R13721 2 C1301 1 2 C1300 1 2 R13201 2 R13151 2 051-8773 10.0.0 13 OF 157 11 OF 48 35 43 35 43 43
  • 15.
    TP TP TP TP TP TP TP TP TP TP IN IN IN IN IN IN IN IN IN IN IN IN IO0-1 IO7-1 IO6-1 IO3-1 IO4-1 IO5-1 IO1-1 IO2-1 IO7-0 IO5-0 IO6-0 IO4-0 IO2-0 IO3-0 IO1-0 IO0-0 VCC CLE1 CE1* CLE0 CE0* WE0* ALE0 RE0 RE0* DQS0* R/B0* DQS0 ALE1 WE1* RE1 RE1* DQS1 DQS1* R/B1* ZQ VREF VSSQVSS VCCQ VDDI TMSC TCKC BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI IN IN IN IN IN IN IN IN IN IN IN IN IO0-1 IO7-1 IO6-1 IO3-1 IO4-1 IO5-1 IO1-1 IO2-1 IO7-0 IO5-0 IO6-0 IO4-0 IO2-0 IO3-0 IO1-0 IO0-0 VCC CLE1 CE1* CLE0 CE0* WE0* ALE0 RE0 RE0* DQS0* R/B0* DQS0 ALE1 WE1* RE1 RE1* DQS1 DQS1* R/B1* ZQ VREF VSSQVSS VCCQ VDDI TMSC TCKC BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI NC NC NC NC NC NC NC NC Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT LEAVE VREF AS TP FOR MLB DO NOT PLACE IN NAND SINGLE PCS SHIELD CAN AREA TEST POINTS LEAVE VREF AS TP FOR MLB 10UF CERM-X5R 0402-1 6.3V 20% CERM 402-LF 2.2UF 6.3V 20% 0.1UF 10% 201 6.3V X5R 6 12 44 6 44 6 12 44 6 12 44 6 12 44 6 12 44 6 12 44 6 44 6 12 44 6 12 44 6 12 44 6 12 44 MF 1/20W 1% 243 201 0.1UF 10% 201 6.3V X5RCERM-X5R 0402-1 10UF 6.3V 20% 0402-1 CERM-X5R 10UF 6.3V 20% 0402-1 CERM-X5R 6.3V 20% 10UF LGA OMIT XXNM-XGBX8-MLC-PPN1.5-ODP 6.3V X5R 0201-MUR 1.0UF 20% 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 MF 1/20W 5% 1K NOSTUFF 201 1K 5% 1/20W MF NOSTUFF 201 0402-1 CERM-X5R 10UF 6.3V 20% 402-LF CERM 2.2UF 6.3V 20% 0.1UF 10% 201 6.3V X5R 0.1UF 10% 201 6.3V X5RCERM-X5R 0402-1 10UF 6.3V 20% CERM-X5R 0402-1 10UF 6.3V 20% 0402-1 CERM-X5R 10UF 6.3V 20% 6 44 6 12 44 6 12 44 6 12 44 6 12 44 6 12 44 6 44 6 12 44 6 12 44 6 12 44 6 12 44 6 12 44 OMIT XXNM-XGBX8-MLC-PPN1.5-ODP LGA MF 1/20W 1% 243 201 6.3V X5R 1.0UF 20% 0201-MUR 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 61244 MF 1/20W 5% 1K NOSTUFF 201 1K MF 5% 1/20W NOSTUFF 201 0.22UF 6.3V X5R 0201 20% 0.22UF 6.3V X5R 0201 20% 0.22UF 6.3V X5R 0201 20% 0.22UF 6.3V X5R 20% 0201 0.22UF 6.3V X5R 0201 20% 0.22UF 6.3V X5R 0201 20% 0.22UF 6.3V X5R 0201 20% 0.22UF 6.3V X5R 0201 20% 5% 1/32W MF 01005 100K 01005 MF 1/32W 5% 100K NAND_IO_3V3 MF 1/20W 0 5% 201 MF 0 5% NAND_IO_1V8 201 1/20W 6.3V X5R 0201-MUR 20% 1.0UF 6.3V X5R 0201-MUR 1.0UF 20% SYNC_DATE=N/A NAND SYNC_MASTER=MIKE FMI0_AD<0> MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.2MM VOLTAGE=1.8V PPVCCQ_NAND =PP3V3_NAND MIN_NECK_WIDTH=0.1MM VOLTAGE=3.3V MAX_NECK_LENGTH=3MM PPVDDI_NAND_U1400 NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.2MM FMI1_AD<0> FMI0_ALE FMI0_WE_L =PP3V3_NAND VOLTAGE=3.3V MIN_LINE_WIDTH=0.2MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM MIN_NECK_WIDTH=0.1MM PPVDDI_NAND_U1410 PPVCCQ_NAND VOLTAGE=1.8V NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.2MM MAX_NECK_LENGTH=3 MM FMI1_RE_N FMI0_RE_N FMI0_AD<1> =PP1V8_NAND FMI0_AD<7> FMI1_CLE FMI0_RE_N FMI0_AD<2> FMI0_AD<1> FMI1_AD<2> FMI1_AD<1> FMI1_AD<0> FMI0_AD<7> FMI0_AD<6> FMI0_AD<5> FMI0_AD<4> FMI0_AD<0> FMI0_ALE FMI0_CLE FMI0_WE_L FMI0_CE1_L FMI0_CLE FMI0_ALE FMI0_WE_L FMI0_RE_N FMI1_CLE FMI1_ALE FMI1_WE_L FMI1_RE_N FMI1_DQS_P TP_VREF_SLOT1 FMI_ZQ_U1410 FMI_TCKC_U1400 FMI1_DQS_P FMI1_ALE FMI0_DQS_P FMI0_CE0_L FMI1_CE0_L FMI0_AD<0> FMI0_AD<3> FMI0_AD<2> FMI0_AD<4> FMI1_AD<5> FMI1_AD<4> FMI1_AD<3> FMI1_AD<6> FMI1_AD<7> FMI1_AD<1> FMI1_AD<0> FMI0_AD<5> FMI0_CLE FMI1_AD<2> FMI1_RE_N FMI1_ALE FMI1_WE_L FMI1_CLE FMI_TMSC_U1400 FMI0_AD<6> FMI1_AD<5> FMI_ZQ_U1400 TP_VREF_SLOT0 FMI1_WE_L FMI_TMSC_U1410 FMI_TCKC_U1410 FMI1_AD<7> FMI1_AD<6> FMI1_CE1_L FMI0_DQS_P NAND_SLOT1_RDYBSY_L FMI1_AD<4> FMI1_AD<3> FMI0_AD<3> NAND_SLOT0_RDYBSY_L =PP3V3_NAND TP14001 TP14011 TP14021 TP14031 TP14041 TP14051 TP14061 TP14071 TP14081 TP14091 C14321 2 C14311 2 C14301 2 R14741 2 C14241 2 C14221 2 C14211 2 C14201 2 U1410 C1 D2 A5 C5 A3 C3 H4 F4 M4 K4 G3 G1 H2 J1 J3 L1 K2 N3 L5 N5 K6 L7 J5 J7 H6 G7 E5 E7 B4 C7 D4 D6 OA0 OB0 B6 F2 M6 N1 N7 OC8 OD8 OE0 OF8 G0 OA8 OB8 G5 B2 F6 L3 A7 M2 OC0 OD0 OE8 OF0 G8 E3 E1 A1 C14701 2 R14731 2 R14721 2 C14121 2 C14111 2 C14101 2 C14041 2 C14021 2 C14011 2 C14001 2 U1400 C1 D2 A5 C5 A3 C3 H4 F4 M4 K4 G3 G1 H2 J1 J3 L1 K2 N3 L5 N5 K6 L7 J5 J7 H6 G7 E5 E7 B4 C7 D4 D6 OA0 OB0 B6 F2 M6 N1 N7 OC8 OD8 OE0 OF8 G0 OA8 OB8 G5 B2 F6 L3 A7 M2 OC0 OD0 OE8 OF0 G8 E3 E1 A1 R14541 2 C14501 2 R14531 2 R14521 2 C14131 2 C14141 2 C14341 2 C14331 2 C14061 2 C14051 2 C14261 2 C14251 2 R1455 1 2 R1475 1 2 R1401 1 2 R1400 1 2 C14511 2 C14711 2 051-8773 10.0.0 14 OF 157 12 OF 48 12 45 1235 45 61244 12 35 12 45 61244 35 61244 61244 61244 61244 61244 61244 61244 61244 1235
  • 16.
    CK_1 DQ13_2 DQ14_2 DQ2_2 DQ1_2 DQ0_2 CKB_2 CKE_2 DQ21_1 DQ12_1 DQ11_1 DQ10_1 DQ0_1 DQ1_1 DQ2_1 DQ3_1 DQ4_1 DQ5_1 CSB_1 CKE_1 CKB_1 CA9_1 CA8_1 CA7_1 CA6_1 CA5_1 CA4_1 CA3_1 CA2_1 CA1_1 CA0_1 DQSB2_1 DQS2_1 DQ20_1 DQ19_1 DQ22_1 DQ23_1 DQ18_1 DQ16_1 DQ17_1 DQ15_1 DQ14_1 DQ13_1 DQ9_1 DQ7_1 DQ8_1 DQ6_1 DQ24_1 DQ31_1 DQ30_1 DQ31_2 DQ29_2 DQ30_2 DQ28_2 DQ26_2 DQ27_2 DQ25_2 DQ24_2 DQ23_2 DQ21_2 DQ22_2 DQ20_2 DQ19_2 DQ18_2 DQ17_2 DQ16_2 DQ15_2 DQ12_2 DQ11_2 DQ10_2 DQ8_2 DQ9_2 DQ6_2 DQ7_2 DQ5_2 DQ4_2 DQ3_2 DQSB3_2 DQS3_2 CA7_2 CA8_2 CA9_2 CK_2 DQS1_2 VREFCA_1 VREFCA_2 VREFDQ_1 VREFDQ_2 ZQ_1ZQ_2 DQSB3_1 DQSB2_2 DQSB1_2DQSB1_1 DQSB0_2DQSB0_1 DQS3_1 DQS2_2 DQS1_1 DQS0_2DQS0_1 DQ29_1 DQ28_1 DQ27_1 DQ26_1 DQ25_1 CA6_2 CA5_2 CA4_2 CA3_2 CA2_2 CA1_2 CA0_2 DM0_1 DM1_1 DM2_1 DM3_1 CSB_2 DM0_2 DM1_2 DM2_2 DM3_2 DDR_1 DDR_2 SYM 1 OF 2 VDD1_3 VDD1_1 VSS55 VSS51 VSS6 VSS49 VSS4 VSS3 VDDQ33 VDDCA1 VDDCA2 VSS46 VDD1_0 VDD1_8 VDD1_5 VDD1_6 VDD1_7 VSS52 VSS0 VSS2 VSS7 VSS9 VSS10 VSS13 VSS18 VSS20 VSS32 VSS33 VSS34 VSS42 VSS43 VSS44 VSS29 VSS28 VSS27 VSS26 VSS25 VSS23 VSS22 VSS47 VSS53 VSS48 VSS50 VSS1 VSS12 VDD1_11 VDD2_3 VDD2_2 VDD1_2 VDD2_6 VDD2_7 VDD2_13 VDD2_14 VDD2_16 VDDQ27 VDDQ32 VDDQ31 VDDQ VDDQ6 VDDQ23 VDDQ30 VDDQ22 VDDQ16 VDDQ34 VDDQ17 VDDQ21 VDDQ19 VDDQ24 VDDQ20 VDDQ28 VDDCA3 VDDCA4 VDDCA5 VDDCA6 VDDCA7 VDDCA8 VDD2_1 VDDQ26 VDDQ25 VSS24 VDD2_9 VDD2_8 VDDQ1 VDD1_9 VDD1_10 VDDCA9 VDDCA10 VDDQ29 VDDQ3 VDD1_4 VDD2_5 VDD2_4 VDD2_15 VSS41 VSS40 VSS39 VSS54 VSS36 VSS35 VDD2_10 VDD2_11 VDD2_12 VSS45 VDD2VDDQVDDCAVDD1 VSS SYM 2 OF 2 Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% XXXMB BGA H4G-DRAM OMIT XXXMB H4G-DRAM BGA OMIT 4.3UF 4V X5R-CERM 0610 20% 603 10UF 6.3V X5R 20% 56PF NP0-C0G 01005 5% 6.3V 6.3V X5R 0201 0.22UF 20% 56PF NP0-C0G 01005 5% 6.3V 0.01UF 10% 01005 6.3V X5R 6.3V X5R 0201 0.22UF 20% 10V 10% 0.01UF X5R 201 01005 0.01UF 10% 6.3V X5R 6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20% 1UF 10% CERM 402 6.3V 10% CERM 1UF 402 6.3V CERM 10% 1UF 402 6.3V 402 10% CERM 1UF 6.3V X5R-CERM 4V 0610 4.3UF 20% 10UF 603 6.3V X5R 20% 603 10UF 6.3V X5R 20% NP0-C0G 01005 56PF 5% 6.3V6.3V X5R 0201 0.22UF 20% 6.3V X5R 0201 0.22UF 20%6.3V X5R 0201 0.22UF 20% 10% 01005 0.01UF 6.3V X5R 5% 56PF 01005 NP0-C0G 6.3V 0.01UF 01005 10% 6.3V X5R 6.3V X5R 0201 0.22UF 20% 10% 402 CERM 1UF 6.3V 6.3V X5R 0201 0.22UF 20% 10% 402 CERM 1UF 6.3V 6.3V X5R 0201 0.22UF 20% 603 10UF 6.3V X5R 20% MF 1/20W 1% 240 201 MF 1/20W 1% 240 201 2.21K 1% 1/32W MF 01005 NOSTUFF 10% 01005 0.01UF 6.3V X5R 01005 MF 2.21K 1% 1/32W 01005 MF 1% 1/32W 2.21K NOSTUFF 10% 01005 0.01UF 6.3V X5R 01005 2.21K 1% MF 1/32W 01005 MF 1% 1.00K 1/32W NOSTUFF 10% 01005 0.01UF 6.3V X5R 01005 1% 1/32W 1.00K MF 01005 1/32W MF 1% 1.00K NOSTUFF 0.01UF 10% 01005 6.3V X5R 0.01UF 10% 01005 6.3V X5R 01005 1.00K MF 1% 1/32W NOSTUFF 0.01UF 01005 10% 6.3V X5R 0.01UF 01005 10% NOSTUFF 6.3V X5R 0.01UF 01005 10% NOSTUFF 6.3V X5R 0.01UF 01005 10% NOSTUFF 6.3V X5R 6.3V X5R 0201 0.22UF 20% SYNC_MASTER=MIKE DDR 0 AND 1 SYNC_DATE=06/21/2010 PPVREF_DDR0_CA NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM PPVREF_DDR0_CA MAX_NECK_LENGTH=3 MM VOLTAGE=0.6V PPVREF_DDR0_DQ NET_SPACING_TYPE=PWR PPVREF_DDR0_DQ VOLTAGE=0.6V MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM MAX_NECK_LENGTH=3 MM PPVREF_DDR1_CA NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.3MM VOLTAGE=0.6V MIN_NECK_WIDTH=0.2MM PPVREF_DDR1_CA PPVREF_DDR1_DQ NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0.6V PPVREF_DDR1_DQ DDR1_DM<3> DDR1_DM<1> DDR0_DQ<8> =PP1V2_VDDQ_DDR DDR0_DQ<30> DDR0_DQ<27> DDR1_DQ<5> DDR0_DQ<1> DDR0_DQ<2> DDR0_DQ<3> DDR0_DQ<4> DDR0_DQ<5> DDR0_DQ<6> DDR0_DQ<10> DDR0_DQ<13> DDR0_DQ<24> DDR0_DQ<25> DDR0_DQ<26> DDR0_DQ<28> DDR0_DQ<12> DDR0_DQ<11> DDR0_DQ<0> DDR0_DM<2> DDR0_DM<3> DDR0_DM<0> DDR0_DQ<7> DDR0_DQS_N<2> =PP1V2_S2R_DDR DDR1_DQ<30> DDR1_DQ<26> DDR0_DQ<18> DDR1_DQ<25> DDR0_DQ<14> DDR0_DQ<9> DDR0_DQ<15> DDR1_DQ<7> DDR1_DQ<6> DDR1_DQ<4> DDR1_DQ<3> DDR1_DQ<2> DDR1_DQ<1> DDR1_DQ<0> DDR1_DQ<8> DDR1_DQ<9> DDR1_DQ<10> DDR1_DQ<11> DDR1_DQ<12> DDR1_DQ<14> DDR1_DQ<15> DDR1_DQ<13> DDR0_DQS_P<3> =PP1V2_S2R_DDR =PP1V8_S2R_DDR DDR1_DQS_P<0> DDR1_DQS_N<1> =PP1V2_VDDQ_DDR =PP1V2_VDDQ_DDR =PP1V2_S2R_DDR =PP1V2_S2R_DDR DDR0_CSN<0> DDR1_DM<2> DDR1_DM<0> DDR0_CA<0> DDR0_CA<1> DDR0_CA<2> DDR0_CA<3> DDR0_CA<4> DDR0_CA<5> DDR0_CA<6> DDR1_DQ<17> DDR1_DQ<18> DDR1_DQ<19> DDR1_DQ<20> DDR1_DQ<21> DDR1_DQS_P<1> DDR1_DQS_P<2> DDR1_DQS_N<0> DDR0_DQS_N<1> DDR0_DQS_N<3> DDR1_DQS_N<2> DDR0_ZQDDR1_ZQ DDR0_CK_P DDR0_CA<9> DDR0_CA<8> DDR0_CA<7> DDR0_DQS_P<2> DDR0_DQ<29> DDR0_DQ<31> DDR0_DQ<23> DDR1_DQ<22> DDR1_DQ<23> DDR1_DQ<16> DDR1_DQ<24> DDR1_DQ<31> DDR1_DQ<27> DDR1_DQ<28> DDR1_DQS_P<3> DDR1_DQS_N<3> DDR1_CA<0> DDR1_CA<1> DDR1_CA<4> DDR1_CA<5> DDR1_CA<6> DDR1_CA<7> DDR1_CA<8> DDR1_CA<9> DDR1_CK_N DDR1_CKE<0> DDR1_CSN<0> DDR1_DQ<29> DDR0_CKE<0> DDR0_CK_N DDR1_CK_P DDR0_DM<1> DDR1_CA<3> DDR1_CA<2> DDR0_DQ<16> DDR0_DQ<22> DDR0_DQ<19> DDR0_DQ<20> DDR0_DQ<17> DDR0_DQS_P<1> DDR0_DQS_N<0> DDR0_DQS_P<0> DDR0_DQ<21> C1622 1 2 C1621 1 2 C1620 1 2 C16231 2 C16131 2 C1619 1 2 C1605 1 2 C1612 1 2 C1618 1 2 C1604 1 2 C1611 1 2 C1610 1 2 C16171 2 C1603 1 2 C1616 1 2 C1602 1 2 C1615 1 2 C1601 1 2 C1614 1 2 C1609 1 2 C16081 2 C16071 2 C1606 1 2 C1631 1 2 C1635 1 2 C1630 1 2 C16341 2 C1629 1 2 C16331 2 C1628 1 2 C1632 1 2 C1627 1 2 R16201 2 R16211 2 R16051 2 C16501 2 R16061 2 R16511 2 C16521 2 R16521 2 R16531 2 C16541 2 R16541 2 R16551 2 C16561 2 R16561 2 C16601 2 C16621 2 C16631 2 C16611 2 C1626 1 2 C1625 1 2 C16241 2 U1600 T15 G16 U15 G17 U14 H17 V14 H18 T13 J16 T9 N16 U9 N17 U8 P17 V8 P18 T7 R16 U12 K17 U11 L17 V13 J18 U13 J17 C12 K3 B10 M2 B16 G4 D7 T2 C15 G3 B8 P5 C8 P4 D8 P3 E8 P2 B7 R4 C7 R3 B18 B2 C18 C2 D18 D3 E18 D2 D15 G2 B17 E4 D17 E3 E17 E2 E16 F2 B6 T5 B5 U5 C5 U4 D5 U2 B4 V5 C4 V4 B14 H5 B3 V3 C3 V2 C14 H4 D14 H3 E14 H2 B13 J3 C13 J2 C9 N4 D9 N3 D13 J4 D10 M4 C16 F4 D6 T3 D12 K4 C10 M3 D16 F3 C6 T4 U10 M17 D11 L4 U7 R17 U1600 A2 B1 W17 U19 B11 F17 L2 M16 T10 U18 V17 V6 E11 W5 W16 W19 W18 V19 A3 T19 E19 L5 M18 U17 T18 V10 V16 V18 F18 T8 H16 K16 L16 P16 T11 T12 T14 V7 E1 U1 J5 K2 N2 R5 A8 A10 A14 A13 C17 C19 H1 E10 E15 B12 U3 W3 M1 P1 A17 D4 A16 A1 D19 E12 E13 F16 A4 G18 J1 K18 K5 L18 L3 M5 N18 N5 A6 R18 R2 T1 T17 U16 U6 B15 V11 V12 V15 T6 V9 W1 W4 A18 B19 C1 E7 G5 T16 V1 W2 A19 B9 C11 D1 051-8773 10.0.0 16 OF 157 13 OF 48 13 44 45 13 44 45 13 44 45 13 44 45 134445 13 44 45 134445 13 44 45 844 844 8 44 131435 8 44 8 44 844 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 40 44 8 44 8 44 8 44 8 44 8 44 131435 844 844 8 44 844 8 40 44 8 44 8 44 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 8 44 131435 1435 844 844 131435 131435 131435 131435 8 44 844 844 8 44 8 44 8 44 8 44 8 44 8 44 8 44 844 844 844 844 844 844 844 844 8 40 44 8 44 844 4444 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 8 44 8 44 844 8 44 844 844 8 44 8 44 8 44 8 44 8 44 8 44 8 40 44 8 40 44 8 44
  • 17.
    CK_1 DQ13_2 DQ14_2 DQ2_2 DQ1_2 DQ0_2 CKB_2 CKE_2 DQ21_1 DQ12_1 DQ11_1 DQ10_1 DQ0_1 DQ1_1 DQ2_1 DQ3_1 DQ4_1 DQ5_1 CSB_1 CKE_1 CKB_1 CA9_1 CA8_1 CA7_1 CA6_1 CA5_1 CA4_1 CA3_1 CA2_1 CA1_1 CA0_1 DQSB2_1 DQS2_1 DQ20_1 DQ19_1 DQ22_1 DQ23_1 DQ18_1 DQ16_1 DQ17_1 DQ15_1 DQ14_1 DQ13_1 DQ9_1 DQ7_1 DQ8_1 DQ6_1 DQ24_1 DQ31_1 DQ30_1 DQ31_2 DQ29_2 DQ30_2 DQ28_2 DQ26_2 DQ27_2 DQ25_2 DQ24_2 DQ23_2 DQ21_2 DQ22_2 DQ20_2 DQ19_2 DQ18_2 DQ17_2 DQ16_2 DQ15_2 DQ12_2 DQ11_2 DQ10_2 DQ8_2 DQ9_2 DQ6_2 DQ7_2 DQ5_2 DQ4_2 DQ3_2 DQSB3_2 DQS3_2 CA7_2 CA8_2 CA9_2 CK_2 DQS1_2 VREFCA_1 VREFCA_2 VREFDQ_1 VREFDQ_2 ZQ_1ZQ_2 DQSB3_1 DQSB2_2 DQSB1_2DQSB1_1 DQSB0_2DQSB0_1 DQS3_1 DQS2_2 DQS1_1 DQS0_2DQS0_1 DQ29_1 DQ28_1 DQ27_1 DQ26_1 DQ25_1 CA6_2 CA5_2 CA4_2 CA3_2 CA2_2 CA1_2 CA0_2 DM0_1 DM1_1 DM2_1 DM3_1 CSB_2 DM0_2 DM1_2 DM2_2 DM3_2 DDR_1 DDR_2 SYM 1 OF 2 VDD1_3 VDD1_1 VSS55 VSS51 VSS6 VSS49 VSS4 VSS3 VDDQ33 VDDCA1 VDDCA2 VSS46 VDD1_0 VDD1_8 VDD1_5 VDD1_6 VDD1_7 VSS52 VSS0 VSS2 VSS7 VSS9 VSS10 VSS13 VSS18 VSS20 VSS32 VSS33 VSS34 VSS42 VSS43 VSS44 VSS29 VSS28 VSS27 VSS26 VSS25 VSS23 VSS22 VSS47 VSS53 VSS48 VSS50 VSS1 VSS12 VDD1_11 VDD2_3 VDD2_2 VDD1_2 VDD2_6 VDD2_7 VDD2_13 VDD2_14 VDD2_16 VDDQ27 VDDQ32 VDDQ31 VDDQ VDDQ6 VDDQ23 VDDQ30 VDDQ22 VDDQ16 VDDQ34 VDDQ17 VDDQ21 VDDQ19 VDDQ24 VDDQ20 VDDQ28 VDDCA3 VDDCA4 VDDCA5 VDDCA6 VDDCA7 VDDCA8 VDD2_1 VDDQ26 VDDQ25 VSS24 VDD2_9 VDD2_8 VDDQ1 VDD1_9 VDD1_10 VDDCA9 VDDCA10 VDDQ29 VDDQ3 VDD1_4 VDD2_5 VDD2_4 VDD2_15 VSS41 VSS40 VSS39 VSS54 VSS36 VSS35 VDD2_10 VDD2_11 VDD2_12 VSS45 VDD2VDDQVDDCAVDD1 VSS SYM 2 OF 2 Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT 20% 0.22UF 0201 X5R 6.3V 20% X5R 6.3V 603 10UF 20% 0.22UF 0201 X5R 6.3V 6.3V NP0-C0G 56PF 5% 01005 X5R 6.3V 0.01UF 01005 10% 6.3V NP0-C0G 5% 56PF 01005 X5R 6.3V 01005 10% 0.01UF 6.3V 01005 5% NP0-C0G 56PF 20% 0.22UF 0201 X5R 6.3V 201 X5R 0.01UF 10% 10V 20% 0.22UF 0201 X5R 6.3V X5R 6.3V 01005 10% 0.01UF 6.3V CERM 1UF 10% 402 20% 0.22UF 0201 X5R 6.3V 20% 0610 4V 4.3UF X5R-CERM 6.3V 1UF 10% CERM 402 20% X5R-CERM 4.3UF 4V 0610 6.3V 01005 5% 56PF NP0-C0G X5R 6.3V 0.01UF 01005 10% 6.3V 1UF 10% 402 CERM 6.3V 1UF CERM 10% 402 20% X5R 6.3V 10UF 603 20% X5R 6.3V 10UF 603 X5R 6.3V 01005 10% 0.01UF 20% X5R 6.3V 10UF 603 20% 0.22UF 0201 X5R 6.3V20% 0.22UF 0201 X5R 6.3V 20% 0.22UF 0201 X5R 6.3V 201 240 1% 1/20W MF 201 MF 1/20W 1% 240 20% 0.22UF 0201 X5R 6.3V X5R 6.3V NOSTUFF 0.01UF 01005 10% 2.21K 01005 1/32W MF 1% 01005 MF 2.21K 1% 1/32W X5R 6.3V NOSTUFF 10% 01005 0.01UF 01005 MF 2.21K 1% 1/32W 2.21K 01005 1% 1/32W MF 1.00K 01005 MF 1% 1/32W 6.3V 10% 402 CERM 1UF X5R 6.3V NOSTUFF 10% 01005 0.01UF1.00K 01005 1% 1/32W MF 01005 1/32W MF 1% 1.00K X5R 6.3V NOSTUFF 0.01UF 10% 0100501005 1.00K MF 1% 1/32W 20% 0.22UF 0201 X5R 6.3V X5R 6.3V NOSTUFF 0.01UF 01005 10% X5R 6.3V NOSTUFF 0.01UF 01005 10% X5R 6.3V 0.01UF 01005 10% NOSTUFF X5R 6.3V NOSTUFF 10% 01005 0.01UF 20% 0.22UF 0201 X5R 6.3V 20% 0.22UF 0201 X5R 6.3V 20% 0.22UF 0201 X5R 6.3V 6.3V 1UF CERM 10% 402 BGA XXXMB H4G-DRAM OMIT BGA H4G-DRAM XXXMB OMIT DDR 2 AND 3 SYNC_DATE=06/21/2010SYNC_MASTER=MIKE NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.3MM PPVREF_DDR2_CA MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0.6V PPVREF_DDR2_CA PPVREF_DDR2_DQ NET_SPACING_TYPE=PWR PPVREF_DDR2_DQ MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0.6V MAX_NECK_LENGTH=3 MM PPVREF_DDR3_CA NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM PPVREF_DDR3_CA VOLTAGE=0.6V PPVREF_DDR3_DQ NET_SPACING_TYPE=PWR PPVREF_DDR3_DQ MIN_LINE_WIDTH=0.3MM VOLTAGE=0.6V MIN_NECK_WIDTH=0.2MM MAX_NECK_LENGTH=3 MM DDR3_DM<2> DDR3_DM<3> DDR3_DM<1> DDR3_DM<0> =PP1V2_S2R_DDR DDR2_DQS_P<1> DDR3_DQ<14> DDR3_DQ<11> DDR3_CSN<0> DDR2_DQ<7> DDR2_DQ<6> DDR2_DQ<4> DDR2_DQ<2> DDR2_DQ<0> DDR2_DQ<1> DDR2_DQ<10> DDR2_DQ<15> DDR2_DQ<8> DDR2_DQ<14> DDR2_DQ<9> DDR2_DQ<13> DDR2_DQ<12> DDR2_DQ<11> DDR3_DQ<4> DDR3_DQ<3> DDR3_DQ<2> DDR3_DQ<7> DDR3_DQ<6> DDR3_DQ<5> DDR3_DQ<1> DDR3_DQ<0> DDR3_DQ<8> DDR3_DQ<9> DDR3_DQ<10> DDR3_DQ<12> DDR3_DQ<13> DDR3_DQ<15> =PP1V2_VDDQ_DDR =PP1V2_VDDQ_DDR =PP1V2_S2R_DDR DDR2_DM<2> DDR2_DM<1> DDR2_DM<0> DDR2_CSN<0> DDR2_CA<0> DDR2_CA<1> DDR2_CA<2> DDR2_CA<3> DDR2_CA<4> DDR2_CA<5> DDR2_CA<6> DDR3_DQ<17> DDR3_DQ<18> DDR3_DQ<19> DDR3_DQ<20> DDR3_DQ<21> DDR3_DQS_P<0> DDR2_DQS_P<0> DDR3_DQS_P<1> DDR2_DQS_P<3> DDR3_DQS_P<2> DDR3_DQS_N<0> DDR2_DQS_N<0> DDR3_DQS_N<1> DDR2_DQS_N<1> DDR2_DQS_N<3> DDR3_DQS_N<2> DDR2_ZQDDR3_ZQ DDR2_CK_P DDR2_CA<9> DDR2_CA<8> DDR2_CA<7> DDR2_DQS_P<2> DDR2_DQS_N<2> DDR2_DQ<24> DDR2_DQ<25> DDR2_DQ<26> DDR2_DQ<27> DDR2_DQ<30> DDR2_DQ<28> DDR2_DQ<29> DDR2_DQ<31> DDR2_DQ<16> DDR2_DQ<20> DDR2_DQ<19> DDR2_DQ<18> DDR2_DQ<23> DDR2_DQ<22> DDR2_DQ<21> DDR2_DQ<17> DDR3_DQ<22> DDR3_DQ<23> DDR3_DQ<16> DDR3_DQ<25> DDR3_DQ<24> DDR3_DQ<26> DDR3_DQ<31> DDR3_DQ<30> DDR3_DQ<27> DDR3_DQ<28> DDR3_DQS_P<3> DDR3_DQS_N<3> DDR3_CA<0> DDR3_CA<1> DDR3_CA<2> DDR3_CA<3> DDR3_CA<4> DDR3_CA<5> DDR3_CA<6> DDR3_CA<7> DDR3_CA<9> DDR3_CK_N DDR3_CKE<0> DDR3_DQ<29> DDR2_CKE<0> DDR2_CK_N DDR3_CK_P =PP1V2_S2R_DDR =PP1V2_S2R_DDR =PP1V8_S2R_DDR DDR2_DM<3> DDR3_CA<8> DDR2_DQ<3> DDR2_DQ<5> =PP1V2_VDDQ_DDR C17231 2 C1705 1 2 C1709 1 2 C1704 1 2 C17081 2 C1703 1 2 C17071 2 C1702 1 2 C1706 1 2 C1701 1 2 C17131 2 C1719 1 2 C1722 1 2 C1731 1 2 C1735 1 2 C1712 1 2 C1718 1 2 C1711 1 2 C17171 2 C1710 1 2 C1715 1 2 C1716 1 2 C1721 1 2 C1730 1 2 C1729 1 2 C1728 1 2 C1714 1 2 C1720 1 2 C1727 1 2 C17341 2 C17331 2 C1732 1 2 R17201 2 R17211 2 C17501 2 R17051 2 R17061 2 C17521 2 R17511 2 R17521 2 R17531 2 C17541 2 R17541 2 R17551 2 C17561 2 R17561 2 C17601 2 C17611 2 C17621 2 C17631 2 C1726 1 2 C1725 1 2 C17241 2 U1700 T15 G16 U15 G17 U14 H17 V14 H18 T13 J16 T9 N16 U9 N17 U8 P17 V8 P18 T7 R16 U12 K17 U11 L17 V13 J18 U13 J17 C12 K3 B10 M2 B16 G4 D7 T2 C15 G3 B8 P5 C8 P4 D8 P3 E8 P2 B7 R4 C7 R3 B18 B2 C18 C2 D18 D3 E18 D2 D15 G2 B17 E4 D17 E3 E17 E2 E16 F2 B6 T5 B5 U5 C5 U4 D5 U2 B4 V5 C4 V4 B14 H5 B3 V3 C3 V2 C14 H4 D14 H3 E14 H2 B13 J3 C13 J2 C9 N4 D9 N3 D13 J4 D10 M4 C16 F4 D6 T3 D12 K4 C10 M3 D16 F3 C6 T4 U10 M17 D11 L4 U7 R17 U1700 A2 B1 W17 U19 B11 F17 L2 M16 T10 U18 V17 V6 E11 W5 W16 W19 W18 V19 A3 T19 E19 L5 M18 U17 T18 V10 V16 V18 F18 T8 H16 K16 L16 P16 T11 T12 T14 V7 E1 U1 J5 K2 N2 R5 A8 A10 A14 A13 C17 C19 H1 E10 E15 B12 U3 W3 M1 P1 A17 D4 A16 A1 D19 E12 E13 F16 A4 G18 J1 K18 K5 L18 L3 M5 N18 N5 A6 R18 R2 T1 T17 U16 U6 B15 V11 V12 V15 T6 V9 W1 W4 A18 B19 C1 E7 G5 T16 V1 W2 A19 B9 C11 D1 051-8773 10.0.0 17 OF 157 14 OF 48 14 45 14 45 14 45 14 45 1445 14 45 1445 14 45 844 844 844 844 131435 8 44 844 844 844 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 844 844 844 844 844 844 844 844 844 844 844 844 844 844 131435 131435 131435 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 844 844 844 844 844 844 8 44 844 8 44 844 844 8 44 844 8 44 8 44 844 4444 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 8 44 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 844 8 44 8 44 844 131435 131435 1335 8 44 844 8 44 8 44 131435
  • 18.
    Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT NEED TO DOUBLE CHECK IF WE NEED THIS IN IPAD, OR IF THIS MIGHT BE A PHONE SPECIFIC ISSUE WIFI ALIASES UART ALIASES OBSOLETE ALIASES SYNC_MASTER=ALEX SYNC_DATE=09/30/2010 MLB ALIASES/CONNECTIONS EXT_PWM_REQ UART0_MUX_TXD UART0_MUX_RXDUART0_AP_RXD MAKE_BASE=TRUE UART0_AP_TXD MAKE_BASE=TRUE WLAN_GPIO4MAKE_BASE=TRUEUART6_WLAN_RXD MAKE_BASE=TRUEUART6_WLAN_TXD HSIC_STROBE_4330 WLAN_ENABLE WLAN_GPIO0 I2S2_VSP_LRCK MAKE_BASE=TRUE BT_PCM_SYNC WLAN_GPIO3 I2S2_VSP_DIN MAKE_BASE=TRUE BT_PCM_DOUT I2S2_VSP_DOUT MAKE_BASE=TRUE BT_PCM_DIN UART3_BT_CTS_L MAKE_BASE=TRUE BT_UART_RTS_N CLK_32K_WLAN MAKE_BASE=TRUE CLK32K I2S2_VSP_BCLK MAKE_BASE=TRUE BT_PCM_CLK UART3_BT_RTS_L MAKE_BASE=TRUE BT_UART_CTS_N UART3_BT_TXD MAKE_BASE=TRUE BT_UART_RXD PM_BT_HOST_WAKE MAKE_BASE=TRUE BT_HOST_WAKE MAKE_BASE=TRUEPM_BT_WAKE BT_WAKE UART3_BT_RXD MAKE_BASE=TRUE BT_UART_TXD MAKE_BASE=TRUERST_BT_L BT_RESET_N RST_WLAN_L MAKE_BASE=TRUE MAKE_BASE=TRUEPM_WLAN_HOST_WAKE MAKE_BASE=TRUEHSIC_HOST_READY_WLAN WLAN_GPIO1 MAKE_BASE=TRUEHSIC1_WLAN_DATA1 HSIC_DATA_4330 MAKE_BASE=TRUEHSIC1_WLAN_STB1 MAKE_BASE=TRUEHSIC_WLAN_RDY HSIC_DEVICE_READY MAKE_BASE=TRUENC_EXT_SMPS_REQ MAKE_BASE=TRUENC_EXT_PWM_REQ MAKE_BASE=TRUENC_BT_GPIO5 EXT_SMPS_REQ BT_GPIO5 MAKE_BASE=TRUETP_WLAN_GPIO5 MAKE_BASE=TRUEGSM_TXBURST_IND LED_DRIVE_GSMB WLAN_GPIO5 051-8773 10.0.0 21 OF 157 15 OF 48 11 42 11 42542 542 31 33542 542 31 33 31 33 31 33 51942 31 31 33 51942 31 51942 31 542 31 33 3742 32 33 51942 31 542 31 33 542 31 33 37 31 33 5 31 33 542 31 33 3745 31 33 3745 37 542 31 33 44042 31 33 44042 542 31 31 53045 31
  • 19.
    S D G D S G IN IN IN SYM_VER-2 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN SYM_VER-2 SYM_VER-2 SYM_VER-2 SYM_VER-2 OUT NC NC NC NC NC NC NC NC NC TABLE_ALT_ITEM TABLE_ALT_ITEM PART NUMBER ALTERNATE FORPARTNUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT EDP CONNECTORIMAX CHANNEL VGS MAX +/- 8V MOSFET RDS(ON) 3 A SIA413DJ P-TYPE SIA413DJ 518S0827 100MOHM @-1.5V CRITICAL FERR-120-OHM-1.5A 0402B 6.3V X5R 0.1UF 201 10% 1/20W 100K MF 1% 201 2N7002TXG SOT-523-3 SIA413DJ SC70-6L CRITICAL 10% X5R 0201 0.015UF 6.3V 39K MF 1% 1/20W 201 NOSTUFF 201 MF 1/20W 1% 10K 201 10K MF 1% 1/20W NOSTUFF 201 MF 1/20W 1% 21.5K 10% 50V 402 CERM 820PF CERM 100PF 5% 402 50V 0201 82PF 25V CERM 5% CERM 5% 82PF 0201 25V 25V CERM 5% 0201 82PF FERR-240-OHM-25%-300MA 0402 CRITICAL 6 743 743 TCM0605-1 90-OHM-50MA 1/20W MF 5% 201 0 0201 82PF 25V 5% CERM 201 1000PF 16V 10% X7R 10%6.3V X5R201 0.1UF 0.1UF 201 6.3V 10% X5R 201 X5R10%6.3V 0.1UF 743 201 X5R6.3V 0.1UF 10% 743 201 6.3V X5R10% 0.1UF 743 X5R10%6.3V 0.1UF 201 743 6.3V 10% X5R 0.1UF 201 743 0.1UF 10%201 X5R6.3V 743 MF 01005 1% 100K 1/32W 1% 1/32W 100K MF 01005 0.1UF X5R201 10%6.3V 6.3V 0.1UF 201 10% X5R 743 743 10% 50V 402 CERM 820PF 5% CERM 100PF 402 50V 0402 CRITICAL FERR-240-OHM-25%-300MA 3743 3743 3743 3743 3743 3743 37 43 37 43 37 43 37 43 37 43 37 43 TCM0806-4SM 12-OHM-100MA-8.5GHZ 12-OHM-100MA-8.5GHZ TCM0806-4SM 12-OHM-100MA-8.5GHZ TCM0806-4SM 12-OHM-100MA-8.5GHZ TCM0806-4SM 402 6.3V CERM 1UF 10% 1% 100K MF 01005 1/32W 502250-8051 F-RT-SM CRITICAL 7 43 01005 1.00M 01005 1.00M 01005 1.00M 01005 1.00M 01005 1.00M 01005 1.00M 1.00M 01005 1.00M 01005 47K MF 1/20W 5% 201 L2242,L5500,L5501,L5600,L5601,L5620 155S0667 VIDEO: EDP CONNECTOR SYNC_DATE=01/19/2011SYNC_MASTER=JOE 376S0903 376S0796 PP3V3_LCDVDD_SW_FMIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.30 MM VOLTAGE=3.3V PP3V3_S0_LCD_FERR VOLTAGE=3.3V MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM =PP3V3_LCD =PP3V3_LCD EDP_AUX_CONN_N EDP_DATA_CONN_N<2> EDP_DATA_CONN_P<3> LED_IO_6_B EDP_AUX_CONN_P EDP_DATA_CONN_P<0> PPLED_BACK_REG_B NET_SPACING_TYPE=PWR VOLTAGE=20.4V MIN_LINE_WIDTH=0.6 MM MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.2 MM EDP_DATA_CONN_N<3> LED_IO_2_B LED_IO_5_A LED_IO_3_A EDP_DATA_CONN_P<3> EDP_DATA_CONN_N<3> EDP_DATA_CONN_P<2> EDP_DATA_CONN_N<2> EDP_DATA_CONN_P<1> EDP_DATA_CONN_N<1> EDP_DATA_CONN_N<0> EDP_DATA_CONN_P<0> EDP_DATA_CONN_P<3> EDP_DATA_CONN_P<1> EDP_DATA_CONN_N<1> EDP_DATA_CONN_P<2> EDP_DATA_CONN_N<3> EDP_DATA_CONN_N<0> EDP_DATA_CONN_P<0> EDP_DATA_CONN_N<2> =PPLED_REG_A =PPLED_REG_B PPLED_BACK_REG_A MIN_LINE_WIDTH=0.6 MM VOLTAGE=20.4V MIN_NECK_WIDTH=0.2 MM MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR EDP_DATA_CONN_P<1> EDP_DATA_CONN_N<1> EDP_EMI_TX_N<1> EDP_EMI_TX_P<1> EDP_AUX_CONN_N EDP_EMI_AUX_P EDP_AP_HPD EDP_AUX_CONN_PEDP_AP_AUX_P EDP_AP_AUX_N EDP_EMI_AUX_N EDP_AP_TX_P<3> EDP_AP_TX_N<3> EDP_AP_TX_P<2> EDP_AP_TX_N<2> EDP_AP_TX_P<1> EDP_AP_TX_N<1> EDP_AP_TX_N<0> EDP_AP_TX_P<0> PP3V3_S0_LCD_FERR LCDVDD_PWREN_L_R LED_IO_4_B LED_IO_3_B EDP_DATA_CONN_P<2> LED_IO_1_B LED_IO_6_A LED_IO_5_B LED_IO_1_A EDP_DATA_CONN_N<0> LED_IO_4_A LED_IO_2_A PM_LCDVDD_PWREN LCDVDD_PWREN_L EDP_EMI_TX_N<0> EDP_EMI_TX_N<2> EDP_EMI_TX_N<3> EDP_EMI_TX_P<3> EDP_EMI_TX_P<2> EDP_EMI_TX_P<0> R2250_1 Q2200 155S0583 RADAR:8616060, RADAR: 9015335 RADAR:8379470 L2201 1 2 C22031 2 R22051 2 Q2201 3 1 2 Q2200 1 3 47 C2204 1 2 R22031 2 R22101 2 R22111 2 R2204 1 2 C22201 2 C22331 2 C22411 2 C22401 2 C22301 2 L2200 1 2 L2242 1 2 3 4 R2250 1 2 C22321 2 C22061 2 C22501 2 C22511 2 C22421 2 C22431 2 C22441 2 C22451 2 C22461 2 C22471 2 R22401 2 R22411 2 C22481 2 C22491 2 C22701 2 C22531 2 L2210 1 2 L2202 1 2 3 4 L2232 1 2 3 4 L2222 1 2 3 4 L2212 1 2 3 4 C22021 2 R22421 2 J2200 1 10 11 12 13 14 15 16 17 18 19 2 20 21 22 23 24 25 26 27 28 29 3 30 31 32 33 34 35 36 37 38 39 4 40 41 42 43 44 45 46 47 48 49 5 50 51 52 53 54 55 6 7 8 9 R2280 1 2 R2281 1 2 R2282 1 2 R2283 1 2 R2284 1 2 R2285 1 2 R2286 1 2 R2287 1 2 R22901 2 051-8773 10.0.0 22 OF 157 16 OF 48 45 1645 1635 1635 16 43 16 43 16 43 1643 16 43 45 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 16 43 35 35 45 16 43 16 43 43 43 16 43 43 16 43 43 1645 16 43 16 43 43 43 43 43 43 43
  • 20.
    CTRL PGND THRML L VIN DO FB SW PAD GND VCCA 1B1 1B2 2A2 1A1 2A1 1A2 2DIR 2OE* 1DIR 1OE* 2B2 2B1 GND VCCB VSTM26 VSTM25 VSTM24 VSTM23 MUX19 MUX17 BON_L0 BON_L1 BON_L2 BON_L3 BON_L4 BON_L5 MUX0 MUX1 MUX2 MUX3 MUX4 MUX5 MUX6 MUX7 MUX8 MUX9 MUX10 MUX11 MUX12 MUX13 MUX16 MUX15 MUX18 MUX20 MUX21 MUX22 MUX23 NC VSTM1 VSTM0 VSTM6 VSTM5 VSTM4 VSTM3 VSTM2 VSTM8 VSTM11 VSTM10 VSTM7 VSTM16 VSTM15 VSTM14 VSTM13 VSTM12 VSTM21 VSTM20 VSTM19 VSTM18 VSTM17 VSTM22 VSTM27 VSTM31 VSTM30 VSTM29 VSTM28 VSTM32 VSTM36 VSTM35 VSTM34 VSTM33 VSTM37 VSTM42 VSTM41 VSTM40 VSTM39 VSTM38 VSTM47 VSTM45 VSTM44 VSTM43 A_AD_R2 A_AD_R1 A_AD_R0 MUX14 VSTM46 GND VSTM9 VDDH VCC_DIG VCC OE A NC Y GND NC OE* IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT IN IN IN IN OUT OUT IN OUT OUT OUT OUT OUT NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Apple Inc. THEINFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT TABLE_5_ITEM CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD P/N 518S0828 (A -> B) LOAD CURRENT ~ 153UA MATES WITH RIGHTMOST GRAPE FLEX TAIL APN:311S0485 TO Z2 TO Z1/Z2 MATES WITH LEFTMOST GRAPE FLEX TAIL MIN_NECK_MIDTH SHOULD BE 0.4MMBOOST CONVERTOR CONNECTORS TO GRAPE FLEX 10% X5R 25V 603-1 1UF VLF 4.7UH-700MA-280MOHM CRITICAL TPS61045 QFN-1 CRITICAL SM 10% X5R 201 6.3V 0.1UF0.1UF 6.3V X5R 10% 201 10K MF 1/20W 5% 201 1/20W 5% MF 201 10K 3.3K 5% 201 1/20W MF MF 1/20W 201 10K 5% 0.1UF 10% X5R 201 6.3V 0.1UF 6.3V X5R 201 10% 201 10K MF 1/20W 5% CRITICAL SN74AVCH4T245RSV PQFP1 10% 25V X5R 402 0.1UF 10% 0.1UF 25V X5R 402 0.1UF 10% 25V X5R 402 201 10% 0.1UF X5R 6.3V GROUNDHOG OMIT CRITICAL BGA CRITICAL SN74LVC1G126DRYR-M LLP CRITICAL SN74LVC1G125DRYR-M LLP 51742 51742 51742 645 51742 51742 51742 6 18 17 18 18 40 17 18 51742 18 1718 1718 1718 18 51742 18 18 18 18 18 18 X5R-X7R 201 470PF 16V 10% 10% 0.1UF X5R 25V 402 1/20W 201 0 5% MF 5% 1/20W MF 0 NOSTUFF 201 502250-8037 F-RT-SM CRITICAL 502250-8037 F-RT-SM CRITICAL MF-LF 1/16W 1M 1% 402 MF 71.5K 201 1/20W 1% 603 10% 6.3V X5R 2.2UF NP0-C0G 5% 33PF 25V 201 SOD-323 B0520WSXG CRITICAL 16V 402 X5R 10% 0.1UF 1/20W 0.1 MF 201 1% U3007311S0485311S0523 311S0532311S0525 U3010 311S0524 311S0533 U3009 U30031343S0525 IC,ASIC,GROUNDHOG B0,120B BGA CRITICAL GRAPE: GROUNDHOG,CONN,BOOST SYNC_DATE=12/17/2010SYNC_MASTER=RAMSIN MT_PANEL_IN<27> MT_PANEL_OUT<34> MT_PANEL_OUT<32> MT_PANEL_OUT<30> MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.2MM VR_BOOST_L PM_BOOST_EN VR_BOOST_FBK MT_PANEL_OUT<22> MT_PANEL_OUT<24> =PP3V0_GRAPE MT_PANEL_IN<0> AGND_U3000 MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.2MM VR_BOOST_SW AG_SHLD_TST_FLEX GRAPE_MISOSPI1_GRAPE_MISO MAKE_BASE=TRUE SPI1_GRAPE_MOSI MAKE_BASE=TRUE RST_GRAPE_Z1_L =PP3V0_GRAPE GRAPE_CS_L SPI1_GRAPE_SCLK MAKE_BASE=TRUE GRAPE_SCLK GRAPE_MOSI DIR_U3007 Z1_CS_L Z1_CS_OE Z1_CS_OE Z2_H_CS_L Z1_MISO Z2_H_CS_L Z1_SCLK NET_SPACING_TYPE=PWR VOLTAGE=18V MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM PP18V_GRAPE MIN_NECK_WIDTH=0.25MM MIN_LINE_WIDTH=0.6MM VOLTAGE=18V PP18V_R_GRAPE NET_SPACING_TYPE=PWR SPI1_GRAPE_MISO Z1_CS_OE SPI1_GRAPE_MOSI RST_GRAPE_Z2_L MAKE_BASE=TRUE RST_GRAPE_L SPI1_GRAPE_CS_L MAKE_BASE=TRUE AG_SHLD_TST =PP3V0_GRAPE MT_PANEL_IN<10> MT_PANEL_IN<8> MT_PANEL_IN<1> MT_PANEL_IN<2> MT_PANEL_IN<3> MT_PANEL_IN<4> MT_PANEL_IN<5> MT_PANEL_IN<6> MT_PANEL_IN<7> MT_PANEL_IN<9> MT_PANEL_IN<11> MT_PANEL_IN<12> MT_PANEL_IN<13> MT_PANEL_IN<14> MT_PANEL_IN<15> MT_PANEL_IN<16> MT_PANEL_IN<17> MT_PANEL_IN<18> MT_PANEL_IN<19> MT_PANEL_IN<20> MT_PANEL_IN<21> MT_PANEL_IN<22> MT_PANEL_IN<23> MT_PANEL_IN<24> MT_PANEL_IN<25> MT_PANEL_IN<26> MT_PANEL_IN<28> MT_PANEL_IN<29> MT_PANEL_OUT<39> MT_PANEL_OUT<38> MT_PANEL_OUT<37> MT_PANEL_OUT<36> AG_SHLD_TST_FLEX MT_PANEL_OUT<26> MT_PANEL_OUT<33> MT_PANEL_OUT<31> MT_PANEL_OUT<29> MT_PANEL_OUT<28> MT_PANEL_OUT<27> MT_PANEL_OUT<25> MT_PANEL_OUT<23> MT_PANEL_OUT<20> MT_PANEL_OUT<19> MT_PANEL_OUT<18> MT_PANEL_OUT<17> MT_PANEL_OUT<16> MT_PANEL_OUT<15> MT_PANEL_OUT<14> MT_PANEL_OUT<13> MT_PANEL_OUT<12> MT_PANEL_OUT<11> MT_PANEL_OUT<10> MT_PANEL_OUT<9> MT_PANEL_OUT<8> MT_PANEL_OUT<7> MT_PANEL_OUT<6> MT_PANEL_OUT<5> MT_PANEL_OUT<4> MT_PANEL_OUT<3> MT_PANEL_OUT<2> MT_PANEL_OUT<1> MT_PANEL_OUT<0> MT_PANEL_OUT<35> SPI1_GRAPE_SCLK SPI1_GRAPE_CS_L MT_PANEL_OUT<21> Z1_MOSI =PP3V0_GRAPE GRAPE_FW_DNLD_EN_L =PP3V0_GRAPE MT_PANEL_OUT<26> MT_PANEL_OUT<25> MT_PANEL_OUT<24> MT_PANEL_OUT<23> MUX_IN<19> MUX_IN<17> Z1_BON_L<0> Z1_BON_L<1> Z1_BON_L<2> Z1_BON_L<3> Z1_BON_L<4> Z1_BON_L<5> MUX_IN<0> MUX_IN<1> MUX_IN<2> MUX_IN<3> MUX_IN<4> MUX_IN<5> MUX_IN<6> MUX_IN<7> MUX_IN<8> MUX_IN<9> MUX_IN<10> MUX_IN<11> MUX_IN<12> MUX_IN<13> MUX_IN<16> MUX_IN<15> MUX_IN<18> MT_PANEL_OUT<1> MT_PANEL_OUT<0> MT_PANEL_OUT<6> MT_PANEL_OUT<5> MT_PANEL_OUT<4> MT_PANEL_OUT<3> MT_PANEL_OUT<2> MT_PANEL_OUT<8> MT_PANEL_OUT<11> MT_PANEL_OUT<10> MT_PANEL_OUT<7> MT_PANEL_OUT<16> MT_PANEL_OUT<15> MT_PANEL_OUT<14> MT_PANEL_OUT<13> MT_PANEL_OUT<12> MT_PANEL_OUT<21> MT_PANEL_OUT<20> MT_PANEL_OUT<19> MT_PANEL_OUT<18> MT_PANEL_OUT<17> MT_PANEL_OUT<22> MT_PANEL_OUT<27> MT_PANEL_OUT<31> MT_PANEL_OUT<30> MT_PANEL_OUT<29> MT_PANEL_OUT<28> MT_PANEL_OUT<32> MT_PANEL_OUT<36> MT_PANEL_OUT<35> MT_PANEL_OUT<34> MT_PANEL_OUT<33> MT_PANEL_OUT<37> MT_PANEL_OUT<39> MT_PANEL_OUT<38> Z1_B_ADR<2> Z1_B_ADR<1> Z1_B_ADR<0> MUX_IN<14> MT_PANEL_OUT<9> PP18V_GRAPE =PP3V0_GRAPE_MARIO1 C30001 2 R3009 1 2 R30121 2 C3008 1 2 D3000 1 2 C3009 1 2 L3000 1 2 U3000 53 4 6 1 7 8 9 2 XW3000 1 2 C30011 2 R3066 1 2 C30311 2 C30301 2 R30311 2 R30301 2 R30321 2 R30251 2 C30411 2 C30501 2 R30331 2 U3007 6 7 15 14 4 1 8 9 13 12 5 16 10 11 3 2 C3005 1 2 C3007 1 2 C3053 1 2 C30061 2 U3003 A10 B9 A9 C7 A7 B7 B8 A8 C8 C9 D7 G7 G8 E3 E5 E6 E7 F6 F7 G5 G6 B1 C1 I5 J8 J9 K8 J10 I10 H10 F11 C11 E10 E1 A11 B4 A5 A2 F2 H1 J1 J2 J3 K4 H5 C6 D3 F5 F8 F9 G3 G4 G9 H3 H4 H7 H8 D4 H9 J6 K7 D5 D6 D8 D9 E4 E8 F4 A6 B6 E9 F3 A1 B2 H2 I2 K1 K2 I3 K3 J4 I4 K6 H6 C2 K5 J5 I7 K9 I8 K10 I6 J7 K11 I9 D1 J11 I11 H11 G11 G10 F10 C10 D10 E11 D11 D2 B11 B10 C4 A4 B5 C5 A3 B3 E2 F1 G1 G2 I1 U3010 2 3 1 6 4 U3009 2 3 1 6 4 C30021 2 C30701 2 R3070 1 2 R3071 12 J3010 1 10 11 12 13 14 15 16 17 18 19 2 20 21 22 23 24 25 26 27 28 29 3 30 31 32 33 34 35 36 37 38 39 4 40 41 5 6 7 8 9 J3011 1 10 11 12 13 14 15 16 17 18 19 2 20 21 22 23 24 25 26 27 28 29 3 30 31 32 33 34 35 36 37 38 39 4 40 41 5 6 7 8 9 051-8773 10.0.0 30 OF 157 17 OF 48 5 5 18 17 17 17 45 18 17 17 171835 18 45 45 17 17 18 35 17 45 45 18 17 18 35 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 18 35 17 18 35 17 17 17 17 18 18 18 18 18 18 1840 1840 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 18 40 18 40 18 40 18 17 1745 35
  • 21.
    OUT OUT IN IN IN OUT IN IN IN IN OUT IN IN OUT IN IN IN IN51 RESET* VDDDIG VDDIO V18 MOSI VDDANA IN25 BON_L0 BON_L1 BON_L2 BON_L3 BON_L4 BON_L5 B_ADR0 B_ADR1 B_ADR2 CS* DONE GNDANA GNDDIG GNDIO GO IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12 IN13 IN14 IN15 IN16 IN17 IN18 IN19 IN20 IN21 IN22 IN23 IN24 IN27 IN28 IN29 IN30 IN31 IN32 IN33 IN34 IN35 IN36 IN37 IN38 IN39 IN40 IN41 IN42 IN43 IN44 IN45 IN46 IN47 IN48 IN49 IN50 IN52 IN53 IN54 IN55 IN56 IN57 IN58 IN59 IN60 IN61 MISO PCLK SCLK STMIN STMOUT TM IN26 IN62 IN63 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VDDANA VDDCORE TM0 TM1 RESET* LFOO A_CS* A_SDI IN7_0 H_SCLK VDDLDO JTAG_TDI JTAG_TCK IN9_1 IN9_0 IN8_1 IN8_0 IN7_1 IN6_1 IN6_0 IN5_1 IN4_1 IN4_0 IN3_1 IN3_0 IN2_1 IN2_0 IN11_1 IN11_0 IN10_1 IN10_0 IN1_1 IN1_0 IN0_1 IN0_0 H_SDO H_SDI H_CS* GPIO7 GPIO6 FLOO BOOT_CFG1 BOOT_CFG0 BON_L5 BON_L4 BON_L3 BON_L2 BON_L1 BON_L0 B_ADR1 ARMTAPMD* A_SDO A_SCLK GPIO1 GPIO0 GPIO2 GPIO3 VDDIO GPIO5 CLKIN CLKOUT EXTFLLIN JTAG_TDO JTAG_TMS GPIO4 IN5_0 B_ADR2 B_ADR0 GND AppleInc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT K94FLOATFLOAT MIN_NECK_MIDTH SHOULD BE 0.4MM INTERNAL PU MODECFG0 AUTONOMOUS DEPENDENT 1 DEPENDENT 2 SLAVE K48 USES DEPENDENT 2 MODE 1 0 1 0 1 1 0 0 CRITICAL ERROR MODE K48X J2FLOAT BON_L3BON_L4 X LOW DEFAULT ALL OTHER STRAPS LOW FLOAT BON_L5 FLOAT J2 Z2 AND BYPASSED OUTSIDE ARE EACH GENERATED WITHIN VDDANA AND VDDCORE ARM9 MCU (Z2 BASED) ZEPHYR 1+ ASIC CFG1 Z2 - PRODUCT STRAP OPTIONS 0 1/20W 201 5% MF 0 0 201 5% 1/20W MF CERM-X5R 10UF 0402-1 6.3V 20% 6.3V X5R-CERM1 402 4.7UF 20% 17 5 17 17 17 17 17 17 17 18 17 18 40 17 18 17 37 42 5% 1/32W 01005 MF 100 01005 5% 100 1/32W MF 17 18 17 18 40 17 17 18 100K 201 1/20W 5% MF 2.2UF 4V X5R 402 20% 0.1UF 10% 201 6.3V X5R 201 0.1UF 10% 6.3V X5R 4V 2.2UF X5R 402 20% 4.7 201 5% 1/20W MF CERM-X5R 10UF 0402-1 6.3V 20% BCM5973 CRITICAL BGA 10% 0.1UF 201 6.3V X5R 201 10% 0.1UF 6.3V X5R 0.1UF 10% 201 6.3V X5R 100K 1/20W 5% 201 MF 0.1UF 10% 201 6.3V X5R 201 10% 0.1UF 6.3V X5R 10UF CERM-X5R 0402-1 6.3V 20% 4V 2.2UF X5R 402 20% CRITICAL Z1_GO FBGA BCM5974CKFBGH 201 MF 1/20W 100K 5% 1.00 201 MF 1% 1/20W GRAPE: Z1, Z2 SYNC_DATE=12/17/2010SYNC_MASTER=RAMSIN =PP3V0_GRAPE_Z1 MT_PANEL_IN<0> MT_PANEL_IN<1> Z1_SCLK TP_Z2_A_SDI Z1_MISO Z2_A_CS_L TP_Z2_A_SDO U3101_TM1 MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM Z2_3V3_1V8_IN VOLTAGE=1.8V NET_SPACING_TYPE=PWR NC_BON_L1 GRAPE_CS_L Z1_CS_OE_R IRQ_GRAPE_HOST_INT_L PM_BOOST_EN NC_BON_L5 TP_U3101_TMS TP_U3101_TDO HOST_REFCLK GRAPE_MOSI Z1_DONE TP_Z2_A_SCLK NC_BON_L3 GRAPE_SCLK Z2_H_CS_L Z1_MOSI TP_U3101_TCK TP_U3101_TDI Z1_SCLK TP_U3101_TM0 BOOT_CFG0_R MAKE_BASE=TRUE CLK_32K_PMU =PP3V0_GRAPE BOOT_CFG1_R =PP3V0_GRAPE =PP3V0_GRAPE AG_SHLD_TST Z1_CS_OE Z1_PCLK MIN_NECK_WIDTH=0.1MM VOLTAGE=1.8V MIN_LINE_WIDTH=0.5MM Z2_VDDANA NET_SPACING_TYPE=PWR Z2_VDDCORE VOLTAGE=1.8V MIN_LINE_WIDTH=0.5MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.1MM =PP3V0_GRAPE_Z2 GRAPE_MISO RST_GRAPE_Z2_L MT_PANEL_IN<26> U3100_TM Z1_STMIN Z1_PCLK Z1_MISO MUX_IN<19> MUX_IN<18> MUX_IN<17> MUX_IN<16> MUX_IN<15> MUX_IN<14> MUX_IN<13> MUX_IN<12> MUX_IN<11> MUX_IN<10> MUX_IN<9> MUX_IN<8> MUX_IN<7> MUX_IN<6> MUX_IN<5> MUX_IN<4> MUX_IN<3> MUX_IN<2> MUX_IN<1> MUX_IN<0> MT_PANEL_IN<29> MT_PANEL_IN<28> MT_PANEL_IN<27> MT_PANEL_IN<24> MT_PANEL_IN<23> MT_PANEL_IN<22> MT_PANEL_IN<21> MT_PANEL_IN<20> MT_PANEL_IN<19> MT_PANEL_IN<18> MT_PANEL_IN<17> MT_PANEL_IN<16> MT_PANEL_IN<15> MT_PANEL_IN<14> MT_PANEL_IN<13> MT_PANEL_IN<12> MT_PANEL_IN<11> MT_PANEL_IN<10> MT_PANEL_IN<9> MT_PANEL_IN<8> MT_PANEL_IN<7> MT_PANEL_IN<6> MT_PANEL_IN<5> MT_PANEL_IN<4> MT_PANEL_IN<3> MT_PANEL_IN<2> Z1_GO Z1_DONE Z1_CS_L Z1_B_ADR<2> Z1_B_ADR<1> Z1_B_ADR<0> Z1_BON_L<5> Z1_BON_L<4> Z1_BON_L<3> Z1_BON_L<2> Z1_BON_L<1> Z1_BON_L<0> MT_PANEL_IN<25> MIN_NECK_WIDTH=0.2MM VOLTAGE=3.0V MIN_LINE_WIDTH=0.2MM NET_SPACING_TYPE=PWR MT_3V3_INT Z1_MOSI RST_GRAPE_Z1_L Z1_1V8_OUT Z1_1V8_OUT MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.8V NET_SPACING_TYPE=PWRC31061 2 C31051 2 C31081 2 R31071 2 C31091 2 C31101 2 C31111 2 C31121 2 U3101 F1 G1 F2 G4 E6 F9 F8 G9 J8 H9 J9 H7 J7 H5 F6 D3 E5 E4 G7 G5 C3 H8 C4 D6 D7 D8 C9 D9 G2 D1 J2 J3 H4 J6 G3 F3 F4 H6 H1 J1 H3 J4 A9 B9 B2 C1 B1 A1 A7 A8 B8 C8 B7 C7 A6 B6 C6 C5 B5 A5 A4 B4 A3 B3 C2 A2 G6 E8 E9 F7 F5 D5 E7 D4 D2 E1 G8 H2 J5 E2 E3 R31601 2 R3190 1 2 R3171 1 2 R31731 2 R3120 1 2 C31911 2 C31071 2 R3180 1 2 R3181 1 2 R31551 2 C31011 2 C31021 2 C31031 2 C31041 2 R3101 1 2 C31921 2 U3100 A5 B5 A6 A2 A1 A3 A4 B4 B3 B10 B7 B1 B2 C12 D3 D11 F7 H7 L3 L4 L5 L6 L7 B12 L8 L9 L10 L11 B13 C2 C3 C6 C7 C8 C11 C4 B11 A8 H2 G2 E1 E2 J2 G1 F2 J7 K2 N4 M5 N5 D7 M6 N3 M3 L1 K1 L2 N6 M2 M4 M1 C1 N2 N1 N13 N12 M10 M13 N8 M12 K13 L13 F1 L12 M11 N11 M8 N9 M9 N10 K12 J13 F12 J1 G13 J12 E12 E13 H13 N7 D13 D12 H12 F13 D2 C13 E7 M7 G12 D1 K7 H1 B9 B8 A12 A7 A11 A13 A10 A9 B6 G6 G7 G8 K4 K10 C10 C5 C9 051-8773 10.0.0 31 OF 157 18 OF 48 18 35 17 17 45 46 46 18 46 171835 17 18 35 17 18 35 17 18 45 45 35 17 18 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 18 18 17 40 17 40 17 40 17 40 17 40 17 17 17 17 17 45 17 1845 18 45
  • 22.
    IN OUT IN OUT IN IN BI OUT OUT OUT IN IN IN OUT IN IN IN SCL SDA INT* SPEAKEROUTB+ SPEAKEROUTB- SPEAKEROUTA+ SPEAKEROUTA- EAROUT+ EAROUT- LINEOUT2B LINEOUT2B_REF LINEOUT2A LINEOUT2A_REF LINEOUT1_REF LINEOUT1A LINEOUT1B HPOUT_REF HPOUTB HPOUTA HP_DETECT VL VA VCP VP VD RESET* MCLK WAKE* ASP_LRCLK ASP_SCLK ASP_SDIN ASP_SDOUT VSP_LRCLK VSP_SLCLK VSP_SDIN VSP_SDOUT XSP_LRCLK XSP_SCLK XSP_SDIN/DAC2B_MUTE DMIC_SCLK LINEINA_REF MIC1 MIC2_REF MIC2_DETECT_REF MIC2_BIAS_FILT MIC3A_BIAS MIC3A_REF MIC3B FLYP -VCP_FILT +VCP_FILT FLYC FLYN SPEAKER_VQ FILT+ GND GNDP GNDA GNDCP GNDD MIC2 MIC2_DETECT MIC2_BIAS MIC1_BIAS_FILT MIC1_REF LINEINB_REF XSP_SDOUT MIC3B_BIAS_FILT MIC3B_REF MIC3B_BIAS MIC3A_BIAS_FILT MIC3A MIC1_BIAS DMIC_SD LINEINA LINEINB OUT IN IN OUT IN OUT OUT IN IN IN OUT IN IN IN OUT IN IN OUT IN NC NC NC NC NC NC NC NC NC NC NC NC Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT I2C ADDRESS: 1001010X?? L63B AUDIO CODEC 2.2UF NOT USING SPEAKER AMPLIFIER WITH SPEAKER LOAD. APN:338S0940 RECOMMENDED 20% X5R 0.1UF 4V 01005 X5R-CERM 6.3V 10% 01005 1000PF 5% NP0-C0G 16V 01005 27PF 20% 402 4V X5R 10UF SM SM SM 20% 6.3V 10UF CERM-X5R 0402-1 6.3V 0.1UF X5R 10% 201 542 21 43 51542 5 3745 510223742 510223742 21 43 21 40 21 40 21 22 21 40 20 43 20 43 20 43 542 542 WLCSP-1 CS42L63B CRITICAL 20% 4.7UF 402-3 TANT 4V 20% 6.3V 10UF CERM-X5R 0402-1 20% 6.3V 0402-1 CERM-X5R 10UF 20 43 20% 4.7UF 402 X5R-CERM1 6.3V 1.00K MF 1/32W 1% 01005 X5R-CERM1 6.3V 402 4.7UF 20% 2243 2243 22 01005 MF1% 1/32W 1.00K 2243 37 542 22 MF5% 010051/32W 542 51542 51542 51542 010051/32W 5% 22 MF 22 01005 MF5% 1/32W 542 542 542 542 20% 01005 0.1UF 4V X5R 23 2243 20% 4.7UF 402 X5R-CERM1 6.3V CRITICAL 5% 01005 MF 22 1/32W 5% MF 22 1/32W 01005 26 26 20% 4.7UF 402 X5R-CERM1 6.3V CRITICAL 20% 402 X5R-CERM 2.2UF 10V 20% 402 X5R-CERM 2.2UF 10V 20% X5R 4V 0.1UF 01005 SYNC_DATE=02/03/2011 AUDIO: L63B CODEC SYNC_MASTER=KAVITHA NC_LINE_IN2_CODEC NC_LINE_IN1_CODEC DMIC_SD_CODEC NC_MIC1_BIAS_CODEC I2S_L63_XSP_SDOUT NC_LINE_IN2_REF_CODEC NC_MIC1N_CODEC NC_MIC1_FILT_CODEC EXT_MIC_BIAS MIC2_DET EXT_MIC_P GND_AUDIO_CODEC MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM MAX_NECK_LENGTH=75 MM FILT_POS SPKR_VQ VHP_FLYN VHP_FLYC VHPPFILT VHPNFILT VHP_FLYP MIC2_BIAS_FILT MIC2_DET_REF EXT_MIC_REF NC_MIC1P_CODEC NC_LINE_IN1_REF_CODEC DMIC_SCLK_CODEC I2S3_XSP_DOUT I2S3_XSP_BCLK I2S3_XSP_LRCK I2S_L63_VSP_SDOUT I2S2_VSP_DOUT I2S2_VSP_BCLK I2S2_VSP_LRCK I2S_L63_ASP_SDOUT I2S0_ASP_DOUT I2S0_ASP_BCLK I2S0_ASP_LRCK AUD_MIK_HS1_INT_L I2S0_ASP_MCK_R RST_L63_L =PPVCC_MAIN_AUDIO =PP1V7_VA_VCP =PP1V8_AUDIO HP_DET HP_L HP_R HP_REF CODEC_LINE_OUT_R CODEC_LINE_OUT_L CODEC_LINE_OUT_REF LEFT_CH_OUT_REF LEFT_CH_OUT_P RIGHT_CH_OUT_REF RIGHT_CH_OUT_P NC_EAROUT_AN NC_EAROUT_AP IRQ_CODEC_L I2C0_SDA_1V8 I2C0_SCL_1V8 I2S0_ASP_DIN I2S2_VSP_DIN I2S3_XSP_DIN GND_AUDIO_HP_AMP MIN_LINE_WIDTH=1.0MM MIN_NECK_WIDTH=0.2MM GND_AUDIO_CODEC DMIC_SCLK_SENSOR DMIC_SD_SENSOR HSMIC_C_N HSMIC_C_P C36171 2 C36181 2 C3602 1 2 C3601 1 2 C3600 1 2 C36051 2 C36061 2 XW3600 1 2 XW3601 1 2 XW3602 1 2 C3603 1 2 C36041 2 U3600 C8 B7 B8 A9 B5 A5 F3 G3 G1 F11 G11 E11 D8 D9 F2 E10 B10 G5 E9 F9 G10 G9 E4 C5 C4 D6 D5 E8 F8 G8 D7 E7 F7 G7 F10 B9 A3 D4 E2 B3 B1 C2 C1 D3 C3 B2 A1 D2 D1 A2 A4 F1 E1 B4 D10 E5 C6 C7 E6 G6 F6 G4 F4 G2 D11 B11 C11 F5 C9 C10 A11 A10 E3 B6 A6 A8 A7 C36081 2 C3614 1 2 C36131 2 C3611 1 2 R3605 1 2 C3609 1 2 R3604 1 2 R3601 1 2 R3602 1 2 R3603 1 2 C36071 2 C36161 2 R36081 2 R36211 2 C36151 2 051-8773 10.0.0 36 OF 157 19 OF 48 46 46 46 42 46 46 46 192145 46 46 42 42 202235 35 35 46 46 21 22 45 19 21 45
  • 23.
    OUT IN IN OUT OUT OUT OUT IN- IN+ OUT+ OUT- GAINSHDN* PVDD NC PGND IN- IN+ OUT+ OUT- GAINSHDN* PVDD NC PGND OUT NC NC IN OUT AppleInc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT NC GAIN:6DB GAIN 100K GND APN:353S3317) TURN ON TIME: 3.5MS NC NC NC100K SHORT NC 12DB NC SHORT 0DB L63 LINEOUT2A IS CONNECTED TO U3700 L63 LINEOUT2B IS CONNECTED TO U3710 6DB GAIN:6DB VDD 9DB 3DB TURN ON DELAY: ?MS SPEAKER CONNECTOR APN 518S0672 MAY NEED TUNING FOR THESE FILTERS 75HZ +/- XXX% SPEAKER AMPLIFIER LEFT CHANNEL IS INVERTED TO FIX CODEC BUG ON LINEOUT2 1943 1943 1943 SM SM 20 43 20 43 20 43 20 43 0603-1 10V X5R 10UF 20% 0603-1 10V X5R 10UF 20% 5% NP0-C0G CRITICAL NOSTUFF 100PF 16V 01005 5% NP0-C0G NOSTUFF 100PF 16V 01005 CRITICAL 0% 1/32W 0.00 MF 01005 1/32W MF 1% 01005 100 01005 0.00 1/32W MF 0% CRITICAL 0.015UF 10% 0201 6.3V X5R MF 1% 100 01005 1/32W 1/32W MF 01005 0% 0.00 01005 0.00 MF 0% 1/32W 5% NP0-C0G 01005 16V 100PF NOSTUFF CRITICAL 5% NP0-C0G 01005 16V 100PF NOSTUFF CRITICAL MAX98304C WLPNDIFPR_BADTERM CRITICAL MAX98304C WLP CRITICAL CRITICAL 0.015UF 0201 X5R 6.3V 10% 0.015UF 0201 6.3V 10% X5R CRITICAL 0.015UF 0201 X5R 6.3V 10% CRITICAL 78171-6006 M-RT-SM CRITICAL 6 0201 240-OHM-0.2A-0.8-OHM 5% 27PF NP0-C0G 25V 0201 520 SM SM 201 X5R 10% 6.3V 0.1UF 1943 01005 5% 1/32W 100K MF 201 X5R 6.3V 10% 0.1UF AUDIO: SPEAKER AMP SYNC_MASTER=KAVITHA SYNC_DATE=02/03/2011 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM GND_SPKR_AMP2 AUD_SPKR_AMP2_PBUS MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.30MM GND_SPKR_AMP1 AUD_SPKR_AMP1_PBUSMIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.30MM MAX983X4_L_IN_P SPKRAMP_L_OUT_N SPKRAMP_L_OUT_P SPKRAMP_R_OUT_P SPKRAMP_R_OUT_N SPK_ID SPK_ID_FILT LEFT_CH_OUT_REF RIGHT_CH_OUT_P LEFT_CH_OUT_P =PPVCC_MAIN_AUDIO LEFT_CH_P RIGHT_CH_OUT_REF RIGHT_CH_P =PPVCC_MAIN_AUDIO AUD_SPKRAMP_MUTE_L MAX983X4_R_GAIN SPKRAMP_R_OUT_N MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MMSPKRAMP_R_OUT_PMAX983X4_R_IN_P MAX983X4_R_IN_N AUD_SPKRAMP_MUTE_L MAX983X4_L_GAIN MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.50MM SPKRAMP_L_OUT_N SPKRAMP_L_OUT_P MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.50MM MAX983X4_L_IN_N XW3700 1 2 XW3701 1 2 C3703 1 2 R37001 2 C3713 1 2 XW3710 1 2 XW3711 1 2 C37041 2 C37141 2 C3753 1 2 C37521 2 R37031 2 R3701 12 R37021 2 C3701 1 2 R3711 12 R37121 2 R37131 2 C3751 1 2 C37501 2 U3700 B3 C2 C3 A1 A2 B1A3 C1 U3710 B3 C2 C3 A1 A2 B1A3 C1 C3702 1 2 C3711 1 2 C3712 1 2 J3700 7 8 1 2 3 4 5 6 L3700 1 2 C37001 2 051-8773 10.0.0 37 OF 157 20 OF 48 B2 B2 45 40 45 40 43 2043 2043 2043 2043 19202235 43 43 19202235 520 43 43 43
  • 24.
    OUT OUT IN IN OUT IN OUT OUT OUT IN IN IN IN Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT HEADPHONE OUTPUT ZOBEL NETWORK CODEC DOCK LINE OUTPUT DOCK 01005 MF 1% 100 1/32W 01005 1% MF 100 1/32W 10% 6.3V X5R 33000PF 201201 6.3V X5R 10% 33000PF 27PF 01005 5% NP0-C0G 16V 01005 16V NP0-C0G 27PF 5% 16V 01005 NP0-C0G-CERM 15PF 5% 15PF 16V 5% 01005 NP0-C0G-CERM 23 43 1922 1943 1943 23 43 1922 27 1940 27 1940 1940 27 45 27 SM SM NP0-C0G-CERM 01005 16V 15PF 5% 01005 5% 16V NP0-C0G 27PF SM SM 01005 1% 100 100 1% 01005 SYNC_DATE=02/03/2011 AUDIO: HEADPHONE OUT SYNC_MASTER=KAVITHA AUDIO_EMI_LO_L MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.07MM MIN_NECK_WIDTH=0.07MM AUDIO_EMI_LO_R MIN_LINE_WIDTH=0.1MM MIN_LINE_WIDTH=0.1MM CODEC_LINE_OUT_R MIN_NECK_WIDTH=0.07MM MIN_NECK_WIDTH=0.07MM MIN_LINE_WIDTH=0.1MM CODEC_LINE_OUT_L GND_AUDIO_PT_DK MAX_NECK_LENGTH=75 MM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MMGND_AUDIO_CODEC MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.07MM CODEC_LINE_OUT_REF HP_R AUD_HP1_MLBCON_L MIN_NECK_WIDTH=0.07MM MIN_LINE_WIDTH=0.1MM AV_EMI_DIFF_SENSE HP_REF HP_ZR AUD_HP1_MLBCON_R HP_L GND_AUDIO_HP_AMP HP_ZL R38511 2 R38501 2 C38511 2 C3850 1 2 C38531 2 C38521 2 C3802 1 2 C38011 2 XW3800 1 2 XW3803 1 2 C3803 1 2 C38541 2 XW3851 1 2 XW3850 1 2 R3800 12 R3801 12 051-8773 10.0.0 38 OF 157 21 OF 48 1945 192245
  • 25.
    OUT OUT IN IN IN OUT OUT OUT ADDR SDA SCL REF MIC CLAMPO CLAMPI RAMPO RAMPI GND2 MIC2 GND MIC1 VDD GND1 IN IN Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT (HSMIC_C_N) (HSMIC_C_P) EXT MIC LPF FC = 677KHZ TO CODEC EXTERNAL (HEADSET) MIC INPUT CIRCUITRY FROM HEADSET 10% 6.3V 201 0.1UF X5R 19 43 19 43 2340 2340 5% 33PF NP0-C0G-CERM 16V 01005 X7R 1000PF 10% 201 16V MF 1/20W 1% 201 470 MF 1/20W 1% 470 201 1% 1/20W 201 MF 1K 19 6.3V 10% X5R 201 0.1UF 201 2.2K 1/20W MF 1% 1/20W 1% 2.2K 201 MF 20% 0402-1 CERM-X5R 10UF 6.3V 19 43 19 43 19 21 SM TS3A8235YFP CRITICAL WCSP NOSTUFF CERM-X5R 6.3V 20% 10UF 0402-1 201 MF 1/20W NOSTUFF 5% 0 MF 1/20W 5% 0 201 2340 2340 201 MF 1/20W 5% 0 NOSTUFF 201 5% 0 MF 1/20W 201 6.3V X5R 10% 0.1UF 5% 01005 NP0-C0G-CERM 16V 15PF SYNC_DATE=02/03/2011 AUDIO: DETECT/MIC BIAS SYNC_MASTER=KAVITHA AUD_HS_MIC2_HI AUD_HS_MIC1_HI GND_AUDIO_HP_AMP =PP3V0_S2R_HALL_CHSW PPVDD_CHSW MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.30MM MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR VOLTAGE=4.6V AUD_HS_MIC2_RET HSMIC_C_P CHS_CAP_REF CHS_CLAMPO HSMIC_R_P EXT_MIC_REFHSMIC_R_N EXT_MIC_P CHS_CLAMPI HP_REF EXT_MIC_BIAS I2C0_SDA_1V8 I2C0_SCL_1V8 HSMIC_C_N =PPVCC_MAIN_AUDIO AUD_HS_MIC1_RET C4211 1 2 C4212 1 2 C4213 1 2 C4216 1 2 C42171 2 R4212 1 2 R4213 1 2 R4201 1 2 C42001 2 R4202 1 2 R4203 1 2 C42011 2 XW4200 1 2 U4200 A2 C4 B4 C2 B2 B3 C3 D2B1 C1 D4 D3 D1 A3 A4 A1 C42021 2 R4204 1 2 R4205 1 2 R4210 1 2 R4211 1 2 051-8773 10.0.0 42 OF 157 22 OF 48 192145 35 43 43 5 10 19 37 42 5 10 19 37 42 192035
  • 26.
    OUT OUT OUT OUT IN IN IN OUT OUT IN IN OUT IN IN IN OUT Apple Inc. THEINFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT HEADSET JACK INSERTION DETECT HEADPHONE JACK CONNECTION IS ON FRONT PANEL FLEX, CSA 55/PDF 29 PLACE ALL COMPONENTS NEAR J5401 22 40 0402 30-OHM-1.7A CRITICAL0402 30-OHM-1.7A CRITICAL 22 40 2443 2443 2440 24 24 0402 30-OHM-1.7A 0402 30-OHM-1.7A CRITICAL 22 40 22 40 0402 30-OHM-1.7A CRITICAL0402 30-OHM-1.7A 2440 2440 0201 240-OHM-0.2A-0.8-OHM 23 40 21 43 21 43 10V 10% 201 X7R 4700PF NOSTUFF1/32W 5% 01005 MF 3.3K 2340 19 SYNC_MASTER=KAVITHA SYNC_DATE=02/03/2011 AUDIO: HP/MIC FILTERS HP_DETAUD_HP1_DET_H MIN_NECK_WIDTH=0.05MM MIN_LINE_WIDTH=0.1MM AUD_HS_MIC2_HI MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM AUD_HS_MIC2_RET MIN_NECK_WIDTH=0.05MM MIN_LINE_WIDTH=0.1MM CONN_AUD_HEADSET_CHS_MIC2 MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM CONN_AUD_HEADSET_CHS_RET2 AUD_HP1_DET_H MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM AUD_HS_MIC1_RET MIN_NECK_WIDTH=0.05MM MIN_LINE_WIDTH=0.1MM AUD_HS_MIC1_HI MIN_NECK_WIDTH=0.05MM MIN_LINE_WIDTH=0.1MM CONN_AUD_HEADSET_CHS_MIC1 MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM CONN_AUD_HEADSET_CHS_RET1 MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.15MM AUD_HP1_MLBCON_R MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.15MM AUD_HP1_MLBCON_L MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.15MM CONN_AUD_HEADSET_LEFT MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.15MM CONN_AUD_HEADSET_RIGHT CONN_AUD_HEADSET_DET L4303 1 2 C43101 2 R4312 1 2 L4306 1 2 L4304 1 2 L4301 1 2 L4302 1 2 L4308 1 2 L4307 1 2 051-8773 10.0.0 43 OF 157 23 OF 48
  • 27.
    NC NC NC NC NC NC NC NC NC NC NC NC Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT APN: 518S0828 APN: 518S0828 CAM CLOCK 0 CAM CLOCK 1 CRITICAL F-RT-SM 502250-8037 CRITICAL F-RT-SM 502250-8037 SYNC_MASTER=MARK CONNECTOR: SENSOR SYNC_DATE=01/11/2011 MIPI0C_CAM_CLK_P CLK_CAM_FF_CONN ISP_CAM_1_SDA MIPI1C_CAM_CLK_P CONN_IRQ_GYRO_INT2 SRL_L AUD_VOL_UP_L CONN_IRQ_ACCEL_INT2_L CONN_AUD_HEADSET_CHS_RET2 CONN_AUD_HEADSET_CHS_MIC2 CONN_AUD_HEADSET_CHS_MIC1 CONN_AUD_HEADSET_RIGHT CONN_AUD_HEADSET_CHS_RET1 ISP_CAM_0_SCL DMIC_DATA_CONN I2C1_SDA_1V8_CONN IRQ_ALS_INT_CONN_L I2C2_SCL_3V0_ALS PM_REAR_CAM_SHUTDOWN_FILT I2C1_SCL_1V8_CONN MIPI1C_CAM_CLK_N ISP_CAM_1_SCL CONN_IRQ_PROX_INT_L MIPI0C_CAM_CLK_N ONOFF_L MIPI1C_CAM_DATA_P<0> MIPI0C_CAM_DATA_P<1> ISP_CAM_0_SDA PP3V0_S2R_HALL_FLT MIPI0C_CAM_DATA_N<1> PP1V8_SENSOR_FLT CLK_CAM_RF_CONN CAM0_RESET_L_FLT PP3V0_SENSOR_FLT PP2V85_CAM_FLT MIPI0C_CAM_DATA_N<0> DMIC_CLK_CONN I2C2_SDA_3V0_ALS CONN_IRQ_GYRO_INT1 CONN_AUD_HEADSET_LEFT CONN_AUD_HEADSET_DET CONN_IRQ_ACCEL_INT1_L AUD_VOL_DOWN_L MIPI1C_CAM_DATA_N<0> CONN_IRQ_HALL MIPI0C_CAM_DATA_P<0> PM_FRONT_CAM_SHUTDOWN_FILT J5400 1 10 11 12 13 14 15 16 17 18 19 2 20 21 22 23 24 25 26 27 28 29 3 30 31 32 33 34 35 36 37 38 39 4 40 41 5 6 7 8 9 J5401 1 10 11 12 13 14 15 16 17 18 19 2 20 21 22 23 24 25 26 27 28 29 3 30 31 32 33 34 35 36 37 38 39 4 40 41 5 6 7 8 9 051-8773 10.0.0 54 OF 157 24 OF 48 25 43 25 42 25 42 25 43 26 5 37 5 26 23 40 2340 23 2343 23 2542 26 25 42 25 102542 25 2542 2543 2542 26 2543 537 25 43 25 43 25 42 26 45 2543 26 45 25 42 26 10 26 45 26 45 25 43 26 10 25 42 26 23 43 2340 26 5 2543 25 2543 25
  • 28.
    IN IN IN1 IN2 IN4 IN3 OUT1 OUT2 OUT3 OUT4 GND IN1 IN2 IN4 IN3 OUT1 OUT2 OUT3 OUT4 GND IN BI BI OUT IN IN BI BI SYM_VER-1 SYM_VER-1 IN BI BI OUT OUT OUT OUT OUT BI BI OUT SYM_VER-1 SYM_VER-1 SYM_VER-1 IN BI IN1 IN2 IN4 IN3 OUT1 OUT2 OUT3 OUT4 GND OUT BI OUT IN1 IN2 IN4 IN3 OUT1 OUT2 OUT3 OUT4 GND BI IN IN IN OUT OUT IN BI OUT BI IN IN BI BI BI BI OUT OUT BI BI BI BI NC NC NC NC Apple Inc. THEINFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT TABLE_ALT_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD PLACE IT NEAR H4 22 OHM PLACE IT NEAR H4 22 OHM 7 742 0603 800MHZ-100MA-27PF 0603 800MHZ-100MA-27PF 742 742 542 5 743 743 743 743 90-OHM-50MA TCM0605-1 90-OHM-50MA TCM0605-1 5% 1/20W MF 201 0 NOSTUFF 1/20W 0 MF5% NOSTUFF201 1/20W 201 MF5% 0 NOSTUFF 201 MF 1/20W 5% 0 NOSTUFF 24 10 24 42 24 42 24 24 24 42 24 43 24 43 24 43 24 43 5% 201 MF 1/20W 100K NOSTUFF 24 42 1/20W 0 MF5% 201 NOSTUFF 1/20W 5% MF 201 NOSTUFF 0 90-OHM-50MA TCM0605-1 1/20W 0 MF5% 201 NOSTUFF 1/20W 5% MF 201 0 NOSTUFF MF 2011/20W 0 5% NOSTUFF 90-OHM-50MA TCM0605-1 90-OHM-50MA TCM0605-1 201 MF 0 5% 1/20W NOSTUFF 742 24 42 0603 800MHZ-100MA-27PF 24 24 42 24 42 800MHZ-100MA-27PF 0603 NOSTUFF 5% 201 MF 1/20W 100K 742 7 742 542 10 24 42 NOSTUFF 5% 100PF CERM 25V 201 25V CERM 100PF 5% NOSTUFF 201 MF-LF 22 1/16W 5% 402 402 MF-LF 1/16W 22 5% 37 51042 51042 24 42 24 42 743 743 743 743 743 743 24 43 24 43 24 43 24 43 24 43 24 43 22 5% 402 1/16W MF-LF 22 5% 402 1/16W MF-LF ?155S0643 155S0373 U5502,U5503,U5500,U5501,U5600,U5601 RADAR:8376668 SYNC_MASTER=MARK SENSOR PANEL FILTERS 1 SYNC_DATE=01/11/2011CLK_CAM_RF_C MIPI0C_CAM_DATA_P<0> MIPI0C_CAM_CLK_N MIPI0C_CAM_CLK_P CLK_CAM_FF_C CLK_CAM_FF_FILT MIPI1C_AP_CLK_N MIPI1C_AP_CLK_P I2C1_SCL_1V8_CONN I2C1_SDA_1V8_CONN MIPI0C_CAM_DATA_N<0> MIPI0C_CAM_DATA_P<1> MIPI0C_CAM_DATA_N<1> MIPI0C_AP_DATA_P<1> MIPI0C_AP_DATA_N<0> MIPI0C_AP_DATA_P<0> MIPI0C_AP_CLK_P MIPI0C_AP_CLK_N MIPI1C_CAM_DATA_N<0> MIPI1C_CAM_DATA_P<0> MIPI1C_CAM_CLK_N MIPI1C_CAM_CLK_P MIPI1C_AP_DATA_P<0> IRQ_HALL I2C1_SDA_1V8 I2C1_SCL_1V8 ISP_CAM_1_SCL IRQ_ALS_INT_CONN_L I2C2_SCL_3V0_ALS I2C2_SDA_3V0_ALS ISP_AP_1_SDA PM_FRONT_CAM_SHUTDOWN_FILT ISP_CAM_1_SDA I2C2_SCL_3V0 CLK_CAM_FF_CONN I2C2_SDA_3V0 IRQ_ALS_INT_L CONN_IRQ_HALL ISP_AP_1_SCL =PP1V8_CAM PM_FRONT_CAM_SHUTDOWN =PP1V8_CAM CLK_CAM_RF ISP_AP_0_SDA PM_REAR_CAM_SHUTDOWN ISP_AP_0_SCL ISP_CAM_0_SDA PM_REAR_CAM_SHUTDOWN_FILT ISP_CAM_0_SCL CLK_CAM_RF_CONN CLK_CAM_RF_FILT CLK_CAM_FF MIPI1C_AP_DATA_N<0> MIPI0C_AP_DATA_N<1> U5500 9 10 1 2 3 4 5 6 7 8 U5501 9 10 1 2 3 4 5 6 7 8 L5500 1 2 3 4 L5501 1 2 3 4 R55101 2 R55111 2 R55121 2 R55131 2 R55011 2 R56201 2 R56211 2 L5620 1 2 3 4 R56101 2 R56111 2 R56121 2 L5600 1 2 3 4 L5601 1 2 3 4 R56131 2 U5502 9 10 1 2 3 4 5 6 7 8 U5503 9 10 1 2 3 4 5 6 7 8 R55021 2 C55011 2 C55001 2 R5601 1 2 R5600 1 2 R5603 1 2 R5602 1 2 051-8773 10.0.0 55 OF 157 25 OF 48 42 42 42 2535 2535 42
  • 29.
    IN1 IN2 IN4 IN3 OUT1 OUT2 OUT3 OUT4 GND OUT IN OUT OUT IN IN OUT OUT IN IN IN OUT IN OUT IN1 IN2 IN4 IN3 OUT1 OUT2 OUT3 OUT4 GND OUT IN AppleInc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT DCR 0.31 DCR 0.31 DCR 0.31 240-OHM-0.2A-0.8-OHM 0201 0603 800MHZ-100MA-27PF 5 24 5 5 24 24 5 5 24 24 0402 240-OHM-25%-400MA 240-OHM-25%-400MA 0402 240-OHM-25%-400MA 0402 7 24 19 19 10% 201 X7R 16V 1000PF 10% X5R 201 6.3V 0.1UF 10% 1UF 402-1 X5R 10V 82PF CERM 0201 5% 25V 10% 16V X7R 201 1000PF 10% 1UF 402-1 X5R 10V 10% 1000PF 201 16V X7R 10% 1UF 402-1 X5R 10V 25V 5% CERM 0201 82PF 0201 CERM 25V 5% 82PF 10% 1000PF 16V X7R 201 10% 1UF 402-1 X5R 10V25V 5% CERM 82PF 0201 800MHZ-100MA-27PF 0603 24 24 SYNC_MASTER=MARK SYNC_DATE=01/11/2011 SENSOR PANEL FILTERS 2 =PP3V0_OPTICAL PP3V0_SENSOR_FLT VOLTAGE=3.0V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR =PP2V85_CAM PP2V85_CAM_FLT NET_SPACING_TYPE=PWR VOLTAGE=2.85V MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm MAX_NECK_LENGTH=3 MM DMIC_SCLK_SENSOR DMIC_SD_SENSOR PP1V8_SENSOR_FLT MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.6 mm PP3V0_S2R_HALL_FLT MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.6 mm VOLTAGE=3.0V MIN_NECK_WIDTH=0.2 mm NET_SPACING_TYPE=PWR =PP1V8_SENSOR =PP3V0_S2R_HALL CAM0_RESET_L_FLT CONN_IRQ_PROX_INT_L CAM0_RESET_L IRQ_PROX_INT_L CONN_IRQ_GYRO_INT2 CONN_IRQ_GYRO_INT1 CONN_IRQ_ACCEL_INT1_L CONN_IRQ_ACCEL_INT2_L IRQ_GYRO_INT2 IRQ_GYRO_INT1 IRQ_ACCEL_INT1_L IRQ_ACCEL_INT2_L DMIC_CLK_CONN DMIC_DATA_CONN C56231 2 C56161 2 C56151 2 C56141 2 C56211 2 C56181 2 C56201 2 C56131 2 C56171 2 C56121 2 C5631 2 C56021 2 C56011 2 U5600 9 10 1 2 3 4 5 6 7 8 L5610 1 2 U5601 9 10 1 2 3 4 5 6 7 8 L5611 1 2 L5613 1 2 L5612 1 2 051-8773 10.0.0 56 OF 157 26 OF 48 35 10 24 45 35 24 45 24 45 24 45 35 35
  • 30.
    GND VBUS IO NC IO NC GND VBUS IO NC IO NC GND VBUS IO NC IO NC REF GND IN OUTBI BI IN IN IN IN IN IN IN IN IN IN IN IN IN OUT IN IN IN OUT OUT OUT OUT SYM_VER-1 SYM_VER-1 SYM_VER-1 SYM_VER-1 GND VBUS IO NC IO NC Apple Inc. THEINFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_ALT_ITEM TABLE_ALT_ITEM ACCESSORY FIREWIRE DETECT/ DISPLAYPORT HPD USB LINEOUTVIDEO RETURN CURRENT DISPLAYPORT (JTAG_TCK) JTAG_AP_TMS = 1.8V: U5730’S IN = 1.16V NOTE: JTAG_AP_TMS = 3.3V: U5730’S IN = 2.13V JTAG PLACE BY PMU NOTE: 0.095 OHM DCR SEPARATION BETWEEN AUDIO AND NOTE: R5700 ADDED TO PROVIDE ANALOG VIDEO MAX CONTINUOUS VOLTAGE IS 19V - SPEC IS 16V (JTAG_TMS) 0201 25V NP0-C0G 27PF 5% 0201 25V NP0-C0G 27PF 5% 0201 25V NP0-C0G 27PF 5% 25V NP0-C0G 27PF 5% 0201 NOSTUFF 0201 25V NP0-C0G 27PF 5% NOSTUFF 0201 25V NP0-C0G 27PF 5% RCLAMP0502N SLP1210N6 RCLAMP0502N SLP1210N6 RCLAMP0502N SLP1210N6 5% 12PF NP0-C0G-CERM 25V 0201 5% 25V NP0-C0G 27PF 0201 0201 22-OHM-25%-900MA 0.01UF 10V 10% X5R 201 10% 402 X7R 0.01UF 25V FERR-120-OHM-1.5A 0402A FERR-120-OHM-1.5A 0402A 30-OHM-1.7A 0402 10% X7R 50V 402 0.01UF201 1/20W MF 47K 5% GDZT2R5.1B GDZ-0201 UCLAMP0511Z 0201 UCLAMP0511Z 0201 6.8V-100PF 0201 150 1/20W MF 201 5% DEVELOPMENT_JTAG 0 DEVELOPMENT_JTAG 0 DEVELOPMENT_JTAG UCSP MAX9061 0.1UF X5R 10% 6.3V DEVELOPMENT_JTAG 201 1/20W MF 220K 201 5% MF 1/20W 10K 201 5% 100K 1/20W MF 1% 201 442 442 2843 2843 2843 2843 2843 2843 101143 101143 101143 21 21 21 2145 1142 1142 1/20W 10K MF 201 5% 442 442 4 30 37 45 37 37 37 0201 0.01UF 16V 10% X5R-CERM DEVELOPMENT_JTAG 01005 MF 1/32W 1% 523K 1% 1/32W MF 01005 DEVELOPMENT_JTAG 1.00M 12-OHM-100MA-8.5GHZ TCM0806-4SM 12-OHM-100MA-8.5GHZ TCM0806-4SM TCM0605 35-OHM-50MA 0201-1 14.2V-6PF 0201 6.8V-100PF OMIT SM 0402 27V-100PF USBULC6-2F3 BGA MF 1/20W 0 201 5% 0 1/20W MF 201 5% 0.200 1% 1/20W MF 201 0201 25V NP0-C0G 27PF 5% 0201 25V NP0-C0G 27PF 5% 5% 27PF NP0-C0G 25V 0201 5% 27PF 0201 25V NP0-C0G NOSTUFF 0201 25V NP0-C0G 27PF 5% NOSTUFF 0201 25V NP0-C0G 27PF 5% NOSTUFF 0201 25V NP0-C0G 27PF 5% NOSTUFF 0201 25V NP0-C0G 27PF 5% NOSTUFF 0201 25V NP0-C0G 27PF 5% NP0-C0G NOSTUFF 0201 25V 27PF 5% 0201 NOSTUFF 25V NP0-C0G 27PF 5% FERR-120-OHM-1.5A 0402A 0603 FERR-70-OHM-4A SOT953 NUP412VP5XXG 0201 8V-100PF 0201 80-OHM-0.2A-0.4-OHM 0201 80-OHM-0.2A-0.4-OHM 0201 80-OHM-0.2A-0.4-OHM TCM0605 35-OHM-50MA 100K 5% 1/20W MF 201 RCLAMP0502N SLP1210N6 RADAR:8849707377S0111 DZ5710,DZ5711 377S0099 RADAR:8972666DZ5751377S0090 377S0081 D5700,D5701,D5702,D5703 377S0107 RADAR:8947642377S0066 RADAR:8423156155S0625 L5700,L5701155S0559 377S0116 377S0108 DZ5760 RADAR:8370432 155S0276155S0725 FL0600, FL5707, FL5708, FL5711 QTY 4 RADAR:9625553 RADAR:9625601L5762155S0513 155S0320 IO FLEX: DOCK COMPONENTS SYNC_DATE=01/19/2011SYNC_MASTER=JOE USB_DK_D0_P USB_DK_D0_N USB_PT_DK_CON_D_N USB_PT_DK_CON_D_P DP_PT_DK_CON_TX_N<1> DP_PT_DK_CON_TX_P<1> AV_PT_DK_CON_RET VIDEO_PT_DK_CON_C_Y MIN_LINE_WIDTH=4.1MM VOLTAGE=5.0V NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.2MM MAX_NECK_LENGTH=3 MM PPVBUS_USB_PT_DK_CON JTAG_AP_TMS =PP1V8_S2R_MISC AUDIO_PT_DK_RET MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VIDEO_PT_DK_CON_CVBS_PB VIDEO_PT_DK_CON_Y_PR ACC_PT_DK_CON_ID D5701_6 D5702_6 DP_PT_DK_CON_AUX_N DP_PT_DK_CON_TX_N<0> DP_PT_DK_CON_TX_P<0> D5703_6 ACC_PT_DK_CON_TX DP_EMI_AUX_N DP_EMI_AUX_P DP_EMI_TX_N<1> DP_EMI_TX_P<1> DP_EMI_TX_N<0> DP_EMI_TX_P<0> ACC_PT_DK_CON_RXUSB11_ACC_RX_P USB11_ACC_TX_N AUDIO_PT_DK_RET VIDEO_EMI_C_Y PORT_DOCK_ACCID PMU_ADC_REF GND_AUDIO_PT_DK AV_EMI_DIFF_SENSE PORT_DOCK_ACC_DET_L =PPVCC_MAIN_DOCK VIDEO_EMI_CVBS_PB VIDEO_EMI_Y_PR VIDEO_PT_DK_CON_Y_PR VIDEO_PT_DK_CON_C_Y VIDEO_PT_DK_CON_CVBS_PB RST_AP_L PT_DK_CON_P14 PT_DK_CON_P17 JTAG_AP_TCK U5730_IN DP_PT_DK_CON_AUX_P MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.07MM AV_PT_DK_CON_DIFF_SENSE ACC_PT_DK_CON_DET_L D5700_6 MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=4.1MM PPVBUS_USB_EMI FW_ZENER_PWR FW_PT_DK_CON_PWR =PP3V3_PORT_ACC MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.1MM VOLTAGE=3.3V NET_SPACING_TYPE=PWR ACC_PT_DK_CON_PP3V3 AUDIO_EMI_LO_L AUDIO_PT_DK_CON_LO_L MIN_NECK_WIDTH=0.07MM MIN_LINE_WIDTH=0.1MM AUDIO_EMI_LO_R AUDIO_PT_DK_CON_LO_R MIN_NECK_WIDTH=0.07MM MIN_LINE_WIDTH=0.1MM L5714 1 2 L5757 1 2 U5700 1 2 3 4 5 DZ5790 1 2 FL5711 1 2 FL5707 1 2 FL5708 1 2 L5716 1 2 3 4 R57901 2 D5703 1 5 4 6 C57501 2 C57511 2 C57521 2 C57531 2 C57541 2 C57551 2 D5702 1 5 4 6 D5701 1 5 4 6 D5700 1 5 4 6 C57221 2 C57211 2 L5762 1 2 C57821 2 C57831 2 L5761 1 2 L5760 1 2 L5763 1 2 C57801 2 R5710 1 2 DZ5720 1 2 DZ5710 1 2 DZ5711 1 2 DZ5712 1 2 R57401 2 R5730 1 2 R5731 1 2 U5730 B2 A2 A1 B1 C57301 2 R57501 2 R5751 1 2 R5752 1 2 R5753 1 2 C57601 2 R57951 2 R57961 2 L5700 1 2 3 4 L5701 1 2 3 4 L5702 1 2 3 4 DZ5752 A C DZ5753 1 2 XW5700 1 2 DZ5760 1 2 DZ5751 A1 A2 B1 B2 R5720 1 2 R5721 1 2 R57001 2 C57031 2 C57001 2 C57011 2 C57021 2 C57051 2 C57061 2 C57071 2 C57081 2 C57101 2 C57111 2 C57121 2 051-8773 10.0.0 57 OF 157 27 OF 48 2 3 2 3 2 3 2 3 29 42 29 42 29 43 29 43 29 27 28 43 29 45 53539 27 27 28 43 27 28 43 29 29 43 29 43 29 43 29 42 29 42 27 37 35 27 28 43 27 28 43 27 28 43 28 28 29 43 29 29 35 29 35 29 45 29 29
  • 31.
    OUT OUT OUT OUT BI BI OUT OUT OUT OUT OUTIN OUTIN OUTIN OUTIN IN OUT IN IN IN IN BI BI Apple Inc. THEINFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT PLACE NEAR J5900. PLACE NEAR R5901 PLACE NEAR R5903 PLACE NEAR J5900. STUFF FOR STEVENOTE STUFFING OPTIONS FOR DP LANES 2, 3 FOR STEVENOTE. PLACE NEAR J5900. ALTERNATE PINOUT FOR JTAG FOR STEVENOTE ON MLB, STUFF ALL OF THE PLACE NEAR J5900. PLACE NEAR J5900. PLACE NEAR R5907 DISPLAYPORT AC COUPLING SUPPORT ON MLB ONLY ALTERNATE PINOUT FOR JTAG R5904, R5906, R5914, R5915, R5916, AND R5917. FOR DEV BOARD, STUFF R5918 AND NOSTUFF R5903. PLACE NEAR R5905 PLACE NEAR J5900. SNOTE BOM OPTIONS. NOSTUFF R5902, R5900,R5908 PLACEMENT NOTE: NEAR U0600 1/32W MF 100K 1% 01005 MF 1/32W 100K 1% 01005 27 43 27 43 27 43 27 43 27 28 43 27 28 43 7 28 43 7 28 43 7 28 43 7 28 43 NOSTUFF SIGNAL_MODEL=EMPTY 150 MF 201 1/20W 5% SIGNAL_MODEL=EMPTY NOSTUFF 150 1/20W MF 201 5% SIGNAL_MODEL=EMPTY 100PF 201 CERM NOSTUFF 25V 5% 201 MF 1/20W 150 NOSTUFF SIGNAL_MODEL=EMPTY 5% MF 201 150 NOSTUFF 1/20W SIGNAL_MODEL=EMPTY 5% NOSTUFF 201 100PF SIGNAL_MODEL=EMPTY CERM 25V 5% 28 43 2016.3V 0.1UF X5R10% 743 28 43 X5R6.3V 201 0.1UF 10% 743 28 43 10% X5R 0.1UF 2016.3V 743 28 43 10% 201 0.1UF 6.3V X5R 743 29 6.8V-100PF 0201 201MF 0 1/20W DEVELOPMENT_JTAG 5% 1/20W SNOTE NO_XNET_CONNECTION=TRUE 201MF 0 SIGNAL_MODEL=EMPTY 5% 201MF 0 1/20W DEVELOPMENT_JTAG 5% 0 1/20W MF 201 SNOTE SIGNAL_MODEL=EMPTY NO_XNET_CONNECTION=TRUE 5% MF1/20W 0 2015% 0 SNOTE 1/20W MF 201 NO_XNET_CONNECTION=TRUE SIGNAL_MODEL=EMPTY 5% 201 0 1/20W MF5% SNOTE 201MF 0 1/20W NO_XNET_CONNECTION=TRUE SIGNAL_MODEL=EMPTY 5% 201MF1/20W 0 5% SNOTE 201 MF 1/20W 0 5% MF 0 201 1/20W 5% 0 1/20W MF 201 SNOTE 5% 0 2011/20W MF SNOTE 5% MF 0 201 1/20W 5% 1% 1/20W MF 45.3 201 1/20W 1% 45.3 MF 201 201 MF 1/20W 1% 45.3 201 MF 1/20W 1% 45.3 5 37 25V NP0-C0G 0201 27PF 5% 25V NP0-C0G 0201 27PF 5% 120-OHM-200MA 0201 72843 72843 72843 72843 743 743 6.3V 201X5R10% 0.1UF 10% 201X5R6.3V 0.1UF 10% 0.1UF 6.3V 201X5R 6.3V 0.1UF X5R10% 201 6.3V 201X5R10% 0.1UF X5R10% 2016.3V 0.1UF SYNC_DATE=01/19/2011 DISPLAY PORT MISC SYNC_MASTER=JOE DP_PT_DK_CON_TX_P<2> DP_PT_DK_CON_TX_P<3> VIDEO_PT_DK_CON_C_Y_R VIDEO_PT_DK_CON_CVBS_PB_R VIDEO_PT_DK_CON_CVBS_PB PT_DK_CON_P15_R PT_DK_CON_P14PT_DK_CON_P14_R DP_AP_TX_N<1> DP_AP_TX_P<1> DP_TERM_C1251 DP_EMI_AUX_N DP_EMI_AUX_P =PP3V0_IO_MISC DP_EMI_TX_P<0> DP_EMI_TX_N<0> DP_EMI_TX_P<1> DP_EMI_TX_N<1> DP_PT_DK_CON_TX_P<2> DP_PT_DK_CON_TX_N<2> DP_PT_DK_CON_TX_P<3> DP_PT_DK_CON_TX_N<3> DP_AP_TX_P<0> DP_AP_TX_N<0> DP_AP_TX_P<1> DP_AP_TX_N<1> DP_AP_TX_N<2> DP_AP_TX_P<2> DP_AP_TX_N<3> DP_AP_TX_P<3> DP_EMI_AUX_P DP_EMI_AUX_N DP_AP_AUX_P VIDEO_PT_DK_CON_C_Y DP_PT_DK_CON_TX_N<3> DP_TERM_C1250 VIDEO_PT_DK_CON_Y_PR_R VIDEO_PT_DK_CON_Y_PR PT_DK_CON_P17_R PT_DK_CON_P16_R PT_DK_CON_P17 DP_PT_DK_CON_TX_N<2> DP_AP_AUX_N DP_AP_TX_N<0> DP_AP_TX_P<0> HOME_L HOME_EMI_L C5802 1 2 C5803 1 2 C5804 1 2 C5805 1 2 C5806 1 2 C5807 1 2 R58201 2 R58231 2 R12531 2 R12521 2 C12511 2 R12511 2 R12501 2 C12501 2 C5808 1 2 C5809 1 2 C5810 1 2 C5811 1 2 DZ5750 1 2 R5900 12 R5901 12 R5902 12 R5903 12 R5904 12 R5905 12 R5906 12 R5907 12 R5908 12 R59091 2 R59121 2 R5913 12 R5911 12 R59101 2 R59141 2 R59151 2 R59161 2 R59171 2 C57661 2 C57651 2 FL5750 1 2 051-8773 10.0.0 58 OF 157 28 OF 48 28 43 28 43 2943 2943 27 43 29 2729 272843 272843 635 27 43 28 43 2943 27 43 29 29 27 28 43
  • 32.
    IN IN IN OUT BI BI IN IN IN IN BI BI IN IN OUT OUT OUT OUT OUT OUT IN IN IN IN IN Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT (JTAG_TMS_BACKUP) (JTAG_TCK_BACKUP) PN 516S0542 (PLUG - MALE) (JTAG_TMS) (JTAG_TCK) (DP_HPD) 28 28 2742 2742 27 42 27 42 27 43 27 43 27 43 27 43 27 43 27 43 27 27 27 27 27 28 27 27 2843 2843 2843 M-ST-SM CPB6450-0101F CRITICAL 28 28 SYNC_MASTER=JOE IO FLEX: B2B CONNECTOR SYNC_DATE=01/19/2011 PPVBUS_USB_PT_DK_CON PT_DK_CON_P15_R PT_DK_CON_P16_R VIDEO_PT_DK_CON_CVBS_PB_R VIDEO_PT_DK_CON_C_Y_R VIDEO_PT_DK_CON_Y_PR_R AUDIO_PT_DK_CON_LO_R PT_DK_CON_P17_R PT_DK_CON_P14_R ACC_PT_DK_CON_TX ACC_PT_DK_CON_RX ACC_PT_DK_CON_PP3V3 FW_PT_DK_CON_PWR ACC_PT_DK_CON_DET_L HOME_L DP_PT_DK_CON_AUX_N DP_PT_DK_CON_AUX_P USB_PT_DK_CON_D_P USB_PT_DK_CON_D_N ACC_PT_DK_CON_ID AV_PT_DK_CON_RET AUDIO_PT_DK_CON_LO_L AV_PT_DK_CON_DIFF_SENSE DP_PT_DK_CON_TX_N<1> DP_PT_DK_CON_TX_P<1> DP_PT_DK_CON_TX_N<0> DP_PT_DK_CON_TX_P<0> J5900 51 52 53 54 1 10 1112 1314 1516 1718 19 2 20 2122 2324 2526 2728 29 3 30 3132 3334 3536 3738 39 4 40 4142 4344 4546 4748 49 5 50 6 78 9 051-8773 10.0.0 59 OF 157 29 OF 48 2745 2745
  • 33.
    BI BI BI BI BI OUT IN OUT IN OUT IN OUT IN OUT IN IN OUT OUT OUT IN OUT IN OUT IN IN NC NC NC NC Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT X26 CELLULAR/GPS CONNECTOR 998-3732 - AP_MODEM_WAKE (RADAR #9179861) - H4G -> BB NOTE FOR IPC_GPIO_X26 (GPIO24): NOTE FOR SPI2_IPC_SRDY (GPIO12): - BB_DIAGS_READY (RADAR #9179861) - BB -> H4G 1142 1142 5 442 442 MF 1/32W 1% 255K 01005 255K 1% 1/32W MF 01005 10% 6.3V 01005 X5R 0.01UF NOSTUFF 37 5 4273745 3745 51545 545 545 542 542 542 542 542 5 37 37 542 542 542 542 542 OMIT HB-SM HOT-BAR-PADS SYNC_DATE=01/19/2011 CONNECTOR: X26 SYNC_MASTER=JOE ADC_IN7 SPI2_IPC_SRDY HSIC_HOST_RDY HSIC0_BB_DATA1 SNSV_BATT_POS_ACF =BATT_POS_F_3G RST_AP_L PM_RADIO_ON RST_BB_PMU_L GSM_TXBURST_IND RST_BB_L RST_DET_L SPI2_IPC_SCLK SPI2_IPC_MOSI SPI2_IPC_MISO BB_EMERGENCY_DWLD PM_BB_HOST_WAKE USB_BB_D_N BB_VBUS_DET USB_BB_D_P UART1_BB_RXD UART1_BB_TXD UART1_BB_CTS_L UART1_BB_RTS_L IPC_GPIO_X26 HSIC_BB_RDY HSIC0_BB_STB1 R61011 2 R61001 2 C61001 2 J6000 1 10 11 12 13 14 15 16 17 18 19 2 20 21 22 23 24 25 26 27 28 29 3 30 31 32 33 34 35 36 37 38 39 4 40 41 42 5 6 7 8 9 051-8773 10.0.0 60 OF 157 30 OF 48 35
  • 34.
    SYM 1 OF3 MISCSR MISC JTAG FM BT WLAN GND LDO WRF_VCO_GND WRF_PA_GND0 WRF_PA_GND1 WRF_PA_GND2 WRF_PADRV_GND WRF_GNDLNA_2G WRF_XTAL_GND WRF_LOGEN_A_GND WRF_AFE_GND WRF_ANA_GND WL_VSS_0 WL_VSS_1 WL_VSS_2 WRF_GND FM_RXVSS VOUT_LNLDO1 VOUT_CLDO VIN_LDO VOUT_3P1 VOUT_3P3 WRF_VCOLDO_OUT_1P2 SR_VLX BT_RFVSS BT_FEVSS BT_VSS SR_PVSS WRF_TCXO_VDD WL_VDDC1 WL_VDDC2 WRF_VDDANA_1P2 WL_VDDC0 WRF_VDDAFE_1P2 WRF_LOGEN_A_VDD1P2 BT_VDDIO WL_VDDIO VDDIO_RF HSIC_AVDD12 BT_PAVDD3P3 BT_VCOVDD1P2 BT_VDDC1 BT_VDDC0 BT_RFVDD1P2 BT_IFVDD1P2 BT_PLLVDD1P2 FM_VDDAUDIO FM_VDD2P5 FM_VDDPLL1P2 FM_RFVDD1P2 PMU_AVSS HSIC_AVSS BT_VSSC BT_IFVSS BT_PLLVSS FM_VSSAUDIO FM_VSSVCO FM_PLLVSS WRF_XTAL_VDD1P2 WRF_VDDLNA_1P2_2G WRF_PADRV_VDD WRF_VDDPA WRF_VDD_VCOLDO_IN_1P8 SR_VDDBAT2 BT_REG_ON WL_REG_ON BT_RST* EXT_SMPS_REQ EXT_PWM_REQ JTAG_SEL SR_VDDBAT1_1 SR_VDDBAT1_0 WLANGPIOHSIC SYM 3 OF 3 BT/FMLOGIC WLANLOGIC GPIOPCMFMI2S TEST UART WLANSDIO SDIO_DATA_0 SDIO_DATA_1 SDIO_DATA_2 SDIO_DATA_3 SDIO_CLK WRF_GPIO_OUT BT_I2S_CLK BT_GPIO_3 BT_GPIO_4 BT_GPIO_5 BT_GPIO_1 BT_GPIO_2 BT_PCM_SYNC BT_GPIO_0 BT_PCM_CLK BT_PCM_IN BT_PCM_OUT BT_UART_TXD BT_UART_RXD BT_UART_RTS* BT_UART_CTS* BT_TM0 BT_I2S_DI HSIC_DATA HSIC_RREF WL_GPIO_1 WL_GPIO_6 WL_GPIO_5 WL_GPIO_3 WL_GPIO_4 WL_GPIO_2 WL_GPIO_0 HSIC_STROBE SDIO_CMD BT_I2S_DO BT_I2S_WS BT_CLK_REQ_IN BT_CLK_REQ_MODE IN OUT OUT IN IN IN OUT OUT IN IN OUT IN IN IN OUT IN OUT IN BI IN IN IN BI IN IN YA B NC GND VCC IN OUT BI NC NC NC NC NC NC NC NC NC NC NC NC Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT TABLE_ALT_ITEM TABLE_ALT_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_ALT_ITEM (NEARM9) ALTERNATE PARTS AVAILABLE: USED FOR BOOTSTRAPPING OPTIONS WE HAVE 500MILIAMP BURST RETURN CURRENTS TO BATTERY PULL-UP/DOWN RESISTORS BOOTSTRAP RESISTORS SDIO_DATA2 PULL DOWN FOR GPIO SET TAU = 200MILISEC WLAN RESET FALLS DEVICE READY DE-ASSERTS WHEN: SW-DEFINED GPIO2 FALLS 1 0 1 1 X 0 1 SDIO_DATA1 GSPI SDIO 1 0 MODE DEF.ARM STATE RESET RESET RUNNING RUNNING HOST WAKE FM I2S NOT WIRED UP GET RFDESIGN OK FOR ANY SEPARATION HSIC DEV RDY / JTAG TCK RF GUYS HATE MULTIPLE GROUND PLANES JTAG TRST_N (UNUSED) UART TX / JTAG TDO UART RX / JTAG TDI HSIC BOOTLOADERLESS HSIC SUPPLY FILTERING GPIO6 WLAN/BT POWER HSIC HOST RDY / JTAG TMS 1 X X BOOTSTRAPPING OPTIONS SDIO NOT WIRED UP WLAN/BT BASEBAND HSIC READY KLUDGE (NEARE1) MF 201 5% 1/20W 10K SHORT-0402 NOSTUFF X5R 20% 6.3V 0201 0.22UF MF 5% 1/20W 10K 201 120-OHM-200MA 0201 0201 120-OHM-200MA 4.7UF X5R 603 20% 6.3V 20% X5R 603 6.3V 4.7UF 0201 600-OHM-150MA WLBGA BCM4330XKUBG CRITICAL CKPLUS_WAIVE=PWRTERM2GND BCM4330XKUBG WLBGA CRITICAL 15 33 15 33 15 33 15 33 15 15 31 33 15 33 15 15 15 1533 1533 3133 1533 1533 15 31 201 1/20W MF 1% 49.9 1533 1533 32 15 31 33 15 33 201 X7R 16V 10% 1000PF 603 X5R 20% 6.3V 4.7UF 603 X5R 20% 6.3V 4.7UF 1UF 402 6.3V 10% CERM CRITICAL 2.2UH-1.3A-0.1OHM 1008 603 4.7UF 20% X5R 6.3V 10% 6.3V X5R 201 0.1UF X7R-CERM 10% 220PF 201 25V 5% 10PF NPO 201 25V 0.1UF 10% 201 6.3V X5R 201 X5R 10% 0.1UF 6.3V 6.3V 0.1UF 10% X5R 201 MF 201 5% 1/20W 10K 31 1/20W 201 0 5% MF NOSTUFF 3133 313335 MF 201 5% 1/20W 100K 20% X5R 6.3V 4.7UF 603 10K 5% 201 1/20W MF 5% 201 CERM 25V 100PF 0201 600-OHM-150MA 201 25V NPO 10PF 5% 74AUP1G08GF SOT891 10% 0.1UF 6.3V X5R 201 2.2M 1/20W MF 201 5% 10% 0.1UF 6.3V X5R 201 153133 10% 6.3V X5R 0.1UF 201 0.1UF 10% 6.3V X5R 201 201 0 5% MF 1/20W 15 31 15 0 5% 1/20W 201 MF 1UF 10% 6.3V 402 CERM 25V 201 NPO 10PF 5% 10% 201 X5R 0.1UF 6.3V MF 100K 1/20W 5% 201100K 201 MF 1/20W 5% MF 201 5% 1/20W 100K MF 201 5% 1/20W 100K MF 201 5% 1/20W 100K NOSTUFF ANDGATE_TI TIU8311S0548 311S0398 155S0657 FERRITE_TY TAIYO YUDENFL2,FL4155S0537 155S0337 155S0444 FERRITE_TDK TDKFL6,FL9 WLAN BB & POWER PWR100VDD_LNLDO_1V2 SR_VLX PWR1000 PWR100VDD_CORE_1V2 PWR1000 VDD_CBUCK_1V5 PWR1000 BATT_VDD_4330 PWR100VDD_LDO_2V5 SDIO_DATA1_4330 VDD_VCO_1V2 VDD_IO_1V8 BT_WAKE VDD_IO_1V8 SDIO_DATA3_4330 SDIO_CLK_4330 SDIO_DATA3_4330 SDIO_DATA2_4330 SDIO_CMD_4330 SDIO_CLK_4330 HSIC_STROBE_4330 HSIC_RREF WLAN_GPIO6 2G_TSSI WLAN_GPIO1 VDD_IO_1V8 WLAN_GPIO2 WLAN_GPIO2_R VDD_IO_1V8 WLAN_ENABLE_RC HSIC_DEVICE_READY_R HSIC_DEVICE_READY WLAN_ENABLE WLAN_GPIO2 HSIC_DEVICE_READY SDIO_DATA2_4330 WLAN_GPIO6 WLAN_GPIO0 WLAN_GPIO2 WLAN_GPIO4 WLAN_GPIO3 WLAN_GPIO5 HSIC_DATA_4330 BT_UART_CTS_N BT_UART_RTS_N BT_UART_RXD BT_UART_TXD BT_PCM_DOUT BT_PCM_DIN BT_PCM_CLK BT_WAKE BT_PCM_SYNC BT_HOST_WAKE BT_GPIO5 SDIO_DATA0_4330 SDIO_CMD_4330 SDIO_DATA0_4330 SDIO_DATA1_4330 VDD_CORE_1V2 VDD_LNLDO_1V2 VDD_IO_1V8 VDD_LDO_3V3 VDD_CORE_1V2 VDD_LDO_3V3 VDD_BTCORE_1V2 VDD_BT_1V2 VDD_LDO_2V5 VDD_BT_1V2 VDD_XTAL_1V2 VDD_WRF_1V2 BATT_VDD_4330 BATT_VDD_4330 BT_RESET_N WLAN_ENABLE JTAG_SEL VDD_LDO_3V3 PWR100 PWR100 VDD_BT_1V2 PWR100 VDD_BTCORE_1V2 BATT_VCC PWR500 PWR100 VDD_WRF_1V2 PWR100 PWR100 VDD_LNLDO_1V2 PWR100 VDD_WRF_1V2 PWR100 VDD_XTAL_1V2 PWR100 VDD_CORE_1V2 R5 1 2 XW1 1 2 C291 2 R4 1 2 FL2 1 2 FL4 1 2 C21 2 C11 2 FL6 1 2 U4 A10 B8 C8 A8 B11 C10 K10 B9 B10 G10 A11 K8 E8 F7 C9 F8 J10 K9 F10 E12 E11 F12 D10 E10 C11 F11 L1 M1 F5 L11 M11 K12 L12 K11 M12 L3 M10 J11 J12 M9 L10 L9 K1 K7 E7 M3 K2 L5 E5 F4 C1 C5 C7 D3D2 B2 B4 B6 C4C3 F3 F1F2 E1 G4 D1 B7 A4 H2H3 U4 D7 E9 F9 D9 H10 H9 H12 J9 H8 G7 H7 G8 H6 J6 J5 K6 G11 G6 F6 E6 D6 L2 J1 M2 M7 L7 M6 M8 M5 L8 H4 G5 H5 D5 J8 L6 D8 E4 R10 1 2 C31 2 C481 2 C491 2 C501 2 L1 1 2 C58 1 2 C561 2 C541 2 C531 2 C551 2 C571 2 C591 2 R11 1 2 R76 1 2 R12 1 2 C701 2 R16 1 2 C791 2 FL9 1 2 C781 2 U8 2 1 36 4 C801 2 R27 1 2 C811 2 C821 2 C521 2 R28 1 2 R26 1 2 C171 2 C851 2 C861 2 R31 1 2 R34 1 2 R33 1 2 R32 1 2 R35 1 2 051-8773 10.0.0 61 OF 157 31 OF 48 5 31 31 313233 31 31 313335 153133 31 31 31 31 31 31 313335 313335 3133 15 31 3131 31 31 31 31 31 313335 313233 31 313233 31 31 31 31 31 31 313233 313233 313233 31 31 3335 31 31 31 31 31
  • 35.
    OUT VDD RX BT TX SW_OUT/NC GND ANT VC3 VC2 VC1 LNA_IN/NC BI BI OUT GND IN BI IN IN RF / CLOCKS BT RFFM CLOCKSWLANRF SYM2 OF 3 FM_RXN FM_TX FM_RXP WRF_XTAL_OP WRF_XTAL_ON WRF_RFOUT_5G WRF_RFIN_5G WRF_RES_EXT RF_SW_CTRL_6 WRF_RFOUT_2G WRF_RFIN_2G WRF_A_TSSI_IN WRF_TCXO_IN LPO BT_RF BT_CLK_REQ_OUT RF_SW_CTRL_2 RF_SW_CTRL_1 RF_SW_CTRL_0 RF_SW_CTRL_5 RF_SW_CTRL_4 RF_SW_CTRL_3 FM_AOUT2 FM_AOUT1 RF_SW_CTRL_7 OUT OUT OUT OUT OUT OUT OUT OUT OUT IN OUT IN IN OUT IN RFIN RFOUT THRM_PAD VDET VCTRL VCC1 VCC2 IN OUT IN IN IN ANT(COMMON) LOW(2.4GHZ) HIGH(5.0GHZ) GND NC NC NC NC NC NC Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT WLAN TRANSCEIVER 2.4GHZ RX + T/R SWITCH 2.4GHZ BPF 0 0 1 WLAN TX RF_SW_CTRL_5: 5G_CTRL_TX RF_SW_CTRL_4: 5G_CTRL_RX 1 0 0 BT TX/RX 0 1 0 WLAN RX RF_SW_CTRL_1: 2G_CTRL_RX RF_SW_CTRL_7: 5G_CTRL_PA_EN RF_SW_CTRL_2: 2G_CTRL_TX 0 0 0 LNA BYPASS VCTL1 VCTL2 VCTL3 MODE . RF_SW_CTRL_3: 2G_CTRL_PA_EN RF I/O PLAN FORM GROUND ISLAND FOR XTAL CKT BACK TO BUMP H4 2.4GHZ/5GHZ DIPLEXER RF_SW_CTRL_6: 5G_CTRL_LNA_EN RF_SW_CTRL_0: 2G_CTRL_BT ANTENNA CONNECTOR SP3T+LNA 2.4GHZ TX CONDUCTED TEST PORT 1% MF 201 1/20W 15K 32 CRITICAL SKY65513-11 QFN 0201 CRITICAL 3.3NH+/-0.1NH-0.45A 201 6.3V X5R 0.1UF 10% CER 8.2PF 25V 0201 +/-0.1PF% 5.6NH 0201 NOSTUFF 33 32 4.7PF 0201 COG-CERM 25V +/-0.1PF NOSTUFF 0201 5.6NH CRITICAL F-ST-SM MM8030-2600RK0 32 1.0PF +/-0.1PF C0G NOSTUFF 25V 201 5.6NH NOSTUFF 0201 MM4829-2702 F-ST-SM CRITICAL 32 32 201 25V CERM 5% 100PF100PF 5% CERM 25V 201 CRITICAL 0805 2.45GHZ-2.4DB 3.3NH+/-0.1NH-0.45A NOSTUFF 0201 +/-0.1PF% 0201 CER 25V 8.2PF 3.3NH+/-0.1NH-0.45A 0201 NOSTUFF 1% 201 1/20W MF 47 WLBGA BCM4330XKUBG CRITICAL +/-0.1PF C0G 25V 1.8PF NOSTUFF 201 10% 6.3V 201 X5R 0.1UF 33PF NP0-C0G 5% 201 25V 10PF 5% NPO 25V 201 1.2NH+/-0.1NH-0.75A NOSTUFF 0201 0201 1.2NH+/-0.1NH-0.75A CRITICAL 0201 25V CER 8.2PF +/-0.1PF% 32 32 32 32 33 33 33 33 33 33 32 32 33 32 SM-2 CRITICAL 37.4MHZ-18PF-10PPM 1% MF 220 1/20W 201 32 LLP MF2425PL-DL0767 CRITICAL 32 31 32 4.7UF 603 20% 6.3V X5R 15 33 CRITICAL 2450MHZ-3.50DB LFB182G45CG3C179 32 0201 25V 8.2PF +/-0.1PF% CER NOSTUFF +/-0.1PF 201 1.8PF 25V C0G 1.8PF C0G 25V 201 +/-0.1PF NOSTUFF NOSTUFF 201 25V 1.8PF C0G +/-0.1PF+/-0.1PF 1.8PF C0G 25V 201 NOSTUFF 8.2PF +/-0.1PF% CER 25V 0201 10K 1% 1/20W MF 201 1% 201 MF 1/20W 2.2K 5% 25V 201 100PF CERM 201 C0G 25V NOSTUFF +/-0.1PF 1.8PF 0201 4.7NH-3%-0.35A CRITICAL CRITICAL 0805 2.4-5.0GHZ 4.7NH-3%-0.35A 0201CRITICAL CRITICAL 0201 4.3NH-3%-0.35A 0.1UF 201 X5R 10% 6.3V 0201 CRITICAL 1/20W MF 0.00 1% 0201 6.8NH-5%-0.3A NOSTUFF 25V NP0-C0G 33PF 5% 201 25V 33PF 5% 201 NP0-C0G 0201 1.2NH+/-0.1NH-0.75A CRITICAL 201 25V NPO 10PF 5% WLAN 2.4GHZ AND ANT50_OHM 50_OHM RF_ANT_MATCH1 RF_ANT 50_OHM 50_OHM 5G_CTRL_RX 2G_CTRL_RX CLK32K 2G_PA_VCRL WLAN_RBIAS_4330 WLAN_XTAL_N_XTAL WLAN_XTAL_P_4330 2G_PA_VDET 2G_CTRL_PA_EN 2G_RF_SP3T_LNA1 2G_RF_SP3T_LNA2 2G_CTRL_BT 2G_RF 5G_RF 2G_PA_VCC2 2G_TSSI BATT_VDD_4330 5G_CTRL_PA_EN 2G_CTRL_PA_EN 5G_CTRL_TX 2G_CTRL_BT 2G_CTRL_RX 2G_CTRL_TX 5G_TSSI 5G_CTRL_LNA_EN WLAN_XTAL_N_4330 2G_CTRL_TX 50_OHM 2G_RF_BPF1_OUT 50_OHM 2G_RF_BPF1_IN 50_OHM 50_OHM 50_OHM 50_OHM 2G_RF_OUT_4330 50_OHM 2G_RF_BT_433050_OHM 50_OHM 50_OHM 2G_RF_IN_4330 2G_RF_TX_SP3T 50_OHM 50_OHM 2G_RF_PA_OUT 50_OHM 50_OHM 50_OHM 50_OHM RF_CAL_MATCH RF_CAL 50_OHM 50_OHM 2G_RF 50_OHM 50_OHM 50_OHM 50_OHM 2G_RF_BPF2_OUT 2G_RF_OUT_4330 50_OHM50_OHM 50_OHM 50_OHM 2G_RF_BT_4330 2G_RF_SP3T_ANT 50_OHM 50_OHM 50_OHM 5G_RF_IN_433050_OHM 50_OHM 2G_RF_IN_433050_OHM 50_OHM 5G_RF_OUT_433050_OHM 50_OHM 50_OHM 2G_RF_RX_SP3T 50_OHM 50_OHM 2G_RF_BPF2_IN PWR100 2G_SP3T_VDD 50_OHM 50_OHM 2G_RF_BT_SP3T PWR100 VDD_LDO_3V3 50_OHM 50_OHM 2G_RF_PA_IN R1 1 2 U3 2 12 7 9 6 8 5 4 1 11 3 10 L2 1 2 C891 2 C18 1 2 L6 1 2 C21 1 2 L7 1 2 J1 3 4 1 2 C111 2 L9 1 2 J2 2 3 4 1 C51 2 C41 2 FL1 2 1 3 L43 1 2 C20 1 2 L5 12 R2 12 U4 G12 A9 A12 B12 D12 D11 C12 J7 K5 J2 L4 M4 K3 J4 J3 K4 D4 E3 A7 B1 A6 A2 G3 H1 G1 C44 1 2 C411 2 C42 1 2 C431 2 L15 1 2 L16 12 C37 12 Y1 24 13 R9 1 2 U6 4 1 7 3 2 5 6 C38 1 2 FL8 2 1 3 C65 1 2 C63 1 2 C67 1 2 C68 1 2 C64 1 2 C66 1 2 R15 12 R14 1 2 C691 2 C45 1 2 L20 1 2 FL10 2 1 3 5 4 6 L14 1 2 L17 1 2 C391 2 R3 1 2 L23 12 C46 1 2 C47 1 2 L24 1 2 C61 2 051-8773 10.0.0 62 OF 157 32 OF 48 3133 31 33
  • 36.
    A A A A A A GND OUTPUT2 OUTPUT1 VCONT2 VCONT1 INPUT A BI VCTL RFIN NC/GND THRM NC/GND VDET RFOUT VCC12 VCC3 PAD A PP PP A A A A A A OUT A THRM GND VCC V_ENABLE RF_INRF_OUT PAD IN A A IN OUT A IN IN AIN AppleInc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT VCRL1 VCTL2 PA_EN LNA_EN MODE 0 1 0 1 RX TEST AND PROBE POINTS TEST POINTS 1 0 1 0 TX 5GHZ PA NEED DC BLOCKING ON ALL PORTS 1 0 0 1 RX SUPERBYPASS MODE -- 26DB GAIN STEP 5GHZ FRONT-END CONTROL 5GHZ BPF 5GHZ LNA 5GHZ T/R SWITCH TP-P6 NOSTUFF TP-P6 NOSTUFF +/-0.05PF 0201 NOSTUFF 0.6PF 25V CERM 2.0PF +/-0.1PF 25V C0G-CERM 0201 CRITICAL TP-P6 NOSTUFF NOSTUFF TP-P6 NOSTUFF TP-P6 NOSTUFF TP-P6 CRITICAL UPG2185T6R TSSON TP-P6 NOSTUFF 201 5% MF 1/20W 62 25V +/-0.1PF C0G-CERM 0201 2.0PF CRITICAL 32 NOSTUFF 1.0NH+/-0.1NH-0.75A 0201 +/-0.1PF C0G-CERM 2.0PF 25V 0201 CRITICAL MF5060PK-DL0967 LGA CRITICAL NOSTUFF TP-P6 0201 1.0NH+/-0.1NH-0.75A NOSTUFF P4MM SM P4MM SM +/-0.1PF 0201 COG-CERM 25V 4.7PF TP-P6 NOSTUFF TP-1P0-TOP NOSTUFF TP-1P0-TOP NOSTUFF NOSTUFF TP-1P0-TOP NOSTUFF TP-1P0-TOP NOSTUFF TP-1P0-TOP 32 TP-P6 NOSTUFF SKY65404-31 QFN 5G_RF_LNA_OUT CRITICAL 100PF CERM 201 25V 5% +/-0.10PF CERM 25V 201 NOSTUFF 0.6PF 32 201 10V 10% 0.01UF X5R NOSTUFF TP-P6 0201 CRITICAL 1.0NH+/-0.1NH-0.75A NOSTUFF TP-P6 C0G-CERM 2.0PF 0201 +/-0.1PF 25V CRITICAL 0201 NOSTUFF 1.0NH+/-0.1NH-0.75A +/-0.1PF C0G-CERM 0201 25V 2.0PF CRITICAL 32 6.3V 20% X5R 603 4.7UF 1.0NH+/-0.1NH-0.75A NOSTUFF 0201 1.0NH+/-0.1NH-0.75A NOSTUFF 0201 10PF NPO 201 25V 5% 32 NP0-C0G 25V 27PF 5% 0201 10K 1% 201 1/20W MF CRITICAL 5.0GHZ-1.7DB DEA165375BT +/-0.10PF CERM 25V 201 0.6PF NOSTUFF 201 NOSTUFF 0.6PF 25V +/-0.10PF CERM C0G-CERM 2.0PF 0201 +/-0.1PF 25V CRITICAL 1/20W MF 201 1% 2.2K NOSTUFF TP-P6 32 32 TP-P6 NOSTUFF 100PF 201 25V CERM 5% 25V 201 CERM 5% 100PF 32 100PF 201 25V CERM 5% 0201 C0G-CERM +/-0.1PF 25V 2.0PF CRITICAL 0.6PF 25V CERM 0201 +/-0.05PF WLAN 5GHZ AND TEST POINTS 5G_PA_VDET VDD_LDO_3V3 50_OHM 50_OHM 5G_RF_RX 50_OHM 50_OHM 5G_RF_TRSW 5G_CTRL_TX 5G_CTRL_LNA_EN WLAN_GPIO2 BATT_VDD_4330 HSIC_STROBE_4330 HSIC_DATA_4330 CLK32K WLAN_GPIO3 WLAN_ENABLE5G_CTRL_PA_EN 5G_TSSI 5G_LNA_CHOKE BATT_VCC VDD_IO_1V8 BATT_VDD_4330 WLAN_GPIO0 WLAN_GPIO1 WLAN_GPIO4 BT_UART_CTS_N BT_HOST_WAKE BT_WAKE BT_UART_RTS_N BT_UART_RXD BT_UART_TXD BT_RESET_N5G_PA_VCTL 50_OHM 50_OHM 5G_RF 50_OHM 5G_RF_RX_BPF_IN 50_OHM 5G_RF_TX_MATCH 50_OHM 50_OHM 5G_RF_PA_OUT 50_OHM 50_OHM 50_OHM 50_OHM 5G_RF_RX_BPF_OUT 5G_RF_LNA_IN 50_OHM 50_OHM50_OHM 50_OHM 5G_RF_IN_4330 5G_RF_OUT_4330 50_OHM 50_OHM 50_OHM 50_OHM 5G_RF_PA_IN 50_OHM 50_OHM 50_OHM 50_OHM 5G_RF_TX 5G_CTRL_RX TP91 TP81 TP71 TP61 TP21TP11 TP291 TP271 TP281 TP261 TP181 TP191 TP161 TP171 TP151 U1 2 5 34 7 1 6 C81 2 C101 2 C71 2 L46 12 C33 1 2 L10 12 C35 1 2 C321 2 L11 12 L12 12 C341 2 C361 2 R7 1 2 FL7 2 4 1 3 C621 2 C60 1 2 C61 1 2 R13 1 2 C76 1 2 C751 2 C741 2 C72 1 2 C731 2 C71 1 2 C77 1 2 TP31 TP41 TP51 TP101 U9 2 51 3 6 4 R29 1 2 C84 1 2 L21 12 C83 1 2 U10 2 3 5 1 9 6 7 4 8 L22 12 PP29 1 PP30 1 C871 2 051-8773 10.0.0 63 OF 157 33 OF 48 31 32 31 313233 15 31 15 31 15 32 15 31 15 31 31 35 31 35 31 32 33 15 31 15 31 15 31 15 31 15 31 15 31 15 31 15 31 15 31 15 31
  • 37.
    BI BI A A A A HDQ THERM PACK_NEG PACK_POS SENSE Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT NOTE: GET RID OF THE MIN_NECK_MIDTH SHOULD BE 0.2MM RES AFTER BRINGUP APN:516S0926 NP0-C0G 5% 25V 201 33PF 1000PF 10% 201 16V X7R 33PF 5% 25V NP0-C0G 201 0201 240-OHM-0.2A-0.8-OHM 0 1/20W 5% MF 201 537 0201 82PF 5% CERM 25V 37 NOSTUFF TP-P55 TP-P55 NOSTUFF NOSTUFF TP-P55 TP-P55 NOSTUFF CRITICAL BATT-J2 F-RT-SMTH SYNC_DATE=01/13/2011 POWER: BATTERY CONNECTOR SYNC_MASTER=MADHAVI MIN_NECK_WIDT=0.15MM MIN_LINE_WIDT=0.25MM BATT_SNS NET_SPACING_TYPE=ANLG =BATT_POS_CONN BATT_NTC_CONN NET_SPACING_TYPE=ANLG BATT_SWI_CONNBATTERY_SWI BATTERY_NTC NET_SPACING_TYPE=ANLG C7522 1 2 C7524 1 2 C7523 1 2 FL7500 1 2 R7541 1 2 C7525 1 2 TP75001 TP75011 TP75021 TP75031 J7500 1 2 3 4 5 6 7 8 051-8773 10.0.0 75 OF 157 34 OF 48 36 35
  • 38.
    Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT VOUT_LED_A (BUCK3) VOUT_LED_B (BUCK3) BUCK4 LDO2 LDO7 LCM_BOOST LDO11 LDO10 LDO9 LDO12 LDO6 LDO5 LDO8 CHARGER MAIN LDO4 LDO3 BATTERY BUCK5 LDO RAILS BUCK3 CPU1V8_SW BUCK2 PROGRAMMABLE ON/OFF BUCK RAILS BUCK0 BUCK4_SW USED BY WIFI_BT LDO1 POWER CONN / ALIAS USB POWER INPUT WDIG_SW POWER ALIASES SYNC_DATE=01/13/2011SYNC_MASTER=MADHAVI =PP3V0_VIDEO_BUF =PP3V3_PORT_ACC =PP3V0_S2R_HALL_CHSW =PP2V85_CAM =PP1V1_PLL_H4 MIN_LINE_WIDTH=0.6 MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE VOLTAGE=1.1V PP1V1 MAX_NECK_LENGTH=3 MM =PP1V1_MIPI_PLL_H4 =PP1V1_USB_H4 =PP1V1_DP_PAD_DVDD_H4 =PP1V1_MIPI_H4 =PP3V0_VDDIOD_H4 =PP3V2_LDO5 =PP3V0_S2R_HALL =PP1V1_HSIC_H4 MIN_LINE_WIDTH=0.6 mm MAKE_BASE=TRUE VOLTAGE=3.0V MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.2 mm PP3V0_VIDEO =PP3V0_VIDEO_H4 =PP1V7_VA_VCP =PP3V0_GRAPE_Z2 =PP3V0_GRAPE_MARIO1 =PP3V0_GRAPE_Z1 =PP3V0_OPTICAL MIN_LINE_WIDTH=0.6MM MAX_NECK_LENGTH=3 MM PPVCC_MAIN VOLTAGE=4.7V MAKE_BASE=TRUE NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.1MM =PPVCC_MAIN_DOCK =PP1V2_HSIC_H4 NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.2MM MAKE_BASE=TRUE PP3V3_OUT VOLTAGE=3.3V MAX_NECK_LENGTH=3MM =PP1V8_AUDIO =PP1V8_CAM =PP1V8_DP_H4 =PP1V8_EDP_H4 =PP1V8_H4 =PP1V8_MIPI_H4 =PP1V8_NAND =PP1V8_NAND_H4 =PP1V8_SENSOR =PP1V8_VDDA18_TS =PP1V8_VDDIO18_H4 =PP1V8_VDDIOD_H4 VOLTAGE=1.1V PP1V8 MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM MAKE_BASE=TRUE =PPVDD_CPU_H4 VOLTAGE=1.2V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 MM MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.25 MM PP1V2_SOC =BATT_POS_CONN =BATT_POS_F_3G BATT_VCC MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR PPBATT_VCC MAKE_BASE=TRUE VOLTAGE=4.2V MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.20 MM =PP1V1_EDP_PAD_DVDD_H4 =PP1V2_VDDIOD_H4 =PP1V2_S2R_DDR =PP1V2_S2R_H4 =PPVDD_SOC_H4 =PP1V8_ALWAYS =PP1V8_S2R_DDR VDD_IO_1V8 =PP3V0_GRAPE =PP3V0_IO_H4 =PP3V0_IO_MISC =PP3V2_S2R_USBMUX =PP3V3_LCD =PP3V3_NAND =PP3V3_NAND_H4 =PP3V3_USB_H4 =PP5V25_GRAPE_VDDH =PPLED_REG_A =PPLED_REG_B =PPVCC_MAIN_AUDIO =PPVCC_MAIN_LED NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 MM MAKE_BASE=TRUE VOLTAGE=1.2V PP1V2 MIN_NECK_WIDTH=0.25 MM MIN_LINE_WIDTH=0.6 MM MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR VOLTAGE=1.2V MAKE_BASE=TRUE PP1V2_S2R MIN_LINE_WIDTH=0.6MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.2MM PP1V7_VA_VCP VOLTAGE=1.7V MAKE_BASE=TRUE PP1V8_ALWAYS MIN_NECK_WIDTH=0.1 MM VOLTAGE=1.8V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.8V MAKE_BASE=TRUE PP1V8_GRAPE MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V MIN_LINE_WIDTH=0.6 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MAKE_BASE=TRUE PP1V25_CPU MIN_LINE_WIDTH=0.6MM VOLTAGE=2.85V PP2V85_CAM MAKE_BASE=TRUE MIN_NECK_WIDTH=0.2MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.2MM MAKE_BASE=TRUE VOLTAGE=3.0V PP3V0_GRAPE MIN_LINE_WIDTH=0.6MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM MAKE_BASE=TRUE VOLTAGE=3.0V NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM PP3V0_IO MIN_NECK_WIDTH=0.2 mm NET_SPACING_TYPE=PWR VOLTAGE=3.0V MAKE_BASE=TRUE MAX_NECK_LENGTH=3 MM PP3V0_OPTICAL MIN_LINE_WIDTH=0.6 MM MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM PP3V0_S2R_HALL VOLTAGE=3.0V NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM PP3V0_VIDEO_BUF MAKE_BASE=TRUE MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR VOLTAGE=3.0V MIN_NECK_WIDTH=0.2MM PP3V2_LDO5 MAKE_BASE=TRUE MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR VOLTAGE=3.2V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.6 MM MAX_NECK_LENGTH=3 MM PP3V2_S2R_USBMUX VOLTAGE=3.2V MAKE_BASE=TRUE MAX_NECK_LENGTH=3 MM PP3V3_ACC NET_SPACING_TYPE=PWR VOLTAGE=3.3V MAKE_BASE=TRUE MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM VOLTAGE=5.25V MIN_LINE_WIDTH=0.6 MM NET_SPACING_TYPE=PWR MAKE_BASE=TRUE MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.25 MM PP5V25_VLCM2 MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.6 MM VOLTAGE=20.4V MAKE_BASE=TRUE MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR PPLED_OUT_B =PP1V8_S2R_MISC MIN_NECK_WIDTH=0.15 MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.8V MAKE_BASE=TRUE PP1V8_S2R =PP1V8_GRAPE =PP1V2_VDDQ_DDR MAX_NECK_LENGTH=3 MM MAKE_BASE=TRUE NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.6 MM VOLTAGE=20.4V PPLED_OUT_A PPVBUS_USB_DCIN MAKE_BASE=TRUE PPVBUS_USB_EMI MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.3MM GND MAKE_BASE=TRUE NET_SPACING_TYPE=GND MAX_NECK_LENGTH=5 MM VOLTAGE=0V 051-8773 10.0.0 80 OF 157 35 OF 48 11 27 22 26 43645 4 4 7 7 9 26 4 3645 7 19 18 17 18 26 363745 27 4 3645 19 25 7 7 4 7 10 7 12 9 26 5 9 5 9 36 45 9 3645 34 30 31 33 363945 7 8 9 13 14 8 9 5 13 14 31 33 17 18 7 9 6 28 11 16 12 9 4 16 16 19 20 22 37 3645 3645 364045 3645 3645 3645 3645 3645 3645 3645 3645 3645 3645 3645 3645 3745 3745 5 27 393645 13 14 3745 36 4527
  • 39.
    S D G S G D TP TP BUCK5_LX VBUCK5_BYP BUCK0_LXL BUCK0_LXM BUCK4_LXL VBUCK4 VLDO10 CPU1V2_SW DSP_SW BUCK2_LXR BUCK2_LXM VBAT CHG_LX BUCK2_FB VLDO4 ACT_DIO VLDO11 VLDO12 ON_BUF VBUS_OV_N BUCK2_LXL XTAL2 XTAL1 WDIG_SW VPUMP VLDO8 VLDO6 VLDO5 VLDO3 VLDO2 VDD_LDO9 VDD_LDO4_7 VDD_LDO3_5_8 VDD_LDO2 VDD_LDO12 VDD_LDO11 VDD_LDO10 VDD_LDO1_6 VDD_BUCK0 VCC_MAIN VCC_MAIN_SENSE VBUS VBUCK3 VBUCK0_SW0_S VBUCK0_SW0_G IBAT CPU1V8_SW BUCK4_LXM BUCK4_FB BUCK3_LXM BUCK3_LXL BUCK3_FB BUCK0_FB IBAT_SENSE VLDO7 VLDO9 VDD_BUCK5 VDD_BUCK3 VDD_BUCK2 VDD_BUCK5_BYP VDD_BUCK4 VLDO1 BUCK5_FB VCENTER LDO LDOINPUTXTALVCC-MAIN SWITCHPOWER SYM 2 OF4 BUCK USB/BAT Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT TABLE_ALT_ITEM TABLE_ALT_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD C8172- PLACE NEAR PMU 6.9 A 27 MOHM @-4.5V P-TYPE FDMC6676BZ (150MA; 2.5-3.6V) USB REVERSE VOLTAGE PROTECTION RDSON=0.0136@VGS=-2.5V R8173- PLACE NEAR PMU R8172- PLACE NEAR BMU (50MA; 2.5-3.3V) (100MA; 1.8-3.3V) (50MA; 1.5-3.3V) (200MA; 2.5-3.55V) RIGHT AT THE PIN (300MA; 2.5-3.6V) ID=12.0A NOTE: FOR NO BATTERY SITUATION ALTERNATE FOUNDRY (BYPASS RON=0.14 OHM MAX) (10MA; 2.0-3.55V) LAYOUT NOTE: PLACE RIGHT AT THE PIN (RON=0.5 OHM MAX) (RON=0.2 OHM MAX) (100MA; 1.65-1.805V; BUCK3) REVIEW THESE ESR MAX=70MOHM NOTE: CONCERNED ABOUT ESR > 20MOHM NOTE: CHANGE SOME 1UF TO 4.7UF ESR MAX=70MOHM +/- 25V LDO BYPASS 25UF (N0 DE-RATING) ADDITIONAL DISTRIBUTED VGS MAX (RON=1 OHM MAX) (300MA; 1.2-3.0V) (150MA; 2.5-3.55V) DCR=64MOHM MAX (DISTRIBUTED AND NO DE-RATING) TOTAL CAPS = ~400UF VCC_MAIN BYPASS (PLACE ONE 10UF CAP AT EACH VDD INPUT) IMAX MOSFET CHANNEL RDS(ON) LAYOUT NOTE: PLACE 14UF (N0 DE-RATING) ADDITIONAL DISTRIBUTED ADDITIONAL DISTRIBUTED 20UF (N0 DE-RATING) (200MA; 1.7-3.0V) (150MA; 0.6-1.3V) ADDITIONAL DISTRIBUTED 30UF (N0 DE-RATING) ADDITIONAL DISTRIBUTED LAYOUT NOTE - DCR=32MOHM MAX NOTE: 10V ZENER (RON=0.1 OHM MAX) 47UF (N0 DE-RATING) 10UF 20% 6.3V CRITICAL 603 X5R 201 5% 25V 18PF NP0-C0G 0201 CERM 5% 82PF 25V 20% 6.3V CRITICAL TANT-1 B15G 150UF X5R-CERM-1 6.3V 20% 22UF 603 CRITICAL NOSTUFF SM SM NOSTUFF NOSTUFF SM NOSTUFF SM SHORT-0201 NOSTUFF 201 MF 470K 1/20W 1% NOSTUFF CRITICAL LLP BZT52C10LP CRITICAL MLP3.3X3.3 FDMC6676BZ 201 1% 1/20W MF 220K 10% CRITICAL X5R-CERM 805 2.2UF 25V 25V CRITICAL X5R 805 10% 10UF 6.3V 402 CERM 10% 1UF 201 5% 18PF 25V NP0-C0G 201 NP0-C0G 25V 18PF 5% CRITICAL 2012 32.768K-20PPM-12.5PF NOSTUFF SM CRITICAL 2.2UH-20%-3.3A-0.064OHM PIME051E-SM CRITICAL SOD-123W PMEG4030ER 402 0.5 MF 1% 1/16W 20% 6.3V CRITICAL 4.7UF 402 X5R-CERM1 6.3V CRITICAL X5R 10% 2.2UF 402 6.3V CRITICAL X5R 10% 2.2UF 402 20% 6.3V CRITICAL CERM-X5R 10UF 0402 6.3V CRITICAL X5R 10% 402 2.2UF 20% 6.3V 0.22UF 0201 X5R 6.3V CRITICAL X5R 402 2.2UF 10% 20% 6.3V CRITICAL X5R-CERM1 402 4.7UF 6.3V CRITICAL 1UF 10% CERM 402 6.3V CRITICAL X5R 402 2.2UF 10% 6.3V CRITICAL X5R 2.2UF 402 10% 6.3V CRITICAL X5R 402 2.2UF 10% 402 CERM 6.3V 10% 1UF X5R-CERM-1 6.3V 20% 22UF 603 CRITICAL X5R-CERM-1 6.3V 20% 22UF 603 CRITICAL X5R-CERM-1 6.3V 20% 22UF 603 CRITICAL X5R-CERM-1 6.3V 20% 22UF 603 CRITICAL X5R-CERM-1 6.3V 20% 22UF 603 CRITICAL X5R-CERM-1 6.3V 20% 22UF 603 CRITICAL X5R-CERM-1 6.3V 20% 22UF 603 CRITICAL X5R-CERM-1 6.3V 20% 22UF 603 CRITICAL 6.3V CERM 1UF 10% 402 6.3V CERM 1UF 10% 402 20% 6.3V X5R 0201 1UF 6.3V CERM 1UF 10% 402 6.3V X5R 0.01UF 01005 10% CRITICAL FDMC6683 MLP3.3X3.3 20% 6.3V CRITICAL 0201 X5R 1UF 6.3V CRITICAL X5R 2.2UF 10% 402 NOSTUFF TP-P55 TP-P55 NOSTUFF 20% 6.3V CRITICAL PLACEMENT_NOTE=PLACE NEAR L8225.1 TANT-1 150UF B15G 20% 6.3V CRITICAL 0402 CERM-X5R 10UF 20% 6.3V CRITICAL 10UF 0402 CERM-X5R 20% 6.3V CRITICAL 0402 CERM-X5R 10UF 20% 6.3V CRITICAL 0402 CERM-X5R 10UF 20% 6.3V CRITICAL 0402 CERM-X5R 10UF 20% 6.3V CRITICAL CERM-X5R 0402 10UF 20% 6.3V CRITICAL 0402 CERM-X5R 10UF 20% 6.3V CRITICAL CERM-X5R 0402 10UF X5R-CERM-1 6.3V 20% 22UF 603 CRITICAL 20% 6.3V CRITICAL 10UF NOSTUFF 0402-1 CERM-X5R 20% 6.3V CRITICAL CERM-X5R 0402-1 10UF NOSTUFF 20% 6.3V CRITICAL 10UF CERM-X5R 0402-1 20% 6.3V CRITICAL CERM-X5R 10UF 0402-1 201 1/20W 0 MF 5% 0402 25V X7R 0.022UF 10% NOSTUFF 201 1/20W MF 499 1% CRITICAL 2.2UH-20%-1.85A-80MOHM PST25201B-SM CRITICAL PST25201B-SM 2.2UH-20%-1.85A-80MOHM CRITICAL 2.2UH-20%-1.85A-80MOHM PST25201B-SM CRITICAL 2.2UH-20%-1.85A-80MOHM PST25201B-SM CRITICAL PST25201B-SM 2.2UH-20%-1.85A-80MOHM CRITICAL 2.2UH-20%-1.85A-80MOHM PST25201B-SM PST25201B-SM 2.2UH-20%-1.85A-80MOHM CRITICAL CRITICAL 2.2UH-20%-1.85A-80MOHM PST25201B-SM CRITICAL 2.2UH-20%-1.85A-80MOHM PST25201B-SM CRITICAL PIME101E-SM 2.2UH-20%-4A-32MOHM OMIT D1974AB TFBGA 20% 6.3V CRITICAL 603 X5R 10UF 197S0299197S0392 Y8138 RADAR:8788152? L8128 RADAR:8376462152S1452 152S1292 ? SYNC_DATE=01/13/2011 POWER: AMELIA PMU SYNC_MASTER=MADHAVI PP1V2_S2R MIN_LINE_WIDTH=0.25 MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.20 MM BUCK5_FB PP3V3_OUT MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM BUCK3_FB NET_SPACING_TYPE=PWR PP3V0_IO PP1V2_SOC PP2V85_CAM PP1V2_S2R PP1V8_S2R VOLTAGE=6.0V MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR PPVBUS_USB_DCIN PPVCC_MAIN PPBATT_VCC VOLTAGE=4.6V MIN_NECK_WIDTH=0.20MM MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.30MM PMU_VPUMP PP3V3_ACC PP1V1 PP1V8_ALWAYS PP3V0_S2R_HALL PP3V0_VIDEO_BUF PP3V0_VIDEO PP3V2_LDO5 PP3V2_S2R_USBMUX PP1V7_VA_VCP PP3V0_GRAPE BATT_POS_RC VOLTAGE=4.6V MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.30MM PPVBUS_USB PP1V25_CPU PP3V0_OPTICAL BATT_SNS MIN_NECK_WIDTH=0.25 MM NET_SPACING_TYPE=PWR BUCK5_LX MIN_LINE_WIDTH=0.6 MM DIDT=TRUE NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.25 MM MIN_LINE_WIDTH=0.6 MM BUCK0_LXL DIDT=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6 MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.25 MM BUCK0_LXM MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM DIDT=TRUE BUCK4_LXL NET_SPACING_TYPE=PWR PP3V0_S2R_HALL PP1V2 DSP_SW DIDT=TRUE MIN_NECK_WIDTH=0.25 MM MIN_LINE_WIDTH=0.6 MM BUCK2_LXR NET_SPACING_TYPE=PWR BUCK2_LXM DIDT=TRUE MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.20 MM NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.25 MM BUCK2_FB PP3V0_OPTICAL PP2V85_CAM PP1V1 PP1V8_ALWAYS MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM DIDT=TRUE NET_SPACING_TYPE=PWR BUCK2_LXL NET_SPACING_TYPE=CRYSTAL PMU_EXTAL PP1V8_GRAPE PMU_VPUMP PP3V2_S2R_USBMUX PP3V3_ACC PP3V2_LDO5 PP3V0_VIDEO PP1V7_VA_VCP PP1V8_S2R NC_PMU_VBUCK0_SW0_S NC_PMU_VBUCK0_SW0_G PP1V8 NET_SPACING_TYPE=SWITCHNODE MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM SW_CHGA DIDT=TRUE DIDT=TRUE MIN_NECK_WIDTH=0.25 MM MIN_LINE_WIDTH=0.6 MM BUCK4_LXM NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.25 MM BUCK0_FB PP3V0_VIDEO_BUF PP3V0_IO PP3V0_GRAPE PPVCC_MAIN MIN_NECK_WIDTH=0.20 MM NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.25 MM BUCK4_FB MIN_NECK_WIDTH=0.25 MM DIDT=TRUE MIN_LINE_WIDTH=0.6 MM NET_SPACING_TYPE=PWR BUCK3_LXM MIN_LINE_WIDTH=0.6 MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.25 MM DIDT=TRUE BUCK3_LXL PPBATT_VCC PMU_VCENTER MIN_LINE_WIDTH=0.60MM NET_SPACING_TYPE=PWR VOLTAGE=6V MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.25MM DIDT=TRUE NC_VBUS_A_OV_L MAX_NECK_LENGTH=3 MM VOLTAGE=6.0V NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.25MM MIN_LINE_WIDTH=0.60MM PPVBUS_PROT DIDT=TRUE MIN_LINE_WIDTH=0.20MM VBUS_PROT_G NET_SPACING_TYPE=ANLG MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=ANLG MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM ACT_DIO BATT_SNS_R PMU_XTAL NET_SPACING_TYPE=CRYSTAL PP1V8_S2R PPVCC_MAIN DIDT=TRUE PP1V8_S2R C81551 2 C81541 2 C81641 2 C81631 2 C8165 1 2 C81021 2 XW8126 1 2 XW8103 1 2 XW8117 1 2 XW8113 1 2 XW8114 12 R81161 2 DZ8120 12 Q8123 5 4 1 2 3 R81301 2 C8124 1 2 C81251 2 C81351 2 C81431 2 C8142 1 2 Y8138 1 2 XW8132 1 2 L8128 1 2 D8100 1 2 R8100 12 C8148 1 2 C8146 1 2 C8145 1 2 C8144 1 2 C8149 1 2 C8169 1 2 C8153 1 2 C8152 1 2 C8151 1 2 C8150 1 2 C8167 1 2 C8168 1 2 C81361 2 C81031 2 C81081 2 C81071 2 C81181 2 C81171 2 C81211 2 C81191 2 C81201 2 C81401 2 C81391 2 C81381 2 C81411 2 C8137 1 2 Q8104 5 4 1 2 3 C81311 2 C8147 1 2 TP81331 TP81011 C8166 1 2 C81561 2 C81571 2 C81581 2 C81591 2 C81601 2 C81611 2 C81621 2 C81301 2 C81221 2 C81001 2 C81011 2 C81701 2 C81711 2 R8172 1 2 C81721 2 R8173 12 L8100 1 2 L8101 1 2 L8105 1 2 L8107 1 2 L8110 1 2 L8115 1 2 L8116 1 2 L8119 1 2 L8121 1 2 L8112 1 2 U8100 B25 D7 A11 A9 D5 A7 A6 A4 D16 A18 A16 D13 A14 A12 G3 E1 E2 F30 G30 H30 A20 A19 B21 A22 A23 A27 L2 K10 B16 B14 B18 A21 H1 H2 E29 F29 G29 H29 J29 A30 A24 A25 A26 E30 J30 A10 B10 A5 B5 A17 A13 B13 F1 F2 G1 G2 M7 M4 M6 M8 K2 M11 M5 M12 N8 N7 N3 N6 K1 N10 N4 N11 N9 N5 M10 N12 B20 B19 N1 N2 81 OF 157 10.0.0 051-8773 36 OF 48 35 36 45 45 35 45 45 353645 35 45 353645 35 36 45 35 36 45 3545 35 36 37 45 35363945 36 353645 353645 353645 353645 353645 353645 353645 353645 35364045 353645 45 445 35 45 353645 34 45 45 45 45 35 36 45 35 45 45 45 45 35 36 45 35 36 45 35 36 45 35 36 45 45 42 3545 36 35 36 45 35 36 45 35 36 45 35 36 45 35 36 40 45 35 36 45 46 46 35 45 45 45 35 36 45 35 36 45 35 36 45 35363745 45 45 45 35363945 46 45 42 353645 35363745 353645
  • 40.
    IN IN OUT IN BI IN OUT IN IN OUT OUT OUT OUT OUT IN OUT OUT OUT OUT OUT IN IN IN IN IN IN OUT OUT IN OUT OUT OUT OUT OUT OUT OUT IN IN IN IN IN IN OUT OUT SYM 1 OF4 I2C&DWI ANALOGMUXLCM/GRAPE LED RESETWDOG ANALOG BACKLIGHTTEMPERATURE REFERENCES DIGITALINPUT GPIO INPUT GPIO9 TDEV7 TDEV1 AMUX_A0 AMUX_A1 AMUX_A2 AMUX_A3 AMUX_AY AMUX_B2 AMUX_B0 WLED_LXB GPIO6 GPIO7 GPIO4 WLED5_A GPIO12 VREF VDD_RTC VDD_REF TDEV8 TDEV5 TCAL TBAT SHDN SDA SCL RESET* IRQ* KEEPACT IREF GPIO8 GPIO3 GPIO2 GPIO16 GPIO15 GPIO14 GPIO13 GPIO11 GPIO1 ADC_REF WLED6_B WLED6_A WLED5_B WLED4_B WLED4_A WLED3_B WLED3_A WLED1_B GPIO5 GPIO10 GPIO17 WLED2_B RESET_IN WLED2_A WLED1_A DWI_DO DWI_DI DWI_CK WLED_LXA LCM2_EN VLCM2 VLCM1 VLCM3 LX_BOOST_LCM LCM_FB VDD_LCM VDD_BOOST_LCM VDD_LCM_SW AMUX_B1 AMUX_BY AMUX_B3 TDEV6 TDEV4 TDEV2 TDEV3 VDD_REF_ABUTTON2 ACC_DET BUTTON1 FW_DPHP_DET DPHP BUTTON3 ACC_ID ADC_IN7 BRICK_ID ADC_IN31 VOUT_WLED_A VOUT_WLED_B OUT Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT (NOTE: 2MHZ) (TEMP1 - BOTTOM SIDE NEAR I/O FLEX CONN) DCR=106MOHM MAX CLOSE TO PMU PLACE XW AND CAP CLOSE TO PMUPLACE XW AND CAP CLOSE TO PMU PLACE XW AND CAP CLOSE TO PMU PLACE XW AND CAP CLOSE TO PMUPLACE XW AND CAP CLOSE TO PMU PLACE XW AND CAP (TEMP5 - TOP SIDE NEAR NAND) RESISTOR FOR TEMP CALIBRATION (INTERNAL PULL-DOWN) PLACEMENT NOTE: PLACE NEAR PIN K4 (PULLUP INSIDE H4P) (INTERNAL PULL-DOWN) (INTERNAL PULL-DOWN) (INTERNAL PULL-DOWN) PLACEMENT NOTE: PLACE NEAR PIN K24 (TEMP2 - BOTTOM SIDE NEAR PMU) (TEMP3 - BOTTOM SIDE NEAR H4G) DWI NAMING RELATIVE TO AP (TEMP4 - BOTTOM SIDE NEAR WIFI) DCR=106MOHM MAX (PPLED_OUT_B) (PPLED_OUT_A) (INTERNAL PULL-DOWN) USED BY ZEPHYR2. WHICH IS NOW POR(CPU1V8; PUSH-PULL) (1.8_S2R; PUSH-PULL; NO PD REQ’D PER BB TEAM) (1.8_S2R; PUSH-PULL; NO PD REQ’D PER BB TEAM) (1.8_S2R; PUSH-PULL) (INTERNAL PD; RISING EDGE SENSITIVE) (INTERNAL PD; RISING EDGE SENSITIVE) CAN’T BE USED FOR 32K CLK OUTPUT (FALLING EDGE SENSITIVE) 2.5V ALWAYS ON PU IN BMU (1.8_S2R; PUSH-PULL) EXT PD BY BB MUXES (1.8_S2R; PUSH-PULL) (INTERNAL PU TO 1.8_S2R) (TEMP6 BOTTOM SIDE NEAR BRIDGE FLEX) (INTERNAL PD; RISING EDGE SENSITIVE) (INTERNAL PU TO PP1V8_S2R; RISING EDGE SENSITIVE) NEED RADAR TO STOP GENERATING 32K CLOCK (BOTH EDGES SENSITIVE) EXT PU (WHAT SIGNALS DO YOU WANT MEASURED?) (INTERNAL PULLDOWN; TE ENABLE) I2C ADDRESS: 0111100X (0X78) X5R 10% 6.3V 0.01UF 01005 X5R 10% 6.3V 0.01UF 01005 0.1% 3.92K 402 MF 1/16W CRITICAL 6.3V 100PF CERM 5% 01005 201 1.00 MF 1% 1/20W 201 1% MF 1/20W 1.00 201 1% 1.00 1/20W MF 201 1.00 1% 1/20W MF 201 1% MF 1.00 1/20W 201 1% MF 1/20W 1.00 201 1/20W 200K 1% MF 402 CERM 1UF 10% 6.3V X5R 10% 201 6.3V 0.1UF 10% 6.3V 1000PF 01005 X5R-CERM X5R 10% 201 6.3V 0.1UF SOD882 PMEG2005AEL CRICITAL 542 542 542 510192242 510192242 5 4273045 445 27 1643 1643 1643 1643 1643 19 11 30 45 15 45 15 45 15 42 30 15 15 5 34 34 0603-1 10V X5R 10UF 20%20% 402 10V X5R-CERM 2.2UF CRITICAL 4.7UH-3.2A PIME051E-SM CRITICAL SOD-323 PMEG4010BEA CRITICAL X5R 603 20% 10V 10UF 10KOHM-1% 0201 CRITICAL 0201 10KOHM-1% CRITICAL 0201 10KOHM-1% CRITICAL 6.3V CERM 5% 100PF 01005 6.3V 5% 100PF CERM 01005 6.3V 01005 CERM 5% 100PF 6.3V 01005 5% 100PF CERM 39 5 10% 50V PLACEMENT_NOTE=PLACE NEAR U8100.K22 X7R 0.01UF 402 X5R 20% 0.22UF 0201 6.3V VLS201612E-SM 2.2UH-1.05A-0.195OHM CRICITAL 19 45 SM NOSTUFF SM NOSTUFF SM NOSTUFF SM NOSTUFF 25 201 MF 1/20W 1.00 1% 201 MF 1.00 1% 1/20W 201 1.00 MF 1/20W 1% 201 1% MF 1/20W 1.00201 1% MF 1/20W 1.00 201 1% MF 1/20W 1.00 1643 1643 1643 1643 1643 1643 CRITICAL PMEG4010BEA SOD-323 CRITICAL 4.7UH-3.2A PIME051E-SMCRITICAL X5R 603 20% 10UF 10V 1643 10% PLACEMENT_NOTE=PLACE NEAR U8100.K23 50V X7R 0.01UF 402 0201 10KOHM-1% 01005 5% 100PF CERM 6.3V 10KOHM-1% 0201 SM NOSTUFF SM NOSTUFF 6.3V 5% 100PF CERM 01005 10KOHM-1% 0201 CRITICAL X5R-CERM 35V 10% 4.7UF 0603 CRITICAL X5R-CERM 35V 10% 4.7UF 0603 CRITICAL X5R-CERM 35V 10% 4.7UF 0603 CRITICAL X5R-CERM 35V 10% 4.7UF 0603 CRITICAL X5R-CERM 35V 10% 4.7UF 0603 CRITICAL X5R-CERM 35V 10% 4.7UF 0603 CRITICAL X5R-CERM 35V 10% 4.7UF 0603 CRITICAL X5R-CERM 35V 10% 4.7UF 0603 CRITICAL 528 524 524 27 27 4 743 220K MF 01005 1/32W 5% NOSTUFF 30 1UF 10% 6.3V CERM 402 X5R 10% 6.3V 2.2UF 402 10% PLACEMENT_NOTE=PLACE NEAR U8100.K220.01UF 402 X7R 50V 10% 0.01UF 50V X7R 402 PLACEMENT_NOTE=PLACE NEAR U8100.K23 TFBGA D1974AB OMIT 18 42 SYNC_MASTER=MLB POWER: AMELIA PMU SYNC_DATE=01/14/2011 MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=6.0V PP6V0_LCM_VBOOST NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.4MM MAX_NECK_LENGTH=3 MM VOLTAGE=6.0V MAKE_BASE=TRUE PP6V0_LCM_HI LCM_LX DIDT=TRUE MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=SWITCHNODE NC_PMU_AMUX_B3 NC_PMU_AMUX_A3 NC_PMU_AMUX_A2 NC_PMU_AMUX_A1 HOME_EMI_L DP_AP_HPD ONOFF_L FW_ZENER_PWR RST_BB_PMU_L PM_BT_HOST_WAKE BATTERY_SWI RST_WLAN_L RST_BT_L PMU_ADC_REFNET_SPACING_TYPE=ANLG MIN_LINE_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM CLK_32K_PMU PM_BB_HOST_WAKE PMU_IREFNET_SPACING_TYPE=ANLG PMU_VREF NET_SPACING_TYPE=ANLG CLK_32K_WLAN PMU_VDD_REF NET_SPACING_TYPE=ANLG BOARD_TEMP2_P NET_SPACING_TYPE=ANLG BOARD_TEMP5_PNET_SPACING_TYPE=ANLG NET_SPACING_TYPE=ANLGNC_BOARD_TEMP7 NC_PMU_AMUX_AY NC_PMU_AMUX_B2 NC_PMU_AMUX_B0 PMU_VDD_RTCNET_SPACING_TYPE=ANLG NET_SPACING_TYPE=ANLGNC_BOARD_TEMP8 PMU_TCAL NET_SPACING_TYPE=ANLG BATTERY_NTC PMU_SHDWN NET_SPACING_TYPE=ANLG I2C0_SDA_1V8 I2C0_SCL_1V8 RST_AP_L IRQ_PMU_L PM_KEEPACT PM_WLAN_HOST_WAKE NC_PMU_GPIO16 IRQ_HALL RST_L63_L NC_PMU_GPIO13 DOCK_BB_EN LED_IO6_B_R MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.2 MM LED_IO4_B_R MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM LED_IO4_A_R MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.2 MM LED_IO3_B_R MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.2 MM LED_IO3_A_R MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM LED_IO1_B_R MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM AUD_MIK_HS1_INT_L LED_IO2_B_R MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.2 MM RST_PMU_IN LED_IO2_A_R MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.2 MM LED_IO1_A_R MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.2 MM DWI_AP_DI DWI_AP_DO DWI_AP_CLK NC_LCM2_EN PP5V25_VLCM2 NC_VLCM1 PPVCC_MAIN NC_PMU_AMUX_B1 NC_PMU_AMUX_BY NET_SPACING_TYPE=ANLGBOARD_TEMP6_P BOARD_TEMP4_P NET_SPACING_TYPE=ANLG PORT_DOCK_ACC_DET_L SRL_L PORT_DOCK_ACCID ADC_IN7 USB_BRICKID PPLED_OUT_B BOARD_TEMP5_N BOARD_TEMP6_N PPLED_OUT_B PPLED_OUT_A BOARD_TEMP3_N =PPVCC_MAIN_LED =PPVCC_MAIN_LED BOARD_TEMP4_N MIN_NECK_WIDTH=0.1 MM LED_IO_2_A MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM LED_IO_3_A MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM LED_IO_4_A MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM LED_IO_6_A MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM LED_IO_6_B MIN_LINE_WIDTH=0.1 MM LED_IO_3_B MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM LED_IO_1_B MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM LED_IO_2_B MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM LED_IO_1_A MIN_LINE_WIDTH=0.1 MM LED_IO_4_B MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM LED_IO_5_B MIN_LINE_WIDTH=0.1 MM NET_SPACING_TYPE=ANLG BOARD_TEMP6_P BOARD_TEMP2_N BOARD_TEMP1_N MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.2 MM LED_IO5_B_R DIDT=TRUE NET_SPACING_TYPE=SWITCHNODE MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM WLED_LX_B MIN_LINE_WIDTH=0.1 MM LED_IO_5_A MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM LED_IO6_A_R MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.2 MM LED_IO5_A_R NC_PMU_GPIO12 BOARD_TEMP5_P NET_SPACING_TYPE=ANLG BOARD_TEMP1_P NET_SPACING_TYPE=ANLG BOARD_TEMP3_P NET_SPACING_TYPE=ANLG NC_PMU_GPIO17 NC_PMU_AMUX_A0 BB_VBUS_DET MIN_NECK_WIDTH=0.25 MM DIDT=TRUE NET_SPACING_TYPE=SWITCHNODEMIN_LINE_WIDTH=0.6 MM WLED_LX_A PPLED_OUT_A C82071 2 C82061 2 R8219 1 2 C8220 1 2 R8227 1 2 R8231 1 2 R8235 1 2 R8232 1 2 R8239 1 2 R8240 1 2 R82031 2 C82091 2 C82041 2 C82141 2 C82121 2 D8230 1 2 C82371 2 C8236 1 2 L8225 1 2 D8228 1 2 C8226 1 2 R8218 1 2 R8222 1 2 R8216 1 2C8215 1 2 C8221 1 2 C8217 1 2 C8223 1 2 C8201 1 2 C82101 2 L8229 1 2 XW8203 1 2 XW8202 1 2 XW8201 1 2 XW8200 1 2 R8257 1 2 R8261 1 2 R8262 1 2 R8269 1 2 R8265 1 2 R8270 1 2 D8258 1 2 L8255 1 2 C8256 1 2 C8251 1 2 R8282 1 2C8282 1 2 R8281 1 2 XW8282 1 2 XW8281 1 2 C8281 1 2 R8280 1 2 C82631 2 C82621 2 C82641 2 C82651 2 C82321 2 C82331 2 C82341 2 C82351 2 R82601 2 C82381 2 C8240 1 2 C8266 1 2 C8267 1 2 U8100 A1 M2 M26 N27 K9 J28 H28 K26 K27 K29 G28 F28 E28 D27 D29 N28 K16 K17 J17 K18 N29 M27 M28 L29 B22 D18 D15 K21 J20 K20 J19 K19 J18 B23 B24 D21 D20 D14 D19 E16 D17 M1 B27 B28 K30 N25 M24 B29 B30 C29 D30 A2 C30 D26 N30 M30 M29 L30 A29 A28 B26 D25 N26 M14 M25 K24 K4 M9 N14 M13 N13 K22 K23 L1 N15 N18 M15 N19 N16 M18 M16 N20 N17 M19 M17 M20 M21 N21 M23 N23 051-8773 10.0.0 82 OF 157 37 OF 48 45 45 46 46 46 46 27 37 46 46 46 46 46 46 46 43 43 43 43 43 43 43 43 43 46 35 45 46 35 36 45 46 46 37 30 353745 35 37 45 35 37 45 3537 3537 37 43 43 43 46 37 46 46 353745
  • 41.
    SYM 3 OF4 VSS_BUCK3 VSS_BUCK5 VSS_BUCK04 VSS_BUCK2 VSS_BUCK02 VSSA_BUCK2 VSS VSSA_BUCK5 VSSA_BUCK4 VSSA_BUCK3 VSSA_BUCK0 VSS VSS_WLED VSS_LCM VSS_BUCK34 VSS VSS SYM 4 OF 4 Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT TFBGA OMIT D1974AB TFBGA D1974AB OMIT SYNC_DATE=01/13/2011SYNC_MASTER=MADHAVI POWER: AMELIA VSS U8100 A3 B1 D23 D24 D4 D9 E10 E11 E12 E13 E14 E17 B2 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 B3 E3 E4 E5 E6 E7 E8 E9 F10 F11 F12 B4 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 B9 F23 F24 F25 F26 F27 C2 D10 D11 D22 A8 B8 B11 B12 B6 B7 B17 A15 B15 D1 D2 N24 M22 N22 D8 D6 E15 D12 C1 U8100 H24 H25 H26 H27 H3 H4 H5 H6 H7 H8 H9 J1 J10 J11 J12 J13 J14 J15 J16 J2 J21 J22 J23 J24 J25 J26 J27 J3 J4 J5 J6 J7 J8 J9 K11 K12 K13 K14 K15 K25 K5 K6 K7 K8 M3 F3 F4 F5 F6 F7 F8 F9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G4 G5 G6 G7 G8 G9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 051-8773 10.0.0 83 OF 157 38 OF 48
  • 42.
    OUT OUT Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT PLACE OUTSIDE OF CAN DEBUG RESET ACCESS 300 5% 1/20W MF 201 NOSTUFF 0603 RED-50MCD-20MA NOSTUFF 1% 1/20W MF 201 1.5K NOSTUFF 37 5 5% 1/20W MF 201 300 NOSTUFF DEBUG AND MISC SYNC_DATE=10/04/2010SYNC_MASTER=ALEX =PP1V8_S2R_MISC FORCE_DFU PMU_SHDWN PPBATT_VCC PWR_ON_LED R90011 2 LED9000 A K R90021 2 R90001 2 051-8773 10.0.0 90 OF 157 39 OF 48 52735 353645
  • 43.
    PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT PLATING SIZE: 1.4MM X 0.7MM DRILL SIZE: 1.1MM X 0.4MM PLATED THROUGH HOLES PROBE POINTS SL-1.1X0.4-1.4X0.7 TH-NSP SL-1.1X0.4-1.4X0.7 TH-NSP SL-1.1X0.4-1.4X0.7 TH-NSP SL-1.1X0.4-1.4X0.7 TH-NSP TH-NSP SL-1.1X0.4-1.4X0.7 TH-NSP SL-1.1X0.4-1.4X0.7 TH-NSP SL-1.1X0.4-1.4X0.7 TH-NSP SL-1.1X0.4-1.4X0.7 SL-1.1X0.4-1.4X0.7 TH-NSP FID 0P5SM1P0SQ-NSP FID 0P5SM1P0SQ-NSP FID 0P5SM1P0SQ-NSP FID 0P5SM1P0SQ-NSP FID 0P5SM1P0SQ-NSP FID 0P5SM1P0SQ-NSP TH-NSP SL-1.1X0.4-1.4X0.7 SL-1.1X0.4-1.4X0.7 TH-NSP P4MM SM P4MM SM SM P4MM P4MM SM P4MM SM P4MM SM P4MM SM P4MM SM P4MM SM SM P4MM P4MM SM P4MM SM P4MM SM P4MM SM P4MM SM P4MM SM P4MM SM P4MM SM P4MM SM SM P4MM SM P4MM P4MM SM P4MM SM P4MM SM P4MM SM P4MM SM SM P4MM SL-1.1X0.4-1.4X0.7 TH-NSP SYNC_DATE=10/04/2010 FCT/ICT TEST/BRACKETS SYNC_MASTER=ALEX Z1_BON_L<4> HSIC1_WLAN_DATA1 DDR0_DQ<14> DDR0_DQS_N<1> DDR0_DQS_P<0> AUD_SPKR_AMP1_PBUS CODEC_LINE_OUT_R AUD_SPKR_AMP2_PBUS CODEC_LINE_OUT_L DDR0_DQ<0> DDR0_DQS_N<0> HSIC1_WLAN_STB1 Z1_BON_L<5> Z1_B_ADR<2> Z1_B_ADR<1> Z1_B_ADR<0> Z1_MISO PP1V7_VA_VCP CONN_AUD_HEADSET_CHS_RET2 CONN_AUD_HEADSET_CHS_MIC2 CONN_AUD_HEADSET_DET AUD_HP1_DET_H AUD_HS_MIC2_RET AUD_HS_MIC1_HI AUD_HS_MIC1_RET AUD_HS_MIC2_HI CODEC_LINE_OUT_REF SL9306 1 SL9305 1 SL9304 1 SL9302 1 SL9310 1 SL9312 1 SL9313 1 SL9314 1 SL9315 1 SL9316 1 FID9300 1 FID9305 1 FID9304 1 FID9303 1 FID9302 1 FID9301 1 SL9300 1 SL9301 1 PP0 1 PP26 1 PP25 1 PP24 1 PP23 1 PP22 1 PP21 1 PP20 1 PP19 1 PP18 1 PP17 1 PP16 1 PP15 1 PP14 1 PP13 1 PP12 1 PP11 1 PP10 1 PP9 1 PP8 1 PP7 1 PP6 1 PP5 1 PP4 1 PP3 1 PP2 1 PP1 1 051-8773 10.0.0 93 OF 157 40 OF 48 17 18 4 15 42 8 13 44 8 13 44 8 13 44 20 19 21 20 19 21 8 13 44 8 13 44 4 15 42 17 18 17 18 17 18 17 18 17 18 35 36 45 23 24 23 24 23 24 23 22 23 22 23 22 23 22 23 19 21
  • 44.
    TABLE_BOARD_INFO VERSION ALLEGRO (MIL or MM) BOARDUNITSBOARD LAYERS BOARD AREAS TABLE_SPACING_RULE_ITEM LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM MINIMUM LINE WIDTHALLOW ROUTE ON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM MINIMUM LINE WIDTHALLOW ROUTE ON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHT TABLE_SPACING_RULE_HEAD MINIMUM LINE WIDTHALLOW ROUTE ON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM MINIMUM LINE WIDTHALLOW ROUTE ON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM MINIMUM LINE WIDTHALLOW ROUTE ON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MINIMUM LINE WIDTHALLOW ROUTE ON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM MINIMUM LINE WIDTHALLOW ROUTE ON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET TABLE_PHYSICAL_RULE_HEAD Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT 0.18 MM ~ 7 MIL 0.3 MM ~ 12 MIL SPACING CONSTRAINTS REGULAR SPACING RULES 0.125 MM ~ 5 MIL 0.140 MM ~ 5.5 MIL 0.075 MM ~ 3 MIL 0.089 MM ~ 3.5 MIL 0.102 MM ~ 4 MIL 0.114 MM ~ 4.5 MIL NOTES: 0.2 MM ~ 8 MIL 0.33 MM ~ 13 MIL 0.4 MM ~ 16 MIL 1.0 MM = 39.37 MIL 0.25 MM ~ 10 MIL 90 OHMS 50 OHMS DIFFERENTIAL PAIR PHYSICAL RULES BGA AREA PHYSICAL RULES SINGLE-ENDED PHYSICAL RULES 45 OHMS PHYSICAL CONSTRAINTS DEFAULT/BGA SPACING RULES 0.15 MM ~ 6 MIL*NOTE: ASSUMING 0.060MM DIELECTRIC THICKNESS POWER/GND SPACING RULES MISC PHYSICAL RULES POWER MISC MLB CONSTRAINTS SYNC_MASTER=MIKE CONSTRAINTS: MLB RULES SYNC_DATE=01/21/2011 0.050 MM 3.0 MM50_OHM_SE 0.050 MMISL3 Y Y 3.0 MM50_OHM_SE 0.088 MM 0.050 MMISL1,ISL12 LED 3:1_SPACING* * ANLG ** 3:1_SPACING SWITCHNODE ** SWITCHNODE GND_P1SPACINGGND ** * PWR_P1SPACING*PWR BGA_SPA* BGACLK BGA* BGA_SPA* 0.10MM0.2 MMLED 0.08 MM0.08 MM10 MMY* SPEAKER * 0.19MMY 10 MM 0.08 MM 0.08 MM0.3 MM 0.08 MM=STANDARD=STANDARD* 0.08 MMY =STANDARD1:1_DIFFPAIR Y 0.060 MMBGA_PHY * 0.060 MM =STANDARD 0.076 MM 0.075 MM 0.120 MM90_OHM_DIFF Y =STANDARD0.075 MM 0.120 MM0.072 MMISL5,ISL8 90_OHM_DIFF =STANDARDYISL3 0.051 MM 0.051 MM 0.120 MM 0.120 MM DEFAULT ?* 0.100 MM 3.0 MM45_OHM_SE * N 0.050 MM0.055 MM 45_OHM_SE 3.0 MMISL3 Y 0.055 MM 0.050 MM 3.0 MMY 0.060 MM45_OHM_SE 0.077 MMISL5,ISL8 3.0 MMY45_OHM_SE 0.060 MM0.110 MMISL1,ISL12 0.050 MM50_OHM_SE * N 3.0 MM0.050 MM 3.0 MMY50_OHM_SE 0.050 MMISL5,ISL8 0.062 MM 10.0 MM0.6MM* YGND_PH 0.075 MM YPWR * 0.6MM 0.25 MM 10.0 MM ?2:1_SPACING 0.114 MM* *3:1_SPACING ?0.171 MM * ?4:1_SPACING 0.228 MM 5:1_SPACING * ?0.285 MM ?STANDARD =DEFAULT* ?BGA_SPA * =DEFAULT 0.1 MMPWR_P1SPACING 900* SWITCHNODE 0.5 MM* 1000 1000SWITCHNODE 0.2 MMTOP,BOTTOM * 0.1 MM 950GND_P1SPACING DEFAULT =45_OHM_SE 30 MM 0 MM0 MMY* =45_OHM_SE 12.7 MM=DEFAULT* =DEFAULTY =DEFAULT =DEFAULTSTANDARD BGA BGA_PHY* 0.110 MMTOP,BOTTOM90_OHM_DIFF Y 0.085 MM 0.110 MM0.085 MM 0P5MM_SPACING * ?0.5 MM * ?2.5:1_SPACING 0.143 MM * ?1.5:1_SPACING 0.086 MM 0.080 MM ?*0P08_SPACING ?* 0.057 MM1:1_SPACING 0P64MM_SPACING 0.64 MM ?* MMNO_TYPE,BGA,BGA06-06 16.2TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM 051-8773 10.0.0 150 OF 157 41 OF 48
  • 45.
    AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM AREA_TYPESPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM ELECTRICAL_CONSTRAINT_SET ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING SPACING NET_TYPE HSIC UART PHYSICAL NET_TYPE SPACING Clock Signal Constraints NET_TYPE USB ELECTRICAL_CONSTRAINT_SET PHYSICAL NET_TYPE SPACING I2S XTAL I2C JTAG ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING PHYSICAL NET_TYPE SPACING PHYSICAL DWI PHYSICAL NET_TYPE SPACING NET_TYPE SPACINGPHYSICALELECTRICAL_CONSTRAINT_SET SPACING NET_TYPE PHYSICALELECTRICAL_CONSTRAINT_SET ELECTRICAL_CONSTRAINT_SET ELECTRICAL_CONSTRAINT_SET SPACING NET_TYPE SPI PHYSICALELECTRICAL_CONSTRAINT_SET ELECTRICAL_CONSTRAINT_SET I1 I100 I101 I102 I103 I124 I125 I128 I129 I13 I130 I131 I14 I140 I141 I142 I143 I144 I145 I146 I147 I148 I149 I15 I150 I151 I152 I153 I156 I157 I158 I159 I16 I160 I161 I162 I171 I172 I173 I174 I175 I176 I177 I178 I179 I180 I181 I182 I183 I184 I185 I186 I187 I188 I189 I190 I191 I192 I193 I194 I195 I196 I197 I198 I199 I2 I20 I200 I201 I202 I203 I204 I205 I206 I207 I208 I209 I210 I211 I212 I213 I214 I215 I216 I217 I218 I219 I221 I222 I223 I224 I225 I226 I227 I228 I229 I230 I231 I232 I233 I234 I235 I236 I237 I3 I4 I5 I6 I61 I62 I63 I7 I8 I81 I82 I83 I84 I85 I88 I89 I90 I92 I93 I94 I95 I96 I98 I99 5:1_SPACING*HSIC * SPI * 2:1_SPACING* *SPI_50S 45_OHM_SE SYNC_MASTER=MIKE SYNC_DATE=01/21/2011 CONSTRAINTS: LOW SPEED BUS 1.5:1_SPACINGI2C ** 5:1_SPACING*CLK * 2:1_SPACINGDWI ** 90_OHM_DIFF*USB_90D CLK_50S * 50_OHM_SE UART_50S 50_OHM_SE* 5:1_SPACING* *CRYSTAL * 5:1_SPACING*USB JTAG * * 2:1_SPACING * 50_OHM_SEHSIC 3:1_SPACINGUART ** I2S *I2S 2:1_SPACING I2S * 3:1_SPACING* I2S_90S 45_OHM_SE* 2:1_SPACINGUARTUART * I2C_50S 50_OHM_SE* UART3_BT_RXDUART_50S UART UART_50S UART UART3_BT_RTS_L UARTUART_50S UART3_BT_CTS_L UART1_BB_RXDUART_50S UART UART0_MUX_TXDUARTUART_50S UART0_MUX_RXDUARTUART_50S UART0_AP_RXDUARTUART_50S UART0_AP_TXDUARTUART_50S UART1_BB_CTS_LUART_50S UART UART1_BB_RTS_LUART_50S UART UART3_BT_TXDUARTUART_50S UART1_BB_TXDUARTUART_50S UART6_WLAN_TXDUARTUART_50S UART6_WLAN_RXDUART_50S UART SPISPI_50S SPI2_IPC_SRDY SPI_50S SPI SPI2_IPC_SCLK SPI2_IPC_MOSISPI_50S SPI SPI_50S SPI SPI2_IPC_MISO SPI1_GRAPE_CS_LSPI_50S SPI SPI1_GRAPE_SCLKSPI_50S SPI SPI1_GRAPE_MOSISPI_50S SPI SPI1_GRAPE_MISOSPI_50S SPI ISP_CAM_0_SDAI2CI2C_50S HSIC1_WLAN_DATA1HSIC HSIC_WLAN CLK_CAM_RF_CCLKCLK_50S CLK_CAM_FF_CCLKCLK_50S CLK_CAM_RF_RCLKCLK_50S CLK_CAM_FF_RCLKCLK_50S I2S0_ASP_MCK_RCLKCLK_50S 0P2MM_SPACINGSE_50S CLK_CAM_FF_CONN CLKCLK_50S CLK_32K_GPS CLK_32K_WLANCLK_50S CLK I2CI2C_50S ISP_CAM_0_SCL I2C1_SDA_1V8_CONNI2CI2C_50S I2C_50S I2C I2C0_SCL_1V8 I2C_50S I2C I2C2_SDA_3V0 I2C_50S I2C I2C1_SCL_1V8_CONN ISP_CAM_1_SCLI2CI2C_50S DWI_AP_CLKDWI CLK_50S CLK CLK_CAM_FF I2S_50S I2S I2S2_VSP_DIN I2S I2S2_VSP_DOUTI2S_50S I2S_50S I2S I2S3_XSP_BCLK I2S_50S I2S3_XSP_DINI2S I2S_50S I2S3_XSP_LRCKI2S I2S_50S I2S I2S3_XSP_DOUT I2SI2S_50S I2S_L63_XSP_SDOUT USB USB_DK_CON_D0_PUSB_90D USB_90D USB USB_DK_CON_D0_NCLKCLK_50S CLK_32K_PMU NC_HSIC1_STB2HSIC HSIC CLK_CAM_FF_FILTCLK_50S CLK I2S0_ASP_LRCKI2S_50S I2S I2S_50S I2S I2S0_ASP_DIN I2SI2S_50S I2S0_ASP_DOUT I2SI2S_50S I2S_L63_ASP_SDOUT I2S_50S I2S2_VSP_BCLKI2S ACC_PT_DK_CON_TXUSB_90D USB ACC_PT_DK_CON_RXUSB_90D USB USB_90D USB USB11_ACC_RX_P USB_90D USB USB_BB_D_N USBUSB_90D USB11_MUX_D0_P USBUSB_90D USB11_MUX_D0_N USBUSB_90D USB11_ACC_TX_N USBUSB_90D USB_BB_D_P NC_USB_D1_NUSB_90D USB NC_USB11_D1_PUSB_90D USB NC_USB11_D1_NUSBUSB_90D TP_WLAN_USB_DPUSBUSB_90D TP_WLAN_USB_DNUSBUSB_90D USB_GPIO_DMUSBUSB_90D USB_GPIO_DP_CONNUSB_90D USB USB_GPIO_DPUSB_90D USB USB_GPIO_DM_CONNUSBUSB_90D USB USB_UART_DM_CONNUSB_90D USB_PT_DK_CON_D_PUSBUSB_90D USB_PT_DK_CON_D_NUSBUSB_90D HSIC HSIC NC_HSIC1_DATA2 HSIC_HOST_READY_WLHSIC HSIC HSIC_HOST_RDYHSICHSIC CLK_50S CLK_CAM_RFCLK CLK_CAM_RF_FILTCLK_50S CLK JTAG_AP_TDOJTAG USBUSB_90D EXTRA_USB_D1_N USB EXTRA_USB_D1_PUSB_90D NC_USB_D1_PUSBUSB_90D HSIC0_BB_DATA1HSIC HSIC_BB NC_HSIC0_STB2HSIC HSIC USB_90D USB USB_DK_D0_P USB_90D USB USB_DK_D0_N JTAG_AP_TRST_LRST I2C_50S I2C ISP_AP_1_SDA I2C1_SDA_1V8I2C_50S I2C I2C_50S I2C I2C1_SCL_1V8 I2C_50S I2C I2C0_SDA_1V8 I2CI2C_50S I2C2_SCL_3V0 I2CI2C_50S ISP_AP_0_SCL I2C_50S I2C ISP_AP_0_SDA I2C_50S I2C ISP_AP_1_SCL I2C_50S I2C I2C2_SCL_3V0_ALS I2C_50S I2C I2C2_SDA_3V0_ALS USB_90D USB EXTRA_USB11_D1_N USB_UART_DMUSBUSB_90D ISP_CAM_1_SDAI2CI2C_50S CRYSTAL XTAL_24M_I CRYSTAL XTAL_24M_O 24M_OCRYSTAL PMU_XTALCRYSTAL PMU_EXTALCRYSTAL HSIC_WLAN_RDYHSIC HSIC HSIC0_BB_STB1HSIC HSIC_BB HSIC_WLAN HSIC1_WLAN_STB1HSIC HSIC_BB_RDYHSIC HSIC HSIC HSIC_HOST_READY_WLANHSIC NC_HSIC0_DATA2HSIC HSIC USB_90D USB EXTRA_USB11_D1_P USBUSB_90D USB_UART_DP_CONN USB USB_UART_DPUSB_90D I2S0_ASP_BCLKI2S_50S I2S I2SI2S_50S I2S2_VSP_LRCK I2SI2S_50S I2S_L63_VSP_SDOUT DWI_AP_DIDWI DWI_AP_DODWI CLK_CAM_RF_CONNCLK_50S CLK I2S0_ASP_MCKCLK_50S CLK JTAG JTAG_AP_TCK JTAG_AP_TMSJTAG JTAG JTAG_AP_TDI 051-8773 10.0.0 151 OF 157 42 OF 48 5 15 5 15 5 15 5 30 11 15 11 15 5 15 5 15 5 30 5 30 5 15 5 30 5 15 5 15 5 30 5 30 5 30 5 30 5 17 5 17 5 17 5 17 24 25 4 15 40 25 25 7 7 5 19 24 25 15 37 24 25 24 25 5 10 19 22 37 5 25 24 25 24 25 5 37 7 25 5 15 19 5 15 19 5 19 5 19 5 19 5 19 19 18 37 4 46 25 5 19 5 19 5 19 19 5 15 19 27 29 27 29 11 27 11 30 4 11 4 11 11 27 11 30 4 46 4 46 4 46 27 29 27 29 4 46 5 5 30 7 25 25 4 10 4 46 4 30 4 46 4 27 4 27 4 10 45 7 25 5 10 25 5 10 25 5 10 19 22 37 5 25 7 25 7 25 7 25 10 24 25 10 24 25 24 25 4 4 4 36 36 5 15 4 30 4 15 40 5 30 5 15 4 46 5 19 5 15 19 19 5 37 5 37 24 25 5 4 27 4 27 4 10
  • 46.
    PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD AREA_TYPESPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD MINIMUM LINE WIDTHALLOW ROUTE ON LAYER?LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT MIPI NET_TYPE SPACING ANALOG VIDEO CONSTRAINTS NET_TYPE PHYSICAL PHYSICAL NET_TYPE SPACING ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACINGPHYSICAL ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING ELECTRICAL_CONSTRAINT_SET DISPLAYPORT NET_TYPE BACKLIGHT NET_TYPE ELECTRICAL_CONSTRAINT_SET SPACING NET_TYPE PHYSICAL EMBEDDED DISPLAYPORT ELECTRICAL_CONSTRAINT_SET AUDIO/SPEAKER SPACINGELECTRICAL_CONSTRAINT_SET I213 I214 I215 I219 I220 I221 I222 I223 I224 I231 I232 I233 I311 I312 I315 I316 I342 I343 I345 I346 I347 I348 I353 I354 I355 I356 I384 I385 I386 I387 I388 I389 I390 I391 I392 I393 I394 I395 I396 I397 I398 I399 I412 I413 I414 I415 I416 I417 I418 I419 I420 I421 I422 I423 I424 I425 I426 I427 I428 I429 I430 I431 I432 I433 I434 I435 I436 I437 I438 I439 I440 I441 I442 I443 I444 I445 I446 I447 I448 I449 I450 I451 I452 I453 I454 I455 I456 I457 I458 I459 I460 I461 I462 I463 I464 I465 I466 I467 I468 I469 I470 I471 I472 I473 I474 I475 I476 I477 I478 I479 I480 I481 I482 I483 I484 I485 I486 I487 I488 I489 I490 I491 I492 I493 I494 I495 I496 I497 I498 I499 I500 I501 I502 I503 I504 I505 I506 I507 I508 I510 I511 I512 I513 I514 I515 I516 I517 I518 I519 I520 I521 I522 I523 I524 I525 I526 I527 I528 I529 I530 I531 I532 I533 I534 I535 I536 I537 I538 I539 I540 I541 I542 I543 I544 I545 SYNC_DATE=01/21/2011 CONSTRAINTS: DISPLAY/AUDIO SYNC_MASTER=MIKE 1:1_DIFFPAIR*AUDIO SPEAKER*SPEAKER 5:1_SPACING* *EDP *EDP_90D 90_OHM_DIFF 50_OHM_SE*EDP_50S 3:1_SPACINGLED ** ANALOG_VIDEO 3:1_SPACING*ANALOG_VIDEO *ANALOG_VIDEO 5:1_SPACING* 4:1_SPACINGMIPI * * * 90_OHM_DIFFDP_90D **DP 5:1_SPACING =50_OHM_SE =50_OHM_SE =STANDARDVID_50S =50_OHM_SE =STANDARDY* MIPI_90D * 90_OHM_DIFF DP_50S * 50_OHM_SE ** 3:1_SPACINGAUDIO LEDLED * AUDIOAUDIO LEFT_CH_OUT_REF AUDIOAUDIO LEFT_CH_P AUDIOAUDIO MAX983X4_L_IN_P AUDIO AUDIO AUD_HP1_MLBCON_L LED LED_IO2_A_RLEDA AUDIO AUDIO HP_L AUDIOAUDIO HP_R AUDIOAUDIO CONN_AUD_HEADSET_RIGHT AUDIOAUDIO CONN_AUD_HEADSET_LEFT AUDIO AUDIO AUD_HP1_MLBCON_R AUDIOAUDIO HSMIC_R_P AUDIOAUDIO HSMIC_R_N AUDIOAUDIO HSMIC_C_P AUDIOAUDIO HSMIC_C_N AUDIO EXT_MIC_PAUDIO AUDIOAUDIO EXT_MIC_REF AUDIOAUDIO SPKRAMP_R_OUT_P AUDIO AUDIO MAX983X4_R_IN_N SPKRAMP_R_OUT_NAUDIOAUDIO RIGHT_CH_PAUDIO AUDIO AUDIOAUDIO MAX983X4_R_IN_P RIGHT_CH_OUT_PAUDIOAUDIO RIGHT_CH_OUT_REFAUDIO AUDIO SPKRAMP_L_OUT_PAUDIOAUDIO AUDIOAUDIO SPKRAMP_L_OUT_N AUDIOAUDIO MAX983X4_L_IN_N AUDIO AUDIO LEFT_CH_OUT_P EDPEDP_90D EDP_EMI_TX_P<2> EDPEDP_90D EDP_EMI_TX_P<3> EDPEDP_90D EDP_EMI_TX_P<1> EDPEDP_90D EDP_EMI_TX_P<0> EDP_EMI_TX_N<3>EDPEDP_90D EDPEDP_90D EDP_EMI_TX_N<1> EDPEDP_90D EDP_EMI_TX_N<2> EDPEDP_90D EDP_EMI_TX_N<0> EDP EDP_EMI_AUX_PEDP_90D EDP_EMI_AUX_NEDPEDP_90D EDP_90D EDP EDP_DATA_CONN_P<0> EDPEDP_90D EDP_DATA_CONN_P<2> EDP EDP_DATA_CONN_P<1>EDP_90D EDPEDP_90D EDP_DATA_CONN_P<3> EDP_90D EDP EDP_DATA_CONN_N<3> EDP_90D EDP EDP_DATA_CONN_N<2> EDP_90D EDP EDP_DATA_CONN_N<0> EDP_90D EDP EDP_DATA_CONN_N<1> EDP_90D EDP EDP_AUX_CONN_P EDP_90D EDP EDP_AUX_CONN_N EDP_90D EDP EDP_AP_TX_P<3> EDP_90D EDP EDP_AP_TX_P<2> EDP_90D EDP EDP_AP_TX_P<1> EDP_90D EDP EDP_AP_TX_N<3> EDP_90D EDP EDP_AP_TX_P<0> EDP_90D EDP EDP_AP_TX_N<2> EDP_90D EDP_AP_TX_N<1>EDP EDP_90D EDP EDP_AP_TX_N<0> EDP_AP_HPDEDP_50S EDP EDP_90D EDP EDP_AP_AUX_P EDP EDP_AP_AUX_NEDP_90D LED_IO3_A_RLED LEDA LED_IO1_B_RLED LEDB DPDP_90D DP_PT_DK_CON_AUX_P DP_EMI_TX_P<3>DP_90D DP MIPI_90D MIPI0C_AP_DATA_P<0>MIPI0C MIPI0C MIPI0C_AP_DATA_N<1>MIPI_90D MIPI0C_CAM_DATA_P<0>CAM_100DVA3 CAM MIPI_90D MIPI1C_CAM_CLK_DEBUG_PMIPI1C MIPI_90D MIPI1C_CAM_CLK_DEBUG_NMIPI1C MIPI1C_CAM_CLK_NMIPI1CMIPI_90D MIPI0C_CAM_D0_DEBUG_PMIPI_90D MIPI0C MIPI0C_CAM_DATA_P<3>MIPI_90D MIPI0C LED_IO_6_BLED LEDB LED_IO4_B_RLED LEDB LED_IO5_A_RLED LEDA DP_90D DP DP_PT_DK_CON_TX_P<3> ANALOG_VIDEO VIDEO_EMI_Y_PRVID_50S ANALOG_VIDEOVID_50S VIDEO_PT_DK_CON_CVBS_PB ANALOG_VIDEOVID_50S VIDEO_PT_DK_CON_C_Y DP_AP_TX_N<3>DPDP_90D DP_AP_TX_P<2>DPDP_90D DP_PT_DK_CON_TX_N<1>DPDP_90D VIDEO_PT_DK_CON_CVBS_PB_RVID_50S ANALOG_VIDEO VIDEO_PT_DK_CON_C_Y_RANALOG_VIDEOVID_50S ANALOG_VIDEO VIDEO_PT_DK_CON_Y_PR_RVID_50S ANALOG_VIDEO VIDEO_PT_DK_CON_Y_PRVID_50S BUF_C_YVID_50S ANALOG_VIDEO DP_PT_DK_CON_AUX_PDP_90D DP DP_PT_DK_CON_AUX_NDP_90D DP DP_EMI_TX_N<0>DP_90D DP NC_MIPI0C_AP_DATA_N<2>MIPI_90D MIPI0C NC_MIPI0C_AP_DATA_P<2>MIPI_90D MIPI0C MIPI0CMIPI_90D MIPI0C_CAM_DATA_N<3> MIPI_90D MIPI0C_CAM_D2_DEBUG_PMIPI0C MIPI0C_CAM_D3_DEBUG_PMIPI_90D MIPI0C LED LEDB LED_IO2_B_R LEDB LED_IO3_B_RLED LED_IO5_B_RLED LEDB LED_IO6_A_RLED LEDA LED_IO4_A_RLED LEDA LEDB LED_IO_2_BLED LED_IO_3_ALED LEDA LED_IO_3_BLED LEDB LED_IO_4_BLED LEDB LED_IO_5_BLED LEDB DPDP_90D DP_PT_DK_CON_TX_N<3> DP_EMI_TX_P<1>DPDP_90D DPDP_90D DP_PT_DK_CON_TX_N<2> LED_IO1_A_RLED LEDA DAC_AP_OUT2ANALOG_VIDEOVID_50S MIPI0C_AP_CLK_NMIPI_90D MIPI0C DP_AP_TX_N<0>DP_90D DP MIPI_90D MIPI0C_AP_DATA_N<0>MIPI0C MIPI0C_CAM_DATA_N<2>MIPI0CMIPI_90D MIPI0C_CAM_D1_DEBUG_NMIPI_90D MIPI0C MIPI0C_CAM_D0_DEBUG_NMIPI0CMIPI_90D DPDP_90D DP_AP_AUX_N DP_90D DP DP_AP_AUX_P VIDEO_EMI_C_YVID_50S ANALOG_VIDEO ANALOG_VIDEOVID_50S VIDEO_EMI_CVBS_PB VID_50S ANALOG_VIDEO BUF_Y_PR ANALOG_VIDEO DAC_AP_OUT3VID_50S DP_50S DP DP_AP_HPD DAC_AP_OUT1VID_50S ANALOG_VIDEO DP_AP_TX_N<1>DP_90D DP DP_AP_TX_P<1>DP_90D DP DP_PT_DK_CON_TX_N<0>DP_90D DP DP_90D DP DP_EMI_TX_P<0> DP_EMI_AUX_NDP_90D DP DP_AP_TX_P<0>DP_90D DP DP_EMI_AUX_PDP_90D DP DP_90D DP_EMI_TX_N<2>DP DP_EMI_TX_N<3>DPDP_90D DP_EMI_AUX_PDPDP_90D DP_EMI_TX_P<2>DPDP_90D DP_90D DP DP_PT_DK_CON_TX_P<2> LEDB LED_IO6_B_RLED LEDB LED_IO_1_BLED LEDA LED_IO_1_ALED LEDA LED_IO_2_ALED LED_IO_4_ALED LEDA LED_IO_5_ALED LEDA LED_IO_6_ALED LEDA DP_EMI_AUX_NDPDP_90D DP_PT_DK_CON_TX_P<1>DPDP_90D DP_90D DP_PT_DK_CON_TX_P<0>DP DP_90D DP_EMI_TX_N<1>DP DP_AP_TX_N<2>DPDP_90D DP_90D DP_AP_TX_P<3>DP MIPI0CMIPI_90D MIPI0C_CAM_DATA_N<1> MIPI0C_CAM_DATA_P<2>MIPI_90D MIPI0C MIPI0C_CAM_DATA_P<1>MIPI0CMIPI_90D MIPI0C_AP_CLK_PMIPI_90D MIPI0C MIPI_90D MIPI1C_CAM_D0_DEBUG_NMIPI1C MIPI_90D MIPI1C_CAM_D0_DEBUG_PMIPI1C MIPI1C_CAM_CLK_PMIPI1CMIPI_90D MIPI0C_CAM_CLK_DEBUG_NMIPI_90D MIPI0C MIPI0C_CAM_CLK_DEBUG_PMIPI0CMIPI_90D MIPI0C_CAM_D1_DEBUG_PMIPI_90D MIPI0C MIPI0C_CAM_D2_DEBUG_NMIPI_90D MIPI0C MIPI0C_CAM_D3_DEBUG_NMIPI_90D MIPI0C MIPI1C MIPI1C_AP_CLK_PMIPI_90D MIPI1CMIPI_90D MIPI1C_AP_CLK_N MIPI1C_CAM_DATA_P<0>CAM_100DVGA CAM MIPI1C_CAM_DATA_N<0>CAM_100DVGA CAM DPDP_90D DP_PT_DK_CON_AUX_N BUF_CVBS_PBVID_50S ANALOG_VIDEO CAM_100DVA3 CAM MIPI0C_CAM_DATA_N<0> NC_MIPI0C_AP_DATA_P<3>MIPI0CMIPI_90D MIPI0C_AP_DATA_P<1>MIPI_90D MIPI0C NC_MIPI0C_AP_DATA_N<3>MIPI_90D MIPI0C MIPI0C_CAM_CLK_NMIPI_90D MIPI0C MIPI0C_CAM_CLK_PMIPI_90D MIPI0C NC_MIPI1C_AP_DATA_N<1>MIPI_90D MIPI1C NC_MIPI1C_AP_DATA_P<1>MIPI_90D MIPI1C MIPI1C MIPI1C_AP_DATA_N<0>MIPI_90D MIPI1C MIPI1C_AP_DATA_P<0>MIPI_90D 051-8773 10.0.0 152 OF 157 43 OF 48 19 20 20 20 21 23 37 19 21 19 21 23 24 23 24 21 23 22 22 19 22 19 22 19 22 19 22 20 20 20 20 20 19 20 19 20 20 20 20 19 20 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 7 16 7 16 7 16 7 16 7 16 7 16 7 16 7 16 7 16 7 16 7 16 37 37 27 29 43 7 25 7 25 24 25 24 25 16 37 37 37 28 10 11 27 27 28 27 28 7 28 7 28 27 29 28 29 28 29 28 29 27 28 11 27 29 43 27 29 43 27 28 7 46 7 46 37 37 37 37 37 16 37 16 37 16 37 16 37 16 37 28 27 28 28 37 7 11 7 25 7 28 7 25 7 28 7 28 10 11 27 10 11 27 11 7 11 7 37 7 11 7 28 7 28 27 29 27 28 27 28 43 7 28 27 28 43 27 28 43 28 37 16 37 16 37 16 37 16 37 16 37 16 37 27 28 43 27 29 27 29 27 28 7 28 7 28 24 25 24 25 7 25 24 25 7 25 7 25 24 25 24 25 27 29 43 11 24 25 7 46 7 25 7 46 24 25 24 25 7 46 7 46 7 25 7 25
  • 47.
    AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM AREA_TYPESPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT NAND DEV NAND PHYSICALELECTRICAL_CONSTRAINT_SET NET_TYPE SPACING DDR DDR VREF PHYSICAL SPACING NET_TYPE ELECTRICAL_CONSTRAINT_SET ELECTRICAL_CONSTRAINT_SET PHYSICAL NET_TYPE SPACING NET_TYPE PHYSICAL SPACING ELECTRICAL_CONSTRAINT_SET I100 I101 I102 I103 I104 I105 I106 I107 I108 I109 I110 I111 I112 I113 I114 I115 I116 I117 I118 I119 I120 I121 I122 I123 I124 I125 I126 I127 I128 I129 I130 I131 I132 I133 I134 I135 I136 I137 I138 I139 I140 I141 I142 I143 I144 I145 I146 I147 I148 I149 I150 I151 I152 I153 I154 I155 I156 I157 I158 I159 I160 I161 I162 I163 I164 I165 I166 I167 I168 I169 I170 I171 I172 I173 I174 I175 I176 I177 I178 I179 I180 I181 I182 I183 I184 I185 I186 I188 I189 I190 I191 I192 I193 I194 I195 I196 I197 I198 I199 I200 I201 I202 I203 I204 I205 I206 I208 I209 I210 I211 I212 I213 I214 I215 I216 I217 I218 I219 I220 I221 I222 I223 I224 I225 I226 I228 I229 I230 I231 I232 I233 I234 I235 I236 I237 I238 I239 I240 I37 I38 I39 I41 I43 I44 I47 I48 I49 I50 I51 I52 I53 I54 I55 I56 I57 I58 I59 I60 I61 I62 I63 I64 I65 I66 I67 I68 I69 I70 I71 I72 I73 I74 I75 I76 I77 I78 I79 I80 I81 I82 I83 I84 I85 I86 I87 I88 I89 I90 I91 I92 I93 I94 I95 I96 I97 I98 I99 SYNC_MASTER=MIKE SYNC_DATE=01/21/2011 CONSTRAINTS: DDR/FMI DDR_50S * 50_OHM_SE 50_OHM_SE*NAND_50S 2:1_SPACING**NAND **VREF 5:1_SPACING 3:1_SPACING**DDR * 90_OHM_DIFFDDR_90D FMI0_RE_PNAND_50S NAND0 FMI1_RE_PNAND_50S NAND1 NAND_50S FMI0_RB0_LNAND0 FMI0_RB1_LNAND_50S NAND0 FMI0_WE_LNAND_50S NAND0 FMI0_WP_LNAND_50S NAND0 NAND1 FMI1_AD<2>NAND_50S FMI1_AD<3>NAND_50S NAND1 NAND_50S FMI1_AD<1>NAND1 DDR_50S DDR DDR1_ZQ DDRDDR_50S DDR1_CSN<2..0> DDR_50S DDR DDR1_CKE<1..0> DDR_90D DDR DDR1_CK_P DDR_50S DDR0_DQ<31..24>DDR3 DDRDDR_50S DDR1_DM<3..0> DDR_50S DDR1_DQ<7..0>DDR0 FMI0_AD<0>NAND_50S NAND0 FMI0_AD<2>NAND_50S NAND0 FMI0_AD<1>NAND_50S NAND0 FMI0_ALENAND_50S NAND0 NAND_50S FMI0_AD<7>NAND0 FMI0_AD<6>NAND_50S NAND0 FMI0_CE1_LNAND_50S NAND0 FMI1_WE_LNAND_50S NAND1 FMI1_ALENAND_50S NAND1 FMI1_WP_LNAND_50S NAND1 FMI1_AD<4>NAND_50S NAND1 FMI1_AD<5>NAND_50S NAND1 FMI1_AD<7>NAND_50S NAND1 FMI1_CE0_LNAND_50S NAND1 FMI1_ALENAND_50S NAND1 FMI1_CE2_LNAND_50S NAND1 FMI1_CE3_LNAND_50S NAND1 FMI1_CE5_LNAND_50S NAND1 NAND_50S FMI1_CE6_LNAND1 FMI1_DQS_NNAND_50S NAND1 NAND_50S FMI1_AD<0>NAND1 FMI0_CE3_LNAND_50S NAND0 FMI0_CE2_LNAND_50S NAND0 FMI0_CE5_LNAND_50S NAND0 FMI0_CE4_LNAND_50S NAND0 FMI0_CE6_LNAND_50S NAND0 FMI1_CE1_LNAND_50S NAND1 FMI1_CLENAND_50S NAND1 NAND_50S SLOT0_FMI0_AD<0>NAND0 NAND_50S SLOT0_FMI0_AD<1>NAND0 NAND_50S SLOT0_FMI0_AD<2>NAND0 NAND_50S SLOT0_FMI0_AD<3>NAND0 NAND_50S SLOT0_FMI0_AD<4>NAND0 NAND_50S SLOT0_FMI0_AD<5>NAND0 NAND_50S SLOT0_FMI0_ALENAND0 NAND_50S SLOT0_FMI0_CE1_LNAND0 NAND_50S SLOT0_FMI0_CE0_LNAND0 NAND_50S SLOT0_FMI0_DQS_PNAND0 NAND_50S SLOT0_FMI0_RE_NNAND0 NAND0NAND_50S SLOT0_FMI0_WE_L NAND_50S SLOT0_FMI1_AD<0>NAND1 NAND_50S SLOT0_FMI1_AD<1>NAND1 NAND_50S SLOT0_FMI1_AD<2>NAND1 NAND_50S SLOT0_FMI1_AD<3>NAND1 NAND_50S SLOT0_FMI1_AD<5>NAND1 SLOT0_FMI1_CE1_LNAND_50S NAND1 SLOT0_FMI1_CLENAND_50S NAND1 SLOT0_FMI1_RE_NNAND_50S NAND1 SLOT1_FMI0_AD<0>NAND_50S NAND0 NAND_50S SLOT1_FMI0_AD<1>NAND0 NAND_50S SLOT1_FMI0_AD<2>NAND0 NAND_50S SLOT1_FMI0_AD<3>NAND0 NAND0NAND_50S SLOT1_FMI0_AD<4> NAND_50S SLOT1_FMI0_ALENAND0 NAND_50S SLOT1_FMI0_AD<7>NAND0 NAND_50S SLOT1_FMI0_CE0_LNAND0 NAND_50S SLOT1_FMI0_CLENAND0 NAND_50S SLOT1_FMI0_WE_LNAND0 NAND_50S SLOT1_FMI1_AD<2>NAND1 NAND1NAND_50S SLOT1_FMI1_AD<1> NAND_50S SLOT1_FMI1_AD<0>NAND1 SLOT1_FMI1_AD<6>NAND_50S NAND1 NAND_50S SLOT1_FMI1_AD<5>NAND1 NAND_50S SLOT1_FMI1_ALENAND1 NAND_50S SLOT1_FMI1_AD<7>NAND1 NAND_50S SLOT1_FMI1_CE0_LNAND1 NAND_50S SLOT1_FMI1_CE1_LNAND1 NAND_50S SLOT1_FMI1_CLENAND1 NAND_50S SLOT1_FMI1_DQS_PNAND1 NAND_50S SLOT1_FMI1_WE_LNAND1 NAND_50S SLOT1_FMI1_AD<4>NAND1 SLOT1_FMI1_AD<3>NAND_50S NAND1FMI1_RE_NNAND_50S NAND1 FMI1_CLENAND_50S NAND1 FMI1_WP_LNAND_50S NAND1 FMI0_AD<5>NAND_50S NAND0 FMI0_AD<3>NAND_50S NAND0 FMI0_AD<4>NAND_50S NAND0 FMI0_RE_NNAND_50S NAND0 NAND_50S FMI0_CE7_LNAND0 NAND_50S FMI0_CLENAND0 NAND_50S FMI0_DQS_NNAND0 NAND_50S FMI0_DQS_PNAND0 FMI1_AD<6>NAND_50S NAND1 FMI1_CE4_LNAND_50S NAND1 PWR PPVREF_DDR0_CA PWR PPVREF_DDR0_DQ PWR PPVREF_DDR1_CA PWR PPVREF_DDR1_DQ DDR3_DQS_N<3>DDR_50S DDR3 DDR3_DQS_P<3>DDR_50S DDR3 DDR3_DQS_N<2>DDR_50S DDR2 DDR3_DQ<31..24>DDR_50S DDR3 DDR3_DQ<23..16>DDR_50S DDR2 DDR3_DQS_P<2>DDR_50S DDR2 DDR3_DQS_N<1>DDR_50S DDR1 DDR3_DQ<15..8>DDR_50S DDR1 DDR3_DQS_P<1>DDR_50S DDR1 DDR3_DQS_P<0>DDR_50S DDR0 DDR3_DQS_N<0>DDR_50S DDR0 DDR3_DQ<7..0>DDR_50S DDR0 DDR_50S DDR DDR3_ZQ DDR3_CSN<2..0>DDR_50S DDR DDRDDR_50S DDR3_CKE<1..0> DDR DDR3_DM<3..0>DDR_50S DDRDDR_90D DDR3_CK_N DDRDDR_90D DDR3_CK_P DDR DDR3_CA<9..0>DDR_50S DDR_50S DDR DDR2_CA<9..0> DDR_90D DDR DDR2_CK_P DDR_50S DDR DDR2_DM<3..0> DDR_50S DDR DDR2_CKE<1..0> DDRDDR_50S DDR2_ZQ DDR_50S DDR2_DQ<7..0>DDR0 DDR_50S DDR2_DQS_N<0>DDR0 DDR_50S DDR2_DQS_P<0>DDR0 DDR_50S DDR2_DQS_P<1>DDR1 DDR_50S DDR2_DQ<15..8>DDR1 DDR_50S DDR2_DQS_P<2>DDR2 DDR_50S DDR2_DQ<23..16>DDR2 DDR_50S DDR2_DQ<31..24>DDR3 DDR_50S DDR2_DQS_P<3>DDR3 DDR_50S DDR2_DQS_N<3>DDR3 DDRDDR_50S DDR1_CA<9..0> DDR_50S DDR1_DQS_N<0>DDR0 DDR_50S DDR1_DQ<15..8>DDR1 DDR_50S DDR1_DQS_N<1>DDR1 DDR_50S DDR1_DQS_P<2>DDR2 DDR_50S DDR1_DQ<23..16>DDR2 DDR_50S DDR1_DQ<31..24>DDR3 DDR_50S DDR1_DQS_P<3>DDR3 DDR_50S DDR1_DQS_N<3>DDR3 DDR_90D DDR DDR1_CK_N DDR_50S DDR1_DQS_N<2>DDR2 DDRDDR_50S DDR2_CSN<2..0> DDR_50S DDR2_DQS_N<1>DDR1 DDR_50S DDR2_DQS_N<2>DDR2 DDR_50S DDR DDR0_CSN<2..0> DDR_50S DDR0_DQS_N<0>DDR0 DDR_50S DDR0_DQS_P<1>DDR1 DDR_50S DDR0_DQ<15..8>DDR1 DDR_50S DDR0_DQS_N<1>DDR1 DDR_50S DDR0_DQS_P<3>DDR3 DDR_50S DDR0_DQS_N<3>DDR3 DDR_50S DDR0_DQS_P<0>DDR0 DDR_50S DDR0_DQ<7..0>DDR0 DDR_50S DDR DDR0_ZQ DDRDDR_50S DDR0_DM<3..0> DDRDDR_90D DDR0_CK_P DDR_50S DDR DDR0_CKE<1..0> DDRDDR_90D DDR0_CK_N DDRDDR_50S DDR0_CA<9..0> DDR_50S DDR0_DQ<23..16>DDR2 DDR_50S DDR0_DQS_P<2>DDR2 DDR_50S DDR0_DQS_N<2>DDR2 DDR_50S DDR1_DQS_P<0>DDR0 DDR_50S DDR1_DQS_P<1>DDR1 DDR_90D DDR DDR2_CK_N SLOT0_FMI1_WE_LNAND_50S NAND1 SLOT0_FMI1_ALENAND_50S NAND1 NAND1NAND_50S SLOT0_FMI1_AD<7> NAND_50S SLOT0_FMI1_AD<4>NAND1 FMI0_CE0_LNAND_50S NAND0 NAND_50S SLOT0_FMI0_AD<6>NAND0 NAND_50S SLOT0_FMI0_AD<7>NAND0 NAND_50S SLOT0_FMI0_CLENAND0 NAND1NAND_50S SLOT0_FMI1_AD<6> NAND_50S SLOT0_FMI1_CE0_LNAND1 NAND_50S SLOT0_FMI1_DQS_PNAND1 NAND_50S SLOT1_FMI0_AD<5>NAND0 NAND_50S SLOT1_FMI0_AD<6>NAND0 NAND_50S SLOT1_FMI0_CE1_LNAND0 NAND_50S SLOT1_FMI0_DQS_PNAND0FMI1_CE7_LNAND_50S NAND1 FMI1_DQS_PNAND_50S NAND1 FMI1_RB0_LNAND_50S NAND1 NAND1 FMI1_RB1_LNAND_50S FMI1_WE_LNAND_50S NAND1 FMI1_RE_LNAND_50S NAND1 NAND_50S SLOT1_FMI1_RE_NNAND1 NAND_50S SLOT1_FMI0_RE_NNAND0 051-8773 10.0.0 153 OF 157 44 OF 48 6 12 6 12 6 12 6 12 13 8 13 8 13 8 13 8 13 8 13 8 13 6 12 6 12 6 12 6 12 6 12 6 12 6 12 6 12 44 6 12 44 44 6 12 6 12 6 12 6 12 6 12 44 6 12 6 12 6 12 44 6 12 6 12 44 44 6 12 6 12 6 12 6 12 6 12 6 12 6 12 13 45 13 45 13 45 13 45 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 14 8 13 8 13 8 13 8 13 8 13 8 13 8 13 8 13 8 13 8 13 8 13 8 14 8 14 8 14 8 13 8 13 40 8 13 8 13 40 8 13 40 8 13 8 13 8 13 40 8 13 40 13 8 13 8 13 8 13 8 13 8 13 8 13 8 13 8 13 8 13 8 13 8 14 6 12 6 12 6 12 44
  • 48.
    Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_ITEM SPACING NET_TYPE PWR PHYSICALVOLTAGE SPACINGPHYSICAL NET_TYPE ELECTRICAL_CONSTRAINT_SET RST SPACING NET_TYPE PHYSICALELECTRICAL_CONSTRAINT_SET SPACING NET_TYPE PHYSICALELECTRICAL_CONSTRAINT_SET GND I1 I10 I11 I12 I13 I14 I15 I16 I165 I166 I167 I168 I169 I17 I170 I171 I172 I173 I174 I175 I176 I177 I178 I179 I18 I180 I181 I182 I183 I19 I199 I2 I20 I200 I201 I202 I203 I205 I206 I207 I21 I217 I219 I22 I220 I221 I223 I224 I225 I226 I23 I24 I25 I255 I256 I257 I258 I259 I26 I27 I28 I29 I3 I30 I31 I32 I33 I34 I35 I36 I37 I38 I39 I4 I40 I41 I42 I43 I44 I45 I46 I47 I49 I5 I50 I51 I52 I53 I54 I55 I56 I57 I58 I59 I6 I60 I61 I62 I63 I64 I65 I66 I67 I68 I69 I7 I70 I71 I72 I73 I74 I75 I76 I77 I78 I79 I8 I80 I81 I82 I83 I84 I85 I9 GNDGND_PH * PWR * PWR_PMU **PWR 3:1_SPACING * 4:1_SPACING*RST CONSTRAINTS: POWER / GND SYNC_MASTER=MIKE SYNC_DATE=01/21/2011 AGNDGND GND AGND_U3000GNDGND VOLTAGE=0V GND_PMUGNDGND VOLTAGE=0V GND_SPKR_AMP1GND GND VOLTAGE=0V GND_SPKR_AMP2GND GND VOLTAGE=0V GND_AUDIO_PT_DKGND GND GNDGNDGND VOLTAGE=0V GND_AUDIO_CODECGNDGND VOLTAGE=0V GND_AUDIO_HP_AMPGNDGND PPVREF_DDR0_DQ0.6V PP_PWR PWR 3.3V PWRPP_PWR PP3V3_S0_LCD_FERR BUCK0_LXLPWRPP_PWR PWR BUCK2_LXMPP_PWR PWRPP_PWR ACC_PT_DK_CON_PP3V33.3V VR_BOOST_SWPP_PWR PWR VR_BOOST_LPWRPP_PWR 6.0V PPVBUS_USB_DCINPWRPP_PWR 1.8V Z2_VDDCOREPP_PWR PWR 1.8V Z2_VDDANAPP_PWR PWR 1.8V Z1_1V8_OUTPWRPP_PWR 3.0V PP_PWR PWR MT_3V3_INT PP_PWR PWR MT_3V3_INT3.0V UD882_RSTRST UD881_RSTRST RST TP_WLAN_TRST_L SIMCRD_RSTRST RST_PMU_INRST RST RST_DET_L RST RST_BB_PMU_L RST_BB_LRST RST_AP_LRST RST_AP_1V8_LRST GSM_TXBURST_INDRST RST JTAG_AP_TRST_L DEBUG_RST_LRST DBG_RSTRST PPVREF_DDR0_CAPP_PWR PWR0.6V PPLED_BACK_REG_B20.4V PP_PWR PWR 4.2V PWRPWR500 PPBATT_VCC 6.0V PWRPP_PWR PP6V0_LCM_HI 6.0V PWRPP_PWR PPVBUS_USB PPLED_OUT_BPWRPP_PWR20.4V PP_PWR PWR BUCK4_FB 3.0V PWRPP_PWR PP3V0_S2R_HALL BUCK0_LXMPP_PWR PWR 1.1V PWRPP_PWR PP1V1_PL2_F PP_PWR PWR BUCK3_FB PP_PWR PWR BUCK3_LXL PP_PWR1.1V PWR PP1V1_PL4_F PP_PWR1.7V PWR PP1V7_VA_VCP 1.1V PWRPP_PWR PP1V1_PL3_F 1.1V PWRPP_PWR PP1V1_PL5_F 1.8V PP_PWR PWR PP1V8_GRAPE 1.8V PP_PWR PWR PP1V8_ALWAYS PP_PWR PWR1.2V PP1V2_S2R PWR1.25V PP_PWR PP1V25_CPU 1.1V PP_PWR PWR PP1V1_PLL_USB_F PP1V2_SOC1.2V PP_PWR PWR 3.0V PWR PP3V0_SENSOR_FLTPP_PWR 1.8V PP_PWR PWR PP1V8_SENSOR_FLT 2.85V PP_PWR PWR PP2V85_CAM 3.2V PP_PWR PP3V2_S2R_USBMUXPWR 3.2V PP_PWR PWR PP3V2_LDO5 PWR1.8V PP_PWR PP1V8_S2R PP_PWR1.8V PWR PP1V8_EDP_AVDD_AUX 3.3V PWR PP3V3_LCDVDD_SW_FPP_PWR 3.0V PP_PWR PWR PP3V0_VIDEO_BUF PPIO_NAND_H41.8V PWRPP_PWR 3.3V PP_PWR PWR PP3V3_ACC 20.4V PPLED_BACK_REG_APP_PWR PWR PWRPP_PWR3.0V PP3V0_S2R_HALL_FLT 3.0V PWR PP3V0_GRAPEPP_PWR 1.8V PWRPP_PWR PP1V8_DP_AVDD_AUX 1.1V PP_PWR PWR PP1V1_PL0_F PWRPP_PWR BUCK5_LX PWRPP_PWR BUCK4_LXL PWR PP1V1PP_PWR1.1V PWR0.6V PP_PWR PPVREF_DDR3_DQ 0.6V PWRPP_PWR PPVREF_DDR3_CA PWRPP_PWR PPVREF_DDR2_DQ_H40.6V PPVDDI_NAND_U14003.3V PP_PWR PWR DAC_AP_VREFPWRPP_PWR PP18V_R_GRAPEPP_PWR PWR18V PP18V_GRAPEPWRPP_PWR18V BATT_POS_RCPP_PWR PWR4.6V PP_PWR PWR0.6V PPVREF_DDR3_DQ_H4 PPVREF_DDR1_DQ_H4PWR0.6V PP_PWR PPVREF_DDR0_DQ_H40.6V PP_PWR PWR PPVREF_DDR1_CAPWR0.6V PP_PWR PPVREF_DDR1_DQPWR0.6V PP_PWR 0.6V PPVREF_DDR2_CAPWRPP_PWR PWR PPVREF_DDR2_DQ0.6V PP_PWR 1.1V PWRPP_PWR PP1V1_MIPID_PLL_F 1.1V PP_PWR PP1V8PWR PP_PWR PWR1.2V PP1V2 PWRPP_PWR PP0V4_MIPI0D0.4V PWRPP_PWR BUCK5_FB PWRPP_PWR BUCK4_LXM PP_PWR PWR BUCK2_LXR PWR BUCK2_LXLPP_PWR PWR BUCK2_FBPP_PWR PWRPP_PWR BUCK0_FB 1.8V Z2_3V3_1V8_INPP_PWR PWR RST BB_TRST_L 2.85V PP_PWR PWR PP2V85_CAM_FLT 3.0V PP_PWR PWR PP3V0_IO 3.0V PP_PWR PWR PP3V0_OPTICAL PP_PWR PWR PP5V25_VLCM25.25V 3.3V PP_PWR PWR PP3V3_OUT 3.0V PP_PWR PWR PP3V0_VIDEO RST_WLAN_LRST RST_L63_LRST GRAPE RST_GRAPE_L RST_BT_LRST PP_PWR PWR BUCK3_LXM 0.4V PP_PWR PWR PP0V4_MIPI1D 1.1V PWRPP_PWR PP1V1_PL1_F 1.8V PP_PWR PWR PP1V8_VDDA18_TS 6.0V PP6V0_LCM_VBOOSTPP_PWR PWR PWRPP_PWR PPVBUS_USB_PT_DK_CON5.0V 4.7V PPVCC_MAINPWRPP_PWR PWR1.8V PP_PWR PPVCCQ_NAND PWR PPVBUS_PROT6.0V PP_PWR PPLED_OUT_APP_PWR20.4V PWR 051-8773 10.0.0 154 OF 157 45 OF 48 17 20 20 21 27 19 21 19 21 22 13 44 16 36 36 27 29 17 17 35 36 18 18 18 18 45 18 45 4 37 5 30 30 37 5 30 4 27 30 37 4 5 15 30 4 10 42 13 44 16 35 36 39 37 4 36 35 37 36 35 36 36 4 36 36 4 35 36 40 4 4 35 36 35 36 35 36 35 36 4 35 36 10 24 26 24 26 35 36 35 36 35 36 35 36 7 16 35 36 6 9 35 36 16 24 26 35 36 7 4 36 36 35 36 14 14 8 12 7 17 17 36 8 8 8 13 44 13 44 14 14 4 35 36 35 36 7 36 36 36 36 36 36 18 24 26 35 36 35 36 35 37 35 36 35 36 15 37 19 37 6 17 15 37 36 7 4 5 37 27 29 35 36 37 12 36 35 37
  • 49.
    AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2 TABLE_SPACING_ASSIGNMENT_HEAD PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD AppleInc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPE TABLE_PHYSICAL_ASSIGNMENT_HEAD SNS I100 I101 I102 I104 I105 I106 I107 I108 I109 I110 I117 I118 I119 I120 I121 I122 I123 I124 I126 I127 I128 I130 I131 I132 I133 I134 I135 I136 I137 I138 I139 I140 I142 I143 I144 I145 I146 I147 I148 I150 I151 I152 I153 I154 I155 I156 I157 I159 I160 I161 I162 I163 I164 I165 I166 I168 I169 I170 I171 I173 I174 I176 I177 I179 I180 I181 I183 I184 I185 I189 I190 I191 I193 I195 I196 I198 I200 I204 I205 I207 I209 I210 I212 I213 I214 I216 I217 I218 I219 I220 I221 I222 I223 I224 I225 I226 I227 I228 I229 I230 I231 I232 I233 I234 I235 I236 I237 I238 I239 I240 I241 I242 I243 I244 I245 I48 I49 I50 I51 I52 I54 I55 I56 I57 I58 I59 I60 I61 I62 I63 I64 I65 I66 I67 I68 I69 I70 I71 I72 I73 I75 I76 I77 I79 I80 I81 I82 I83 I85 I90 I91 I92 I93 I94 I95 I96 I97 I98 I99 50_OHM_SESNS_50S * SNS_90D * 90_OHM_DIFF 3:1_SPACING**SNS SYNC_MASTER=MIKE SYNC_DATE=01/21/2011 CONSTRAINTS: DEBUG NC_MIC1_FILT_CODEC NO_TEST=TRUE NC_MIC1N_CODEC NO_TEST=TRUE NC_MIC1P_CODEC NO_TEST=TRUE NC_MIC1_BIAS_CODEC NO_TEST=TRUE NC_LINE_IN2_REF_CODEC NO_TEST=TRUE NC_LINE_IN2_CODEC NO_TEST=TRUE NC_LINE_IN1_REF_CODEC NO_TEST=TRUE NC_LINE_IN1_CODEC NO_TEST=TRUE NC_VLCM1 NO_TEST=TRUE NC_LCM2_EN NO_TEST=TRUE NC_D5702_6 NO_TEST=TRUE NC_D5701_6 NO_TEST=TRUE NC_D5700_6 NO_TEST=TRUE NC_D5703_6 NO_TEST=TRUE NC_EAROUT_AN NO_TEST=TRUE NC_EAROUT_AP NO_TEST=TRUE NC_BON_L5 NO_TEST=TRUE NC_BON_L3 NO_TEST=TRUE NC_BON_L1 NO_TEST=TRUE NC_VBUS_A_OV_L NO_TEST=TRUE NC_USB_D1_N NO_TEST=TRUE NC_PMU_AMUX_BY NO_TEST=TRUE NC_PMU_AMUX_B2 NO_TEST=TRUE NC_PMU_AMUX_B3 NO_TEST=TRUE NC_PMU_AMUX_B1 NO_TEST=TRUE NC_PMU_AMUX_B0 NO_TEST=TRUE NC_PMU_AMUX_AY NO_TEST=TRUE NC_PMU_AMUX_A3 NO_TEST=TRUE NC_PMU_AMUX_A2 NO_TEST=TRUE NC_PMU_AMUX_A1 NO_TEST=TRUE NC_PMU_AMUX_A0 NO_TEST=TRUE NC_PMU_GPIO17 NO_TEST=TRUE NC_PMU_GPIO16 NO_TEST=TRUE NC_PMU_GPIO13 NO_TEST=TRUE NC_PMU_GPIO12 NO_TEST=TRUE NET_SPACING_TYPE=ANLG NO_TEST=TRUENC_BOARD_TEMP8 NC_BOARD_TEMP7 NET_SPACING_TYPE=ANLG NO_TEST=TRUE NC_PMU_VBUCK0_SW0_S NO_TEST=TRUE NC_PMU_VBUCK0_SW0_G NO_TEST=TRUE NC_DDR3_CSN<1> NO_TEST=TRUE NC_DDR2_CSN<1> NO_TEST=TRUE NC_DDR0_CSN<1> NO_TEST=TRUE NC_DDR1_CSN<1> NO_TEST=TRUE NC_DDR3_CKE<1> NO_TEST=TRUE NC_DDR0_CKE<1> NO_TEST=TRUE NC_DDR2_CKE<1> NO_TEST=TRUE NC_DDR1_CKE<1> NO_TEST=TRUE NC_JTAG_AP_TRTCK NO_TEST=TRUE NC_USB_D1_P NO_TEST=TRUE NC_USB11_D1_P NO_TEST=TRUE NC_USB11_D1_N NO_TEST=TRUE NC_USB_ANALOGTEST0 NO_TEST=TRUE NC_USB_ANALOGTEST1 NO_TEST=TRUE NC_USB_ID0 NO_TEST=TRUE NC_USB_ID1 NO_TEST=TRUE NC_USB_BRICKID1 NO_TEST=TRUE NC_I2S1_MCK NO_TEST=TRUE NC_I2S1_BCLK NO_TEST=TRUE NC_I2S1_LRCK NO_TEST=TRUE NC_I2S1_DIN NO_TEST=TRUE NC_I2S1_DOUT NO_TEST=TRUE NC_I2S2_MCK NO_TEST=TRUE NC_I2S3_MCK NO_TEST=TRUE NC_AP_GPIO216 NO_TEST=TRUE NC_SPI_FLASH_CS_L NO_TEST=TRUE NC_SDIO0_WL_DATA<2> NO_TEST=TRUE NC_SDIO0_WL_DATA<3> NO_TEST=TRUE NC_SDIO0_WL_DATA<1> NO_TEST=TRUE NC_SDIO0_WL_CMD NO_TEST=TRUE NC_SDIO0_WL_DATA<0> NO_TEST=TRUE NC_SDIO0_WL_CLK NO_TEST=TRUE NC_SWI_AP NO_TEST=TRUE NC_SPI3_CS_L NO_TEST=TRUE NC_SPI3_MOSI NO_TEST=TRUE NC_SPI3_SCLK NO_TEST=TRUE NC_SPI3_MISO NO_TEST=TRUE NC_AP_GPIO19 NO_TEST=TRUE NC_AP_GPIO31 NO_TEST=TRUE NC_AP_GPIO35 NO_TEST=TRUE NC_BOARD_ID_3 NO_TEST=TRUE NC_AP_GPIO11 NO_TEST=TRUE NC_AP_GPIO13 NO_TEST=TRUE NC_AP_GPIO7 NO_TEST=TRUE NC_AP_GPIO8 NO_TEST=TRUE NC_AP_GPIO3 NO_TEST=TRUE NC_UART4_CTS_L NO_TEST=TRUE NC_UART4_RTS_L NO_TEST=TRUE NC_UART4_RXD NO_TEST=TRUE NC_UART2_TXD NO_TEST=TRUE NC_UART2_RXD NO_TEST=TRUE NC_AP_GPIO185 NO_TEST=TRUE NC_AP_GPIO186 NO_TEST=TRUE NC_AP_GPIO3V1 NO_TEST=TRUE NC_UART6_CTSN NO_TEST=TRUE NO_TEST=TRUENC_UART6_RTSN NC_UART4_TXD NO_TEST=TRUE NO_TEST=TRUENC_HSIC0_DATA2 NC_HSIC0_STB2 NO_TEST=TRUE NC_HSIC1_DATA2 NO_TEST=TRUE NC_HSIC1_STB2 NO_TEST=TRUE NC_ISP_AP_1_PRE_FLASH NO_TEST=TRUE NC_ISP_AP_1_FLASH NO_TEST=TRUE NC_MIPI1C_AP_DATA_N<1> NO_TEST=TRUE NC_MIPI1C_AP_DATA_P<1> NO_TEST=TRUE NC_MIPI0C_AP_DATA_N<3> NO_TEST=TRUE NC_MIPI0C_AP_DATA_P<3> NO_TEST=TRUE NC_MIPI0C_AP_DATA_N<2> NO_TEST=TRUE NC_MIPI0C_AP_DATA_P<2> NO_TEST=TRUE NC_MIPI_VSYNC_H4 NO_TEST=TRUE NC_FMI3_DQS NO_TEST=TRUE NC_FMI3_RE_L NO_TEST=TRUE NC_FMI3_CLE NO_TEST=TRUE NC_FMI3_WE_L NO_TEST=TRUE NC_FMI3_ALE NO_TEST=TRUE NC_FMI3_AD<7> NO_TEST=TRUE NC_FMI3_AD<5> NO_TEST=TRUE NC_FMI3_AD<6> NO_TEST=TRUE NC_FMI3_AD<3> NO_TEST=TRUE NC_FMI3_AD<4> NO_TEST=TRUE NC_FMI3_AD<2> NO_TEST=TRUE NC_FMI3_AD<1> NO_TEST=TRUE NC_FMI3_AD<0> NO_TEST=TRUE NC_FMI3_CE7_L NO_TEST=TRUE NC_FMI3_CE6_L NO_TEST=TRUE NC_FMI3_CE4_L NO_TEST=TRUE NC_FMI3_CE5_L NO_TEST=TRUE NC_FMI3_CE2_L NO_TEST=TRUE NC_FMI3_CE3_L NO_TEST=TRUE NC_FMI3_CE1_L NO_TEST=TRUE NC_FMI3_CE0_L NO_TEST=TRUE NC_FMI2_DQS NO_TEST=TRUE NC_FMI2_WE_L NO_TEST=TRUE NC_FMI2_RE_L NO_TEST=TRUE NC_FMI2_ALE NO_TEST=TRUE NC_FMI2_CLE NO_TEST=TRUE NC_FMI2_AD<7> NO_TEST=TRUE NC_FMI2_AD<6> NO_TEST=TRUE NC_FMI2_AD<4> NO_TEST=TRUE NC_FMI2_AD<5> NO_TEST=TRUE NC_FMI2_AD<3> NO_TEST=TRUE NC_FMI2_AD<2> NO_TEST=TRUE NC_FMI2_AD<1> NO_TEST=TRUE NC_FMI2_AD<0> NO_TEST=TRUE NC_FMI2_CE5_L NO_TEST=TRUE NC_FMI2_CE3_L NO_TEST=TRUE NC_FMI2_CE2_L NO_TEST=TRUE NC_FMI2_CE1_L NO_TEST=TRUE NC_FMI1_CE7_L NO_TEST=TRUE NC_FMI1_CE6_L NO_TEST=TRUE NC_FMI1_CE5_L NO_TEST=TRUE NO_TEST=TRUENC_FMI1_CE4_L NC_FMI1_CE2_L NO_TEST=TRUE NC_FMI0_CE6_L NO_TEST=TRUE NC_FMI0_CE2_L NO_TEST=TRUE NC_FMI1_CE3_L NO_TEST=TRUE NC_FMI0_CE3_L NO_TEST=TRUE NC_FMI0_CE4_L NO_TEST=TRUE NC_FMI0_CE5_L NO_TEST=TRUE NC_FMI0_CE7_L NO_TEST=TRUE 051-8773 10.0.0 155 OF 157 46 OF 48 19 19 19 19 19 19 19 19 37 37 19 19 18 18 18 36 4 42 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 37 36 36 8 8 8 8 8 8 8 8 4 4 42 4 42 4 42 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 42 4 42 4 42 4 42 7 7 7 43 7 43 7 43 7 43 7 43 7 43 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
  • 50.
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    Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT FUNC TEST POINTS SYNC_DATE=01/21/2011SYNC_MASTER=MIKE 051-8773 10.0.0 157 OF 157 48 OF 48