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Minimizing power consumption is a primary consideration in hardware design of portable devices where high performance and functionality is required with limited battery power. With the scaling of technology and the need for high performance and more functionality, power dissipation becomes a major bottleneck for microprocessor systems design. Clock power can be significant in high performance systems. Dynamic power can contribute up to 50% of the total power dissipation. The main goal of this work is to implement a prototype power optimized datapath unit and ALU of Hybrid Embedded Controller Architecture targeted on to the FPGA chip and analyze the power consumption of the datapath, ALU etc. Dynamic power management system which includes clock gating, qualified system latches are incorporated into this design. The whole design is captured using VHDL make use of Xilinx tool. This paper gives complete guidelines for authors submitting papers for the AIRCC Journals.
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