The document summarizes a term project on designing a carry lookahead adder in VLSI. It discusses carry lookahead adders which improve speed over ripple carry adders by reducing the time to determine carry bits. The project includes generating schematics and layouts for 4-bit, 16-bit, and 32-bit carry lookahead adders and verifying the layout against the schematic. Simulation results will analyze carry propagation delay and worst case delay.

1. 12/17/2015 EE 4311 DESIGN OF VLSI
TERM PROJECT
Syed Salik Hafeez
UNIVERSITY OF MINNESOTA DULUTH
Shaiful Islam Swapan

2. Carry Lookahead adder
A carry-lookaheadadder (CLA) or fast adder is a type of adder usedin digital logic.A carry-lookahead
adderimprovesspeedbyreducingthe amountof time requiredtodetermine carrybits.Itcan be
contrastedwiththe simpler,butusuallyslower, ripplecarryadderforwhichthe carry bitis calculated
alongside the sumbit,andeachbit mustwaituntil the previouscarryhas beencalculatedtobegin
calculatingitsownresultandcarry bits.The carry-lookaheadaddercalculatesone ormore carry bits
before the sum,whichreducesthe waittime tocalculate the resultof the largervalue bits.
PGC Generator (Circuit)

3. PGC Generator (Symbol)
DOT (Circuit)

4. DOT (Symbol)
CLA 4-bit (Schematic)

5. CLA 16-bit (Schematic)
CLA 32-bit (Schematic)

6. CLA 16-bit (Layout)
LVS verification (Layout vs Schematic)

7. Simulation Results
1) Carry propagation delay
2) Worst delay (S31)