Presentation on VLSI circuit generation technology by Motorola Labs and JRS Research, Inc. Presented at DATE 2000 - Paris, France.

1. Circuit Generation for Creating
Architecture -Based Virtual Components
Gary L. Dare, Dan Linzmeier, Brian Deitrich
DigitalDNA Systems Architecture Lab,
Motorola Labs
Motorola, Inc.
&
Kim Whitelaw
JRS Research Laboratories Inc.
© 1999, 2000 - Motorola, Inc. DATE 2000 – Paris, France 1

2. Objectives
• Create scalable IP (intellectual property) for
reuse in System-on-chip design.
– Cycle Time Reduction/Productivity Improvement
• design once; reuse again & again …
– Improve Quality: reconfiguration of IP solely
constrained by parameters
• Reuse = scaling an instance of base architecture
• Controlled deployment
– no ad hoc modification/destruction of IP
– Develop a widely applicable methodology suited
to EDA for SoC system synthesis
• Behavioral to RTL models
• HDL, C/C++, Java
© 1999, 2000 - Motorola, Inc. DATE 2000 – Paris, France 2

3. IP Generator Architecture, Process Flow
• IP Model Template is based on a Reference Design
• IP Configuration mechanism (e.g., Java GUI)
• Conversion Program (e.g., MCT – ASDEN Project)
– Converter processes Template using Configuration input.
– A range of circuits realizable for a single architecture.
HDL
© 1999, 2000 - Motorola, Inc. DATE 2000 – Paris, France 3

4. Reference Design & IP Template
• A working reference design desired for reuse is first
identified
– Prime candidate: SoC architecture standard component
• IP Template created from Reference Design
– VHDL, Verilog, C/C++, Java
– Parameters for Design Configuration are identified
• Template HDL embedded with MCT/DRF meta-language
• MCT will only process meta-language tokens &
macros
– Base model structure otherwise untouched
– Resulting design retains original structure/organization
© 1999, 2000 - Motorola, Inc. DATE 2000 – Paris, France 4

5. MCT/DRF Token & Macro examples
• Token
SIGNAL addrBus: OUT UNSIGNED(@addrWide-1@) downto 0);
– Yields (for a 16 bit bus):
SIGNAL addrBus: OUT UNSIGNED (15 downto 0);
• Macro
@@FOR (i := 0..(N-1))
A@I@: full_adder1 PORT MAP (a@i@, b@i@, S@i@, C@I@);
@@ENDFOR
– Yields:
A0: full_adder1 PORT MAP (a0, b0, S0, C0);
A1: full_adder1 PORT MAP (a1, b1, S1, C1);
A2: full_adder1 PORT MAP (a2, b2, S2, C2);
A3: full_adder1 PORT MAP (a3, b3, S3, C3); (etc.)
© 1999, 2000 - Motorola, Inc. DATE 2000 – Paris, France 5

6. Application Results
• First Application: a standard architecture
module interface circuit
– Processor-bus interface module
• Variations in Processor Data & Address Bus Widths
• Supports multiple proprietary busses
– Defined as part of scalable multimedia research
architecture
– N SoC system bus definitions
– M processor modules
• N x M interface circuits derived from a single reference
design & template
© 1999, 2000 - Motorola, Inc. DATE 2000 – Paris, France 6

7. Conclusions & Future Work
• Initial work completed on template-based circuit
generation approach for IP reuse & cycle time
reduction.
– Single reference design leads to multiple circuit
configurations from single scalable template.
• Need EDA support in template creation
– Manual process of reference design conversion
• Expand methodology to other SoC architecture-
standard components developed at Motorola
– Create libraries of reconfigurable IP for design reuse
– Complement with other IP design, reuse methods
© 1999, 2000 - Motorola, Inc. DATE 2000 – Paris, France 7