Larry Lawler from Unicom Global presented on their experience using CICS TS v5.1. Their system includes a z114 mainframe with 1 IFL processor and 1 zIIP processor, running z/OS 1.13 as a z/VM guest with 1.5GB memory. They run 15+ CICS regions at once supporting releases from TS 3.1 to 5.1. Key points from the presentation include: CICS TS 5.1 provides 64-bit addressing support for assembler programs; control blocks like the CPE, APE, and CSECT lists are now stored in 64-bit addressable storage; and areas like the TCA and AICB saw changes in v
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SIMD extensions have been used since early 70’s in vector programming. They are mainly CPU specific and not Oracle specific. Nevertheless, they are used by Oracle and especially by In-Memory option to perform operations against Oracle In-Memory Compression Units. Oracle exploits SIMD extensions to perform data parallelism but without concurrency.
In this presentation, the data structure (vectors), CPU Registers, SIMD instructions and how they are used outside Oracle will be presented. As a consequence, we will see how the combination of both (data structure and instructions) can significantly reduce the number of operations. During this part, code samples written in C will be presented and executed to demonstrate it.
Then, a focus will be made on SIMD instructions inside Oracle and how it uses them: usage of specific libraries and Oracle kernel components that should use SIMD instructions.
The GNU Linux debugger helps us in this way to detect internal procedures usage that are based on SIMD instructions. It helps us to establish the link between SIMD instructions and Oracle operations like filters and aggregates. Then, it will be showed how SIMD instructions are involved in performance improvement.
Finally, a conclusion will be made on “why Oracle In-Memory performances would be improved in future versions”.
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The Hadoop ecosystem has improved real-time access capabilities recently, narrowing the gap with relational database technologies. However, gaps remain in the storage layer that complicate the transition to Hadoop-based architectures. In this session, the presenter will describe these gaps and discuss the tradeoffs between real-time transactional access and fast analytic performance from the perspective of storage engine internals. The session also will cover Kudu (currently in beta), the new addition to the open source Hadoop ecosystem with outof-the-box integration with Apache Spark and Apache Impala (incubating), that achieves fast scans and fast random access from a single API.
In this presentation from the DDN User Meeting at SC13, Tommy Minyard from the Texas Advanced Computing Center describes TACC's new Corral data storage system.
Watch the video presentation: http://insidehpc.com/2013/11/13/ddn-user-meeting-coming-sc13-nov-18/
This is a summary of the sessions I attended at PASS Summit 2017. Out of the week-long conference, I put together these slides to summarize the conference and present at my company. The slides are about my favorite sessions that I found had the most value. The slides included screenshotted demos I personally developed and tested alike the speakers at the conference.
ESCRITO ESTA EN ACCIÓN. LOS HERMANOS DE JOSE REGRESAN CON BENJAMÍN A EGIPTO. ...CPV
TRIPTICO ESCRITO ESTA EN ACCION QUE TRATA SOBRE LA OCASIÓN CUANDO LOS HERMANOS DE JOSE REGRASAN CON BENJAMIN A EGIPTO A ENCONTRASE CON JOSE COMO GOBERNADOR. SE ENCUENTRA EN GENESIS 43:1-34. HAY UNA ANECDOTA O ILUSTRACION CRISTIANA, ALGUNOS PENSAMIENTOS SABIOS, UN CRUCIGRAMA DE LA LECCION CON SU RESPUESTA Y UN VERSICULO PARA MEMORIZAR
Advanced High-Performance Computing Features of the OpenPOWER ISAGanesan Narayanasamy
Power ISA processors have a long history of offering superior features for HPC applications. Well known examples include POWER3, used in the ASCI White supercomputer, various PowerPC processors used in the Blue Gene family of massively parallel computers, and POWER9, present in the leading supercomputers of today, Summit and Sierra. OpenPOWER ISA has enabled open access to many of these features. IBM's most recent contribution to OpenPOWER ISA, in the form of Power ISA Version 3.1, includes the Matrix-Multiply Assist (MMA) instructions. The MMA instructions are designed to deliver additional performance both for classical high-performance computing, in the space of scientific and technical computing, and for the increasingly important space of business analytics. In addition, the Open Memory Interface (OMI), also developed by IBM, opens new levels of memory bandwidth and capacity for the most demanding applications. Our goal is to raise awareness of and interest in these new features, which we believe can lead to further research in processor architecture and programming environments. Some of the most promising application areas include graph algorithms, classical machine learning and deep learning.
Latest (storage IO) patterns for cloud-native applications OpenEBS
Applying micro service patterns to storage giving each workload its own Container Attached Storage (CAS) system. This puts the DevOps persona within full control of the storage requirements and brings data agility to k8s persistent workloads. We will go over the concept and the implementation of CAS, as well as its orchestration.
Hhm 3470 mq v8 and more recent new things for z osPete Siddall
IBM MQ for z/OS makes use of many system features and facilities to provide a very high level of availability and performance for your messages. Come along to this session to learn the detail behind all the new features and enhancements in the latest release of IBM MQ for z/OS.
SIMD extensions have been used since early 70’s in vector programming. They are mainly CPU specific and not Oracle specific. Nevertheless, they are used by Oracle and especially by In-Memory option to perform operations against Oracle In-Memory Compression Units. Oracle exploits SIMD extensions to perform data parallelism but without concurrency.
In this presentation, the data structure (vectors), CPU Registers, SIMD instructions and how they are used outside Oracle will be presented. As a consequence, we will see how the combination of both (data structure and instructions) can significantly reduce the number of operations. During this part, code samples written in C will be presented and executed to demonstrate it.
Then, a focus will be made on SIMD instructions inside Oracle and how it uses them: usage of specific libraries and Oracle kernel components that should use SIMD instructions.
The GNU Linux debugger helps us in this way to detect internal procedures usage that are based on SIMD instructions. It helps us to establish the link between SIMD instructions and Oracle operations like filters and aggregates. Then, it will be showed how SIMD instructions are involved in performance improvement.
Finally, a conclusion will be made on “why Oracle In-Memory performances would be improved in future versions”.
This presentation will help user to understand, by a bottom up analysis, how non-specific programming techniques are used by Oracle to improve performance with In-Memory Option and how the column format can benefit from this improvement.
Apache Kudu (Incubating): New Hadoop Storage for Fast Analytics on Fast Data ...Cloudera, Inc.
The Hadoop ecosystem has improved real-time access capabilities recently, narrowing the gap with relational database technologies. However, gaps remain in the storage layer that complicate the transition to Hadoop-based architectures. In this session, the presenter will describe these gaps and discuss the tradeoffs between real-time transactional access and fast analytic performance from the perspective of storage engine internals. The session also will cover Kudu (currently in beta), the new addition to the open source Hadoop ecosystem with outof-the-box integration with Apache Spark and Apache Impala (incubating), that achieves fast scans and fast random access from a single API.
In this presentation from the DDN User Meeting at SC13, Tommy Minyard from the Texas Advanced Computing Center describes TACC's new Corral data storage system.
Watch the video presentation: http://insidehpc.com/2013/11/13/ddn-user-meeting-coming-sc13-nov-18/
This is a summary of the sessions I attended at PASS Summit 2017. Out of the week-long conference, I put together these slides to summarize the conference and present at my company. The slides are about my favorite sessions that I found had the most value. The slides included screenshotted demos I personally developed and tested alike the speakers at the conference.
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for beginners, providing thorough training in areas such as SEO, digital communication marketing, and PPC training in Noida. After finishing the program, students receive the certifications recognised by top different universitie, setting a strong foundation for a successful career in digital marketing.
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Published classroom materials form the basis of syllabuses, drive teacher professional development, and have a potentially huge influence on learners, teachers and education systems. All teachers also create their own materials, whether a few sentences on a blackboard, a highly-structured fully-realised online course, or anything in between. Despite this, the knowledge and skills needed to create effective language learning materials are rarely part of teacher training, and are mostly learnt by trial and error.
Knowledge and skills frameworks, generally called competency frameworks, for ELT teachers, trainers and managers have existed for a few years now. However, until I created one for my MA dissertation, there wasn’t one drawing together what we need to know and do to be able to effectively produce language learning materials.
This webinar will introduce you to my framework, highlighting the key competencies I identified from my research. It will also show how anybody involved in language teaching (any language, not just English!), teacher training, managing schools or developing language learning materials can benefit from using the framework.
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Cics TS 5.1 user experience
1. CICS TS v5.1 User Experience
Larry Lawler
Unicom Global
Monday February 4th, 2013 - 4:30 PM
Session Number 12416
Larry.Lawler@UnicomGlobal.com
www.linkedin.com/pub/larry-lawler/18/698/877/
2. CICS TS v5.1 User Experience
• z114-M10 – L04 with 1 IFL, and 1 zIIP processor
• z/VM with an average of 10 LPARs
• z/OS 1.13 as a z/VM Guest, with 1.5Gig of memory
• 15+ CICS regions running at all times on our z/VM Guest.
We run all 5 supported CICS releases, from TS 3.1 to 5.1
• No DB2, No MQ, No IMS, Mostly VSAM datasets.
2
3. CICS TS v5.1 Beta Experience
• Installed 6 of the Beta drops, before the GM drop
• Observed 64-bit addressing support being enhanced on
each drop. Sometimes the same control block field
changed in several drops.
• Had a problem on one drop because we forgot to delete
and redefine Local and Global Catalog datasets.
3
4. CICS TS v5.1 User Experience
• CICS TS 5.1 64-bit command level Assembler
• CICS TS 5.1 Loader Domain Changes
• Other CICS TS 5.1 Control Block Changes
• Wish List
• Questions
4
6. CICS TS v5.1 64-bit Assembler
6
• CICS TS 5.1 has provided the ability to execute assembler
programs in 64-bit AMODE.
• This does not imply 64-bit RMODE is supported !
• LE assembler not supported by CICS or LE
• There is no PPT option to indicate you want 64-bit task
related storage
• If you are in 64-bit amode and you issue EXEC CICS
GETMAIN64, then CICS will give you 64-bit storage, if not
CICS with give you only 31-bit storage !
7. Using 64-bit Assembler
7
• New “stubs” are provided for 64-bit assembler: DFHEAG
and DFHEAG0 replace DFHEAI and DFHEAI0
• Currently the DFHEISTG will always be non 64-bit storage,
even though TCAPCDSA, TCAEISTG and the DFHEISTG
prefix area has been enhanced to support 64-bit chains
• CEDF screen layout doesn’t currently support displaying
64-bit addresses anyway
• SYSSTATE AMODE64=YES is required for proper
generation of 64-bit DFHEIENT and DFHECALL Macros
8. Other 64-bit assembler items
• Depending on SYSSTATE, the DFHEISTG macro’s work
area at the beginning of the area has increased in size
from x’0F8’ to a size of x’188’ or x’200’
• DFHEIENT must be coded a new way, with STATREG,
and STATIC parameters: DFHEIENT CODEREG=*,
DATAREG=(13), STATREG=(R10), STATIC=LITERALS
• STATREG= generates a LARL statement like this:
LARL R10,LITERALS Load static storage base
EXEC CICS Cmds generate: LLGT R15,=V(DFHEG1)
8
9. AMODE64 DFHEISTG
• +DFHEISTG DSECT ,
• +DFHEISA DS 18FD F4SA
• +DFHEIBP DS AD EIB pointer
• +DFHEICAP DS AD COMMAREA pointer
• +DFHEIR13 DS AD Register 13
• +DFHEIVER DS H Version
• +DFHEIV00 DS H Used by DFHECALL
• +DFHEIRS3 DS F Used by DFHECALL
• +DFHEIPL DS 64A Parameter list
• +DFHEITP1 DS A Used by DFHECALL
• +DFHEITP2 DS A Used by DFHECALL
• +DFHEITP3 DS A Used by DFHECALL
• +DFHEITP4 DS A Used by DFHECALL
• +DFHEITG1 DS AD Used by DFHECALL
• +DFHEITG2 DS AD Used by DFHECALL
• +DFHEITG3 DS AD Used by DFHECALL
• +DFHEITG4 DS AD Used by DFHECALL
• + DS 4FD Reserved
• See: http://tinyurl.com/Share2013SF-Assembler
9
10. AMODE64 DFHEIENT
• DFHEIENT CODEREG=*,STATREG=(10),EIBREG=(12),DATAREG=(13),STATIC=LITERALS
• + STMG R14,R12,8(R13) Save callers registers
• + JAS R1,DFH0020D Setup base & skip constants
• + DC AL4(DFHEIEND-DFHEISTG) Length of storage
• + DC V(DFHEAG0) Entry point
• + DC AL2(0) Version
• +DFH0020D DS 0H
• + LLGT R15,4(,R1) Load entry point
• + BASR R14,R15 Call DFHEAG0
• + LARL R10,LITERALS Load static storage base
• + USING LITERALS,10
• + LGR R13,R1
• + USING DFHEISTG,R13
• + LG DFHEIBR,DFHEIBP
• + USING DFHEIBLK,DFHEIBR
• See: http://tinyurl.com/Share2013SF-Assembler
10
11. EXEC CICS GETMAIN64
• * EXEC CICS GETMAIN64 FLENGTH(EIS_LENGTH) SET(R8)
• * SHARED CICSDATAKEY NOSUSPEND NOHANDLE
• DFHECALL =X'0C121800280000301800000000',,,, +
• (FB_4,EIS_LENGTH),(PTR8__RG,R8)
• + LA 1,DFHEIPL
• + LA 14,=X'0C121800280000301800000000'
• + SR 15,15
• + SR 0,0
• + STM 14,0,0(1)
• + SR 14,14
• + LA 15,EIS_LENGTH
• + LA 0,DFHEITG1
• + STM 14,0,12(1)
• + OI 20(1),X'80'
• + LLGT 15,=V(DFHEG1)
• + BASR 14,15
• + LG R8,DFHEITG1
• See: http://tinyurl.com/Share2013SF-Assembler
11
12. Other 64-bit assembler items
• The Epilog code generated by DFHEIRET is significantly
different than non 64-bit assembler:
• LG 13,128(,DFHEIPLR) Get Caller's save area
• SGR 1,1 Clear R1 for FREEMAIN
• LLGT 15,=V(DFHEAG0) @of 64-bit FREEMAIN Rtn.
• BASR 14,15 Free storage
• LMG 14,12,8(13) Restore callers 64bit Regs
• BR 14 Return to caller
• See: http://tinyurl.com/Share2013SF-Assembler
12
13. Wish List
• Enhance: EXEC CICS GETMAIN64 with an option to get
64-bit storage in 31-bit amode.
• Due to the massive changes to the DFHEISTG area and
the fact that we need to support multiple CICS releases,
GETMAINing 64-bit storage at PLTPI or startup time, for a
down the line EXIT or 64-bit program to use requires 2
load module versions of the same initialization program.
Even though the GETMAINing program only stores the 64-
bit address for future use.
13
15. Control Blocks Changed in TS v5.1
15
Control Blocks moved to 64-bit (VSCR)
Control block fields added, deleted, or changed
16. Some Loader Domain Control Blocks
• APE Active Program Element
• CPE Current Program Element
• CSECTL CSECT List
• LDA Loader Domain Anchor area
16
17. CICS TS v5.1 Loader
• The CICS TS Loader has been improved in TS v5.1 to
move all the CPE, APE and CSECT List control blocks into
64-bit addressable storage (31-bit VSCR)
• New CPE Chain added from the Library Resource (PLIBE)
to keep track of all programs loaded from that Library.
This is done for support of Application Bundles.
• Another major improvement to the loader domain was that
LOAD requests for Threadsafe tasks no longer have to
switch to the Loader “RO” TCB. LLACOPY and BLDL still
use the RO TCB
17
24. Remaining Topics
• Order of magnitude improvement in the Loader domain for
Threadsafe tasks, which can load their own programs
without Queuing up on the Loader TCB. Are the bulk of
your tasks still on the QR TCB?
• The single RO or Loader TCB is still used for: SAF calls,
BLDLs, LLACOPYs, NEWCOPYs, PHASEINs and QR
task LOADs!
• Are your Loader Domain Global user exits: XLDLOAD and
XLDELETE Threadsafe, so they can be driven on Multiple
TCBs ?
24
25. Wish List
• Create a new TCB for SAF/RACF requests, that is
separate from the Loader TCB
• Option when defining a “Library” resource via CEDA or
RDO to indicate you want a separate TCB for this Library.
• When defining a Program via CEDA, or EXEC CICS
Create; allow the specification of a single Library definition.
25
26. Control Blocks Changed in TS v5.1
26
• The following macros are provided in dataset:
&alias..CICSTS51.CICS.SDFHMAC
• CSA Common System Area
• (OFL) CSA Optional Features List
• TCA Task Control area (contig)
• SIT System Initialization Table
• SSA Static Storage area
• AFCB Authorized Facilities Control Block
• AICB Application Interface Control Block
• See: http://tinyurl.com/Share2013SF-Changes
30. CICS TS v5.1 User Experience
Larry Lawler
Unicom Global
Monday February 4th, 2013 - 4:30 PM
Session Number 12416
Larry.Lawler@UnicomGlobal.com
www.linkedin.com/pub/larry-lawler/18/698/877/