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![Hardware design (for logic)
module up_counter
(
out
,
enable ,
counter ,
clk
,
reset
);
output [7:0] out;
input enable, clk, reset;
reg [7:0] out;
std cell library
+ memories
always @(posedge clk)
if (reset) begin
out <= 8'b0 ;
end else if (enable) begin
out <= out + 1;
end
endmodule
+ MHz target
synthesis
source code
GDS II
place & route
Quite similar to software design](https://image.slidesharecdn.com/appsterdamchipsinsideyourphone-140122091721-phpapp02/85/Appsterdam-talk-about-the-chips-inside-your-phone-30-320.jpg)
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