SlideShare a Scribd company logo
1 of 121
Download to read offline
Workshop on
Recent Trends in VLSI & Job Opportunities
Vikas Billa
S.no Timings Topic
1. 9.30 AM – 10.00 AM Inaugural Speech
2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc..
3. 10.30 AM – 10.45 AM Networking Break
4. 10.45 AM – 11.00 AM Moore’s Law
5. 11.00 AM – 11.30 AM Chip Designing – Video Talk
6. 11.30 AM – 12.45 PM Importance of HDL
7. 12.45 PM – 1.30 PM Lunch Break
8. 1.30 PM – 2.30 PM Internet of Things
9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips
10. 3.00 PM – 3.15 PM Networking Break
11. 3.15 PM – 3.45 PM How to Write a Research paper?
12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities
13. 4.00 PM – 4.30 PM Closing Speech
KITS(S)_2015 2
Agenda
KITS(S)_2015 3
S.no Timings Topic
1. 9.30 AM – 10.00 AM Inaugural Speech
2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc..
3. 10.30 AM – 10.45 AM Networking Break
4. 10.45 AM – 11.00 AM Moore’s Law
5. 11.00 AM – 11.30 AM Chip Designing – Video Talk
6. 11.30 AM – 12.45 PM Importance of HDL
7. 12.45 PM – 1.30 PM Lunch Break
8. 1.30 PM – 2.30 PM Internet of Things
9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips
10. 3.00 PM – 3.15 PM Networking Break
11. 3.15 PM – 3.45 PM How to Write a Research paper?
12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities
13. 4.00 PM – 4.30 PM Closing Speech
KITS(S)_2015 4
Agenda 9.30 AM – 10.00 AM Inaugural Speech
S.no Timings Topic
1. 9.30 AM – 10.00 AM Inaugural Speech
2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc..
3. 10.30 AM – 10.45 AM Networking Break
4. 10.45 AM – 11.00 AM Moore’s Law
5. 11.00 AM – 11.30 AM Chip Designing – Video Talk
6. 11.30 AM – 12.45 PM Importance of HDL
7. 12.45 PM – 1.30 PM Lunch Break
8. 1.30 PM – 2.30 PM Internet of Things
9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips
10. 3.00 PM – 3.15 PM Networking Break
11. 3.15 PM – 3.45 PM How to Write a Research paper?
12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities
13. 4.00 PM – 4.30 PM Closing Speech
KITS(S)_2015 5
Agenda
10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc..
KITS(S)_2015 6
What is VLSI ..?
“Very Large Scale Integration”
SSI – Small-Scale Integration (0-102)
MSI – Medium-Scale Integration (102-103)
LSI – Large-Scale Integration (103-105)
VLSI – Very Large-Scale Integration (105-107)
ULSI – Ultra Large-Scale Integration (>=107)
KITS(S)_2015 7
VLSI Flow
KITS(S)_2015 8
ENTITY test is
port a: in bit;
end ENTITY test;
DRC
LVS
ERC
Circuit Design
Functional Design
and Logic Design
Physical Design
Physical Verification
and Signoff
Fabrication
System Specification
Architectural Design
Chip
Packaging and Testing
Chip Planning
Placement
Signal Routing
Partitioning
Timing Closure
Clock Tree Synthesis
VLSI Flow
Power IR Drop
Analysis
Hierarchical Clock
Tree Synthesis
Full Chip Power
Planning
Block-Level Optimization
Timing
Closure
150ps
skew
120ps skew
50ps
skew
50ps
skew
100ps
skew
130ps
skew
Place
Detailed Trial Route
RC Extraction
Delay Calc / STA
IPO
Full Chip
Physical
Prototype
Partition
“Tape Out Every Day”
Cool Pictures of the Pieces…
M. Courtoy, Silicon Perspective
Physical Prototype Partitioning
Block 1
Block 2
Block 3
Block-Level Timing Budgets
Block-Level Pin Assignments
M. Courtoy, Silicon Perspective
Cool Pictures of the Pieces…
Verilog/
VHDL
Library
Std., Cell.
Library
Tech file
For layout
values
Look up
Table for
timing
Tech file
For RC
Parasite
extraction
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Digital Design Flow
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Design Analysis
This is a very crucial step in digital
design where the design functionality
is stated.
Like if we are making a processor,
what type of functionality is expected??
Digital Design Flow
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Design Specification
This step involved stating in definite
terms the performance of the chip.
Like if we are making a processor,
data size, processor speed, special
functions, power etc. is clearly stated
at this point. Also somewhat it is decided,
the way to implement the design.
So, it deals with architectural part of the
design at highest level possible.
Based on these foundation , the whole
design is built
Digital Design Flow
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
HDL
Hardware Description Language is used
to run the simulations.
It is very expensive to build the entire
chip and then verify the performance of
the architecture. Imagine if after designing
a chip for a whole year, the chip fabricated,
does not come even closer to the stated
specifications.
Digital Design Flow
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
HDL (contd.)
Hardware description languages provides
a way to implement a design without going
into much architecture, simulate and verify
the design output and functionality.
For eg. rather than building a mux design
in hardware, we can write verilog code
and verify the output at higher level
of abstraction.
Examples of HDL: VHDL, Verilog HDL
Digital Design Flow
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
HDL (Contd.)
At this time we can see the design
in the form of Source Codes.
It seems more of the software
visualization of the circuit.
The simulated code is taken to
Synthesis to generate the Logic
Circuit.
Digital Design Flow
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Synthesis
Imagine the use of K-Maps and Truth
Tables to make and implement a digital
design.
If you notice, most of the digital designs
are build up of some basic elements or
components like gates, registers, counters,
adders, subtractors, comparators, RAM,
ROM etc.
It forms the fundamentals of Logic
Synthesis using EDA tools.
Digital Design Flow
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Synthesis (Contd.)
Standard Cell Library is the collection
of such building blocks which comprises
most of the digital designs.
These cell libraries are fabrication
technology specific.
Digital Design Flow
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Synthesis ( Contd.)
After the RTL simulation, the HDL,
code is taken as input by Synthesis
Tool and converted to Gate level.
At this stage that the digital design
becomes dependent on the
fabrication process.
At the end of this stage, we have
the logic circuit I.e. in terms of
gates and memories.
Digital Design Flow
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Synthesis ( Contd.)
What synthesis does is , when it
encounters a specific construct
in HDL it replaces it with the
corresponding Standard Cell
Component from the library to
build the entire design.
Like if we use a for loop , it gets
converted to counter and a
combinational circuit.
Digital Design Flow
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Synthesis ( Contd.)
The output of synthesis is a gate
level netlist.
Netlist is an ASCII file which
enlists and indicates the devices
and the interconnections
between
them.
Digital Design Flow
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Simulation
After the netlist is generated as part
of synthesis, this netlist is simulated
to verify the functionality of this
gate level implementation of design.
Till this level we just dealt with
functionality part. Now each step
onward deals with performance
part too.
Digital Design Flow
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Timing Analysis
RTL and Gate Level simulation
doesn’t take into account the physical
time delay in signal propagation from
one device to another and through
the device.
This time delay is dependent on the
fabrication process adopted.
Digital Design Flow
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Timing Analysis (Contd.)
Each component in standard cell
library is associated with some
specific delay.
Delay Lookup Tables list the
delays associated with the
components.
Delays are in the form of
rise time, fall time and turn off
time delays.
Digital Design Flow
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Timing Analysis (Contd.)
Most of the digital designs employ
concept of timing by using clocks.
This makes the circuits synchronous.
Digital Design Flow
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Timing Analysis (Contd.)
In timing analysis, using Delay
Lookup Tables, all the inputs
and outputs of components are
verified with timing introduced.
Digital Design Flow
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Place & Route
This is the actual stage where
the design implemented at
semiconductor layout level.
This the stage which really
requires more knowledge of
semiconductor physics than
digital design.
Digital Design Flow
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Place & Route (Contd.)
Semiconductor layout has to follow
certain design rules to lay devices
at semiconductor level.
These design rules are fabrication
process dependent.
The layout uses layers as p/n diffusion,
nwell, pwell, metals, via, iso etc.
Rules involving min. spacing, and
electrical relation between two layers
are known as DESIGN RULES.
Digital Design Flow
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Place & Route (Contd.)
Placement and Routing involves
laying of the devices, placing them
and making interconnection between
them, following the Design Rules.
The result is the design implemented
in the form of semiconductor layers.
Digital Design Flow
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Extraction
Once the layout is made, there always
is parasitic capacitances and resistances
associated with the design.
This is because of the compact layouts
to make the chips smaller. More you make
compact layout more will it introduce
these parasitic components. These
interferes in the functioning and
performance of the circuit in terms of
timing, speed and power consumption.
Digital Design Flow
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Extraction (Contd.)
Due to these factors it becomes very
much important to extract these devices
from layout and check the design for
performance and functionality.
Extraction would extract from the layout,
the devices formed because of junctions
of different semiconductor and metal
layers and the interconnections.
Digital Design Flow
Design Analysis
Design Specification
Synthesis
Design Implementation using HDL
Simulation
Timing Analysis
Place & Route
Extraction
Verification
Verification
Verification would either be the
tape out stage of the chip or the stage
where design is again taken back
through the same flow for
optimization or modification.
It verifies the extracted view of the
chip for performance and functionality.
Digital Design Flow
KITS(S)_2015 33
KITS(S)_2015 34
35
• ~ 70% of project development cycle: design verification
• Every approach to reduce this time has a considerable influence on economic success of a product.
• Not unusual for ~complex chip to go through multiple tape-outs before release.
Verification Costs
36
• Verification is a bottleneck in the design process:
• High cost of design debug
• designers (sometimes verification engineers = 2 * design engineers)
• time-to-market
• High cost of faulty designs (loss of life, product recall)
Importance of Verification
37
Problems found on 1st spin ICs/ASICs
43%
20%
17%14%
12%
11%
11%
10%
10% 7% 4% 3% Functional Logic Error
Analog Tuning Issue
Signal Integrity Issue
Clock Scheme ErrorReliability Issue
Uses Too
Much Power
Mixed Signal Problem
Has Path Too Slow
Has Path Too Fast
IR Drop Issues
Firmware Error
Other Problem
Source: DeepChip, Aart de Geus, Chairman & CEO of Synopsys used it during Wed, 10 Sep 2003
Boston SNUG keynote address
 Overall 61% of New ICs/ASICs Require At Least One Re-Spin
 %43 due to functional error
38
Flow of Simulation-Based Verification
design
testbench design
simulation
debug
regression
revision control
bug tracking
coverage metrics
stimulus
generation
test plan linting
• Dashed line: Components specific to sim-
based methodology (are replaced by
components in formal methodology)
2/10/03 ECE 426 - Lecture 5 39
Functional Verification Approaches
• Black box
• Verify using module I/O ports only
• No knowledge of implementation
• No access to internals
• White box
• Verify using module I/O ports and internals
• Full knowledge of implementation
• Full access to internals during simulation
• Gray box
• Verify using module I/O ports only
• Full knowledge of implementation
• No access to internals during simulation
2/10/03 ECE 426 - Lecture 5 40
Testbenches
Module Instance:
Device
Under
Verification
(DUV)
Testbench Module
KITS(S)_2015 41
S.no Timings Topic
1. 9.30 AM – 10.00 AM Inaugural Speech
2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc..
3. 10.30 AM – 10.45 AM Networking Break
4. 10.45 AM – 11.00 AM Moore’s Law
5. 11.00 AM – 11.30 AM Chip Designing – Video Talk
6. 11.30 AM – 12.45 PM Importance of HDL
7. 12.45 PM – 1.30 PM Lunch Break
8. 1.30 PM – 2.30 PM Internet of Things
9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips
10. 3.00 PM – 3.15 PM Networking Break
11. 3.15 PM – 3.45 PM How to Write a Research paper?
12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities
13. 4.00 PM – 4.30 PM Closing Speech
KITS(S)_2015 42
Agenda
10.30 AM – 10.45 AM Networking Break
KITS(S)_2015 43
S.no Timings Topic
1. 9.30 AM – 10.00 AM Inaugural Speech
2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc..
3. 10.30 AM – 10.45 AM Networking Break
4. 10.45 AM – 11.00 AM Moore’s Law
5. 11.00 AM – 11.30 AM Chip Designing – Video Talk
6. 11.30 AM – 12.45 PM Importance of HDL
7. 12.45 PM – 1.30 PM Lunch Break
8. 1.30 PM – 2.30 PM Internet of Things
9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips
10. 3.00 PM – 3.15 PM Networking Break
11. 3.15 PM – 3.45 PM How to Write a Research paper?
12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities
13. 4.00 PM – 4.30 PM Closing Speech
KITS(S)_2015 44
Agenda
10.45 AM – 11.00 AM Moore’s Law
KITS(S)_2015 45
Moore’s Law
The performance of an IC, including the number components on it, doubles every 18-24
months with the same chip price ... - Gordon Moore - 1960
KITS(S)_2015 46
Moore’s Law – It’s all about Economics
…
Moore’s Law and Technology Scaling
S.no Timings Topic
1. 9.30 AM – 10.00 AM Inaugural Speech
2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc..
3. 10.30 AM – 10.45 AM Networking Break
4. 10.45 AM – 11.00 AM Moore’s Law
5. 11.00 AM – 11.30 AM Chip Designing – Video Talk
6. 11.30 AM – 12.45 PM Importance of HDL
7. 12.45 PM – 1.30 PM Lunch Break
8. 1.30 PM – 2.30 PM Internet of Things
9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips
10. 3.00 PM – 3.15 PM Networking Break
11. 3.15 PM – 3.45 PM How to Write a Research paper?
12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities
13. 4.00 PM – 4.30 PM Closing Speech
KITS(S)_2015 48
Agenda
11.00 AM – 11.30 AM Chip Designing – Video Talk
Chip Designing – Video Talk
KITS(S)_2015 49
S.no Timings Topic
1. 9.30 AM – 10.00 AM Inaugural Speech
2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc..
3. 10.30 AM – 10.45 AM Networking Break
4. 10.45 AM – 11.00 AM Moore’s Law
5. 11.00 AM – 11.30 AM Chip Designing – Video Talk
6. 11.30 AM – 12.45 PM Importance of HDL
7. 12.45 PM – 1.30 PM Lunch Break
8. 1.30 PM – 2.30 PM Internet of Things
9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips
10. 3.00 PM – 3.15 PM Networking Break
11. 3.15 PM – 3.45 PM How to Write a Research paper?
12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities
13. 4.00 PM – 4.30 PM Closing Speech
KITS(S)_2015 50
Agenda
11.30 AM – 12.45 PM Importance of HDL
• Initially proprietary language of Gateway Design Automation Inc.around 1984
• In 1989 Cadence acquired Gateway Design Automation
• In 1990 Cadence organized Open Verilog International(OVI)
• In 1995 Verilog became a IEEE standard Ieee 1364-1995
KITS(S)_2015 51
History of Verilog
• Easier to understand than schematics
• Enables design at higher levels of abstraction
• Works on all available CAE(Computer aided Engineering ) Tools
• Provides Technology Independence
• Verilog can be coded for synthesis or simulation.
• Some constructs used for simulation can not be synthesized
• For Simulation CAE tools uses timing information defined in a Verilog model.
KITS(S)_2015 52
Importance of Verilog
Design Flow Using Verilog
KITS(S)_2015 53
Design Methodologies
Top Down Design Methodology
KITS(S)_2015 54
Bottom-Up Design Methodology
KITS(S)_2015 55
KITS(S)_2015 56
Port Declaration
KITS(S)_2015 57
Module Declaration
KITS(S)_2015 58
Simulation
Describe this In Verilog
KITS(S)_2015 59
KITS(S)_2015 60
Example 1 : Vending Machine
KITS(S)_2015 61
Example 2 : Traffic Light Controller
KITS(S)_2015 62
Example 2 : Traffic Light Controller
S.no Timings Topic
1. 9.30 AM – 10.00 AM Inaugural Speech
2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc..
3. 10.30 AM – 10.45 AM Networking Break
4. 10.45 AM – 11.00 AM Moore’s Law
5. 11.00 AM – 11.30 AM Chip Designing – Video Talk
6. 11.30 AM – 12.45 PM Importance of HDL
7. 12.45 PM – 1.30 PM Lunch Break
8. 1.30 PM – 2.30 PM Internet of Things
9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips
10. 3.00 PM – 3.15 PM Networking Break
11. 3.15 PM – 3.45 PM How to Write a Research paper?
12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities
13. 4.00 PM – 4.30 PM Closing Speech
KITS(S)_2015 63
Agenda
12.45 PM – 1.30 PM Lunch Break
S.no Timings Topic
1. 9.30 AM – 10.00 AM Inaugural Speech
2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc..
3. 10.30 AM – 10.45 AM Networking Break
4. 10.45 AM – 11.00 AM Moore’s Law
5. 11.00 AM – 11.30 AM Chip Designing – Video Talk
6. 11.30 AM – 12.45 PM Importance of HDL
7. 12.45 PM – 1.30 PM Lunch Break
8. 1.30 PM – 2.30 PM Internet of Things
9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips
10. 3.00 PM – 3.15 PM Networking Break
11. 3.15 PM – 3.45 PM How to Write a Research paper?
12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities
13. 4.00 PM – 4.30 PM Closing Speech
KITS(S)_2015 64
Agenda
1.30 PM – 2.30 PM Internet of Things
Internet of Things
KITS(S)_2015 66
KITS(S)_2015 67
68
Motion sensor
Motion sensor
Motion sensor
ECG sensor
Internet
KITS(S)_2015
People Connecting to Things
KITS(S)_2015 69
KITS(S)_2015 70
KITS(S)_2015 71
KITS(S)_2015 72
KITS(S)_2015 73
KITS(S)_2015 74
KITS(S)_2015 75
KITS(S)_2015 76
KITS(S)_2015 77
KITS(S)_2015 78
KITS(S)_2015 79
KITS(S)_2015 80
KITS(S)_2015 81
KITS(S)_2015 82
KITS(S)_2015 83
KITS(S)_2015 84
KITS(S)_2015 85
KITS(S)_2015 86
KITS(S)_2015 87
Technology Roadmap
88
Source: Siemens, http://www.siemens.com/innovation/apps/pof_microsite/_pof-fall-2012/_html_en/facts-and-forecasts-growth-market-of-the-future.html
KITS(S)_2015
Internet Connected Devices
KITS(S)_2015 89
S.no Timings Topic
1. 9.30 AM – 10.00 AM Inaugural Speech
2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc..
3. 10.30 AM – 10.45 AM Networking Break
4. 10.45 AM – 11.00 AM Moore’s Law
5. 11.00 AM – 11.30 AM Chip Designing – Video Talk
6. 11.30 AM – 12.45 PM Importance of HDL
7. 12.45 PM – 1.30 PM Lunch Break
8. 1.30 PM – 2.30 PM Internet of Things
9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips
10. 3.00 PM – 3.15 PM Networking Break
11. 3.15 PM – 3.45 PM How to Write a Research paper?
12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities
13. 4.00 PM – 4.30 PM Closing Speech
KITS(S)_2015 90
Agenda
1.30 PM – 2.30 PM Smart Device Idea Design Contest
Smart Device Idea Design Contest
S.no Timings Topic
1. 9.30 AM – 10.00 AM Inaugural Speech
2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc..
3. 10.30 AM – 10.45 AM Networking Break
4. 10.45 AM – 11.00 AM Moore’s Law
5. 11.00 AM – 11.30 AM Chip Designing – Video Talk
6. 11.30 AM – 12.45 PM Importance of HDL
7. 12.45 PM – 1.30 PM Lunch Break
8. 1.30 PM – 2.30 PM Internet of Things
9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips
10. 3.00 PM – 3.15 PM Networking Break
11. 3.15 PM – 3.45 PM How to Write a Research paper?
12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities
13. 4.00 PM – 4.30 PM Closing Speech
KITS(S)_2015 92
Agenda
2.30 PM – 3.00 PM Bio- Neuro VLSI
Bio-Neuro chips
• Carver Mead introduce the term Neuromorphic Engineering to describe a new field of
engineering whose design principles and architecture are biologically Inspired.
• Neuro“to do with neurons i.e. neutrally inspired”
• Morphic “structure or form”
KITS(S)_2015 94
Neuromorphic Engineering
• Build machines that have similar perception capabilities as human perception
• Adaptable and self organizing
• Robust to changing environments
Realisation of future “THINKING”machines
(intelligent and interactive systems)
KITS(S)_2015 95
Principles of Neuromorphic Technology
KITS(S)_2015 96
Biology
Computer science
Neuroscience
VLSI
Neuromorphic
Disciplinary Integration
KITS(S)_2015 97
Neuron Physiology
KITS(S)_2015 98
3D Retina Chip in to Human Eye
KITS(S)_2015 99
Cross-Section of Human & Artificial Retina
S.no Timings Topic
1. 9.30 AM – 10.00 AM Inaugural Speech
2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc..
3. 10.30 AM – 10.45 AM Networking Break
4. 10.45 AM – 11.00 AM Moore’s Law
5. 11.00 AM – 11.30 AM Chip Designing – Video Talk
6. 11.30 AM – 12.45 PM Importance of HDL
7. 12.45 PM – 1.30 PM Lunch Break
8. 1.30 PM – 2.30 PM Internet of Things
9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips
10. 3.00 PM – 3.15 PM Networking Break
11. 3.15 PM – 3.45 PM How to Write a Research paper?
12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities
13. 4.00 PM – 4.30 PM Closing Speech
KITS(S)_2015 100
Agenda
2.30 PM – 3.00 PM 3D chips
•There is a saying in real estate; when land get expensive, multi-storied buildings are
the alternative solution.
KITS(S)_2015 101
3D Chips
• The unprecedented growth of the computer and the information technology industry
is demanding Very Large Scale Integrated (VLSI) circuits with increasing functionality
and performance at minimum cost and power dissipation.
• Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing
interconnects delays.
• Limits of Moore’s Law?
KITS(S)_2015 102
Motivation for 3D Chips
KITS(S)_2015 103
3D Architecture
Many options available for realization of 3D circuits
Choice of Fabrication depends on requirements of Circuit System
• Wafer bonding
• Epitaxial growth
KITS(S)_2015 104
3D Fabrication Technologies
 Die to Wafer
 Wafer to Wafer
KITS(S)_2015 105
3D Artificial Retina Chip
KITS(S)_2015 106
Brain Information Processing System
• 3D VLSI can influence market only with high quality products improved quality/low cost will
sell
• Little immediate impact expected more research and small scale development needed
• expensive change of fabrication process required
• long time-to-market
KITS(S)_2015 107
Market
• 3D VLSI requires major paradigm shift in industry
• Initial participants -large capital risk to modify fabrication process
• Success of one company will require shift in industry as a whole (competition)
KITS(S)_2015 108
Impact
KITS(S)_2015 109
Fields of Application for Dream Chips
• Effective interdependence collaborations among the key areas of biology, electrical & electronics
engineering, physiology and computer science are very fundamental to develop this emerging
area.
KITS(S)_2015 110
3D VLSI Key Areas
• As the systems mature, human parts replacements would become a major application area. The
fundamental principle is by observing how biological systems perform these functions robust
artificial systems are designed.
KITS(S)_2015 111
Future
S.no Timings Topic
1. 9.30 AM – 10.00 AM Inaugural Speech
2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc..
3. 10.30 AM – 10.45 AM Networking Break
4. 10.45 AM – 11.00 AM Moore’s Law
5. 11.00 AM – 11.30 AM Chip Designing – Video Talk
6. 11.30 AM – 12.45 PM Importance of HDL
7. 12.45 PM – 1.30 PM Lunch Break
8. 1.30 PM – 2.30 PM Internet of Things
9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips
10. 3.00 PM – 3.15 PM Networking Break
11. 3.15 PM – 3.45 PM How to Write a Research paper?
12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities
13. 4.00 PM – 4.30 PM Closing Speech
KITS(S)_2015 112
Agenda
3.00 PM – 3.15 PM Networking Break
S.no Timings Topic
1. 9.30 AM – 10.00 AM Inaugural Speech
2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc..
3. 10.30 AM – 10.45 AM Networking Break
4. 10.45 AM – 11.00 AM Moore’s Law
5. 11.00 AM – 11.30 AM Chip Designing – Video Talk
6. 11.30 AM – 12.45 PM Importance of HDL
7. 12.45 PM – 1.30 PM Lunch Break
8. 1.30 PM – 2.30 PM Internet of Things
9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips
10. 3.00 PM – 3.15 PM Networking Break
11. 3.15 PM – 3.45 PM How to Write a Research paper?
12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities
13. 4.00 PM – 4.30 PM Closing Speech
KITS(S)_2015 113
Agenda
3.15 PM – 3.45 PM How to Write a Research Paper?
How to Write a Research Paper..?
S.no Timings Topic
1. 9.30 AM – 10.00 AM Inaugural Speech
2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc..
3. 10.30 AM – 10.45 AM Networking Break
4. 10.45 AM – 11.00 AM Moore’s Law
5. 11.00 AM – 11.30 AM Chip Designing – Video Talk
6. 11.30 AM – 12.45 PM Importance of HDL
7. 12.45 PM – 1.30 PM Lunch Break
8. 1.30 PM – 2.30 PM Internet of Things
9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips
10. 3.00 PM – 3.15 PM Networking Break
11. 3.15 PM – 3.45 PM How to Write a Research paper?
12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities
13. 4.00 PM – 4.30 PM Closing Speech
KITS(S)_2015 115
Agenda
3.45 PM – 4.00 PM Higher Studies & Job opportunities
Higher Studies & Job Opportunities
KITS(S)_2015 117
• If you ever tinkered with a broken radio set, you have already started.
• Academically, the right time to acquaint yourself with various specializations of Electronics is
when you are in second or third year of engineering.
When is the right time to think about VLSI ?
KITS(S)_2015 118
What Sort of Jobs does an Electronic Engineer do ?
ENTITY test is
port a: in bit;
end ENTITY test;
DRC
LVS
ERC
Circuit Design
Functional Design
and Logic Design
Physical Design
Physical Verification
and Signoff
Fabrication
System Specification
Architectural Design
Chip
Packaging and Testing
Chip Planning
Placement
Signal Routing
Partitioning
Timing Closure
Clock Tree Synthesis
S.no Timings Topic
1. 9.30 AM – 10.00 AM Inaugural Speech
2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc..
3. 10.30 AM – 10.45 AM Networking Break
4. 10.45 AM – 11.00 AM Moore’s Law
5. 11.00 AM – 11.30 AM Chip Designing – Video Talk
6. 11.30 AM – 12.45 PM Importance of HDL
7. 12.45 PM – 1.30 PM Lunch Break
8. 1.30 PM – 2.30 PM Internet of Things
9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips
10. 3.00 PM – 3.15 PM Networking Break
11. 3.15 PM – 3.45 PM How to Write a Research paper?
12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities
13. 4.00 PM – 4.30 PM Closing Speech
KITS(S)_2015 119
Agenda
4.00 PM – 4.30 PM Closing Speech
KITS(S)_2015 120
Q & A
Thank you ...121

More Related Content

Recently uploaded

CERTIFICATE TEMPLATES FOR PORTFOLIO DAYS
CERTIFICATE TEMPLATES FOR PORTFOLIO DAYSCERTIFICATE TEMPLATES FOR PORTFOLIO DAYS
CERTIFICATE TEMPLATES FOR PORTFOLIO DAYSCarloJamesSablan1
 
PORTFOLIO 2024 ANASTASIYA KUDINOVA
PORTFOLIO 2024       ANASTASIYA KUDINOVAPORTFOLIO 2024       ANASTASIYA KUDINOVA
PORTFOLIO 2024 ANASTASIYA KUDINOVAAnastasiya Kudinova
 
ALISIA: HOW MIGHT WE ACHIEVE HIGH ENVIRONMENTAL PERFORMANCE WHILE MAINTAINING...
ALISIA: HOW MIGHT WE ACHIEVE HIGH ENVIRONMENTAL PERFORMANCE WHILE MAINTAINING...ALISIA: HOW MIGHT WE ACHIEVE HIGH ENVIRONMENTAL PERFORMANCE WHILE MAINTAINING...
ALISIA: HOW MIGHT WE ACHIEVE HIGH ENVIRONMENTAL PERFORMANCE WHILE MAINTAINING...Pranav Subramanian
 
Cities Light Up in Solidarity With Ukraine: From Internationally Synchronized...
Cities Light Up in Solidarity With Ukraine: From Internationally Synchronized...Cities Light Up in Solidarity With Ukraine: From Internationally Synchronized...
Cities Light Up in Solidarity With Ukraine: From Internationally Synchronized...Thomas Schielke
 
Niintendo Wii Presentation Template.pptx
Niintendo Wii Presentation Template.pptxNiintendo Wii Presentation Template.pptx
Niintendo Wii Presentation Template.pptxKevinYaelJimnezSanti
 
eCultify brand guidelines- Shamika Dukle.pdf
eCultify brand guidelines- Shamika Dukle.pdfeCultify brand guidelines- Shamika Dukle.pdf
eCultify brand guidelines- Shamika Dukle.pdfswdukle
 
Highway LOS - Freeway-- Multilane -- highway class 2 & 3 Housam Siyoufi
Highway LOS - Freeway-- Multilane -- highway class 2 & 3 Housam SiyoufiHighway LOS - Freeway-- Multilane -- highway class 2 & 3 Housam Siyoufi
Highway LOS - Freeway-- Multilane -- highway class 2 & 3 Housam Siyoufisiyoufihoussam
 
Karim apartment ideas 02 ppppppppppppppp
Karim apartment ideas 02 pppppppppppppppKarim apartment ideas 02 ppppppppppppppp
Karim apartment ideas 02 pppppppppppppppNadaMohammed714321
 
Interior Design for Office a cura di RMG Project Studio
Interior Design for Office a cura di RMG Project StudioInterior Design for Office a cura di RMG Project Studio
Interior Design for Office a cura di RMG Project StudioRMG Project Studio
 
Unlock Canva Pro for Free Today - Canva Pro for Free.pdf
Unlock Canva Pro for Free Today - Canva Pro for Free.pdfUnlock Canva Pro for Free Today - Canva Pro for Free.pdf
Unlock Canva Pro for Free Today - Canva Pro for Free.pdfLewis John
 
Map of St. Louis Parks
Map of St. Louis Parks                              Map of St. Louis Parks
Map of St. Louis Parks CharlottePulte
 
LIGHTSCAPES: HOW MIGHT WE DESIGN AN INCLUSIVE AND ACCESSIBLE CLASSICAL CONCER...
LIGHTSCAPES: HOW MIGHT WE DESIGN AN INCLUSIVE AND ACCESSIBLE CLASSICAL CONCER...LIGHTSCAPES: HOW MIGHT WE DESIGN AN INCLUSIVE AND ACCESSIBLE CLASSICAL CONCER...
LIGHTSCAPES: HOW MIGHT WE DESIGN AN INCLUSIVE AND ACCESSIBLE CLASSICAL CONCER...Pranav Subramanian
 
simpson-lee_house_dt20ajshsjsjsjsjj15.pdf
simpson-lee_house_dt20ajshsjsjsjsjj15.pdfsimpson-lee_house_dt20ajshsjsjsjsjj15.pdf
simpson-lee_house_dt20ajshsjsjsjsjj15.pdfLucyBonelli
 
_Neighborhood Planning in Capital City of Chandigarh- An Appraisal (2) - Copy...
_Neighborhood Planning in Capital City of Chandigarh- An Appraisal (2) - Copy..._Neighborhood Planning in Capital City of Chandigarh- An Appraisal (2) - Copy...
_Neighborhood Planning in Capital City of Chandigarh- An Appraisal (2) - Copy...JIT KUMAR GUPTA
 
Exploring Tehran's Architectural Marvels: A Glimpse into Vilaas Studio's Dyna...
Exploring Tehran's Architectural Marvels: A Glimpse into Vilaas Studio's Dyna...Exploring Tehran's Architectural Marvels: A Glimpse into Vilaas Studio's Dyna...
Exploring Tehran's Architectural Marvels: A Glimpse into Vilaas Studio's Dyna...Yantram Animation Studio Corporation
 
ArtWaves 2024 - embracing Curves in Modern Homes
ArtWaves 2024 - embracing Curves in Modern HomesArtWaves 2024 - embracing Curves in Modern Homes
ArtWaves 2024 - embracing Curves in Modern HomesVellyslav Petrov
 
FW25-26 Knit Cut & Sew Trend Book Peclers Paris
FW25-26 Knit Cut & Sew Trend Book Peclers ParisFW25-26 Knit Cut & Sew Trend Book Peclers Paris
FW25-26 Knit Cut & Sew Trend Book Peclers ParisPeclers Paris
 
Piece by Piece Magazine
Piece by Piece Magazine                      Piece by Piece Magazine
Piece by Piece Magazine CharlottePulte
 
Understanding Image Masking: What It Is and Why It's Matters
Understanding Image Masking: What It Is and Why It's MattersUnderstanding Image Masking: What It Is and Why It's Matters
Understanding Image Masking: What It Is and Why It's MattersCre8iveskill
 

Recently uploaded (20)

ASME B31.4-2022 estandar ductos año 2022
ASME B31.4-2022 estandar ductos año 2022ASME B31.4-2022 estandar ductos año 2022
ASME B31.4-2022 estandar ductos año 2022
 
CERTIFICATE TEMPLATES FOR PORTFOLIO DAYS
CERTIFICATE TEMPLATES FOR PORTFOLIO DAYSCERTIFICATE TEMPLATES FOR PORTFOLIO DAYS
CERTIFICATE TEMPLATES FOR PORTFOLIO DAYS
 
PORTFOLIO 2024 ANASTASIYA KUDINOVA
PORTFOLIO 2024       ANASTASIYA KUDINOVAPORTFOLIO 2024       ANASTASIYA KUDINOVA
PORTFOLIO 2024 ANASTASIYA KUDINOVA
 
ALISIA: HOW MIGHT WE ACHIEVE HIGH ENVIRONMENTAL PERFORMANCE WHILE MAINTAINING...
ALISIA: HOW MIGHT WE ACHIEVE HIGH ENVIRONMENTAL PERFORMANCE WHILE MAINTAINING...ALISIA: HOW MIGHT WE ACHIEVE HIGH ENVIRONMENTAL PERFORMANCE WHILE MAINTAINING...
ALISIA: HOW MIGHT WE ACHIEVE HIGH ENVIRONMENTAL PERFORMANCE WHILE MAINTAINING...
 
Cities Light Up in Solidarity With Ukraine: From Internationally Synchronized...
Cities Light Up in Solidarity With Ukraine: From Internationally Synchronized...Cities Light Up in Solidarity With Ukraine: From Internationally Synchronized...
Cities Light Up in Solidarity With Ukraine: From Internationally Synchronized...
 
Niintendo Wii Presentation Template.pptx
Niintendo Wii Presentation Template.pptxNiintendo Wii Presentation Template.pptx
Niintendo Wii Presentation Template.pptx
 
eCultify brand guidelines- Shamika Dukle.pdf
eCultify brand guidelines- Shamika Dukle.pdfeCultify brand guidelines- Shamika Dukle.pdf
eCultify brand guidelines- Shamika Dukle.pdf
 
Highway LOS - Freeway-- Multilane -- highway class 2 & 3 Housam Siyoufi
Highway LOS - Freeway-- Multilane -- highway class 2 & 3 Housam SiyoufiHighway LOS - Freeway-- Multilane -- highway class 2 & 3 Housam Siyoufi
Highway LOS - Freeway-- Multilane -- highway class 2 & 3 Housam Siyoufi
 
Karim apartment ideas 02 ppppppppppppppp
Karim apartment ideas 02 pppppppppppppppKarim apartment ideas 02 ppppppppppppppp
Karim apartment ideas 02 ppppppppppppppp
 
Interior Design for Office a cura di RMG Project Studio
Interior Design for Office a cura di RMG Project StudioInterior Design for Office a cura di RMG Project Studio
Interior Design for Office a cura di RMG Project Studio
 
Unlock Canva Pro for Free Today - Canva Pro for Free.pdf
Unlock Canva Pro for Free Today - Canva Pro for Free.pdfUnlock Canva Pro for Free Today - Canva Pro for Free.pdf
Unlock Canva Pro for Free Today - Canva Pro for Free.pdf
 
Map of St. Louis Parks
Map of St. Louis Parks                              Map of St. Louis Parks
Map of St. Louis Parks
 
LIGHTSCAPES: HOW MIGHT WE DESIGN AN INCLUSIVE AND ACCESSIBLE CLASSICAL CONCER...
LIGHTSCAPES: HOW MIGHT WE DESIGN AN INCLUSIVE AND ACCESSIBLE CLASSICAL CONCER...LIGHTSCAPES: HOW MIGHT WE DESIGN AN INCLUSIVE AND ACCESSIBLE CLASSICAL CONCER...
LIGHTSCAPES: HOW MIGHT WE DESIGN AN INCLUSIVE AND ACCESSIBLE CLASSICAL CONCER...
 
simpson-lee_house_dt20ajshsjsjsjsjj15.pdf
simpson-lee_house_dt20ajshsjsjsjsjj15.pdfsimpson-lee_house_dt20ajshsjsjsjsjj15.pdf
simpson-lee_house_dt20ajshsjsjsjsjj15.pdf
 
_Neighborhood Planning in Capital City of Chandigarh- An Appraisal (2) - Copy...
_Neighborhood Planning in Capital City of Chandigarh- An Appraisal (2) - Copy..._Neighborhood Planning in Capital City of Chandigarh- An Appraisal (2) - Copy...
_Neighborhood Planning in Capital City of Chandigarh- An Appraisal (2) - Copy...
 
Exploring Tehran's Architectural Marvels: A Glimpse into Vilaas Studio's Dyna...
Exploring Tehran's Architectural Marvels: A Glimpse into Vilaas Studio's Dyna...Exploring Tehran's Architectural Marvels: A Glimpse into Vilaas Studio's Dyna...
Exploring Tehran's Architectural Marvels: A Glimpse into Vilaas Studio's Dyna...
 
ArtWaves 2024 - embracing Curves in Modern Homes
ArtWaves 2024 - embracing Curves in Modern HomesArtWaves 2024 - embracing Curves in Modern Homes
ArtWaves 2024 - embracing Curves in Modern Homes
 
FW25-26 Knit Cut & Sew Trend Book Peclers Paris
FW25-26 Knit Cut & Sew Trend Book Peclers ParisFW25-26 Knit Cut & Sew Trend Book Peclers Paris
FW25-26 Knit Cut & Sew Trend Book Peclers Paris
 
Piece by Piece Magazine
Piece by Piece Magazine                      Piece by Piece Magazine
Piece by Piece Magazine
 
Understanding Image Masking: What It Is and Why It's Matters
Understanding Image Masking: What It Is and Why It's MattersUnderstanding Image Masking: What It Is and Why It's Matters
Understanding Image Masking: What It Is and Why It's Matters
 

Vlsi workshop

  • 1. Workshop on Recent Trends in VLSI & Job Opportunities Vikas Billa
  • 2. S.no Timings Topic 1. 9.30 AM – 10.00 AM Inaugural Speech 2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc.. 3. 10.30 AM – 10.45 AM Networking Break 4. 10.45 AM – 11.00 AM Moore’s Law 5. 11.00 AM – 11.30 AM Chip Designing – Video Talk 6. 11.30 AM – 12.45 PM Importance of HDL 7. 12.45 PM – 1.30 PM Lunch Break 8. 1.30 PM – 2.30 PM Internet of Things 9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips 10. 3.00 PM – 3.15 PM Networking Break 11. 3.15 PM – 3.45 PM How to Write a Research paper? 12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities 13. 4.00 PM – 4.30 PM Closing Speech KITS(S)_2015 2 Agenda
  • 4. S.no Timings Topic 1. 9.30 AM – 10.00 AM Inaugural Speech 2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc.. 3. 10.30 AM – 10.45 AM Networking Break 4. 10.45 AM – 11.00 AM Moore’s Law 5. 11.00 AM – 11.30 AM Chip Designing – Video Talk 6. 11.30 AM – 12.45 PM Importance of HDL 7. 12.45 PM – 1.30 PM Lunch Break 8. 1.30 PM – 2.30 PM Internet of Things 9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips 10. 3.00 PM – 3.15 PM Networking Break 11. 3.15 PM – 3.45 PM How to Write a Research paper? 12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities 13. 4.00 PM – 4.30 PM Closing Speech KITS(S)_2015 4 Agenda 9.30 AM – 10.00 AM Inaugural Speech
  • 5. S.no Timings Topic 1. 9.30 AM – 10.00 AM Inaugural Speech 2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc.. 3. 10.30 AM – 10.45 AM Networking Break 4. 10.45 AM – 11.00 AM Moore’s Law 5. 11.00 AM – 11.30 AM Chip Designing – Video Talk 6. 11.30 AM – 12.45 PM Importance of HDL 7. 12.45 PM – 1.30 PM Lunch Break 8. 1.30 PM – 2.30 PM Internet of Things 9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips 10. 3.00 PM – 3.15 PM Networking Break 11. 3.15 PM – 3.45 PM How to Write a Research paper? 12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities 13. 4.00 PM – 4.30 PM Closing Speech KITS(S)_2015 5 Agenda 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc..
  • 6. KITS(S)_2015 6 What is VLSI ..? “Very Large Scale Integration” SSI – Small-Scale Integration (0-102) MSI – Medium-Scale Integration (102-103) LSI – Large-Scale Integration (103-105) VLSI – Very Large-Scale Integration (105-107) ULSI – Ultra Large-Scale Integration (>=107)
  • 8. KITS(S)_2015 8 ENTITY test is port a: in bit; end ENTITY test; DRC LVS ERC Circuit Design Functional Design and Logic Design Physical Design Physical Verification and Signoff Fabrication System Specification Architectural Design Chip Packaging and Testing Chip Planning Placement Signal Routing Partitioning Timing Closure Clock Tree Synthesis VLSI Flow
  • 9. Power IR Drop Analysis Hierarchical Clock Tree Synthesis Full Chip Power Planning Block-Level Optimization Timing Closure 150ps skew 120ps skew 50ps skew 50ps skew 100ps skew 130ps skew Place Detailed Trial Route RC Extraction Delay Calc / STA IPO Full Chip Physical Prototype Partition “Tape Out Every Day” Cool Pictures of the Pieces… M. Courtoy, Silicon Perspective
  • 10. Physical Prototype Partitioning Block 1 Block 2 Block 3 Block-Level Timing Budgets Block-Level Pin Assignments M. Courtoy, Silicon Perspective Cool Pictures of the Pieces…
  • 11. Verilog/ VHDL Library Std., Cell. Library Tech file For layout values Look up Table for timing Tech file For RC Parasite extraction Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Digital Design Flow
  • 12. Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Design Analysis This is a very crucial step in digital design where the design functionality is stated. Like if we are making a processor, what type of functionality is expected?? Digital Design Flow
  • 13. Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Design Specification This step involved stating in definite terms the performance of the chip. Like if we are making a processor, data size, processor speed, special functions, power etc. is clearly stated at this point. Also somewhat it is decided, the way to implement the design. So, it deals with architectural part of the design at highest level possible. Based on these foundation , the whole design is built Digital Design Flow
  • 14. Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification HDL Hardware Description Language is used to run the simulations. It is very expensive to build the entire chip and then verify the performance of the architecture. Imagine if after designing a chip for a whole year, the chip fabricated, does not come even closer to the stated specifications. Digital Design Flow
  • 15. Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification HDL (contd.) Hardware description languages provides a way to implement a design without going into much architecture, simulate and verify the design output and functionality. For eg. rather than building a mux design in hardware, we can write verilog code and verify the output at higher level of abstraction. Examples of HDL: VHDL, Verilog HDL Digital Design Flow
  • 16. Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification HDL (Contd.) At this time we can see the design in the form of Source Codes. It seems more of the software visualization of the circuit. The simulated code is taken to Synthesis to generate the Logic Circuit. Digital Design Flow
  • 17. Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Synthesis Imagine the use of K-Maps and Truth Tables to make and implement a digital design. If you notice, most of the digital designs are build up of some basic elements or components like gates, registers, counters, adders, subtractors, comparators, RAM, ROM etc. It forms the fundamentals of Logic Synthesis using EDA tools. Digital Design Flow
  • 18. Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Synthesis (Contd.) Standard Cell Library is the collection of such building blocks which comprises most of the digital designs. These cell libraries are fabrication technology specific. Digital Design Flow
  • 19. Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Synthesis ( Contd.) After the RTL simulation, the HDL, code is taken as input by Synthesis Tool and converted to Gate level. At this stage that the digital design becomes dependent on the fabrication process. At the end of this stage, we have the logic circuit I.e. in terms of gates and memories. Digital Design Flow
  • 20. Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Synthesis ( Contd.) What synthesis does is , when it encounters a specific construct in HDL it replaces it with the corresponding Standard Cell Component from the library to build the entire design. Like if we use a for loop , it gets converted to counter and a combinational circuit. Digital Design Flow
  • 21. Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Synthesis ( Contd.) The output of synthesis is a gate level netlist. Netlist is an ASCII file which enlists and indicates the devices and the interconnections between them. Digital Design Flow
  • 22. Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Simulation After the netlist is generated as part of synthesis, this netlist is simulated to verify the functionality of this gate level implementation of design. Till this level we just dealt with functionality part. Now each step onward deals with performance part too. Digital Design Flow
  • 23. Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Timing Analysis RTL and Gate Level simulation doesn’t take into account the physical time delay in signal propagation from one device to another and through the device. This time delay is dependent on the fabrication process adopted. Digital Design Flow
  • 24. Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Timing Analysis (Contd.) Each component in standard cell library is associated with some specific delay. Delay Lookup Tables list the delays associated with the components. Delays are in the form of rise time, fall time and turn off time delays. Digital Design Flow
  • 25. Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Timing Analysis (Contd.) Most of the digital designs employ concept of timing by using clocks. This makes the circuits synchronous. Digital Design Flow
  • 26. Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Timing Analysis (Contd.) In timing analysis, using Delay Lookup Tables, all the inputs and outputs of components are verified with timing introduced. Digital Design Flow
  • 27. Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Place & Route This is the actual stage where the design implemented at semiconductor layout level. This the stage which really requires more knowledge of semiconductor physics than digital design. Digital Design Flow
  • 28. Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Place & Route (Contd.) Semiconductor layout has to follow certain design rules to lay devices at semiconductor level. These design rules are fabrication process dependent. The layout uses layers as p/n diffusion, nwell, pwell, metals, via, iso etc. Rules involving min. spacing, and electrical relation between two layers are known as DESIGN RULES. Digital Design Flow
  • 29. Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Place & Route (Contd.) Placement and Routing involves laying of the devices, placing them and making interconnection between them, following the Design Rules. The result is the design implemented in the form of semiconductor layers. Digital Design Flow
  • 30. Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Extraction Once the layout is made, there always is parasitic capacitances and resistances associated with the design. This is because of the compact layouts to make the chips smaller. More you make compact layout more will it introduce these parasitic components. These interferes in the functioning and performance of the circuit in terms of timing, speed and power consumption. Digital Design Flow
  • 31. Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Extraction (Contd.) Due to these factors it becomes very much important to extract these devices from layout and check the design for performance and functionality. Extraction would extract from the layout, the devices formed because of junctions of different semiconductor and metal layers and the interconnections. Digital Design Flow
  • 32. Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Verification Verification would either be the tape out stage of the chip or the stage where design is again taken back through the same flow for optimization or modification. It verifies the extracted view of the chip for performance and functionality. Digital Design Flow
  • 35. 35 • ~ 70% of project development cycle: design verification • Every approach to reduce this time has a considerable influence on economic success of a product. • Not unusual for ~complex chip to go through multiple tape-outs before release. Verification Costs
  • 36. 36 • Verification is a bottleneck in the design process: • High cost of design debug • designers (sometimes verification engineers = 2 * design engineers) • time-to-market • High cost of faulty designs (loss of life, product recall) Importance of Verification
  • 37. 37 Problems found on 1st spin ICs/ASICs 43% 20% 17%14% 12% 11% 11% 10% 10% 7% 4% 3% Functional Logic Error Analog Tuning Issue Signal Integrity Issue Clock Scheme ErrorReliability Issue Uses Too Much Power Mixed Signal Problem Has Path Too Slow Has Path Too Fast IR Drop Issues Firmware Error Other Problem Source: DeepChip, Aart de Geus, Chairman & CEO of Synopsys used it during Wed, 10 Sep 2003 Boston SNUG keynote address  Overall 61% of New ICs/ASICs Require At Least One Re-Spin  %43 due to functional error
  • 38. 38 Flow of Simulation-Based Verification design testbench design simulation debug regression revision control bug tracking coverage metrics stimulus generation test plan linting • Dashed line: Components specific to sim- based methodology (are replaced by components in formal methodology)
  • 39. 2/10/03 ECE 426 - Lecture 5 39 Functional Verification Approaches • Black box • Verify using module I/O ports only • No knowledge of implementation • No access to internals • White box • Verify using module I/O ports and internals • Full knowledge of implementation • Full access to internals during simulation • Gray box • Verify using module I/O ports only • Full knowledge of implementation • No access to internals during simulation
  • 40. 2/10/03 ECE 426 - Lecture 5 40 Testbenches Module Instance: Device Under Verification (DUV) Testbench Module
  • 42. S.no Timings Topic 1. 9.30 AM – 10.00 AM Inaugural Speech 2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc.. 3. 10.30 AM – 10.45 AM Networking Break 4. 10.45 AM – 11.00 AM Moore’s Law 5. 11.00 AM – 11.30 AM Chip Designing – Video Talk 6. 11.30 AM – 12.45 PM Importance of HDL 7. 12.45 PM – 1.30 PM Lunch Break 8. 1.30 PM – 2.30 PM Internet of Things 9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips 10. 3.00 PM – 3.15 PM Networking Break 11. 3.15 PM – 3.45 PM How to Write a Research paper? 12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities 13. 4.00 PM – 4.30 PM Closing Speech KITS(S)_2015 42 Agenda 10.30 AM – 10.45 AM Networking Break
  • 44. S.no Timings Topic 1. 9.30 AM – 10.00 AM Inaugural Speech 2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc.. 3. 10.30 AM – 10.45 AM Networking Break 4. 10.45 AM – 11.00 AM Moore’s Law 5. 11.00 AM – 11.30 AM Chip Designing – Video Talk 6. 11.30 AM – 12.45 PM Importance of HDL 7. 12.45 PM – 1.30 PM Lunch Break 8. 1.30 PM – 2.30 PM Internet of Things 9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips 10. 3.00 PM – 3.15 PM Networking Break 11. 3.15 PM – 3.45 PM How to Write a Research paper? 12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities 13. 4.00 PM – 4.30 PM Closing Speech KITS(S)_2015 44 Agenda 10.45 AM – 11.00 AM Moore’s Law
  • 45. KITS(S)_2015 45 Moore’s Law The performance of an IC, including the number components on it, doubles every 18-24 months with the same chip price ... - Gordon Moore - 1960
  • 46. KITS(S)_2015 46 Moore’s Law – It’s all about Economics
  • 47. … Moore’s Law and Technology Scaling
  • 48. S.no Timings Topic 1. 9.30 AM – 10.00 AM Inaugural Speech 2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc.. 3. 10.30 AM – 10.45 AM Networking Break 4. 10.45 AM – 11.00 AM Moore’s Law 5. 11.00 AM – 11.30 AM Chip Designing – Video Talk 6. 11.30 AM – 12.45 PM Importance of HDL 7. 12.45 PM – 1.30 PM Lunch Break 8. 1.30 PM – 2.30 PM Internet of Things 9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips 10. 3.00 PM – 3.15 PM Networking Break 11. 3.15 PM – 3.45 PM How to Write a Research paper? 12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities 13. 4.00 PM – 4.30 PM Closing Speech KITS(S)_2015 48 Agenda 11.00 AM – 11.30 AM Chip Designing – Video Talk
  • 49. Chip Designing – Video Talk KITS(S)_2015 49
  • 50. S.no Timings Topic 1. 9.30 AM – 10.00 AM Inaugural Speech 2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc.. 3. 10.30 AM – 10.45 AM Networking Break 4. 10.45 AM – 11.00 AM Moore’s Law 5. 11.00 AM – 11.30 AM Chip Designing – Video Talk 6. 11.30 AM – 12.45 PM Importance of HDL 7. 12.45 PM – 1.30 PM Lunch Break 8. 1.30 PM – 2.30 PM Internet of Things 9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips 10. 3.00 PM – 3.15 PM Networking Break 11. 3.15 PM – 3.45 PM How to Write a Research paper? 12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities 13. 4.00 PM – 4.30 PM Closing Speech KITS(S)_2015 50 Agenda 11.30 AM – 12.45 PM Importance of HDL
  • 51. • Initially proprietary language of Gateway Design Automation Inc.around 1984 • In 1989 Cadence acquired Gateway Design Automation • In 1990 Cadence organized Open Verilog International(OVI) • In 1995 Verilog became a IEEE standard Ieee 1364-1995 KITS(S)_2015 51 History of Verilog
  • 52. • Easier to understand than schematics • Enables design at higher levels of abstraction • Works on all available CAE(Computer aided Engineering ) Tools • Provides Technology Independence • Verilog can be coded for synthesis or simulation. • Some constructs used for simulation can not be synthesized • For Simulation CAE tools uses timing information defined in a Verilog model. KITS(S)_2015 52 Importance of Verilog
  • 53. Design Flow Using Verilog KITS(S)_2015 53
  • 54. Design Methodologies Top Down Design Methodology KITS(S)_2015 54
  • 59. Describe this In Verilog KITS(S)_2015 59
  • 60. KITS(S)_2015 60 Example 1 : Vending Machine
  • 61. KITS(S)_2015 61 Example 2 : Traffic Light Controller
  • 62. KITS(S)_2015 62 Example 2 : Traffic Light Controller
  • 63. S.no Timings Topic 1. 9.30 AM – 10.00 AM Inaugural Speech 2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc.. 3. 10.30 AM – 10.45 AM Networking Break 4. 10.45 AM – 11.00 AM Moore’s Law 5. 11.00 AM – 11.30 AM Chip Designing – Video Talk 6. 11.30 AM – 12.45 PM Importance of HDL 7. 12.45 PM – 1.30 PM Lunch Break 8. 1.30 PM – 2.30 PM Internet of Things 9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips 10. 3.00 PM – 3.15 PM Networking Break 11. 3.15 PM – 3.45 PM How to Write a Research paper? 12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities 13. 4.00 PM – 4.30 PM Closing Speech KITS(S)_2015 63 Agenda 12.45 PM – 1.30 PM Lunch Break
  • 64. S.no Timings Topic 1. 9.30 AM – 10.00 AM Inaugural Speech 2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc.. 3. 10.30 AM – 10.45 AM Networking Break 4. 10.45 AM – 11.00 AM Moore’s Law 5. 11.00 AM – 11.30 AM Chip Designing – Video Talk 6. 11.30 AM – 12.45 PM Importance of HDL 7. 12.45 PM – 1.30 PM Lunch Break 8. 1.30 PM – 2.30 PM Internet of Things 9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips 10. 3.00 PM – 3.15 PM Networking Break 11. 3.15 PM – 3.45 PM How to Write a Research paper? 12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities 13. 4.00 PM – 4.30 PM Closing Speech KITS(S)_2015 64 Agenda 1.30 PM – 2.30 PM Internet of Things
  • 68. 68 Motion sensor Motion sensor Motion sensor ECG sensor Internet KITS(S)_2015 People Connecting to Things
  • 90. S.no Timings Topic 1. 9.30 AM – 10.00 AM Inaugural Speech 2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc.. 3. 10.30 AM – 10.45 AM Networking Break 4. 10.45 AM – 11.00 AM Moore’s Law 5. 11.00 AM – 11.30 AM Chip Designing – Video Talk 6. 11.30 AM – 12.45 PM Importance of HDL 7. 12.45 PM – 1.30 PM Lunch Break 8. 1.30 PM – 2.30 PM Internet of Things 9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips 10. 3.00 PM – 3.15 PM Networking Break 11. 3.15 PM – 3.45 PM How to Write a Research paper? 12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities 13. 4.00 PM – 4.30 PM Closing Speech KITS(S)_2015 90 Agenda 1.30 PM – 2.30 PM Smart Device Idea Design Contest
  • 91. Smart Device Idea Design Contest
  • 92. S.no Timings Topic 1. 9.30 AM – 10.00 AM Inaugural Speech 2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc.. 3. 10.30 AM – 10.45 AM Networking Break 4. 10.45 AM – 11.00 AM Moore’s Law 5. 11.00 AM – 11.30 AM Chip Designing – Video Talk 6. 11.30 AM – 12.45 PM Importance of HDL 7. 12.45 PM – 1.30 PM Lunch Break 8. 1.30 PM – 2.30 PM Internet of Things 9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips 10. 3.00 PM – 3.15 PM Networking Break 11. 3.15 PM – 3.45 PM How to Write a Research paper? 12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities 13. 4.00 PM – 4.30 PM Closing Speech KITS(S)_2015 92 Agenda 2.30 PM – 3.00 PM Bio- Neuro VLSI
  • 94. • Carver Mead introduce the term Neuromorphic Engineering to describe a new field of engineering whose design principles and architecture are biologically Inspired. • Neuro“to do with neurons i.e. neutrally inspired” • Morphic “structure or form” KITS(S)_2015 94 Neuromorphic Engineering
  • 95. • Build machines that have similar perception capabilities as human perception • Adaptable and self organizing • Robust to changing environments Realisation of future “THINKING”machines (intelligent and interactive systems) KITS(S)_2015 95 Principles of Neuromorphic Technology
  • 98. KITS(S)_2015 98 3D Retina Chip in to Human Eye
  • 99. KITS(S)_2015 99 Cross-Section of Human & Artificial Retina
  • 100. S.no Timings Topic 1. 9.30 AM – 10.00 AM Inaugural Speech 2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc.. 3. 10.30 AM – 10.45 AM Networking Break 4. 10.45 AM – 11.00 AM Moore’s Law 5. 11.00 AM – 11.30 AM Chip Designing – Video Talk 6. 11.30 AM – 12.45 PM Importance of HDL 7. 12.45 PM – 1.30 PM Lunch Break 8. 1.30 PM – 2.30 PM Internet of Things 9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips 10. 3.00 PM – 3.15 PM Networking Break 11. 3.15 PM – 3.45 PM How to Write a Research paper? 12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities 13. 4.00 PM – 4.30 PM Closing Speech KITS(S)_2015 100 Agenda 2.30 PM – 3.00 PM 3D chips
  • 101. •There is a saying in real estate; when land get expensive, multi-storied buildings are the alternative solution. KITS(S)_2015 101 3D Chips
  • 102. • The unprecedented growth of the computer and the information technology industry is demanding Very Large Scale Integrated (VLSI) circuits with increasing functionality and performance at minimum cost and power dissipation. • Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnects delays. • Limits of Moore’s Law? KITS(S)_2015 102 Motivation for 3D Chips
  • 104. Many options available for realization of 3D circuits Choice of Fabrication depends on requirements of Circuit System • Wafer bonding • Epitaxial growth KITS(S)_2015 104 3D Fabrication Technologies  Die to Wafer  Wafer to Wafer
  • 107. • 3D VLSI can influence market only with high quality products improved quality/low cost will sell • Little immediate impact expected more research and small scale development needed • expensive change of fabrication process required • long time-to-market KITS(S)_2015 107 Market
  • 108. • 3D VLSI requires major paradigm shift in industry • Initial participants -large capital risk to modify fabrication process • Success of one company will require shift in industry as a whole (competition) KITS(S)_2015 108 Impact
  • 109. KITS(S)_2015 109 Fields of Application for Dream Chips
  • 110. • Effective interdependence collaborations among the key areas of biology, electrical & electronics engineering, physiology and computer science are very fundamental to develop this emerging area. KITS(S)_2015 110 3D VLSI Key Areas
  • 111. • As the systems mature, human parts replacements would become a major application area. The fundamental principle is by observing how biological systems perform these functions robust artificial systems are designed. KITS(S)_2015 111 Future
  • 112. S.no Timings Topic 1. 9.30 AM – 10.00 AM Inaugural Speech 2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc.. 3. 10.30 AM – 10.45 AM Networking Break 4. 10.45 AM – 11.00 AM Moore’s Law 5. 11.00 AM – 11.30 AM Chip Designing – Video Talk 6. 11.30 AM – 12.45 PM Importance of HDL 7. 12.45 PM – 1.30 PM Lunch Break 8. 1.30 PM – 2.30 PM Internet of Things 9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips 10. 3.00 PM – 3.15 PM Networking Break 11. 3.15 PM – 3.45 PM How to Write a Research paper? 12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities 13. 4.00 PM – 4.30 PM Closing Speech KITS(S)_2015 112 Agenda 3.00 PM – 3.15 PM Networking Break
  • 113. S.no Timings Topic 1. 9.30 AM – 10.00 AM Inaugural Speech 2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc.. 3. 10.30 AM – 10.45 AM Networking Break 4. 10.45 AM – 11.00 AM Moore’s Law 5. 11.00 AM – 11.30 AM Chip Designing – Video Talk 6. 11.30 AM – 12.45 PM Importance of HDL 7. 12.45 PM – 1.30 PM Lunch Break 8. 1.30 PM – 2.30 PM Internet of Things 9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips 10. 3.00 PM – 3.15 PM Networking Break 11. 3.15 PM – 3.45 PM How to Write a Research paper? 12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities 13. 4.00 PM – 4.30 PM Closing Speech KITS(S)_2015 113 Agenda 3.15 PM – 3.45 PM How to Write a Research Paper?
  • 114. How to Write a Research Paper..?
  • 115. S.no Timings Topic 1. 9.30 AM – 10.00 AM Inaugural Speech 2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc.. 3. 10.30 AM – 10.45 AM Networking Break 4. 10.45 AM – 11.00 AM Moore’s Law 5. 11.00 AM – 11.30 AM Chip Designing – Video Talk 6. 11.30 AM – 12.45 PM Importance of HDL 7. 12.45 PM – 1.30 PM Lunch Break 8. 1.30 PM – 2.30 PM Internet of Things 9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips 10. 3.00 PM – 3.15 PM Networking Break 11. 3.15 PM – 3.45 PM How to Write a Research paper? 12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities 13. 4.00 PM – 4.30 PM Closing Speech KITS(S)_2015 115 Agenda 3.45 PM – 4.00 PM Higher Studies & Job opportunities
  • 116. Higher Studies & Job Opportunities
  • 117. KITS(S)_2015 117 • If you ever tinkered with a broken radio set, you have already started. • Academically, the right time to acquaint yourself with various specializations of Electronics is when you are in second or third year of engineering. When is the right time to think about VLSI ?
  • 118. KITS(S)_2015 118 What Sort of Jobs does an Electronic Engineer do ? ENTITY test is port a: in bit; end ENTITY test; DRC LVS ERC Circuit Design Functional Design and Logic Design Physical Design Physical Verification and Signoff Fabrication System Specification Architectural Design Chip Packaging and Testing Chip Planning Placement Signal Routing Partitioning Timing Closure Clock Tree Synthesis
  • 119. S.no Timings Topic 1. 9.30 AM – 10.00 AM Inaugural Speech 2. 10.00 AM – 10.30 AM VLSI Intro, VLSI Flow etc.. 3. 10.30 AM – 10.45 AM Networking Break 4. 10.45 AM – 11.00 AM Moore’s Law 5. 11.00 AM – 11.30 AM Chip Designing – Video Talk 6. 11.30 AM – 12.45 PM Importance of HDL 7. 12.45 PM – 1.30 PM Lunch Break 8. 1.30 PM – 2.30 PM Internet of Things 9. 2.30 PM – 3.00 PM Bio - Neuro VLSI and 3D chips 10. 3.00 PM – 3.15 PM Networking Break 11. 3.15 PM – 3.45 PM How to Write a Research paper? 12. 3.45 PM – 4.00 PM Higher Studies & Job Opportunities 13. 4.00 PM – 4.30 PM Closing Speech KITS(S)_2015 119 Agenda 4.00 PM – 4.30 PM Closing Speech
  • 121. Q & A Thank you ...121