BOOK

1. Information Classification: General
Chapter 1
Fundamentals of digital system design
Figure 1.0.1: A simple ASIC digital system design flow.
1.1 MATLAB, Scilab, Octave tools and basic syntax
Hallo
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% Peaks detection module: finds max and these indexs of a given signal "x"
% INPUT: x: signal in a one-dimensional array
% OUTPUT: Maxs: max peak indexs and max peak values
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
function peaks = myPeaksDetector(x)
leng = length(x);
dx = [];

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peaks = [];
for j = 2 : leng -1
dx(j) = x(j) - x(j-1);
dx(j+1) = x(j+1) - x(j);
if(dx(j) == 0 || (dx(j) >= 0 && dx(j+1) < 0))
peaks = [peaks; j, x(j)];
end
end
end
Table 1.2.1: Basic format of a MATLAB program.
Figure 1.1.1: MATLAB environment development.
1.2 Verilog HDL and basic syntax
Verilog language is parallel, each always block is executed at the same time, while C
language is executed in sequence. Verilog is also hardware description language; when
programming with Verilog, it is better to describe a circuit with Verilog, while C is a program.
module a(b， c， d，...z)； // module header a: module name (b,c,d,...z): port list
input b; // Input declaration
input wire c; // Enter and declare wire for wire network type, wire can be omitted
input wire [7:0] d; // [7:0]: input bus bit width 0 ~ 7, so it is 8 bit bus
output e; // Output declaration
output [7:0] f; // Description of the output bus bit width, the default is wire type,
wire is omitted here
output reg [7:0] f; // reg for output bus register type
assign d = a & b; // The assignment statement is also called the data flow modeling
statement or the continuous assignment statement, followed by the combination logic
assign e = (f < g)? 1 : 0; // ternary operator
//always statement, posedge is triggered by rising edge, nagedge is triggered by falling edge, followed
by a signal that when the signal rises or falls, the following program is executed

3. Information Classification: General
always @ (posedge a or negedge b or posedge c...)
begin // begin...end is equivalent to ()
if(!b) begin
h <= 4'b0000; // The nonblocking assignment statement uses < =, 4'b0000 to indicate
that the bit width is 4, and the binary number 0000
i <= 32'haabbccdd; // Here is the 32-bit width, and the hexadecimal number aabbccdd
end
else // else for branch
case(j) // case statement
0 : k <= k + 1'b1; // There is no self-adding representation in Verilog, so k = k + 1'b1
1 : if(k<m) begin
l <= 8'd7;
j <= 2;
end // j < = 2 indicates next clock jumps to 2: statement after triggering
2 : m < = 4'b0001 << 2; //< shift symbol
default: j <=0; // default means to go when the value of j is not 0,1,2 listed above
endcase // case multi branch statement end flag
end // End of the entire always loop flag
endmodule // End of whole module
Table 1.2.1: Basic format of a Verilog program.
Figure 1.2.1: FSM Moore model.
// module declaration
module xxx
# (parameter p1= 16, p2= 4)
(
input [] iii,
output [] ooo
);
// Internals
reg [] _present, _next;
//---------------1) State registers: --------------
always@ (posedge clk or negedge rst_n)
begin
if(~rst_n) begin
_present <= 0;
end
else begin
_present <= FFF(_next);
end
end
end
//---------------2) Next state logic: --------------
always@ (*)
begin
_next = FFF (_present, iii);
end

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//-------------- 3) Output logics: --------------
assign ooo = FFF (_present); // with Moore model
assign ooo = FFF (_present, iii); // with Mealy model
endmodule
Table 1.2.2: Basic format of a Verilog program as FSM Moore model.
1.3 Quartus Prime lite edition tool
Figure 1.3.1: Quartus Prime lite environment development.
1.4 ModelSim INTEL FPGA STARTER EDITION 10.5b

5. Information Classification: General
Figure 1.4.1: ModelSim development environment.
1.5 An introduction of MATLAB HDL

6. Information Classification: General
Figure 1.5.1: Quartus Prime lite environment development.